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CXA3246Q 8-bit 120msps flash a/d converter description the CXA3246Q is an 8-bit high-speed flash a/d converter capable of digitizing analog signals at the maximum rate of 120msps. ecl, pecl or ttl can be selected as the digital input level in accordance with the application. the ttl digital output level allows 1: 2 demultiplexed output. features differential linearity error: 0.5lsb or less integral linearity error: 0.5lsb or less high-speed operation with a maximum conversion rate of 120msps low input capacitance: 10pf wide analog input bandwidth: 250mhz low power consumption: 500mw 1: 2 demultiplexed output 1/2 frequency-divided clock output (with reset function) compatible with ecl, pecl and ttl digital input levels ttl output "h" levels: 2.8v (typ.) +3.3v line cmos ic direct connecting available single +5v power supply operation available surface mounting package (48-pin qfp) pin configuration (top view) structure bipolar silicon monolithic ic applications magnetic recording (prml) communications (qpsk, qam) lcds digital oscilloscopes ?1 e97902a8x-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. clk/e n.c. clk/t n.c. n.c. dv cc 2 dgnd2 pad0 pad1 pad2 pad3 clkn/e pad4 pad7 pad6 dgnd1 dv cc 1 dv cc 2 dgnd2 pbd0 pbd1 pbd2 pbd3 pad5 resetn/e select resetn/t inv clkout dv cc 2 dgnd2 pbd7 pbd6 pbd5 pbd4 reset/e dv ee 3 v rm 1 agnd av cc v in v rm 2 av cc v rm 3 agnd v rt dgnd3 v rb 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 48 pin qfp (plastic) lead treatment: palladium plating
? 2 CXA3246Q absolute maximum ratings (ta = 25 c) unit supply voltage av cc , dv cc 1, dv cc 2 ?.5 to +7.0 v dgnd3 ?.5 to +7.0 v dv ee 3 ?.0 to +0.5 v dgnd3 ?dv ee 3 ?.5 to +7.0 v analog input voltage v in v rt ?2.7 to av cc v reference input voltage v rt 2.7 to av cc v v rb v in ?2.7 to av cc v |v rt ?v rb | 2.5 v digital input voltage ecl/pecl input pin dv ee 3 ?0.5 to dgnd3 + 0.5 v ttl input pin dgnd1 ?0.5 to dv cc 1 + 0.5 v vid * 1 (| *** /e ? *** n/e| ) 2.7 v storage temperature tstg ?5 to +150 c allowable power dissipation p d 1.6 w (when mounted on a two-layer glass fabric base epoxy board with dimentions of 50mm 50mm, 1.6mm thick) recommended operating conditions with a single power supply with dual power supply unit min. typ. max. min. typ. max. supply voltage dv cc 1, dv cc 2, av cc +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 v dgnd1, dgnd2, agnd ?.05 0 +0.05 ?.05 0 +0.05 v dgnd3 +4.75 +5.0 +5.25 ?.05 0 +0.05 v dv ee 3 ?.05 0 +0.05 ?.5 ?.0 ?.75 v analog input voltage v in v rb v rt v rb v rt v reference input voltage v rt +2.9 +4.1 +2.9 +4.1 v v rb +1.4 +2.6 +1.4 +2.6 v |v rt ?v rb | 1.5 2.1 1.5 2.1 v digital input voltage ecl/pecl input pin : v ih dv ee 3 + 1.5 dgnd3 dv ee 3 + 1.5 dgnd3 v : v il dv ee 3 + 1.1 v ih ?0.4 dv ee 3 + 1.1 v ih ?0.4 v ttl input pin : v ih 2.0 2.0 v : v il 0.8 0.8 v vid * 1 (| *** /e ? *** n/e| ) 0.4 0.8 0.4 0.8 v maximum conversion rate fc (straight mode) 100 100 msps (dmux mode) 120 120 msps ambient temperature ta ?0 +75 ?0 +75 c * 1 vid: input voltage differential ecl and pecl switching level v i d v i l ( m i n . ) v i h v t h ( d g n d 3 1 . 2 v ) v i l v i h ( m a x . ) d g n d 3
? 3 CXA3246Q pin description [symbol] [pin no.] [description] digital power supply bottom reference voltage analog ground reference voltage mid point analog power supply analog signal input reference voltage mid point analog power supply reference voltage mid point analog ground reference voltage (typ.) digital power supply ecl/pecl clock input ecl/pecl clock input ttl clock input no connected pin digital power supply digital ground pa side data output digital ground digital power supply digital power supply digital ground pb side data output digital ground digital power supply clock output data output polarity inversion output mode selection ttl reset input ecl/pecl reset input ecl/pecl reset input 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 18 19 20 21 to 28 29 30 31 32 33 to 40 41 42 43 44 45 46 47 48 dv ee 3 v rb agnd v rm 1 av cc v in v rm 2 av cc v rm 3 agnd v rt dgnd3 clk/e clkn/e clk/t n.c. dv cc 2 dgnd2 pad0 to pad7 dgnd1 dv cc 1 dv cc 2 dgnd2 pbd0 to pbd7 dgnd2 dv cc 2 clkout inv select resetn/t reset/e resetn/e 0v 1.4 to 2.6v 0v +5v v rb to v rt +5v 0v 2.9 to 4.1v +5v pecl pecl ttl +5v 0v ttl 0v +5v +5v 0v ttl 0v +5v ttl ttl ttl ttl pecl pecl ?.0v 1.4 to 2.6v 0v +5v v rb to v rt +5v 0v 2.9 to 4.1v 0v ecl ecl ttl +5v 0v ttl 0v +5v +5v 0v ttl 0v +5v ttl ttl ttl ttl ecl ecl typical voltage level with a single power supply typical voltage level with dual power supply
? 4 CXA3246Q block diagram 6 b i t v r t 2 3 5 8 1 0 1 2 1 3 1 4 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 4 1 1 2 r / 2 6 3 6 4 6 5 1 2 6 1 2 7 1 2 8 1 2 9 1 9 1 1 9 2 1 9 3 2 5 4 2 5 5 r 6 b i t 9 7 4 r 1 r 2 r r r r r r r r r r r r r r / 2 6 b i t 6 b i t 8 b i t 8 b i t 1 5 4 6 4 7 4 8 s e l e c t d q q 4 5 s e l e c t 1 1 4 3 d g n d 1 d v e e 3 d g n d 2 a g n d a v c c d v c c 2 d v c c 1 i n v d g n d 3 v r m 3 v i n v r m 2 6 v r b v r m 1 c l k / t c l k / e c l k n / e r e s e t n / t r e s e t n / e r e s e t / e c l k o u t p a d 0 p a d 1 p a d 2 p a d 3 p a d 4 p a d 5 p a d 6 p a d 7 p b d 0 p b d 1 p b d 2 p b d 3 p b d 4 p b d 5 p b d 6 p b d 7 t t l o u t l a t c h a t t l o u t l a t c h b 6 b i t l a t c h + e n c o d e r e n c o d e r ( l s b ) ( m s b ) ( l s b ) ( m s b ) l a t c h b n . c . n . c . n . c .
? 5 CXA3246Q pin description and i/o pin equivalent circuit analog ground. separated from the digital ground. analog power supply. separated from the digital power supply. digital ground. digital power supply. digital power supply. ground for ecl input. +5v for pecl and ttl inputs. digital power supply. ?v for ecl input. ground for pecl and ttl inputs. no connected pin. not connected with the internal circuits. n.c. 16, 17 18 3, 10 5, 8 20, 29 32, 41 19, 30 31, 42 12 1 agnd av cc dgnd1 dgnd2 dv cc 1 dv cc 2 dgnd3 dv ee 3 gnd +5v (typ.) gnd +5v (typ.) +5v (typ.) (with a single power supply) gnd (with dual power supply) gnd (with a single power supply) ?v (typ.) (with dual power supply) pin no. symbol i/o standard voltage level equivalent circuit description
? 6 CXA3246Q pin no. 15 clk/t clock input. 46 resetn/t ttl ttl vcc or gnd reset signal input. when left open, this pin goes to high level. when set to low level, the built-in clk frequency divider circuit can be reset. 44 inv data output polarity inversion input. when left open, this input goes to high level. (see table 1. i/o correspondence table.) 45 select data output mode selection. (see table 2. operation mode table.) symbol standard voltage level equivalent circuit description 1 5 4 6 d v c c 1 d g n d 1 d v e e 3 4 4 4 5 o r , 1 . 5 v i i i i/o clock input. clk/e complementary input. when left open, this pin goes to the threshold voltage. only clk/e can be used for operation, but complementary inputs are recommended to attain fast and stable operation. reset signal input. when set to low level, the built-in clk frequency divider circuit can be reset. resetn/e complementary input. when left open, this pin goes to the threshold voltage. only resetn/e can be used for operation. ecl/ pecl 13 14 48 47 clk/e clkn/e resetn/e reset/e i i i i 1 3 1 4 4 8 4 7 d g n d 3 d v e e 3
? 7 CXA3246Q 4.0v (typ.) 11 v rt top reference voltage. by-pass to agnd with a 1 f tantal capacitor and a 0.1 f chip capacitor. v rb + (v rt ?v rb ) 9 v rm 3 reference voltage mid point. by-pass to agnd with a 0.1 f chip capacitor. 7 v rm 2 reference voltage mid point. by-pass to agnd with a 0.1 f chip capacitor. 4 v rm 1 reference voltage mid point. by-pass to agnd with a 0.1 f chip capacitor. 2.0v (typ.) 2 v rb bottom reference voltage. by-pass to agnd with a 1 f tantal capacitor and a 0.1 f chip capacitor. r 1 r / 2 c o m p a r a t o r 1 c o m p a r a t o r 6 3 c o m p a r a t o r 6 4 c o m p a r a t o r 1 2 8 c o m p a r a t o r 1 9 1 c o m p a r a t o r 1 2 7 c o m p a r a t o r 1 9 2 c o m p a r a t o r 2 5 5 r r 2 r / 2 r r r r 4 7 9 2 1 1 r i i 4 3 4 2 v rb + (v rt ?v rb ) 4 1 v rb + (v rt ?v rb ) pin no. symbol i/o standard voltage level equivalent circuit description clock output. (see table 2. operation mode table.) ttl output; the high level is clamped to approximately 2.8v. 21 to 28 pad0 to pad7 port a side data output. ttl output; the high level is clamped to approximately 2.8v. 33 to 40 pbd0 to pbd7 43 clkout port b side data output. ttl output; the high level is clamped to approximately 2.8v. 6 v in v rt to v rb i ttl o o o analog input. a v c c c o m p a r a t o r v r e f a g n d d v e e 3 a v c c 6 d v c c 2 d g n d 2 d v c c 1 d g n d 1 1 0 0 k d v e e 3 2 1 2 8 3 3 4 0 4 3 t o t o
? 8 CXA3246Q resolution dc characteristics integral linearity error differential linearity error analog input analog input capacitance analog input resistance analog input current reference input reference resistance reference current offset voltage v rt side v rb side digital input (ecl, pecl) digital input voltage : high : low threshold voltage digital input current : high : low digital input capacitance digital input (ttl) digital input voltage : high : low threshold voltage digital input current : high : low digital input capacitance digital output (ttl) digital output voltage : high : low switching characteristics maximum conversion rate aperture jitter sampling delay clock high pulse width clock low pulse width reset signal setup time reset signal hold time clock output delay data output delay output rise time output fall time electrical characteristics (av cc , dv cc 1, 2, dgnd3 = +5v, agnd, dgnd1, 2, dv ee 3 = 0v, v rt = 4v, v rb = 2v, ta = 25 c) item symbol min. typ. max. unit conditions e il e dl c in r in i in rref * 2 iref * 3 eot eob v ih v il v th i ih i il v ih v il v th i ih i il v oh v ol fc taj tds tpw1 tpw0 t_rs t_rh td_clk tdo1 tdo2 tr tf 7 0 400 2.7 6 0 dv ee 3 + 1.5 dv ee 3 + 1.1 ?0 ?0 2.0 ?0 ?0 2.4 120 1.2 3.0 4.5 1.0 ?.5 3.0 3.5 8 10 20 100 600 3.3 8 1.5 dgnd3 ?1.2 1.5 10 1.4 4.5 t * 4 + 0.5 5.0 1 1 0.5 0.5 40 285 740 5.0 10 3 dgnd3 v ih ?0.4 20 20 5 0.8 5 0 5 0.5 1.6 7.0 7.5 bits lsb lsb pf k a ma mv mv v v v a a pf v v v a a pf v v msps ps ns ns ns ns ns ns ns ns ns ns v in = 2vp-p, fc = 5msps v in = +3.0v + 0.07vrms v ih = dgnd3 ?0.8v v il = dgnd3 ?1.6v v ih = 3.5v v il = 0.2v i oh = ?ma i ol = 1ma dmux mode clk clk resetn ?clk resetn ?clk (c l = 5pf) dmux mode (c l = 5pf) (c l = 5pf) 0.8 to 2.0v (c l = 5pf) 0.8 to 2.0v (c l = 5pf) * these characteristics are for pecl input unless otherwise specified.
? 9 CXA3246Q * 4 t = * 5 tps: times per sample * 6 pd = (i cc + i ee ) ?v cc + (v rt ?v rb ) 2 rref dynamic characteristics input bandwidth s/n ratio error rate power supply supply current avcc pin supply current dvcc1 pin supply current dvcc2 pin supply current dgnd3 pin supply current power consumption i cc + i ee ai cc di cc 1 di cc 2 i ee pd * 6 250 70 45 20 5 0.5 400 46 42 98 500 10 ?2 10 ? 10 ? 140 87 36 15 1.5 700 mhz db db tps * 5 tps tps ma ma ma ma ma mw v in = 2vp-p, ?db fc = 120msps, fin = 1khz fs dmux mode fc = 120msps, fin = 29.999mhz fs dmux mode fc = 120msps, fin = 1khz fs dmux mode error > 16lsb fc = 120msps, fin = 29.999mhz fs dmux mode error > 16lsb fc = 100msps, fin = 24.999mhz fs straight mode error > 16lsb { { { { { 1 fc item symbol min. typ. max. unit conditions * 2 rref: resistance value between v rt and v rb * 3 iref = v rt ?v rb rref
? 10 CXA3246Q table 1. i/o correspondence table inv 1 d7 d0 d7 d0 0 v in v rt v rm 2 v rb 255 254 . . . 128 127 . . . 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 . . . 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 . . . 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 . . . 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 step
? 11 CXA3246Q electrical characteristics measurement circuit current consumption measurement circuit v r t v i n v r b a v c c d v c c 1 d v c c 2 d g n d 3 d g n d 2 d g n d 1 a g n d c l k / e d v e e 3 5 m h z p e c l 4 v 1 . 9 5 v 2 v 5 v 5 v i c c i e e integral linearity error measurement circuit differential linearity error measurement circuit c x a 3 2 4 6 q a < b a > b c o m p a r a t o r a 8 t o a 1 a 0 b 8 t o b 1 b 0 b u f f e r c o n t r o l l e r d v m 8 8 1 0 0 0 0 0 0 t o 1 1 1 1 0 v i n + v v s 2 s 1 s 1 : o n w h e n a < b s 2 : o n w h e n a > b sampling delay measurement circuit aperture jitter measurement circuit c x a 3 2 4 6 q o s c 1 f : v a r i a b l e o s c 2 l o g i c a n a l i z e r 1 0 0 m h z 1 0 0 m h z a m p e c l b u f f e r c l k v i n 8 f r 1 0 2 4 s a m p l e s aperture jitter measurement method v i n c l k v i n c l k v r t v r m 2 v r b 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 s a m p l i n g t i m i n g f l u c t u a t i o n ( = a p e r t u r e j i t t e r ) s ( l s b ) d u d t error rate measurement circuit c o m p a r a t o r a > b p u l s e c o u n t e r c x a 3 2 4 6 q s i g n a l s o u r c e l a t c h l a t c h 1 / 8 + s i g n a l s o u r c e f c 4 1 k h z 2 v p - p s i n e w a v e f c v i n c l k c l k 8 1 6 l s b a b where s (lsb) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter taj is: taj = s / = s / ( ) ? t ? u 2 256 2 p f
? 12 CXA3246Q description of operation modes the CXA3246Q has two types of operation modes which are selected with pin 45 (select). 1. dmux mode (see application circuit 1-(1), (2) and (3).) set the select pin to vcc for this mode. in this mode, the clock frequency is divided by 2 in the ic, and the data is output after being demultiplexed by this 1/2 frequency-divided clock. the 1/2 frequency-divided clock, which has adequate setup time and hold time for the output data, is output from the clock output pin. when using the multiple CXA3246Q in dmux mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example on the next page. as a countermeasure, the CXA3246Q has a function that resets the 1/2 frequency-divided clocks. when resetting this 1/2 frequency-divided clock, the low level of the reset signal should be input to the resetn pin (pin 46 or 48). the reset signal requires the setup time (t_rs 3 1.0ns) and hold time (t_rh 3 ?.5ns) to the clock rising edge because it is synchronized with and taken in the clock. the reset period can be extended by making the low level period of the reset signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. if the reset start timing is regarded as not important, the timing where the reset signal is set from high to low is not so consequence. however, when the reset is released the timing where the reset signal is set from low to high must become significant because the timing is used to commence the 1/2 frequency-divided clock. in this case, the setup time (t_rs) is also necessary. see the timing chart for detail. (this chart shows the example of reset for 2t.) the a/d converter can operate at fc (min.) = 120msps in this mode. table 2. operation mode table select pin v cc gnd dmux mode straight mode 120msps 100msps demultiplexed output 60mbps straight output 100mbps the input clock is 1/2 frequency divided and output. 60mhz the input clock is inverted and output. 100mhz operation mode maximum conversion rate data output clock output
? 13 CXA3246Q 8 b i t c l k o u t d a t a 8 b i t c l k o u t d a t a c l k a b c l k a a a a a a a a a a a a a a a c x a 3 2 4 6 q c x a 3 2 4 6 q c l k r e s e t n c l k r e s e t n a b a a a a a a a a a a a a a a a 8 b i t c l k o u t d a t a 8 b i t c l k o u t d a t a c l k c x a 3 2 4 6 q c x a 3 2 4 6 q a b c l k r e s e t n c l k r e s e t n c l k r e s e t s i g n a l r e s e t s i g n a l ( r e s e t p e r i o d ) ( r e s e t p e r i o d ) 2. straight mode (see application circuits 1-(4), (5) and (6).) set the select pin to gnd for this mode. in this mode, data output can be obtained in accordance with the clock frequency applied to the a/d converter for applications which use the clock applied to the a/d converter as the system clock. the a/d converter can operate at fc (min.) = 100msps in this mode. digital input level and supply voltage settings the logic input level for the CXA3246Q supports ecl, pecl and ttl levels. the power supplies (dv ee 3, dgnd3) for the logic input block must be set to match the logic input (clk and reset signals) level. digital input level ecl pecl ttl ?v 0v 0v 0v +5v +5v 5v +5v +5v (1) (4) (2) (5) (3) (6) dv ee 3 dgnd3 supply voltage application circuits table 3. logic input level and power supply settings when the reset signal is not used when the reset signal is used
? 14 CXA3246Q application circuit 1 (1) dmux ecl input + 5 v ( d ) d g 5 v ( d ) a g d g + 5 v ( a ) 4 v + 5 v ( d ) d g 8 b i t d i g i t a l d a t a l a t c h 8 b i t d i g i t a l d a t a l a t c h p b d 0 t o p b d 7 8 b i t d i g i t a l d a t a p a d 0 t o p a d 7 8 b i t d i g i t a l d a t a e c l r e s e t s i g n a l e c l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 v + 5 v ( a ) 2 a g a g a g a g (2) dmux pecl input + 5 v ( d ) d g + 5 v ( d ) d g 8 b i t d i g i t a l d a t a l a t c h 8 b i t d i g i t a l d a t a l a t c h p b d 0 t o p b d 7 8 b i t d i g i t a l d a t a p a d 0 t o p a d 7 8 b i t d i g i t a l d a t a p e c l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 + 5 v ( d ) a g d g + 5 v ( a ) 4 v 2 v + 5 v ( a ) a g a g a g a g p e c l r e s e t s i g n a l 1 2 (3) dmux ttl input + 5 v ( d ) d g a g a g + 5 v ( a ) 4 v + 5 v ( d ) d g 8 b i t d i g i t a l d a t a l a t c h 8 b i t d i g i t a l d a t a l a t c h p b d 0 t o p b d 7 8 b i t d i g i t a l d a t a p a d 0 t o p a d 7 8 b i t d i g i t a l d a t a t t l r e s e t s i g n a l t t l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 v a g + 5 v ( a ) 2 + 5 v ( d ) d g a g a g 1 2
? 15 CXA3246Q (4) straight ecl input + 5 v ( d ) d g + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h p b d 0 t o p b d 7 8 - b i t d i g i t a l d a t a e c l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 e c l ? t t l d g 4 5 a g a g + 5 v ( a ) 4 v 2 v a g + 5 v ( a ) 5 v ( d ) d g a g a g (5) straight pecl input + 5 v ( d ) d g + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h p b d 0 t o p b d 7 8 - b i t d i g i t a l d a t a p e c l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 p e c l ? t t l d g 4 5 a g a g + 5 v ( a ) 4 v 2 v a g + 5 v ( a ) + 5 v ( d ) d g a g a g (6) straight ttl input + 5 v ( d ) d g + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h p b d 0 t o p b d 7 8 - b i t d i g i t a l d a t a t t l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 d g 4 5 a g a g + 5 v ( a ) 4 v 2 v a g + 5 v ( a ) + 5 v ( d ) d g a g a g
? 16 CXA3246Q application circuit 2 dmux mode ttl i/o (when a single power supply is used) c l k / e n . c . c l k / t n . c . n . c . d v c c 2 d g n d 2 p a d 0 p a d 1 p a d 2 p a d 3 c l k n / e r e s e t n / e s e l e c t r e s e t n / t i n v c l k o u t d v c c 2 d g n d 2 p b d 7 p b d 6 p b d 5 p b d 4 r e s e t / e d v e e 3 v r m 1 a g n d a v c c v i n v r m 2 a v c c v r m 3 a g n d v r t d g n d 3 v r b p a d 4 p a d 7 p a d 6 d v c c 1 d v c c 2 d g n d 2 p b d 0 p b d 1 p b d 2 p b d 3 p a d 5 d g n d 1 a a a n a l o g i n p u t a g + 5 v ( a ) 2 v 4 v t t l c l k ( l s b ) p a d 0 p a d 1 p a d 2 p a d 3 p a d 4 p a d 5 p a d 6 ( m s b ) p a d 7 ( l s b ) p b d 0 ( m s b ) p b d 7 p b d 1 p b d 2 p b d 3 p b d 4 p b d 5 p b d 6 1 f 1 0 f 1 0 f 1 f 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 a g a g d g + 5 v ( d ) a g a g 2 4 s h o r t s h o r t s h o r t t h e a n a l o g s y s t e m a n d d i g i t a l s y s t e m a t o n e p o i n t i m m e d i a t e l y u n d e r t h e a / d c o n v e r t e r . s e e t h e n o t e s o n o p e r a t i o n . i s t h e c h i p c a p a c i t o r o f 0 . 1 f . a l s o , c * i s i m p o r t a n t t o s u p p r e s s t h e n o i s e g e n e r a t e d d u r i n g t h e t t l o u t p u t c i r c u i t i s o p e r a t i n g . p l a c e c * a t t h e f i x e d p o s i t i o n b e t w e e n t h e p i n s w i t h t h e s h o r t e s t d i s t a n c e . c * c * c * application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 17 CXA3246Q dmux mode timing chart (select = v cc ) c l k v i n t t p w 0 t p w 1 n + 2 n + 3 n + 1 n + 4 n + 5 n n + 6 t d s 1 . 4 n s ( t y p . ) n 1 n 2 2 . 0 v 0 . 8 v n + 1 2 . 0 v 0 . 8 v t d o 1 ? t ? t p b d 0 t o d 7 p a d 0 t o d 7 n n + 2 n + 3 c l k o u t r e s e t n t _ r s t _ r h t _ r s t _ r h a a 2 . 0 v a a a a 0 . 8 v ( r e s e t p e r i o d ) a a 2 . 0 v a a a a 0 . 8 v t d o 2 ; 5 . 0 n s ( t y p . ) t d _ c l k ; 4 . 5 n s ( t y p . ) a a 2 . 0 v a a a a 0 . 8 v t + 0 . 5 n s ( t y p . ) 3 . 5 n s ( m i n ) 7 . 5 n s ( m a x ) 7 . 0 n s ( m a x ) 3 . 0 n s ( m i n ) ( p i n 6 ) ( p i n 1 3 ) ( p i n s 2 1 t o 2 8 ) ( p i n s 3 3 t o 4 0 ) ( p i n 4 3 ) ( p i n 4 8 )
? 18 CXA3246Q straight mode timing chart (select = gnd) t d s t t p w 1 n + 1 n 1 n n + 2 n + 3 c l k v i n t p w 0 1 . 4 n s ( t y p . ) n 2 n p b d 0 t o d 7 n + 1 n 1 n 3 2 . 0 v 0 . 8 v p a d 0 t o d 7 n 3 n 1 n n 2 n 4 2 . 0 v 0 . 8 v c l k o u t ( c l k i s i n v e r t e d a n d o u t p u t . ) 2 . 0 v 0 . 8 v t d _ c l k ; 4 . 5 n s ( t y p . ) t d o 2 ; 5 . 0 n s ( t y p . ) 7 . 0 n s ( m a x ) 3 . 0 n s ( m i n ) 3 . 5 n s ( m i n ) 7 . 5 n s ( m a x ) ( p i n 6 ) ( p i n 1 3 ) ( p i n s 2 1 t o 2 8 ) ( p i n s 3 3 t o 4 0 ) ( p i n 4 3 )
? 19 CXA3246Q notes on operation the CXA3246Q has the pecl and ttl input pins for the clock and reset input pins. when the clock is input in pecl level, inputting the reset signal in pecl level is recommended. also, when the clock is input in ttl level, inputting the reset signal in ttl is recommended. the impedance of the input signal should be properly matched to ensure the CXA3246Q's stable operation at the high speed. the power supply and grounding have a profound influence on converter performance. the power supply and grounding method are particularly important during high-speed operation. general points for caution are as follows. the ground pattern should be as large as possible. it is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. to prevent interference between agnd and dgnd and between avcc and dvcc, make sure the respective patterns are separated. to prevent a dc offset in the power supply pattern, connect the avcc and dvcc lines at one point each via a ferrite-bead filter, etc. shorting the agnd and dgnd patterns in one place immediately under the a/d converter improves a/d converter performance. be sure to turn the analog and digital power supplies on simultaneously. if not simultaneously, the ic does not operate correctly. ground the power supply pins (avcc, dvcc1, dvcc2, dv ee 3) as close to each pin as possible with a 0.1 f or larger ceramic chip capacitor. (connect the avcc pin to the agnd pattern and the dvcc1, dvcc2 and dv ee 3 pins to the dgnd pattern.) it is recommended to place the ceramic chip capacitor of 0.1 f or more, in particular, between dvcc2 and dgnd2 with the shortest distance. this has the effect to suppress the noise generated when the CXA3246Q ttl output circuit operates. the digital output wiring should be as short as possible. if the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. the analog input pin v in has an input capacitance of approximately 10pf. to drive the a/d converter with the proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. the v rt and v rb pins must have adequate by-pass to protect them from high-frequency noise. by-pass them to agnd with approximately 1 f tantal capacitor and 0.1 f chip capacitor as short as possible. if the clkn/e pin is not used, by-pass this pin to dgnd with an approximately 0.1 f capacitor. at this time, approximately dgnd3 ?1.2v voltage is generated. however, this is not recommended for use as the threshold voltage v bb because it is too weak. when the digital input level is ecl or pecl level, *** /e pins should be used and *** /t pins left open. when the digital input level is ttl, *** /t pins should be used and *** /e pins left open. the CXA3246Q ttl output high level is clamped to approximately 2.8v in the ic. this makes it possible to directly interface with the 3.5v system cmos ic. the cxa3026q has the output pins p1 ** and p2 ** . however, in the CXA3246Q, these symbols are changed as pa ** and pb ** . at this time, the p1 side of the cxa3026q is changed to the pb side for the CXA3246Q; the p2 side of the cxa3026q to the pa side for the CXA3246Q. the pipeline delay of the CXA3246Q is smaller by one clock, compared to that of cxa3026q.
? 20 CXA3246Q c u r r e n t c o n s u m p t i o n v s . a m b i e n t t e m p e r a t u r e c h a r a c t e r i s t i c s t a a m b i e n t t e m p e r a t u r e [ c ] 2 5 9 0 2 5 7 5 c u r r e n t c o n s u m p t i o n [ m a ] 9 5 1 0 0 1 0 5 1 1 0 c u r r e n t c o n s u m p t i o n v s . c o n v e r s i o n r a t e c h a r a c t e r i s t i c s f c c o n v e r s i o n r a t e [ m s p s ] 0 9 0 6 0 c u r r e n t c o n s u m p t i o n [ m a ] 9 5 1 0 0 1 0 5 1 1 0 1 2 0 d m u x m o d e c l = 5 p f f i n = 1 k h z f c l k 4 a n a l o g i n p u t c u r r e n t v s . a n a l o g i n p u t v o l t a g e c h a r a c t e r i s t i c s a n a l o g i n p u t v o l t a g e [ v ] 2 3 4 a n a l o g i n p u t c u r r e n t [ a ] 5 0 1 0 0 0 r e f e r e n c e c u r r e n t v s . a m b i e n t t e m p e r a t u r e c h a r a c t e r i s t i c s t a a m b i e n t t e m p e r a t u r e [ c ] 2 5 2 2 5 7 5 r e f e r e n c e c u r r e n t [ m a ] 3 4 v r t = 4 v v r b = 2 v example of representative characteristics
? 21 CXA3246Q s n r v s . i n p u t f r e q u e n c y r e s p o n s e i n p u t f r e q u e n c y [ m h z ] 1 2 0 5 5 0 s n r [ d b ] 3 0 4 0 5 0 3 0 3 1 0 e r r o r r a t e v s . c o n v e r s i o n r a t e c h a r a c t e r i s t i c s 1 2 0 1 4 0 1 6 0 1 0 6 1 0 7 1 0 8 1 0 9 1 0 1 0 e r r o r > 1 6 l s b f i n = 1 k h z f c l k 4 m a x i m u m c o n v e r s i o n r a t e v s . a m b i e n t t e m p e r a t u r e c h a r a c t e r i s t i c s t a a m b i e n t t e m p e r a t u r e [ c ] 2 5 1 3 0 2 5 7 5 f c m a x i m u m c o n v e r s i o n r a t e [ m s p s ] 1 5 0 1 7 0 f i n = 1 k h z f c l k 4 1 4 0 1 6 0 f c = 1 2 0 m s p s e r r o r > 1 6 l s b e r r o r r a t e : 1 0 9 t p s e r r o r r a t e [ t p s ] f c c o n v e r s i o n r a t e [ m s p s ]
? 22 CXA3246Q package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e m p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m p l a t i n g 4 2 / c o p p e r a l l o y 4 8 p i n q f p ( p l a s t i c ) 1 5 . 3 0 . 4 1 2 . 0 0 . 1 + 0 . 4 0 . 8 0 . 3 0 . 1 + 0 . 1 5 0 . 2 4 1 3 2 4 2 5 3 6 3 7 4 8 1 1 2 2 . 2 0 . 1 5 + 0 . 3 5 0 . 9 0 . 2 0 . 1 0 . 1 + 0 . 2 1 3 . 5 0 . 1 5 0 . 0 5 + 0 . 1 q f p - 4 8 p - l 0 4 q f p 0 4 8 - p - 1 2 1 2 0 . 7 g 0 . 1 5 n o t e : p a l l a d i u m p l a t i n g t h i s p r o d u c t u s e s s - p d p p f ( s o n y s p e c . - p a l l a d i u m p r e - p l a t e d l e a d f r a m e ) .

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