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1/19 december 2004 M30W0R6500T0 96 mbit (64 + 32mb, x16, multiple bank, burst, flash memories) 1.8v supply, multi-chip package features summary multi-chip package ? 1 die of 64 mbit (4mb x 16) flash memory ? 1 die of 32 mbit (2mb x 16) flash memory supply voltage ?v ddf1 = v ddf2 = v ddq = 1.7 to 2.2v ?v pp = 12v for fast program (optional) low power consumption electronic signature ? manufacturer code: 20h ? 64mb device code (top configuration): 8810h ? 32mb device code (top configuration): 8814h package ? compliant with lead-free soldering processes ? lead-free versions flash memory synchronous / asynchronous read ? synchronous burst read mode: 54mhz ? asynchronous/ synchronous page read mode ? random access: 70ns programming time ? 8s by word typical for fast factory program ? double/quadruple word program option ? enhanced factory program options architecture ? 64mbit and 32mbit flash memories ? multiple bank memory array: 4 mbit banks ? parameter blocks (top location) dual operations ? program erase in one bank while read in others ? no delay between read and write operations figure 1. packages block locking ? all blocks locked at power up ? any combination of blocks can be locked ?wp for block lock-down security ? 128 bit user programmable otp cells ? 64 bit unique device number ? one parameter block permanently lockable common flash interface (cfi) 100,000 program/erase cycles per block fbga stacked lfbga88 (za) 8 x 10mm
M30W0R6500T0 2/19 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. lfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 address inputs (a0-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chip enable (e (f1/f2) ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 output enable (g (f1/f2) ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 write protect (wp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 reset (rp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 latch enable (l ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 clock (k).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 wait (wait). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v dd(f1/f2) supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ssq ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 64mbit flash memory component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 32mbit flash memory component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/19 M30W0R6500T0 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. stacked lfbga88 8x10mm, 8x10 array, 0.8mm pitch, bottom view package outline . 16 table 8. stacked lfbga88 8x10mm - 8x10 ball array, 0.8mm pitch, package mechanical data 16 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M30W0R6500T0 4/19 summary description the M30W0R6500T0 is a 96 mbit device that is composed of two separate 64-mbit and 32-mbit flash memories, both with top boot block archi- tecture. each flash memory can be erased electrically at block level and programmed in-system on a word- by-word basis using a 1.7 to 2.2v v dd supply for the circuitry and a 1.7 to 2.2v v ddq supply for the input/output pins. an optional 12v v pp power supply is provided to speed up customer program- ming. two chip enable signals are provided to select and enable each memory. only one memory can be selected at a time. once selected the memory operates in the same way as the single memory devices m58wr064e and m58wr032e (refer to the respective datasheets). the 64 mbit flash memory features an asymmet- rical block architecture with an array of 135 blocks divided into 4 mbit banks. it has 15 banks each containing 8 main blocks of 32 kwords, and one parameter bank containing 8 parameter blocks of 4 kwords and 7 main blocks of 32 kwords. the 32 mbit flash memory features an asymmet- rical block architecture with an array of 71 blocks divided into 4 mbit banks. it has 7 banks each con- taining 8 main blocks of 32 kwords, and one pa- rameter bank containing 8 parameter blocks of 4 kwords and 7 main blocks of 32 kwords. the multiple bank architecture allows dual oper- ations, while programming or erasing in one bank, read operations are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. each block can be erased separately. erase can be suspended, in order to perform program in any other block, and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles using the supply voltage v dd . there are two enhanced factory programming commands available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec stan- dards. the M30W0R6500T0 supports synchronous burst read and asynchronous read from all blocks of each memory array; at power-up each device is configured for asynchronous read. in synchronous burst mode, data is output on each clock cycle at frequencies of up to 54mhz. each device features an automatic standby mode. when the bus is inactive during asynchro- nous read operations, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value i dd4 and the outputs are still driven. the M30W0R6500T0 features an instant, individ- ual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any acciden- tal programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power- up. each memory includes a protection register and a security block to increase the protection of a system?s design. each protection register is divid- ed into two segments: a 64 bit segment containing a unique device number written by st, and a 128 bit segment one time programmable (otp) by the user. the user programmable segments can be permanently protected. the security blocks, parameter blocks 0, can be permanently protected by the user. the memory is offered in a stacked lfbga88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) pack- age. in addition to the standard version, the packages are also available in lead-free version, in compli- ance with jedec std j-std-020b, the st eco- pack 7191395 specification, and the rohs (restriction of hazardous substances) directive. all packages are compliant with lead-free solder- ing processes. the memory is supplied with all the bits erased (set to ?1?).
5/19 M30W0R6500T0 figure 2. logic diagram table 1. signal names note: 1. a21 is not connected to the 32mbit flash memory com- ponent. ai08597 22 a0-a21 w dq0-dq15 v ddf1 M30W0R6500T0 e f1 v ss 16 g f1 rp wp v ddq v pp l k wait v ssq e f2 g f2 v ddf2 a0-a21 1 address inputs dq0-dq15 data input/outputs, command inputs e f1 chip enable of 64mb flash device e f2 chip enable of 32mb flash device g f1 output enable of 64mb flash device g f2 output enable of 32mb flash device w write enable rp reset wp write protect k clock l latch enable wait wait v ddf1 supply voltage of 64mb flash device v ddf2 supply voltage of 32mb flash device v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply nc not connected internally du do not use
M30W0R6500T0 6/19 figure 3. lfbga connections (top view through package) 8 7 6 5 4 3 2 1 c b a21 k a4 a11 d e f du du w v ss a19 a18 nc a5 a12 v ss nc nc a9 a3 a13 v pp nc a17 a10 a20 a2 a15 l wp nc a7 a14 a8 a1 a16 rp nc a6 wait dq13 a0 dq5 dq10 dq2 dq8 dq7 dq14 nc dq12 dq3 dq1 dq0 dq15 dq6 dq4 dq11 dq9 g f1 v ddq e f1 nc nc v ss v ss v ss v ss v ss v ddf1 v ddq v ss du du du du du du a g h j k ai08598 l m v ddf1 v ddf2 nc nc v ddf2 e f2 nc nc nc nc g f2 nc v ddq
7/19 M30W0R6500T0 signal descriptions see figure 2., logic diagram , and table 1., signal names , for a brief overview of the sig- nals connected to this device. certain signals are common to both internal flash memories, howev- er the chip enable, output enable and v dd volt- ages are separate for each internal memory. address inputs (a0-a21). addresses a0-a20 are common inputs for both flash memory compo- nents. a21 is an input for the 64mbit flash memo- ry component only. the address inputs select the cells in the selected memory array to access during bus read opera- tions. during bus write operations they control the commands sent to the command interface of the internal state machine. data input/output (dq0-dq15). the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a bus write operation. chip enable (e (f1/f2) ). each flash memory has its own chip enable input that activates the mem- ory control logic, input buffers, decoders and sense amplifiers. when a chip enable is at v il and reset is at v ih the corresponding flash memory is in active mode. when a chip enable is at v ih the corresponding flash memory is deselected, the outputs are high impedance and the power con- sumption is reduced to the stand-by level. only one flash memory should be enabled at a time, which means that e f1 should be high when- ever e f2 is low and that e f2 should be high when- ever e f1 is low. output enable (g (f1/f2) ). each flash memory has its own output enable that controls data out- puts during the bus read operation of the memo- ry. write enable (w ). the write enable controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. write protect (wp ). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock- down is enabled and the protection status of the locked-down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or un- locked. reset (rp ). the reset input provides a hard- ware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is re- duced to the reset supply current i dd2 . refer to table 2, dc characteristics - currents for the val- ue of i dd2. after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal op- eration. exiting reset mode the device enters asynchronous read mode, but a negative transi- tion of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic with- out any additional circuitry. it can be tied to v rph (refer to table 7., dc characteristics - voltages ). latch enable (l ). latch enable latches the ad- dress bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . latch en- able can be kept low (also at board level) when the latch enable function is not required or sup- ported. clock (k). the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configura- tion settings) when latch enable is at v il . clock is don't care during asynchronous read and in write operations. wait (wait). wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high imped- ance when chip enable is at v ih or reset is at v il . it can be configured to be active during the wait cy- cle or one clock cycle in advance. the wait signal is not gated by output enable. v dd(f1/f2) supply voltages. v ddf1 and v ddf2 provide the power supply to the internal cores of the flash memories. they are the main power supplies for all operations (read, program and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. v pp program supply voltage. v pp is both a control input and a power supply pin. the two functions are selected by the voltage range ap- plied to the pin. if v pp is kept in a low voltage range (0v to v ddq ) v pp is seen as a control input. in this case a volt- age lower than v pplk gives an absolute protection against program or erase, while v pp > v pp1 en- ables these functions (see tables 6 and 7 , dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue.
M30W0R6500T0 8/19 if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable un- til the program/erase algorithm is completed. v ss ground. v ss ground is the reference for the core supply. it must be connected to the system ground. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1f ce- ramic capacitor close to the pin (high frequen- cy, inherently low inductance capacitors should be as close as possible to the pack- age). see figure 6., ac measurement load cir- cuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents.
9/19 M30W0R6500T0 functional description the two flash memory components have sepa- rate power supplies but share the same grounds. they are distinguished by two chip enable inputs: e f1 and e f2 . recommended operating conditions do not allow more than one device to be active at a time. the most common example is simultaneous read oper- ations on both of the flash memories which would result in a data bus contention. therefore it is rec- ommended to put the one device in the high im- pedance state when reading the other. figure 4. functional block diagram ai08599 rp f wp f dq0-dq15 v ddf1 v ppf a0-a20 e f2 g f1 w f wait f k f l f v ddq v ss 32 mbit flash memory 64 mbit flash memory v ddf2 e f1 g f2 a21
M30W0R6500T0 10/19 table 2. main operating modes note: 1. x = don't care. 2. depends on g f . 3. wait signal polarity is configured using the set configur ation register command. see m58wr064e and m58wr032e datasheets for details. operation e f1 g f1 e f2 g f2 w f rp f wait f (3) dq15-dq0 flash1 read v il v il flash2 must be disabled v ih v ih flash1 data out flash1 write v il v ih v il v ih flash1 data in flash1 address latch v il x v ih v ih flash1 data out or hi-z (2) flash1 output disable v il v ih any mode in flash2 is allowed. v ih v ih flash1 hi-z flash1 standby v ih xx v ih hi-z flash1 hi-z flash1 reset x x x v il hi-z flash1 hi-z flash2 read flash1 must be disabled v il v il v ih v ih flash2 data out flash2 write v il v ih v il v ih flash2 data in flash2 address latch v il x v ih v ih flash2 data out or hi-z (2) flash2 output disable any mode in flash1 is allowed. v il v ih v ih v ih flash2 hi-z flash2 standby v ih xx v ih hi-z flash2 hi-z flash2 reset x x x v il hi-z flash2 hi-z
11/19 M30W0R6500T0 64mbit flash memory component the M30W0R6500T0 contains a 64mbit flash memory. only one flash memory can be enabled at a time. for detailed information on how to use the device, refer to the m58wr064e datasheet which is available from the internet site http:// www.st.com or from your local stmicroelectronics distributor. 32mbit flash memory component the M30W0R6500T0 contains a 32mbit flash memory. only one flash memory can be enabled at a time. for detailed information on how to use the device, refer to the m58wr032e datasheet which is available from the internet site http:// www.st.com or from your local stmicroelectronics distributor.
M30W0R6500T0 12/19 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 3. absolute maximum ratings note: 1. compliant with the jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. symbol value unit parameter min max t a ambient operating temperature ?40 85 c t bias temperature under bias ?40 125 c t stg storage temperature ?65 155 c t lead lead temperature during soldering (1) c v io input or output voltage ?0.5 v ddq +0.6 v v dd supply voltage ?0.2 2.45 v v ddq input/output supply voltage ?0.2 3.6 v v pp program voltage ?0.2 14 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
13/19 M30W0R6500T0 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 4. operating and ac measurement conditions figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit table 5. capacitance note: sampled only, not 100% tested. parameter min max units v dd supply voltage 1.7 2.2 v v ddq supply voltage 1.7 2.2 v v pp supply voltage (factory environment) 11.4 12.6 v v pp supply voltage (application environment) -0.4 v ddq +0.4 v ambient operating temperature ?40 85 c load capacitance (c l ) 30 pf input rise and fall times 5 ns input pulse voltages 0 to v ddq v input and output timing ref. voltages v ddq /2 v ai06161 v ddq 0v v ddq /2 ai06162 v ddq c l c l includes jig capacitance 16.7k ? device under test 0.1f v dd 0.1f v ddq 16.7k ? symbol parameter test condition min max unit c in input capacitance v in = 0v 12 pf c out output capacitance v out = 0v 15 pf
M30W0R6500T0 14/19 table 6. dc characteristics - currents note: 1. sampled only, not 100% tested. 2. v dd dual operation current is the sum of read and program or erase currents. 3. chip enable, e , is either e f1 or e f2 and output enable, g , is either g f1 or g f2 depending on the memory selected. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=6mhz) e = v il , g = v ih 36ma supply current synchronous read (f=40mhz) 4 word 6 13 ma 8 word 8 14 ma continuous 6 10 ma supply current synchronous read (f=54mhz) 4 word 7 16 ma 8 word 10 18 ma continuous 13 25 ma i dd2 supply current (reset) rp = v ss 0.2v 10 50 a i dd3 supply current (standby) e = v dd 0.2v 10 50 a i dd4 supply current (automatic standby) e = v il , g = v ih 10 50 a i dd5 (1) supply current (program) v pp = v pph 815ma v pp = v dd 10 20 ma supply current (erase) v pp = v pph 815ma v pp = v dd 10 20 ma i dd6 (1,2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 13 26 ma program/erase in one bank, synchronous read in another bank 16 30 ma i dd7 (1) supply current program/ erase suspended (standby) e = v dd 0.2v 10 50 a i pp1 (1) v pp supply current (program) v pp = v pph 25ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 25ma v pp = v dd 0.2 5 a i pp2 v pp supply current (read) v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a
15/19 M30W0R6500T0 table 7. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage ?0.5 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = ?100a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 1 1.8 1.95 v v pph v pp program voltage factory program, erase 11.4 12 12.6 v v pplk program or erase lockout 0.9 v v lko v dd lock voltage 1v v rph rp pin extended high voltage 3.3 v
M30W0R6500T0 16/19 package mechanical figure 7. stacked lfbga88 8x10mm, 8x10 array, 0.8mm pitch, bottom view package outline note: drawing is not to scale. table 8. stacked lfbga88 8x10mm - 8x10 ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.400 0.0551 a1 0.250 0.0098 a2 1.000 0.0394 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 ? ? 0.2205 ? ? ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 ? ? 0.2835 ? ? e2 8.800 ? ? 0.3465 ? ? e 0.800 ? ? 0.0315 ? ? fd 1.200 ? ? 0.0472 ? ? fe 1.400 ? ? 0.0551 ? ? fe1 0.600 ? ? 0.0236 ? ? sd 0.400 ? ? 0.0157 ? ? se 0.400 ? ? 0.0157 ? ? a2 a1 a bga-z42 ddd d e e b se fd e2 d1 sd ball "a1" e1 fe fe1
17/19 M30W0R6500T0 part numbering table 9. ordering information scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m30 w0 r 6 5 0 0 t 0 zaq t device type m30 = multi-chip package (multiple flash) flash 1 / flash 2 architecture w = multiple bank, burst mode flash 3 / flash 4 architecture 0 = no die operating voltage r = v ddf1 = v ddf2 = v ddq = 1.7 to 2.2v flash 1 density 6 = 64 mbit flash 2 density 5 = 32 mbit flash 3 density 0 = no die flash 4 density 0 = no die parameter blocks location t = top boot block flash memory product version 0 = 0.15m flash technology, 70ns speeds (both flash memories) package zaq = stacked lfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch option blank = standard packing t = tape & reel packing e = lead-free and rohs package, standard packing f = lead-free and rohs package, tape & reel packing
M30W0R6500T0 18/19 revision history table 10. document revision history date version revision details 23-jun-2003 1.0 first issue 03-dec-2004 2.0 lfbga88 package specification updated. table 6., dc characteristics - currents updated. e and f lead-free options added to table 9., ordering information scheme . lfbga88 package fully compatible with the st ecopack specification. document status promoted from product preview to full datasheet.
19/19 M30W0R6500T0 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. ecopack is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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