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june 2000 copyright ?2000 alliance semiconductor. all rights reserved. ? as6wa5128 7/14/00 alliance semiconductor 1 3.0v to 3.6v 512k 8 inte lliwatt? l ow-power cmos sram with one chip enable features ? as6wa5128 ? intelliwatt? active power circuitry ? industrial and commercial temperature ranges available ? organization: 524,288 words 8 bits ? 3.0v to 3.6v at 55 ns ? low power consumption: active - 144 mw at 3.6v and 55 ns ? low power consumption: standby - 72 w max at 3.6v ? 1.2v data retention ? equal access and cycle times ? easy memory expansion with cs , oe inputs ? smallest footprint packages - 36(48)-ball fbga - 32-pin tsop i (available september 2000) - 32-pin stsop i (available september 2000) - 32-pin tsop ii (forward) (available september 2000) - 32-pin tsop ii (reverse) (available september 2000) ? esd protection 3 3 3 3 2000 volts ? latch-up current 3 3 3 3 200 ma logic block diagram 36(48)-csp bga package (shading indicates no ball) 123456 aa 0 a 1 nc a 3 a 6 a 8 bi/o 5 a 2 we a 4 a 7 i/o 1 ci/o 6 nc a 5 i/o 2 dv ss v cc ev cc v ss fi/o 7 a 18 a 17 i/o 3 gi/o 8 oe cs a 16 a 15 i/o 4 ha 9 a 10 a 11 a 12 a 13 a 14 sense amp input buffer a10 a11 a12 a13 a14 a15 a16 i/o1 i/o8 oe cs we row decoder control circuit a9 a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 column decoder 512k 8 array (4,194,304) pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 v cc a15 a17 we a13 a8 a9 a11 oe a10 cs i/o5 i/o4 i/o1 i/o2 i/o3 v ss i/o8 i/o7 i/o6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 v cc a15 a17 we a13 a8 a9 a11 oe a10 cs i/o5 i/o4 i/o1 i/o2 i/o3 v ss i/o8 i/o7 i/o6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 29 28 27 26 24 23 22 21 20 19 18 17 30 25 oe a10 i/o8 i/o7 i/o6 i/o5 v ss i/o3 i/o2 i/o1 a0 a1 a2 a3 cs i/o4 a11 a9 a13 we a17 a15 a18 a16 a14 a12 a7 a6 a5 a4 a8 v cc 32-pin tsopii (forward) 32-pin tsopii (reverse) 32-pin tsopii 32-pin stsopi (forward) selection guide product v cc range speed (ns) power dissipation min (v) typ 2 (v) max (v) operating (i cc1 )standby (i sb2 ) max (ma) max ( m m m m a) as6wa5128 3.0 3.3 3.6 55 2 20
? 2 alliance semiconductor 7/14/00 as6wa5128 functional description the as6wa5128 is a low-power cmos 4,194,304-bit static random access memory (sram) device organized as 524,288 words 8 bits. it is designed for memory applications where slow data access, low power, and simple interfacing are d esired. equal address access and cycle times (t aa , t rc , t wc ) of 55 ns are ideal for low-power applications. active high and low chip selects (cs ) permit easy memory expansion with multiple-bank memory systems. when cs is high, the device enters standby mode: the as6wa5128 is g uaranteed not to exceed 72 m w power consumption at 3.6v and 55ns. the device also returns data when v cc is reduced to 1.5v for even lower power consumption. a write cycle is accomplished by asserting write enable (we ) and chip select (cs ) low. data on the input pins i/o1Ci/o8 is written on the rising edge of we (write cycle 1) or cs (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable ( oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ), chip select (cs ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip select or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. all chip inputs and outputs are cmos-compatible, and operation is from a single 3.0 to 3.6v supply. the device is available in the jedec standard 32-pin tsop i, 32-pin stsop i, 400-ml tsop ii, and 36(48)-ball fbga packages. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = dont care, l = low, h = high. parameter device symbol min max unit volt age on v cc relative to v ss v tin C0.5 v cc + 0.5 v voltage on any i/o pin relative to gnd v ti/o C0.5 v power dissipation p d C1.0w storage temperature (plastic) t stg C65 +150 c temperature with v cc applied t bias C55 +125 c dc output current (low) i out C20ma cs we oe supply current i/o1Ci/o8 mode hxxi sb high z standby (i sb ) lxxi sb high z standby (i sb ) lhhi cc high z output disable (i cc ) lhli cc d out read (i cc ) llxi cc d in write (i cc )
? as6wa5128 7/14/00 alliance semiconductor 3 recommended operating condition (over the operating range) capacitance (f = 1 mhz, t a = room temperature, v cc = nominal) 2 parameter description test conditions min max unit v oh output high voltage i oh = C2.1ma v cc = 3.0v 2.4 v v ol output low voltage i ol = 2.1ma v cc = 3.0v 0.4 v v ih input high voltage v cc = 3.0v 2.2 v cc + 0.5 v v il input low voltage v cc = 3.0v C0.5 0.8 v i ix input load current gnd < v in < v cc C1 +1 m a i oz output load current gnd < v o < v cc ; outputs high z C1 +1 m a i cc v cc operating supply current cs = v il , i out = 0ma, f = 0, v in = v il or v ih v cc = 3.6v 2 ma i cc1 @ 1mhz average v cc operating supply current at 1 mhz cs < 0.2v, v in < 0.2v, or v in > v cc C 0.2v, f = 1 ms v cc = 3.6v 2 ma i cc2 average v cc operating supply current cs 1 v il , v in = v il or v ih , f = f max v cc = 3.6v (55 ns) 40 ma i sb cs power down current; ttl inputs cs > v ih , other inputs = 0v C v cc v cc = 3.6v 100 m a i sb1 cs power down current; cmos inputs cs > v cc C 0.2v, other inputs = 0v C v cc , f = f max v cc = 3.6v 20 m a i sbdr data retention cs > v cc C 0.1v, f = 0 v cc = 1.2v 2 m a parameter symbol signals test conditions max unit input capacitance c in a, cs , we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? 4 alliance semiconductor 7/14/00 as6wa5128 read cycle (over the operating range) 3,9 shaded areas indicate preliminary information. key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (cs , oe controlled) 3,6,8,9 parameter symbol min max unit notes read cycle time t rc 55 C ns address access time t aa C55ns3 chip select (cs ) access time t acs C55ns3 output enable (oe ) access time t oe C25ns output hold from address change t oh 10 C ns 5 cs low to output in low z t clz 10 C ns 4, 5 cs high to output in high z t chz 020ns4, 5 oe low to output in low z t olz 5 C ns 4, 5 oe high to output in high z t ohz 020ns4, 5 power up time t pu 0 C ns 4, 5 power down time t pd C55ns4, 5 undefined/dont care falling input rising input t oh t aa t rc t oh d out address data valid previous data valid current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% t ohz data valid t rc1 cs
? as6wa5128 7/14/00 alliance semiconductor 5 write cycle (over the operating range) 11 shaded aread indicate preliminary information. write waveform 1 (we controlled) 10,11 write waveform 2 (cs controlled) 10,11 parameter symbol min max unit notes write cycle time t wc 55 C ns chip select to write end t cw 40 C ns 12 address setup to write end t aw 40 C ns address setup time t as 0Cns12 write pulse width t wp 35 C ns address hold from end of write t ah 0Cns data valid to write end t dw 25 C ns data hold time t dh 0 C ns 4, 5 write enable to output in high z t wz 020ns4, 5 output active from write end t ow 5 C ns 4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t aw address cs we d out t cw t wp t dw t dh t ah t wz t wc t as data valid d in
? 6 alliance semiconductor 7/14/00 as6wa5128 data retention characteristics (over the operating range) 13,5 data retention waveform ac test loads and waveforms notes 1during v cc power-up, a pull-up resistor to v cc on cs is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7cs and oe are low for read cy cle. 8 address valid prior to or coincident with cs transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 cs or we must be high during address transitions. either cs or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 n/a. 13 1.2v data retention applies to commercial and industrial temperature range operations. 14 c = 30pf, except at high z and low z parameters, where c = 5pf. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 1.2v cs 3 v cc C 0.1v or v in 3 v cc C 0.1v or v in 0.1v 1.2v 3.6 v data retention current i ccdr C2ma chip deselect to data retention time t cdr 0C operation recovery time t r t rc Cns parameters v cc = 3.0v v cc = 2.5v v cc = 2.0v unit r1 1105 16670 15294 ohms r2 1550 15380 11300 ohms r th 645 8000 6500 ohms v th 1.75v 1.2v 0.85v volts v cc cs t r t cdr data retention mode v cc v cc v dr 3 1.2v v ih v ih v dr v cc r1 r2 output 30 pf including jig and scope (a) v cc r1 r2 output 5 pf all input pulses (b) 10% 90% 10% 90% gnd v cc typ < 5 ns (c) thevenin equivalent: output r th v including jig and scope
? as6wa5128 7/14/00 alliance semiconductor 7 typical dc and ac characteristics v cc = v cc typ supply voltage (v) 1.7 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current supply voltage (v) 0.0 0.25 0.5 0.75 1.0 normalized t aa normalized access time vs. supply voltage vs. supply voltage ambient temperature (c) C 55 105 25 0.5 1.0 0.0 1.5 2.0 2.5 normalized i sb2 normalized standby current vs. ambient temperature supply voltage (v) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i sb normalized standby current vs. supply voltage i sb2 supply voltage (v) 0.10 0.50 1.0 1.5 normalized i cc normalized i cc vs. cycle time 2.2 2.7 3.2 3.7 1.7 2.2 2.7 3.2 3.7 t a = 25 c 3.0 C 0.5 v in = v cc typ 1 5 10 15 11.9 2.8 3.7 v in = v cc typ t a = 25 c v in = 3.6v t a = 25 c v in = v cc typ t a = 25 c
? 8 alliance semiconductor 7/14/00 as6wa5128 package diagrams and dimensions 0.45 ~0.75 0.018 ~0.030 20.00+0.20 0.787+0.008 0.20 0.008 +0.10 -0.05 +0.004 -0.002 #1 #17 #16 #32 0.50 0.0197 8.40 0.331 max 8.00 0.315 0.25 0.010 () 0.05 0.002 min 1.00+0.10 0.039+0.004 1.20 max 0.047 1.10 max 0.004 max 0.15 0.006 +0.10 -0.05 +0.004 -0.002 0.50 0.020 ( ) 0~8o 18.40 0.528 +0.10 +0.004 0.25 0.010 typ 0.45 ~0.75 0.018 ~0.030 13.40 0.528 0.20 0.008 +0.10 -0.05 +0.004 -0.002 #1 #17 #16 #32 0.50 0.0197 8.40 0.331 max 8.00 0.315 0.25 0.010 () 0.05 0.002 min 1.00+0.10 0.039+0.004 1.20 max 0.047 1.10 max 0.004 max 0.15 0.006 +0.10 -0.05 +0.004 -0.002 0.50 0.020 ( ) 0~8o 11.80 0.465 +0.10 +0.004 0.25 0.010 typ +0.10 +0.008 32-pin thin small outline package type i (forward) (t) 32-pin thin small outline package type i (forward) (t)
? as6wa5128 7/14/00 alliance semiconductor 9 11.76+0.20 0.463+0.008 #1 #17 #16 #32 21.35 0.841 max 20.95 0.825 0.95 0.037 ) ( 0.05 0.002 min 1.00+0.10 0.039+0.004 1.20 max 0.047 1.10 max 0.004 max 0~8o 0.25 0.010 () 0.50 0.020 () 0.15 0.006 0.45~0.75 0.018~0.030 +0.10 -0.05 +0.004 -0.002 10.16 0.400 +0.10 +0.004 0.40 0.016 +0.10 +0.004 1.27 0.050 11.76+0.20 0.463+0.008 #32 #16 #17 #1 21.35 0.841 max 20.95 0.825 0.95 0.037 ) ( 0.05 0.002 min 1.00+0.10 0.039+0.004 1.20 max 0.047 1.10 max 0.004 max 0~8o 0.25 0.010 () 0.50 0.020 () 0.15 0.006 0.45~0.75 0.018~0.030 +0.10 -0.05 +0.004 -0.002 10.16 0.400 +0.10 +0.004 0.40 0.016 +0.10 +0.004 1.27 0.050 32-pin thin small outline package type ii (forward) (he) 32-pin thin small outline package type ii (reverse) (hr)
? 10 alliance semiconductor 7/14/00 as6wa5128 minimum typical maximum a C 0.75 C b 6.907.007.10 b1 C 3.75 C c 10.90 11.00 11.10 c1 C 5.25 C d 0.300.350.40 eCC1.20 e1 C 0.68 C e2 0.22 0.25 0.27 yCC0.08 notes 1. bump counts: 36(48) (8 row 6 column). 2. pitch: (x,y) = 0.75 mm 0.75 mm (typ). 3. units: millimeters. 4. all tolerance are 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.08 (max). 36(48)-ball fbga bottom view top view 1 2 3 4 5 6 a b c d e f g h a b1 a1 c1 ball #a1 ball #a1 index sram die c elastomer b side view detail view e2 e e1 d die die e e2 a y 0.3/typ
copyright ? 2000. alliance semiconductor corporation (alliance)'s three-point logo, our name, and intelliwatt? are trademarks o r registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this web site and its products at any time without notice. alliance assumes no responsibility for any errors that ma y appear in this web site. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as expressly agreed to in alliance's terms and conditions of sale (available from a l liance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify all iance against all claim s arising from such use. ? as6wa5128 7/14/00 alliance semiconductor 11 ordering codes part numbering system speed (ns) ordering code package type operating range 55 as6wa5128-tc 32-pin 820 tsop i commercial as6wa5128-stc 32-pin 813.4 tsop i as6wa5128-hfc 32-pin tsop ii (forward) as6wa5128-hrc 32-pin tsop ii (reverse) as6wa5128-bc 48-ball fine pitch bga 55 as6wa5128-ti 32-pin 820 tsop i industrial AS6WA5128-STI 32-pin 813.4 tsop i as6wa5128-hfi 32-pin tsop ii (forward) as6wa5128-hri 32-pin tsop ii (reverse) as6wa5128-bi 48-ball fine pitch bga as6wa 5128 t, st, hf, hr, b c, i sram intelliwatt? prefix device number package: t: tsop i st: stsopi hf: tsop2 forward hr: tsop2 reverse b: csp bga temperature range: c: commercial: 0 c to 70 c i: industrial: C 40c to 85 c

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