View MD56V62320_858969.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor MD56V62320 1/29 description the MD56V62320 is a 4-bank 524,288-word 32-bit synchronous dynamic ram, fabricated in oki's cmos silicon-gate process technology. the device operates at 3.3 v. the inputs and outputs are lvttl compatible. features ? silicon gate, quadruple polysilicon cmos, 1-transistor memory cell ? 4-bank 524,288-word 32-bit configuration ? 3.3 v power supply, 0.3 v tolerance ? input : lvttl compatible ? output : lvttl compatible ? refresh : 4096 cycles/64 ms ? programmable data transfer mode C cas latency (2, 3) C burst length (2, 4, 8) C data scramble (sequential, interleave) ? cbr auto-refresh, self-refresh capability ? package: 86-pin 400 mil plastic tsop (type ii) (tsopii86-p-400-0.50-k) (product : MD56V62320-xxta) xx indicates speed rank. product family ? semiconductor MD56V62320 4-bank 524,288-word 32-bit synchronous dynamic ram preliminary family access time (max.) MD56V62320-10 max. frequency 100 mhz 9 ns t ac2 9 ns t ac3 this version: apr. 1999 e2g1057-29-41
? semiconductor MD56V62320 2/29 pin configuration (top view) v cc 1 v ss dq1 2 v cc q 3 dq2 4 dq3 5 v ss q 6 dq4 7 dq5 8 v cc q 9 dq6 10 dq7 11 v ss q 12 dq8 13 nc 14 v cc 15 dqm0 16 we 17 cas 18 ras 19 cs 20 nc 21 ba0 22 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 dq16 v ss q dq15 dq14 v cc q dq13 dq12 v ss q dq11 dq10 v cc q dq9 nc v ss dqm1 nc nc clk cke a9 a8 ba1 23 a10 24 a0 25 64 63 62 a7 a6 a5 86-pin plastic tsop ( ii ) ( k type ) a1 26 a2 27 61 60 a4 a3 dqm2 28 dqm3 v cc 29 nc 30 dq17 31 v ss q 32 dq18 33 dq19 34 v cc q 35 dq20 36 dq21 37 v ss q 38 dq22 39 dq23 40 v cc q 41 dq24 42 v cc 43 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v ss nc dq32 v cc q dq31 dq30 v ss q dq29 dq28 v cc q dq27 dq26 v ss q dq25 v ss pin name function system clock clock enable address row address strobe column address strobe write enable data input/output mask data input/output power supply (3.3 v) ground (0 v) data output power supply (3.3 v) data output ground (0 v) clk cke a0 - a10 ras cas we dqm0 - 3 dqi v cc v ss v cc q v ss q chip select cs bank select address ba0, ba1 no connection nc pin name function note: the same power supply voltage must be provided to every v cc pin and v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin.
? semiconductor MD56V62320 3/29 pin description clk fetches all inputs at the "h" edge. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be masked so that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. row & column multiplexed. row address: ra0 - ra10 column address: ca0 - ca7 ras cas we functionality depends on the combination. for details, see the function truth table. dqm0 - 3 dqm0 controls dq1 - 8. dqm1 controls dq9 - 16. dqm2 controls dq17 - 24. dqm3 controls dq25 - 32. address dqi data inputs/outputs are multiplexed on the same pin. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke, dqm0 - 3. bank access pins. these pins are dedicated to select one of 4 banks. ba0, ba1
? semiconductor MD56V62320 4/29 block diagram clock buffer clk cke command buffers cs ras cas we dqm0 - dqm3 address buffers command decoding logic mode register bank d row decoders word drivers memory cells column decoders sense amplifiers bank a bank b bank c dq1 - dq32 input buffers input data register output buffers output data register latency & burst controller control logic row address latches & refresh counter column address latches & counter a0 - a10 ba0, ba1
? semiconductor MD56V62320 5/29 electrical characteristics absolute maximum ratings (voltages referenced to v ss ) parameter unit symbol voltage on any pin relative to v ss rating v in , v out C0.5 to v cc + 0.5 v v cc supply voltage v cc , v cc q C0.5 to 4.6 v storage temperature t stg C55 to 150 c power dissipation p d * 1w short circuit current i os 50 ma operating temperature t opr 0 to 70 c *: ta = 25 c (voltages referenced to v ss = 0 v) parameter unit symbol power supply voltage v cc , v cc q input high voltage v ih input low voltage v il min. 3.0 2.0 C0.3 v v v typ. 3.3 max. 3.6 v cc + 0.3 0.8 recommended operating conditions capacitance (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) parameter unit symbol input capacitance (clk, cke, cs , ras , cas , we , dqm0 - 3) input/output capacitance (dq1 - dq32) c in2 c out 2 2 pf pf input capacitance (addr) c in1 2pf 5 5 7 min. max.
? semiconductor MD56V62320 6/29 dc characteristics parameter condition version unit note cke others -10 symbol output high voltage output low voltage input leakage current 2.4 C 10 v v m a i oh = C2 ma i ol = 2 ma v oh v ol i li 0.4 10 output leakage current C 10 m a i lo 10 min. max. average power supply current (operating) ma 1, 2 cke 3 v ih t cc = min t rc = min no burst i cc 1 170 power supply current (stand by) ma 3 cke 3 v ih t cc = min cs 3 v ih i cc 2 40 average power supply current (clock suspension) ma 2 cke v il t cc = min i cc 3s 6 power supply current (burst) ma 1, 2 cke 3 v ih t cc = min i cc 4 290 power supply current (auto-refresh) ma 2 cke 3 v ih t cc = min t rc = min i cc 5 190 average power supply current (self-refresh) ma cke v il t cc = min i cc 6 2 average power supply current (power down) ma cke v il t cc = min i cc 7 2 average power supply current (active stand by) ma 3 cke 3 v ih t cc = min cs 3 v ih i cc 3 100 notes: 1. measured with outputs open. 2. the address and data can be changed once or left unchanged during one cycle. 3. the address and data can be changed once or left unchanged during two cycles.
? semiconductor MD56V62320 7/29 mode set address keys a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 cas latency burst type burst length 000 reserved 0 sequential 000 reserved reserved 001 reserved 1 interleave 001 2 2 010 2 010 4 4 011 3 011 8 8 100 reserved 100 reserved reserved 101 reserved 101 reserved reserved 110 reserved 110 reserved reserved 111 reserved 111 reserved reserved note: a7, a8, a9, a10, ba1 and ba0 should stay "l" during mode set cycle. power on sequence 1. with inputs in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 m s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply a cbr auto-refresh eight or more times. 5. enter the mode register setting command.
? semiconductor MD56V62320 8/29 ac characteristics clock "h" pulse time clock "l" pulse time input setup time input hold time output low impedance time from clock output high impedance time from clock output hold from clock ras cycle time ras precharge time ras active time write recovery time refresh time power-down exit set-up time ras to cas delay time t ch t cl t si t hi t rc t rp t ras t wr t ref t pde t rcd t olz t ohz 3 3 3 1 90 30 60 15 t si + 1 clk 30 3 10 5 64 8 ns ns ns ns ns ns ns ns ms ns ns ns ns ras to ras bank active delay time t rrd 20 ns input level transition time t t 3ns t oh 3 ns 3 cas to cas delay time (min.) l ccd 1 cycle 1 clock disable time from cke l cke cycle 2 data output high impedance time from dqm l doz cycle 0 data input mask time from dqm l dod cycle 0 data input time from write command l dwd cycle data output high impedance time from precharge command 3 active command input time from mode register set command input (min.) l mrd cycle 2 l roh cycle access time from clock cl = 3 cl = 2 9 9 ns ns 3, 4 3, 4 parameter MD56V62320-10 clock cycles time cl = 3 cl = 2 symbol t cc min. 10 15 max. unit ns ns note note 1, 2 2 write command input time from output l owd cycle t ac
? semiconductor MD56V62320 9/29 notes : 1. ac measurements assume that t t = 1 ns. 2. the reference level for timing of input signals is 1.4 v. 3. output load. output z = 50 w 50 pf 50 w 1.4 v 4. the access time is defined at 1.4 v. 5. if t t is longer than 1 ns, then the reference level for timing of input signals is v ih and v il .
? semiconductor MD56V62320 10/29 timing waveform read & write cycle (same bank) @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we ra ca0 qa0 t oh t rc cs t rp t rcd ba1 a10 rb cb0 qa1 qa2 qa3 db0 db1 db2 db3 t ohz row active read command prechar g e command row active write command precharge command ra rb t wr t ac ba0 dqm0 - 3
? semiconductor MD56V62320 11/29 single bit read-write-read cycle (same page) @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we ra ca qa cs ba1 a10 cb cc db qc row active read command read command write command precharge command t ch t cc t cl t si t hi t si t hi t si l ccd t hi t si t si t hi ra t hi t si t ac t olz t ohz t hi t si t oh high l owd ba0 dqm0 - 3
? semiconductor MD56V62320 12/29 ba1 0 operation after the end of burst, bank a holds the idle status. ba0 0 0 0 after the end of burst, bank b holds the idle status. 1 1 after the end of burst, bank a is precharged automatically. after the end of burst, bank b is precharged automatically. 0 0 a10 0 0 1 1 1 after the end of burst, bank c holds the idle status. 0 0 1 after the end of burst, bank d holds the idle status. 1 1 after the end of burst, bank c is precharged automatically. after the end of burst, bank d is precharged automatically. 1 1 0 0 1 1 * notes: 1. when cs is set "high" at a clock transition from "low" to "high", all inputs except cke, dqm0 - 3 are invalid. 2. when issuing an active, read or write command, the bank is selected by ba0 and ba1. 3. the auto precharge function is enabled or disabled by the a10 input when the read or write command is issued. ba0 0 1 active, read or write bank a bank b ba1 0 0 0 1 bank c bank d 1 1 4. when issuing a precharge command, the bank to be precharged is selected by the a10, ba1 and ba0 inputs. ba1 0 0 1 ba0 0 1 0 operation bank a is precharged. bank b is precharged. bank c is precharged. a10 0 0 0 1 x 1 x bank d is precharged. all banks are precharged. 0 1 5. the input data and the write command are latched by the same clock (write latency = 0). 6. the output is forced to high impedance by (1 clk + t ohz ) after dqm0 - 3 entry.
? semiconductor MD56V62320 13/29 page read & write cycle (same bank) @ cas latency = 2, burst length = 4 * notes: 1. to write data before a burst read ends, dqm0 - 3 should be asserted three cycles prior to the write command, to avoid bus contention. 2. to assert row precharge before a burst write ends, wait t wr after the last write data input. input data during the precharge input cycle will be masked internally. clk 012345678910111213141516171819 cke ras cas addr dq we ca0 cb0 cs ba1 a10 cc0 cd0 qa0 read command write command prechar g e command t wr bank a active qa1 qb0 qb1 dc0 dc1 dd0 read command write command high l ccd *note2 *note1 ba0 l owd dqm0 - 3
? semiconductor MD56V62320 14/29 read & write cycle with auto precharge @ burst length = 4 clk 012345678910111213141516171819 cke ras cas addr we dq raa cs ba1 a10 rdb caa row active (a-bank) row active ( d-bank ) a-bank precharge start d bank write with auto precharge cdb cas latency = 2 dq cas latency = 3 qaa0 qaa1 qaa2 qaa3 ddb0 ddb1 ddb2 ddb3 qaa0 qaa1 qaa2 qaa3 ddb0 ddb1 ddb2 ddb3 a bank read with auto precharge d bank precharge start point high t rrd a-bank precharge start t wr raa rdb ba0 dqm0 - 3 dqm0 - 3
? semiconductor MD56V62320 15/29 bank interleave random row read cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we raa caa cs ba1 a10 qaa0 row active (a-bank) row active ( a-bank ) read command (c-bank) precharge command (c-bank) t rc raa t rrd rcb ccb rac cac rcb rac qaa1 qaa2 qaa3 qcb0 qcb1 qcb2 qcb3 qac0 qac1 qac2 read command (a-bank) row active (c-bank) precharge command ( a-bank ) read command (a-bank) high qac3 ba0 dqm0 - 3
? semiconductor MD56V62320 16/29 bank interleave random row write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we raa caa cs ba1 a10 daa0 row active (a-bank) precharge command (a-bank) raa rbb cbb rac cac daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 write command (a-bank) row active (b-bank) rac rbb write command (b-bank) precharge command (a-bank) row active (a-bank) precharge command ( b-bank ) write command (a-bank) high ba0 dqm0 - 3
? semiconductor MD56V62320 17/29 clk 012345678910111213141516171819 cke ras cas addr dq we raa caa cs ba1 a10 qaa0 row active (a-bank) read command ( a-bank ) raa rcb ccb cac ccd qaa1 qaa2 qaa3 qcb0 qcb1 qcb2 qcb3 qae0 qae1 read command ( a-bank ) row active (c-bank) rca read command ( c-bank ) read command ( a-bank ) read command (c-bank) cae qac0 qac1 qcd0 qcd1 precharge command (a-bank) high l roh *note1 ba0 dqm0 - 3 bank interleave page read cycle @ cas latency = 2, burst length = 4 *note: 1. cs is ignored when ras , cas and we are high at the same cycle.
? semiconductor MD56V62320 18/29 bank interleave page write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we rba cba cs ba1 a10 dba0 row active (b-bank) precharge command ( all banks ) rba rdb cdb cbc cdd dba1 dba2 dba3 ddb0 ddb1 ddb2 ddb3 dbc0 dbc1 write command ( b-bank ) row active (d-bank) rdb write command ( d-bank ) write command ( b-bank ) write command (d-bank) ddd0 high ba0 dqm0 - 3
? semiconductor MD56V62320 19/29 bank interleave random row read/write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we raa caa cs ba1 a10 qaa0 row active (a-bank) raa rcb ccb rac qaa1 qaa2 qaa3 read command ( a-bank ) row active (c-bank) precharge command ( a-bank ) cac rac rcb dcb0 dcb1 dcb2 dcb3 qac0 qac1 qac2 qac3 write command (c-bank) row active ( a-bank ) read command (a-bank) high ba0 dqm0 - 3
? semiconductor MD56V62320 20/29 bank interleave page read/write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we caa0 qac3 cs cdb0 cac0 ba1 a10 high read command ( a-bank ) write command ( d-bank ) read command ( a-bank ) ddb3 qaa3 qaa2 qaa1 qaa0 ddb2 ddb1 ddb0 qac2 qac1 qac0 ba0 dqm0 - 3
? semiconductor MD56V62320 21/29 clock suspension & dqm operation cycle @ cas latency = 2, burst length = 4 clock suspension clk 012345678910111213141516171819 cke ras cas addr dq1 - 8 cs ca cb a10 row active qb1 qb0 read command read command read dqm write command clock suspension write dqm cc dc2 qa1 qa2 *note1 ? *note1 *note3 ? ba1 ba0 ra qa3 dc1 dc3 qa1 qa0 qa0 t ohz qb1 qb0 dc2 qa2 qa3 dc3 dc0 qb1 qb0 *note2 qa3 dc3 dc0 dc1 qa1 qa0 qa2 qb1 qb0 dc0 dc1 dc2 we dqm0 dqm1 dqm2 dqm3 read dqm dq25 - 32 dq17 - 24 dq9 - 16 *note4 *note4 ra *notes: 1. when cke is deactivated, the next clock will be ignored. 2. when dqm0 - 3 are asserted, the read data after two clock cycles will be masked. 3. when dqm0 - 3 are asserted, the write data in the same clock cycles will be masked. 4. when dqm0 is set high, the input/output data of dq1 - dq8 will be masked. when dqm1 is set high, the input/output data of dq9 - dq16 will be masked. when dqm2 is set high, the input/output data of dq17 - dq24 will be masked. when dqm3 is set high, the input/output data of dq25 - dq32 will be masked.
? semiconductor MD56V62320 22/29 read interruption by precharge command @ burst length = 8 *note: 1. if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. we clk 012345678910111213141516171819 cke ras cas addr dq cs ca ba1 a10 high row active read command prechar g e command qa3 qa2 qa1 qa0 dq cas latency = 3 cas latency = 2 qa4 qa3 qa2 qa1 qa0 qa4 ra qa5 *note1 *note1 ra ba0 dqm0 - 3 dqm0 - 3
? semiconductor MD56V62320 23/29 power down mode @ cas latency = 2, burst length = 4 *notes: 1. when all banks are in precharge state, and if cke is set low, then the MD56V62320 enters power-down mode and maintains the mode while cke is low. 2. to release the circuit from power-down mode, cke has to be set high for longer than t pde (t si + 1 clk). clock suspention exit clk 012345678910111213141516171819 cke ras cas addr dq we cs ba1 a10 qa2 qa1 qa0 t si t pde t si t si ra ca row active power-down entry power-down exit clock suspention entr y read command precharge command *note1 *note2 ra ba0 dqm0 - 3
? semiconductor MD56V62320 24/29 self refresh cycle clk 012 cke ras cas addr dq we cs ba1 a10 t si hi - z hi - z self refresh entr y self refresh exit row active ra ra bs ba0 bs t rc dqm0 - 3
? semiconductor MD56V62320 25/29 mode register set cycle clk 012345 012345678910 cke ras cas addr dq we cs key ra mrs high high hi - z hi - z new command auto refresh t rc 6 11 12 l mrd auto refresh dqm0 - 3 auto refresh cycle
? semiconductor MD56V62320 26/29 function truth table (table 1) (1/2) current state 1 cs ras cas we ba addr hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllhx x hxxxx x lhhxx x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 lhllx x l l h x ba ra, a10 lllxx x idle row active read write read with auto precharge hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 lhllx x l l h x ba ra, a10 lllxx x write with auto precharge action nop nop illegal 2 illegal 2 row active nop 4 auto-refresh or self-refresh 5 nop nop read write illegal 2 precharge illegal nop (continue row active after burst ends) nop (continue row active after burst ends) reserved term burst, start new burst read term burst, start new burst write illegal 2 term burst, execute row precharge illegal nop (continue row active after burst ends) nop (continue row active after burst ends) reserved (term burst) --> row active term burst, start new burst read term burst, start new burst write illegal 2 term burst, execute row precharge illegal nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal 2 illegal 2 illegal illegal 2 illegal nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal 2 illegal 2 illegal illegal 2 lllxx x illegal llll op code mode register write l
? semiconductor MD56V62320 27/29 function truth table (table 1) (2/2) notes: 1. all inputs are enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of l ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle. current state 1 cs ras cas we ba addr hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhxx x lhlxx x llhxx x lllxx x hxxxx x lhhhx x lhhlx x lhlxx x llxxx x precharge write recovery row active refresh mode register access action nop --> idle after t rp nop --> idle after t rp illegal 2 illegal 2 illegal 2 nop 4 illegal nop nop illegal 2 illegal 2 illegal 2 illegal 2 illegal nop --> row active after t rcd nop --> row active after t rcd illegal 2 illegal 2 illegal 2 illegal 2 illegal nop --> idle after t rc nop --> idle after t rc illegal illegal illegal nop nop illegal illegal illegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge
? semiconductor MD56V62320 28/29 current state (n) cken-1 cs ras cas we addr h xxxx x l hxxx x l lhhh x llhhlx llhlxx lllxxx l xxxx x h xxxx x l hxxx x l lhhh x llhhlx llhlxx lllxxx l xxxx x h xxxx x h hxxx x h lhhh x hlhhlx hlhlxx hllhlx h lllh x h xxxx x h xxxx x l xxxx x l xxxx x self refresh power down all banks idle 6 any state other action invalid exit self refresh --> abi exit self refresh --> abi illegal illegal illegal nop (maintain self refresh) invalid exit power down --> abi exit power down --> abi illegal illegal illegal 6 nop (continue power down mode) refer to table 1 enter power down enter power down illegal illegal illegal enter self refresh refer to operations in table 1 begin clock suspend next cycle enable clock of next cycle continue clock suspension cken x h h h h h l x h h h h h l h l l l l l l h l h l (abi) than listed above h llll x illegal l l xxxx x nop l function truth table for cke (table 2) note: 6. power-down and self refresh can be entered only when all the banks are in an idle state.
? semiconductor MD56V62320 29/29 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop ii 86-p-400-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more typ. mirror finish preliminary
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-11

▲Up To Search▲

Price & Availability of MD56V62320

	To Download MD56V62320 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .