? 1/10 USBLC6-4SC6 very low capacitance esd protection rev. 1 sot23-6l december 2004 main applications usb2.0 ports up to 480mb/s (high speed) backwards compatible with usb1.1 low and full speed ethernet port: 10/100mb/s sim card protection video line protection portable electronics description the USBLC6-4SC6 is a monolithic application specific discrete dedicated to esd protection of high speed interfaces, such as usb2.0, ethernet links and video lines. its very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringent characterized esd strikes. features 4 data lines protection protects v bus at both 5v (low and full speed) and 3.3v (high speed) operations very low capacitance: 3pf typ. sot23-6l package benefits very low capacitance between lines to gnd for optimized data integrity and speed low pcb space consuming, 9mm2 maximum foot print enhanced esd protection iec61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level esd protection of v bus . allows esd current flowing to ground when esd event occurs on data line high reliability offered by monolithic integration low leakage current for longer operation of battery powered devices fast response time consistent d+ / d- signal balance: - best capacitance matching tolerance i/o to gnd = 0.015pf - compliant with usb 2.0 requirements < 1pf table 1: order code part number marking USBLC6-4SC6 ul46 asd? figure 1: functional diagram 1 1 6 2 5 3 4 i/o1 i/o4 gnd v bus i/o2 i/o3 tm: asd is a trademark of stmicroelectronics. complies with the following standards: iec61000-4-2 level4: 15kv (air discharge) 8kv (contact discharge)
USBLC6-4SC6 2/10 table 2: absolute ratings table 3: electrical characteristics ( tamb = 25c) symbol parameter value unit v pp peak pulse voltage at device level: iec61000-4-2 air discharge iec61000-4-2 contact discharge mil std883c-method 3015-6 15 15 25 kv t stg storage temperature range -55 to +150 c t j maximum junction temperature 125 c t l lead solder temperature (10 seconds duration) 260 c symbol parameter test conditions value unit min. typ. max. v rm reverse stand-off voltage 5v i rm leakage current v rm = 5v 2a v br breakdown voltage between v bus and gnd i r = 1ma 6v v f forward voltage i r = 10ma 0.86 v v cl clamping voltage i pp = 1a, t p = 8/20s any i/o pin to gnd 12 v i pp = 5a, t p = 8/20s any i/o pin to gnd 17 v c i/o-gnd capacitance between i/o and gnd v r = 1.65v 3 4 pf ? c i/o-gnd 0.015 c i/o-i/o capacitance between i/o v r = 1.65v 1.85 2.7 pf ? c i/o-i/o 0.04
USBLC6-4SC6 3/10 figure 2: capacitance versus voltage (typical values) figure 3: line capacitance versus frequency (typical values) figure 4: relative variation of leakage current versus junction temperature (typical values) figure 5: frequency response 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 c(pf) f=1mhz v =30mv t =25c osc rms j c =i/o-i/o j c =i/o-gnd o data line voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 1000 c(pf) v =30mv t =25c osc rms j v =1.65v cc f(mhz) v =0v cc 1 10 100 25 50 75 100 125 t (c) j v =5v bus i[t rm j ] / i [t rm j =25c] 100.0k 1.0m 10.0m 100.0m 1.0g -20.00 -15.00 -10.00 -5.00 0.00 USBLC6-4SC6 (50 ) ? s21(db) f(hz)
USBLC6-4SC6 4/10 technical information 1. surge protection the USBLC6-4SC6 is particularly optimized to perform surge protection based on the rail to rail topology. the clamping voltage v cl can be calculated as follow : v cl + = v bus + v f for positive surges v cl - = - v f for negative surges with: v f = v t + r d .i p (v f forward drop voltage) / (v t forward drop threshold voltage) we assume that the value of the dynamic resistance of the clamping diode is typically: r d = 1.4 ? and v t = 1.2v. for an iec61000-4-2 surge level 4 (contact discharge: v g =8kv, r g =330 ? ), v bus = +5v, and if in first approximation, we assume that : i p = v g / r g = 24a. so, we find: v cl + = +39v v cl - = -34v note: the calculations do not take into account phenomena due to parasitic inductances. 2. surge protection application example if we consider that the connections from the pin v bus to v cc and from gnd to pcb gnd are done by two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances lw of these tracks are about 6nh. so when an iec61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the voltage v cl has an extra value equal to lw.di/dt. the di/dt is calculated as: di/dt = ip/tr = 24 a/ns the overvoltage due to the parasitic inductances is: lw.di/dt = 6 x 24 = 144v by taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : v cl + = +39 + 144 = 183v v cl - = -34 - 144 = -178v we can reduce as much as possible these phenomena with simple layout optimization. it?s the reason why some recommendations have to be followed (see paragraph ?how to ensure a good esd protection?). figure 6: esd behavior; parasitic phenomena due to unsuitable layout lw vi/o esd surge gnd i/o +v cc v bus v f lw di dt lw di dt v+ = cl v +v +lw bus f di dt surge >0 di dt surge <0 v- = cl -v -lw f t tr=1ns vv cc f + lw di dt v cl + positive surge 183v -lw di dt t tr=1ns - v f v cl - negative surge -178v
USBLC6-4SC6 5/10 3. how to ensure a good esd protection while the USBLC6-4SC6 provides a high immunity to esd surge, an efficient protection depends on the layout of the board. in the same way, with the rail to rail topology, the track from the v bus pin to the power supply +v cc and from the v bus pin to gnd must be as short as possible to avoid overvoltages due to parasitic phenomena (see figure 6). it?s often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to the ground plane that allows a short connection. to ensure the same efficiency for positive surges when the connections can?t be short enough, we recommend to put close to the USBLC6-4SC6, between v bus and ground, a capacitance of 100nf to prevent from these kinds of overvoltage disturbances (see figure 7). the add of this capacitance will allow a better protection by providing during surge a constant voltage. the figures 8, 9 and 10 show the improvement of the esd protection according to the recommendations described above. important: a main precaution to take is to put the protection device closer to the disturbance source (generally the connector). note: the measurements have been done with the USBLC6-4SC6 in open circuit. figure 7: esd behavior: optimized layout and add of a capacitance of 100nf figure 8: esd behavior: measurements conditions (with coupling capacitance) figure 9: remaining voltage after the USBLC6-4SC6 during positive esd surge figure 10: remaining voltage after the USBLC6-4SC6 during negative esd surge ref1=gnd vi/o esd surge i/o ref2=+ v cc c=100nf lw v+ v cl cc f v+ = surge >0 surge <0 vv cl f - - = t v+ cl positive surge t v- cl negative surge +5v c=100nf test board USBLC6-4SC6 esd surge
USBLC6-4SC6 6/10 4. crosstalk behavior 4.1. crosstalk phenomena figure 11: crosstalk phenomena the crosstalk phenomena are due to the coupling between 2 lines. the coupling factor ( 12 or 21) increases when the gap across lines decreases, particularly in silicon dice. in the example above the expected signal on load r l2 is 2 v g2 , in fact the real voltage at this point has got an extra value 21 v g1 . this part of the v g1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. this phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. the perturbed line will be more affected if it works with low voltage signal or high load impedance (few k ? ). figure 12: analog crosstalk measurements figure 12 gives the measurement circuit for the analog application. in usual frequency range of analog signals (up to 240mhz) the effect on disturbed line is less than -55 db (please see figure 13). line 1 line 2 v g1 v g2 r g1 r g2 drivers r l1 r l2 receivers + 1 12 v g1 v g2 + 2 21 v g2 v g1 spectrum analyser vout 50 ? tracking generator vg vin 50 ? test board +5v USBLC6-4SC6 c=100nf figure 13: analog crosstalk results as the USBLC6-4SC6 is designed to protect high speed data lines, it must ensure a good transmis- sion of operating signals. the frequency response (figure 5) gives attenuation information and shows that the USBLC6-4SC6 is well suitable for data line transmission up to 480 mbit/s while it works as a filter for undesirable signals like gsm (900mhz) frequencies, for instance. 100.0k 1.0m 10.0m 100.0m 1.0g -120.00 -90.00 -60.00 -30.00 0.00 USBLC6-4SC6 aplac 7.70 user: st microelectronics oct 29 2004 db f/hz
USBLC6-4SC6 7/10 5. application examples figure 14: usb2.0 port application diagram using USBLC6-4SC6 figure 15: t1/e1/ethernet protection hub- downstream transceiver + 5v r s r s r s r s r pd r pd r pd r pd protecting bus switch device- upstream transceiver + 3.3v sw 1 r pu v bus d+ d- gnd v bus v bus v bus r x ls/fs + r x ls/fs + r x ls/fs + r x ls/fs + r x hs + r x hs + r x hs + r x hs + t x hs + t x hs + t x hs + t x hs + t x ls/fs + t x ls/fs + t x ls/fs + t x ls/fs + r s r s usb connector t x ls/fs - t x ls/fs - t x ls/fs - t x ls/fs - r x ls/fs - r x ls/fs - r x ls/fs - r x ls/fs - r x hs - r x hs - r x hs - r x hs - t x hs - t x hs - t x hs - t x hs - gnd gnd gnd gnd sw 2 device- upstream transceiver USBLC6-4SC6 usblc6-2p6 usblc6-2sc6 + 3.3v sw 1 r pu v bus d+ d- gnd r s r s usb connector sw 2 open closed then open high speed hs open closed full speed fs closed open low speed ls sw 2 sw 1 mode USBLC6-4SC6 +v cc 100nf data transceiver smp75-8 smp75-8 tx rx
USBLC6-4SC6 8/10 6. pspice model figure 16 shows the pspice model of one USBLC6-4SC6 cell. in this model, the diodes are defined by the pspice parameters given in figure 17. note: this simulation model is available only for an ambient temperature of 27c. figure 16: pspice model figure 17: pspice parameters figure 18: USBLC6-4SC6 pcb layout considerations vcc lpinsot 23 io1 lbondsot 23 100m lpinsot 23 lpi nsot 23 100m io2 lbondsot 23 100m lpinsot 23 lbondsot 23 io3 model = dhigh model = dhigh model = dhigh model = dhigh model = dlow model = dlow model = dlow model = dlow model = dzener rg n d lgnd lbondsot 23 100m lpinsot 23 lpinsot 23 io4 lbondsot 23 100m rvcc lvc c 100m lbondsot 23 100m lbondsot 23 0.1u 0.1u 0.1u tt 0.6 0.6 0.6 vj 0.42 0.63 0.38 rs 0.3333 0.3333 0.3333 m 1.24 1.13 1.62 n 100p 100p 100p isr 3.21p 2.27f 55.2p is 2.42 0.018 0.038 ikf 1m 1m 1m ibv 20p 2.4p 2.4p cj0 7.3 50 50 bv dzener dhigh dlow 100p lvcc 350m rvcc 100p lgnd 350m rgnd 0.15n lpinsot23 0.564n lbondsot23 d+1 c = 100nf bus d-1 gnd USBLC6-4SC6 d+2 d-2 v bus 1
USBLC6-4SC6 9/10 figure 19: sot23-6l package mechanical data figure 20: foot print dimensions (in millimeters) a2 a l h c b e d e e a1 0.95 0.60 1.20 1.10 3.50 2.30 table 4: ordering information ordering code marking package weight base qty delivery mode USBLC6-4SC6 ul46 sot23-6l 16.7 mg 3000 tape & reel table 5: revision history date revision description of changes 10-dec-2004 1 first issue ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.90 1.45 0.035 0.057 a1 0 0.10 0 0.004 a2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.014 0.02 c 0.09 0.20 0.004 0.008 d 2.80 3.05 0.110 0.120 e 1.50 1.75 0.059 0.069 e 0.95 0.037 h 2.60 3.00 0.102 0.118 l 0.10 0.60 0.004 0.024 0 10 0 10
USBLC6-4SC6 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered tr ademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
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