ess technology, inc. sam0378-053001 1 ES4228/es4227 internet set-top box solution product brief description the ES4228 mpeg video/audio decoder works as the central processing unit for internet set-top box applications, while the es4227 companion chip integrates all of the necessary discrete components for internet set-top boxes. the high level of flexibility and versatility provided by the ES4228/es4227 chipset makes it the most cost-effective, high-performance solution for the internet set-top box market. the ES4228 includes a programmable internal risc processor core that makes it adaptable for use in embedded systems applications such as set-top boxes. the es4227 companion chip supplies proper video sync capabilities and performs ntsc- and pal-based video encoding and decoding as necessary to provide broadcast quality video to the television screen. the es4227 is a mixed-signal chip that includes a high quality ntsc/pal encoder, two programmable 16-bit sigma-delta audio dacs, a pll clock synthesizer, two microphone a/d converters, an i/o expansion port, and an echo/surround sound circuit. the ES4228 controls the es4227 through a proprietary bus, the device serial communication (dsc) bus. the es4227 gets video input and audio input from the ES4228. video format is 8- bit yuv, and audio format is i 2 s. command and register accesses are issued through the dsc interface from the ES4228 to the es4227 through the dsc interface for accessing the internal registers of the es4227. the dsc interface port is comprised of three interface signals, the strobe (dsc_s), data (dsc_d), and clock (dsc_c). the dsc port is selected when the dsc strobe goes high and latches the data at the rising edge of the clock. each 16-bit dsc transfer is comprised of an address followed by data. the digital video encoder of the es4227 uses three 9-bit video dacs to generate composite and s-video analog signals. one video dac handles the composite video output, while the other two handle the s-video outputs. color space conversions are provided to match the input data to the required output format, then the data is filtered to meet the selected video standards. the programmable audio dacs of the es4227 offer differential audio outputs. these outputs ensure further noise reduction while providing a dual audio output with a signal-to-noise ratio better than 90 db. the expansion i/o port is address-mapped to the ES4228. four pins of the port can be configured as edge- triggered interrupts, supporting critical functions such as handling remote control and modem interrupt requests, dvd/ svcd loader resets and modem board resets. the ES4228 is available in an industry-standard 208-pin plastic quad flat pack (pqfp) package, while the es4227 is available in an industry-standard 100-pin pqfp package. ES4228 features ? single-chip mpeg-2 video/audio decoder and system parser in 208-pin pqfp package. ? 640 x 480 ntsc and 640 x 576 pal television video resolutions supported. ? software-configurable for internet e-mail and web browser functions. ? karaoke, on-screen display (osd), playback control (pbc) for video cd 2.0 and 3.0 and trick mode functions supported. ? videocd 1.1, 2.0, interactive 3.0, super vcd and audio cd compatible (svcd and dvd configurations only). ? smartscale? video scaling supports both x-axis and y-axis interpolationa and bidirectional ntsc to pal and pal to ntsc conversion. ? smartzoom ? supports 4x picture enlargement and reduction ? smartstream? supports video bit stream error concealment. es4227 features ? multi-standard tv encoder in 100-pin pqfp package supports ccir601 non-square operation, ntsc/pal formats, simultaneous composite and s-video output, and interlaced operation. ? two programmable 16-bit sigma-delta audio dacs accept i 2 s format data, and provide dual audio output with snr better than 90 db. ? dual microphone input and vocal assist hardware support provided. ? pll clock synthesizer based on 27 mhz crystal input generates required clocks for video encoder, audio dac, echo and surround sound, and video processor. ? device serial communication (dsc) port for command issued/ register access. ? digitally controlled echo with up to 130 ms delay. software support ? software stack support for the pop3, smtp and snmp internet e-mail protocols defined by rfc 821, rfc 1157and rfc 2449. ? software stack support provided for the http web browsing protocol defined by rfc 1945, rfc 2068 and rfc 2616. ? software stack support provided for the tcp/ip internet protocols defined by rfc 791 and rfc 793. ? software stack support provided for rtp payload format for mpeg-1/2 and h.261 video streaming protocols defined by rfc 2032, rfc 2038 and rfc 2250. ? character generation and software support for english, big 5/gb chinese and japanese fonts. ? software support for infrared remote control and wireless keyboard.
2 sam0378-053001 ess technology, inc. ES4228/es4227 product brief ES4228 pinout figure 1 shows the ES4228 device pinout. figure 1 ES4228 device pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 lcs1# loe# ld0 vss lcs3# lcs2# aux0 la21 la20 reset# vcc nc nc nc vss nc nc nc hd4 hd5 hd6 hd2 hd3 vcc vcc db8 vcc db5 db9 dcs0# vcc vss tsd/sel_pll0 sel_pll2 tdmfs tdmclk tdmdr tdmtsc# tws/sel_pll1 vcc la4 la5 la6 la7 la8 la9 vss vcc la10 la11 la12 la13 la14 la15 la16 vss vcc la17 la18 la19 tdmdx/rsel vss nc nc nc vss mclk tbck vcc vcc vss vss dqm rsd rws rbck apllcap xin xout vcc dsck vss db15 db13 db11 db1 vss dras2# dras0# doe#/dsck_en vcc dma9 dma7 vss dma5 dma3 vcc dcs1# db14 db12 db10 db0 vcc dras1# dwe# dcas# vss dma8 dma6 vcc dma4 dma2 vss db7 db6 vss db4 db3 db2 dma11 dma10 dma1 dma0 nc nc vss nc vss hd13 hd12 hd11 hd10 hd9 hd8 vss nc nc nc nc hd15 hd14 vcc hd7 hd1 hd0 vcc vss hsync# pclk2xscn yuv7 yuv6 pclkqscn vsync# yuv5 vss vcc yuv4 yuv3 yuv2 yuv1 yuv0 dclk vcc aux7 aux6 vcc ld1 ld2 la3 ld12 vcc nc vpp vcc ld3 ld5 ld9 ld13 lwrhl# nc aux1 aux3 ld4 ld6 ld10 ld14 vss la0 aux2 aux4 vcc ld7 ld11 ld15 vcc la1 vss aux5 vss ld8 vss lwrll# nc la2 vss vcc lcs0# 208-pin pqfp package ES4228 vss 104
ess technology, inc. sam0378-053001 3 ES4228/es4227 product brief ES4228 pin description table 1 lists the pin descriptions for the ES4228. table 1 ES4228 pin descriptions list name number i/o description vcc 1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92, 99, 104, 111, 121, 130, 139, 148, 157, 164, 172, 183, 193, 201 i 3.45 v power supply. la[21:0] 23:19, 16:10, 7:2, 207:204 o device address output. vss 8, 17, 26, 34, 43, 52, 60, 67, 76, 84, 91, 98, 103, 112, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 i ground. reset# 24 i reset input, active low. tdmdx 25 o tdm transmit data. rsel i rom select. tdmdr 28 i tdm receive data. tdmclk 29 i tdm clock input. tdmfs 30 i tdm frame sync. tdmtsc# 31 o tdm output enable, active low. tws 32 o audio transmit frame sync. sel_pll1 i refer to the description and matrix for sel_pll0 pin 33. tsd 33 o audio transmit serial data port. sel_pll0 i system and dsck output clock frequency selection at reset time. the matrix below lists the available clock frequencies and their respecitve pll bit settings. sel_pll2 36 i refer to the description and matrix for sel_pll0 pin 33. mclk 39 i/o audio master clock for audio dac. tbck 40 i/o audio transmit bit clock. rsd 45 i audio receive serial data. rws 46 i audio receive frame sync. rbck 47 i audio receive bit clock. apllcap 48 i analog pll capacitor. xin 49 i crystal input. xout 50 o crystal output. rsel selection 0 8-bit rom 1 16-bit rom sel_pll2 sel_pll1 sel_pll0 clock output 000 vco doesnt work. 0 0 1 27 mhz 0 1 0 bypass mode 0 1 1 54 mhz 1 0 0 121.5 mhz 1 0 1 81 mhz 1 1 0 94.5 mhz 1 1 1 108 mhz
4 sam0378-053001 ess technology, inc. ES4228/es4227 product brief name number i/o description dma[11:0] 66:61, 58:53 o dram address bus. dcas# 69 o dram column address strobe. doe# 70 o dram output enable. dsck_en o dram system clock enable. dwe# 71 o dram write enable. dras[2:0]# 74:72 o dram row address strobe. db[15:0] 96:93, 90:85 ,82:77 i/o dram data bus. dcs[1:0]# 97, 100 o sdram chip select [1:0]. dqm 101 o data input/output mask. dsck 102 o dram system clock to sdram. dclk 105 i clock input (bypass/test mode). yuv[7:0] 115:113, 110:106 o 8-bit yuv output. pclk2xscn 116 i/o 2x pixel clock. pclkqscn 117 i/o pixel clock. vsync# 118 i/o vertical sync. hsync# 119 i/o horizontal sync. hd[15:0] 141:140, 137:131, 128:122 i/o host data bus vpp 159 i 5 v power supply. aux[7:0] 169:165, 162:160 i/o auxiliary ports. loe# 170 o eprom device output enable. lcs[3:0]# 176:173 o eprom chip select [3:0]. ld[15:0] 197:194,191:185,182:178 i/o eprom device data bus. lwrll# 198 o eprom device low byte write enable. lwrhl# 199 o eprom device high byte write enable. nc 37, 38, 41, 42, 146:142, 155:149, 158, 203:202 no connect. table 1 ES4228 pin descriptions list (continued)
ess technology, inc. sam0378-053001 5 ES4228/es4227 product brief es4227 pinout figure 2 shows the es4227 device pinout. figure 2 es4227 device pinout 1 mic1 mic2 aol+ aol- aor- aor+ vccaa vrefp vcm vssaa aux15/ir aux14 aux13 rbck/ser_in aux12/c2po aux11/irq aux10 rsd/sel_pll0 vcc vss dsc_d7 hsync# dsc_d6 vsync# dsc_d5 yuv7 yuv6 yuv5 yuv4 vcc vss yuv3 dsc_d4 yuv2 dsc_d3 yuv1 dsc_d2 yuv0 dsc_d1 vss tsd aux9 tws/spll_out aux8 mclk vcc mute aux7 reset# dclk/ext_clk aux2 dsc_s aux1 dsc_d0 aux0 dsc_c vcc nc nc vss nc nc nc nc nc vss vss rstout# rws/sel_pll1 tbck ydac vssav vssav vdac acap vcc aux6 aux5 aux4 aux3 xout vss vcc xin vss nc vss vcc pclk 2xpclk vssaa vref vrefm rset comp vssav vssav cdac vccav vccav 31 30 51 50 80 81 100 2 3 4 5 6 7 8 9 10111213141516 1718 1920212223242526272829 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 es4227 100-pin pqfp
6 sam0378-053001 ess technology, inc. ES4228/es4227 product brief es4227 pin description table 2 lists the pin descriptions for the es4227. table 2 es4227 pin descriptions list name number i/o definition vss 1, 25:26, 31, 72, 75, 77, 91, 100 i ground. vcc 5, 16, 32, 66, 73, 78, 90 i 5.0v power supply. dsc_c 6 i clock for programming to access internal registers. aux0 7 i/o general purpose i/o. aux1 9 i/o general purpose i/o. aux2 11 i/o general purpose i/o. aux3 70 i/o cd loader reset. aux4 69 i/o modem dsp reset. aux5 68 i/o general purpose i/o. aux6 67 i/o general purpose i/o. aux7 14 i/o general purpose i/o. aux8 18 i/o general purpose i/o. aux9 20 i/o general purpose i/o. aux10 34 i/o general purpose i/o. aux11 35 i/o interrupt output to ES4228. aux12 36 i/o cd loader c2po. aux13 38 i/o general purpose i/o. aux14 39 i/o interrupt input from modem dsp. aux15 40 i/o ir interrupt input. dsc_d[7:0] 8, 81, 83, 85, 93, 95, 97, 99 i/o data for programming to access internal registers. dsc_s 10 i strobe for programming to access internal registers. dclk 12 o dual-purpose pin dclk is the ES4228 clock. ext_clk i external clock input during bypass pll mode. reset# 13 i reset. mute 15 o audio mute. mclk 17 i audio master clock. tws 19 i dual-purpose pin tws is the transmit audio frame sync. spll_out o spll_out is the select pll output. tsd 21 i transmit audio data input. tbck 22 i transmit audio bit clock. rws 23 o dual-purpose pin rws is the receive audio frame sync. sel_pll1 i pins sel_pll[1:0] select the pll clock frequency for the dclk output. rstout# 24 o reset output (active-low). nc 2:4,27:30,76 no connect. do not connect to these pins. sel_pll1 sel_pll0 dclk 0 0 bypass pll (input mode) 0 1 27 mhz (output mode) default 1 0 32.4 mhz (output mode) 1 1 40.5 mhz (output mode)
ess technology, inc. sam0378-053001 7 ES4228/es4227 product brief rsd 33 o dual-purpose pin. rsd is the receive audio data input. sel_pll0 i sel_pll0 along with sel_pll1 select the pll clock frequency for the dclk output. see the table for pin number 23. rbck 37 o dual-purpose pin. rbck is the receive audio bit clock. ser_in i ser_in is the serial input dsc mode. 0 - parallel dsc mode. 1 - serial dsc mode. vssaa 41,51 i audio analog ground. vcm 42 i adc common mode reference (cmr) buffer output. cmr is approximately 2.25 v. bypass to analog ground with 47 m f electrolytic in parallel with 0.1 m f. vrefp 43 i dac and adc maximum reference. bypass to vcmr with 10 m f in parallel with 0.1 m f. vccaa 44 i analog vcc, 5 v. aor+, aor- 45, 46 o right channel output. aol-, aol+ 47, 48 o left channel output. mic2 49 i microphone input 2. mic1 50 i microphone input 1. vref 52 i internal resistor divider generates common mode reference (cmr) voltage. bypass to analog ground with 0.1 m f. vrefm 53 i dac and adc minimum reference. bypass to vcmr with 10 m f in parallel with 0.1 m f. rset 54 i full scale dac current adjustment. comp 55 i compensation pin. vssav 56:57, 62:63 i video analog ground cdac 58 o modulated chrominance output. vccav 59, 60 i 5.0v video power supply. ydac 61 o y luminance data bus for screen video port. vdac 64 o composite video output. acap 65 i audio cap xout 71 o 27 mhz crystal output. xin 74 i 27 mhz crystal input. pclk 79 i/o 13.5 mhz pixel clock. 2xpclk 80 i/o doubled 27 mhz pixel clock. hsync# 82 o horizontal sync. vsync# 84 o vertical sync. yuv[7:0] 86:89, 92, 94, 96, 98 i yuv data bus for screen video port. table 2 es4227 pin descriptions list (continued) name number i/o definition
8 ? 20002001 ess technology, inc. all rights reserved. sam0378-053001 ES4228/es4227 product brief no part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ess technology, inc. ess technology, inc. makes no representations or warranties regarding the content of this document. all specifications are subject to change without prior notice. ess technology, inc. assumes no responsibility for any errors contained herein. (p) u.s. patent 4,384,169 and others, other patents pending. mpeg is the moving picture experts group of the iso/ iec. references to mpeg in this document refer to the iso/iec jtc1 sc29 committee draft iso 11172 dated january 9, 1992. video drive ? , smartscale ? , smartzoom ? and smartstream ? are trademarks of ess technology, inc. dolby is a trademark of dolby laboratories, inc. h.261 refers to the international standard described in recommendation h.261 of the ccitt working party 15-1. all other trademarks are trademarks of their respective companies and are used for identification purposes only. all other trademarks are owned by their respective holders and are used for identification purposes only. system block diagram figure 3 shows the ES4228/es4227 chipset implemented in a sample system block diagram. figure 3 ES4228/es4227 system block diagram ordering information audio video sdram rom or flash rom daa/telephone remote control companion chip es2828 es4227 mc97 es2898 modem video encoder audio dacs dsc pll i/o expansion echo/surround mic inputs mpeg processor ES4228 cd loader ir input front panel / line interface vcd/svcd option interrupt port keypad part number description package ES4228 mpeg processor 208-pin pqfp es4227 video encoder companion chip 100-pin pqfp
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