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| HC05CL4GRS/h rev 2.0 ? motorola, inc., 1997 68hc05cl4 68hc705cl4 specification (general release) ?february 12, 1997 singapore design center csic group motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part.
february 12, 1997 general release specification mc68hc05cl4 motorola rev 2.0 i table of contents section page section 1 general description 1.1 features ...................................................................................................... 1-1 1.2 mask options.............................................................................................. 1-1 1.3 mcu structure.......................................................................................... 1-2 1.4 pin assignments ........................................................................................ 1-3 1.5 functional pin description.................................................................. 1-3 1.5.1 vdd and vss ............................................................................................ 1-3 1.5.2 osc1, osc2 ............................................................................................... 1-4 1.5.3 reset......................................................................................................... 1-4 1.5.4 irq / vpp .................................................................................................... 1-5 1.5.5 pa0-pa7 ...................................................................................................... 1-5 1.5.6 pb0-pb5 ...................................................................................................... 1-5 1.5.7 tcmp/rdo.................................................................................................. 1-5 1.5.8 tcap/rdi .................................................................................................... 1-6 1.5.9 fsk+, fsk ................................................................................................. 1-6 1.5.10 rt ................................................................................................................ 1-6 1.5.11 rd1 and rd2 .............................................................................................. 1-6 1.5.12 bp0 - bp7 .................................................................................................... 1-6 1.5.13 fp0 - fp44 .................................................................................................. 1-6 section 2 memory 2.1 i/o and control registers ................................................................... 2-1 2.2 ram ................................................................................................................. 2-1 2.3 rom................................................................................................................. 2-1 section 3 central processing unit 3.1 registers .................................................................................................... 3-1 3.2 accumulator (a)........................................................................................ 3-2 3.3 index register (x) ..................................................................................... 3-2 3.4 stack pointer (sp) .................................................................................... 3-2 3.5 program counter (pc) ........................................................................... 3-2 3.6 condition code register (ccr) ........................................................... 3-3 3.6.1 half carry bit (h-bit) .................................................................................... 3-3 3.6.2 interrupt mask (i-bit) .................................................................................... 3-3 3.6.3 negative bit (n-bit) ...................................................................................... 3-3 3.6.4 zero bit (z-bit) ............................................................................................. 3-3 3.6.5 carry/borrow bit (c-bit) ............................................................................... 3-4 general release specification february 12, 1997 motorola mc68hc05cl4 ii rev 2.0 table of contents section page section 4 interrupts 4.1 cpu interrupt processing ................................................................... 4-1 4.2 reset interrupt sequence .................................................................. 4-4 4.3 software interrupt (swi) ..................................................................... 4-4 4.4 hardware interrupts ............................................................................ 4-4 4.5 external interrupt (irq)....................................................................... 4-4 4.5.1 keyboard interrupt (kbi).............................................................................. 4-6 4.5.2 low voltage interrupt................................................................................... 4-6 4.5.3 lvi control register .................................................................................... 4-7 4.5.4 ring/carrier detect interrupts (rdi/cdi)...................................................... 4-7 4.5.5 ctimer interrupt (core timer).................................................................. 4-7 4.5.6 timer interrupt (timer)............................................................................... 4-7 section 5 resets 5.1 external reset (reset).......................................................................... 5-1 5.2 internal resets ........................................................................................ 5-1 5.2.1 power-on reset (por)................................................................................ 5-2 5.2.2 computer operating properly reset (copr).............................................. 5-2 5.2.3 low voltage reset (lvr) ............................................................................ 5-2 section 6 low power modes 6.1 stop instruction...................................................................................... 6-1 6.2 wait instruction....................................................................................... 6-1 6.3 data-retention mode.............................................................................. 6-2 6.4 cop watchdog timer considerations ............................................. 6-2 section 7 input/output ports 7.1 parallel ports a and b .......................................................................... 7-1 7.1.1 port a and b data registers........................................................................ 7-2 7.1.2 port a and b data direction registers ........................................................ 7-2 7.2 ports c and d ............................................................................................. 7-2 7.2.1 port c and d data registers ....................................................................... 7-3 7.2.2 port c and d configuration registers ......................................................... 7-3 7.2.3 keyboard interrupt ....................................................................................... 7-3 7.2.4 kbi register................................................................................................. 7-4 february 12, 1997 general release specification mc68hc05cl4 motorola rev 2.0 iii table of contents section page section 8 timers 8.1 multi-functional timer .......................................................................... 8-1 8.1.1 counter ........................................................................................................ 8-1 8.1.2 output compare register............................................................................ 8-6 8.1.3 input capture register................................................................................. 8-8 8.1.4 timer control register (tcr)...................................................................... 8-9 8.1.5 timer status register (tsr) ..................................................................... 8-10 8.1.6 operation during low power mode........................................................... 8-11 8.2 core timer................................................................................................. 8-12 8.2.1 computer operating properly (cop) watchdog reset ............................. 8-12 8.2.2 ctimer control and status register (ctcsr)........................................... 8-14 8.2.3 ctimer counter register (ctcr)............................................................... 8-15 8.2.4 operation during low power mode ........................................................... 8-15 section 9 lcd driver 9.1 lcd ram. ........................................................................................................ 9-1 9.2 lcd operation............................................................................................ 9-2 9.3 lcd voltage generation ....................................................................... 9-4 9.4 lcd control register (lcdctr) .......................................................... 9-5 section 10 caller id 10.1 introduction............................................................................................ 10-1 10.1.1 fsk demodulator ...................................................................................... 10-2 10.1.2 carrier detector ......................................................................................... 10-2 10.1.3 ring detector............................................................................................. 10-2 10.1.4 power management................................................................................... 10-2 10.1.5 data interface ............................................................................................ 10-4 10.2 caller id register ................................................................................. 10-5 10.2.1 control/status register1 (clcsr1) .......................................................... 10-5 10.2.2 control/status register 2 (clcsr2) ........................................................... 10-6 10.2.3 control/status register 3 (clcsr3) ........................................................... 10-6 10.3 design parameters................................................................................ 10-8 10.4 message format ..................................................................................... 10-9 section 11 instruction set 11.1 addressing modes ................................................................................. 11-1 11.1.1 inherent...................................................................................................... 11-1 11.1.2 immediate .................................................................................................. 11-1 11.1.3 direct ......................................................................................................... 11-1 general release specification february 12, 1997 motorola mc68hc05cl4 iv rev 2.0 table of contents section page 11.1.4 extended.................................................................................................... 11-2 11.1.5 indexed, no offset..................................................................................... 11-2 11.1.6 indexed, 8-bit offset .................................................................................. 11-2 11.1.7 indexed, 16-bit offset ................................................................................ 11-2 11.1.8 relative...................................................................................................... 11-3 11.1.9 instruction types ....................................................................................... 11-3 11.1.10 register/memory instructions .................................................................... 11-4 11.1.11 read-modify-write instructions ................................................................. 11-5 11.1.12 jump/branch instructions .......................................................................... 11-5 11.1.13 bit manipulation instructions...................................................................... 11-7 11.1.14 control instructions.................................................................................... 11-7 11.1.15 instruction set summary ........................................................................... 11-8 section 12 electrical specification 12.1 maximum ratings..................................................................................... 12-1 12.2 thermal characteristics ................................................................... 12-1 12.3 dc electrical characteristics........................................................ 12-2 12.4 control timing ........................................................................................ 12-3 section 13 mechanical specification 13.1 80-pin quad-flat-package (case 841b-01) ........................................ 13-2 appendix a mc68hc705cl4 a.1 introduction..............................................................................................a-1 a.2 memory .........................................................................................................a-1 a.2.1 option register ($1d)..................................................................................a-1 a.3 eprom ............................................................................................................a-3 a.4 bootstrap mode .......................................................................................a-3 a.5 eprom programming ...............................................................................a-3 a.5.1 program control register (pcr) .................................................................a-3 a.5.2 programming sequence ..............................................................................a-4 a.6 maximum ratings.......................................................................................a-6 a.7 dc electrical characteristics..........................................................a-6 a.8 control timing ..........................................................................................a-6 february 12, 1997 general release specification mc68hc05cl4 motorola rev 2.0 v list of figures figure title page 1-1 mc68hc05cl4 block diagram ....................................................................... 1-2 1-2 mc68hc05cl4 pin assignments .................................................................... 1-3 1-3 oscillator connections ..................................................................................... 1-4 2-1 memory map .................................................................................................... 2-2 2-2 i/o registers .................................................................................................... 2-3 3-1 mc68hc05 programming model ..................................................................... 3-1 4-1 interrupt processing flowchart ........................................................................ 4-3 4-2 interrupt status and control register............................................................... 4-5 6-1 stop/halt/wait flowcharts......................................................................... 6-3 7-1 port i/o circuitry............................................................................................... 7-1 7-2 port c/d circuitry ............................................................................................. 7-3 8-1 timer block diagram........................................................................................ 8-3 8-2 timer state timing diagram for reset............................................................. 8-4 8-3 timer state timing diagram for timer overflow.............................................. 8-4 8-4 timer state timing diagram for output compare .......................................... 8-7 8-5 timer state timing diagram for input capture ............................................... 8-9 8-6 core timer block diagram............................................................................ 8-13 9-1 lcd block diagram. ......................................................................................... 9-1 9-2 lcd waveforms with 8 back planes. ............................................................... 9-3 9-3 voltage generation .......................................................................................... 9-4 10-1 clid block diagram....................................................................................... 10-1 10-2 cpu-clid power-up sequence from stop mode ....................................... 10-3 10-3 cpu-clid power-up sequence from wait mode........................................ 10-4 10-4 single message format ................................................................................. 10-9 10-5 clid timing diagram................................................................................... 10-10 general release specification february 12, 1997 motorola mc68hc05cl4 vi rev 2.0 list of figures figure title page february 12, 1997 general release specification mc68hc05cl4 motorola rev 2.0 vii list of tables table title page 4-1 vector address for interrupts and reset.......................................................... 4-2 7-1 port a & b i/o functions .................................................................................. 7-2 7-2 port c and d pin functions.............................................................................. 7-3 8-1 rti and cop rates ....................................................................................... 8-16 9-1 lcd ram organization.................................................................................... 9-2 9-2 voltage divider resistor options ..................................................................... 9-5 10-1 typical input parameters................................................................................ 10-8 10-2 critical design characteristics ....................................................................... 10-8 10-3 switching characteristics (v dd = 5v; ta=25 c) ............................................. 10-9 11-1 register/memory instructions ........................................................................ 11-4 11-2 read-modify-write instructions...................................................................... 11-5 11-3 jump and branch instructions........................................................................ 11-6 11-4 bit manipulation instructions .......................................................................... 11-7 11-5 control instructions ........................................................................................ 11-7 11-6 instruction set summary............................................................................... 11-8 11-7 opcode map................................................................................................. 11-14 general release specification february 12, 1997 motorola mc68hc05cl4 viii rev 2.0 list of tables table title page february 12, 1997 general release specification mc68hc05cl4 general description motorola rev 2.0 1-1 section 1 general description the mc68hc05cl4 hcmos microcontroller is a member of the mc68hc05 family of low-cost single-chip microcontrollers. it is particularly suitable as a caller-id telephone controller. this 8-bit microcontroller unit (mcu) contains on- chip oscillator, cpu, ram, rom, i/o, timer, watchdog timer, caller id subsystem and 45 x 8 lcd driver. 1.1 features industry standard 8-bit m68hc05 core power saving stop, wait modes 6k bytes of rom 1k bytes of ram (64 bytes for stack) hardware caller id subsystem 14 bidirectional i/o lines 16 input lines keyboard interrupt lines 45 x 8 (or 49 x 4) lcd driver 16 bit free-running timer with 1 input capture and 1 output compare cop watchdog reset low voltage reset (lvr) on-chip crystal oscillator internal reset pin pull-down for lvr, cop watchdog and power-on reset user and self test modes available in 80-pin qfp 1.2 mask options two mask options are available for the mc68hc05cl4. low-voltage-reset (disabled or enabled) cop watchdog reset (disabled or enabled) general release specification february 12, 1997 motorola general description mc68hc05cl4 1-2 rev 2.0 1.3 mcu structure the overall block diagram of the mc68hc05cl4 is shown in figure 1-1 . figure 1-1. mc68hc05cl4 block diagram note a line over a signal name indicates an active low signal. any reference to voltage, current, or frequency speci?d in the following sections will refer to the nominal values. the exact values and their tolerance or limits are speci?d in section 12 . pb0 pb1 pb2 pb3 pb4 pb5 oscillator and divide by 2 data dir reg port b reg osc1 osc2 core timer (cop) 1k bytes ram (64 stack) pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 data dir reg port a reg reset irq 16 bits timer tcmp/rdo tcap/rdi caller id fsk+ fsk- rt vdd vss stk ptr cond code reg 1 1 1 i n z c h index reg cpu control 0 0 0 1 1 0 0 0 0 0 alu 68hc05 cpu accum program counter cpu registers fp(0:44) lvi/lvr bp(0:7) lcd 6k bytes rom rd1 rd2 february 12, 1997 general release specification mc68hc05cl4 general description motorola rev 2.0 1-3 1.4 pin assignments the mc68hc05cl4 is available in the 80-pin qfp package. the pin assignments for this packages are shown in figure 1-2 . figure 1-2. mc68hc05cl4 pin assignments 1.5 functional pin description the following paragraphs give a description of the general function of each pin. 1.5.1 vdd and vss power is supplied to the mcu through vdd and vss. vdd is the positive supply, and vss is ground. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care should be taken to provide good power supply bypassing at the mcu by using bypass capacitors with good high-frequency char- acteristics that are positioned as close to the mcu as possible. bp2 bp1 tcmp/rdo 21 22 24 25 26 27 28 29 30 31 33 34 35 36 23 60 59 57 56 55 54 53 52 51 50 49 48 47 46 45 58 fp40/pd3 fp39/pd2 fp37/pd0 fp36/pc7 fp35/pc6 fp34/pc5 fp33/pc4 fp32/pc3 fp31/pc2 fp30/pc1 fp29/pc0 fp28 fp27 fp26 fp25 fp38/pd1 pa0 pa1 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 fsk+ fsk? pa2 fp1 fp2 fp4 fp5 fp6 fp7 fp9 fp10 fp11 fp12 fp13 fp14 fp15 fp16 fp3 irq reset osc2 vdd vss tcap/rdi bp0 bp3 bp4/fp48 bp5/fp47 bp6/fp46 bp7/fp45 osc1 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 3 fp8 32 80 79 77 76 75 74 72 71 70 69 68 67 66 65 78 73 rt rd1 rd2 fp0 17 18 19 20 fp41/pd4 fp42/pd5 fp44/pd7 fp43/pd6 63 62 61 64 37 38 40 39 fp17 fp18 fp10 fp19 44 43 41 42 fp24 fp23 fp21 fp22 mc68hc05cl4 general release specification february 12, 1997 motorola general description mc68hc05cl4 1-4 rev 2.0 1.5.2 osc1, osc2 the osc1 and osc2 pins are the connections for the on-chip oscillator. the osc1, and ocs2 pins can accept the following sets of components: 1. a crystal as shown in figure 1-3(a) 2. an external clock signal as shown in figure 1-3(b) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . the circuit in figure 1-3(a) shows a typical oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturer s recommendations should be fol- lowed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an external start-up resistor of approximately 2 m w is needed between osc1 and osc2 for the crys- tal type oscillator. figure 1-3. oscillator connections an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-3(b) . 1.5.3 reset this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains a steering diode to discharge any voltage on the pin to vdd, when the power is removed. the reset pin con- tains an internal schmitt trigger to improve its noise immunity as an input. the reset pin has an internal pull-down device that pulls the reset pin low when there is an internal cop watchdog reset or during the power-on reset cycles. refer to section 5 . mcu 36 pf (a) crystal or ceramic resonator connections osc1 osc2 36 pf 2m w unconnected external clock (b) external clock source connection osc1 osc2 mcu february 12, 1997 general release specification mc68hc05cl4 general description motorola rev 2.0 1-5 1.5.4 irq / v pp this pin has two choices of interrupt triggering sensitivity through the irq bit in the interrupt status and control register (iscr). the choices are: 1. edge-sensitive triggering only, or 2. both edge-sensitive and level-sensitive triggering. in addition, the irq pin may be selected to trigger and interrupt on either the rising or falling edge of the irq pin signal through the edge bit in the iscr. the mcu completes the current instruction before it responds to the interrupt request. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for ?ire-or operation. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. see section 4 . this pin is also used to supply the mc68hc705cl48 eprom array with the pro- gramming voltage. note if the voltage level applied to the irq pin exceeds v dd it may affect the mcu s mode of operation. 1.5.5 pa0-pa7 these eight i/o lines comprise port a. the state of any pin is software program- mable and all port a lines are con?ured as inputs during power-on or reset. see section 7 for more details on the i/o ports. pa4 to pa7 have internal pull-up resis- tors and can generate key board interrupt. 1.5.6 pb0-pb5 these six i/o lines comprise port b. the state of any pin is software programma- ble and all port b lines are con?ured as inputs during power-on or reset. see section 7 for more details on the i/o ports. all the port b pins pb0 - pb5 can sink 10ma to drive leds. 1.5.7 tcmp/rdo this pin provides an output for the output compare feature (tcmp) of the on-chip programmable timer system and can be programed to as raw data out (rdo) from the caller id module. refer to section 8 for additional information. general release specification february 12, 1997 motorola general description mc68hc05cl4 1-6 rev 2.0 1.5.8 tcap/rdi this pin is used as tcap input to the input capture feature of the on-chip pro- grammable timer system and can be con?ured as the raw data input (rdi) to the mcu under software control if an external caller id device is used. refer to section 8 for additional information. 1.5.9 fsk+, fsk these two inputs are the non-inverting and inverting fsk signals. 1.5.10 rt this input is an incoming ring detect power-up control. 1.5.11 rd1 and rd2 these inputs are incoming ring quali?rs. 1.5.12 bp0 - bp7 these are the backplane drivers dedicated to the lcd subsystem. when the lcd is used in multiplex by four mode bp4 - bp7 are con?ured as extra frontplanes fp45 - fp48. 1.5.13 fp0 - fp44 these are the front plane drivers dedicated to the lcd subsystem. fp29 to fp44 can be con?ured as input only ports c and d under software control. february 12, 1997 general release specification mc68hc05cl4 memory motorola rev 2.0 2-1 section 2 memory when the mc68hc05cl4 is in the single-chip mode the 32 bytes of i/o,1k bytes of user ram, and 6k bytes of user rom are all active as shown in figure 2-1 . 2.1 i/o and control registers the i/o and control registers reside in locations $0000-$001f. the overall orga- nization of these registers is shown in figure 2-1 . the bit assignments for each register are shown in figure 2-2 . reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. 2.2 ram the total ram consists of 1k bytes (including the stack) at locations $0050 thru $044f. the stack begins at address $00ff and proceeds down to $00c0. the stack pointer can access 64 locations from $00c0 to $00ff. using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 2.3 rom there are a total of 6656 bytes of user rom on chip. this includes 6144 bytes of user rom with locations $0800 thru $1fdf for user program storage and16 bytes for user vectors at locations $1ff0 thru $1fff. (there are 16 bytes reserved for self-check program vectors, located at $1fe0-$1fef.) general release specification february 12, 1997 motorola memory mc68hc05cl4 2-2 rev 2.0 figure 2-1. memory map port a data register port b data register port a direction register port b direction register timer status register timer control register input capture high register input capture low register output compare high register reserved (eprom program control register) $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f $0000 $001f $0020 $00bf $00c0 $00ff $0100 $044f $0450 $1fef $1fff $1ff0 user registers 32 bytes ram 1k bytes stack 64 bytes ram user vectors 16 bytes ctimer irq swi reset $1ff0 $1ff2 $1ff4 $1ff6 $1ff8 $1ffa $1ffc $1ffe $1ff1 $1ff3 $1ff5 $1ff7 $1ff9 $1ffb $1ffd $1fff user rom 6k bytes self check vectors 16 bytes 0 31 32 1103 1104 8191 8175 8176 191 192 255 256 core timer control & status register core timer register cdi lcd ram $004c $0050 76 80 output compare low register counter high register counter low register alternate counter high register alternate counter low register reserved $1fdf $1fe0 8159 8160 $07ff $0800 self check rom 512 bytes 2047 2048 $05ff $0600 1535 1536 not used irq status/control register lcd control register rdi lvi port c data register port d data register port c configuration register port d configuration register lvi control register clid control/status register 1 clid control/status register 2 option register timer keyboard interrupt register clid control/status register 3 reserved reserved february 12, 1997 general release specification mc68hc05cl4 memory motorola rev 2.0 2-3 addr register r/w bit 7 bit 6 bit 5 bit 4 bit3 bit2 bit1 bit 0 $0000 port a data porta read pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write $0001 port b data portb read 0 0 pb5 pb4 pb3 pb2 pb1 pb0 write $0002 port c data portc read pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write $0003 port d data portd read pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write $0004 port a data direction ddra read ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write $0005 port b data direction ddrb read 0 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write $0006 port c configuration cfgc read cfgc7 cfgc6 cfgc5 cfgc4 cfgc3 cfgc2 cfgc1 cfgc0 write $0007 port d configuration cfgd read cfgd7 cfgd6 cfgd5 cfgd4 cfgd3 cfgd2 cfgd1 cfgd0 write $0008 core timer control ctcsr read ctof rtif ctofe rtie 00 rt1 rt0 write $0009 core timer register ctr read ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 write $000a lcd control lcdctr read cc3 cc2 cc1 mx4 fc lc dison write $000b reserved read r rrrrrrr write $000c clrid control status1 clcsr1 read rdif rdie cdif cdie rdo cdo write 00 $000d clrid control status2 clcsr2 read cdpw rdpw cidsd rd cd write $000e clrid control status3 clcsr3 read sdsl rdedg cdedg rdoe cdoe write $000f irq status/control iscr read irqm irqs edge 0 req 0 0 0 write ack = unimplemented r = reserved figure 2-2. i/o registers general release specification february 12, 1997 motorola memory mc68hc05cl4 2-4 rev 2.0 $0010 lvi control lvscr read lvis lvif lvie write 0 $0011 keyboard interrupt kbir read kbie7 kbie6 kbie5 kbie4 0 kedge kbif 0 write kbic $0012 timer control tcr read icie ocie toie 0 0 0 iedg olvl write $0013 timer status tsr read icf ocf tof 0 0 0 0 0 write $0014 input capture h ich read ic15 ic14 ic13 ic12 ic11 ic10 ic9 ic8 write $0015 input capture l icl read ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 write $0016 output compare h och read oc15 oc14 oc13 oc12 oc11 oc10 oc9 oc8 write $0017 output compare l ocl read oc7 oc6 oc5 oc4 oc3 oc2 oc1 oc0 write $0018 timer counter h tch read tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 write $0019 timer counter l tcl read tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 write $001a alternate counter h ach read ac15 ac14 ac13 ac12 ac11 ac10 ac9 ac8 write $001b alternate counter l acl read ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write $001c reserved for eprom control read r rrrrr elat pgm write $001d reserved for option read cop lvre write $001e reserved read r rrrrrrr write $001f reserved read r rrrrrrr write = unimplemented r = reserved addr register r/w bit 7 bit 6 bit 5 bit 4 bit3 bit2 bit1 bit 0 figure 2-2. i/o registers february 12, 1997 general release specification mc68hc05cl4 central processing unit motorola rev 2.0 3-1 section 3 central processing unit the mc68hc05cl4 has an 8k memory map. therefore it uses only the lower 13 bits of the address bus. in the following discussion the upper 3 bits of the address bus can be ignored. the stack has only 64 bytes. therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00c0 and then wrap-around to $00ff. all other instructions and registers behave as described in this chapter. 3.1 registers the mcu contains ?e registers which are hard-wired within the cpu and are not part of the memory map. these ?e registers are shown in figure 3-1 and are described in the following paragraphs. figure 3-1. mc68hc05 programming model condition code register i accumulator 60 a index register 71 x 4 52 3 stack pointer sp 14 8 15 9 12 13 10 11 pc cc 111 11 0 0 0 0 0 0 0 0 program counter h nzc half-carry bit (from bit 3) interrupt mask negative bit zero bit carry bit general release specification february 12, 1997 motorola central processing unit mc68hc05cl4 3-2 rev 2.0 3.2 accumulator (a) the accumulator is a general purpose 8-bit register as shown in figure 3-1 . the cpu uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. the accumulator is unaffected by a reset of the device. 3.3 index register (x) the index register shown in figure 3-1 is an 8-bit register that can perform two functions: indexed addressing temporary storage in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu ?ds the operand address by adding the index register contents to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu ?ds the operand address by adding the index register con- tents to a 16-bit immediate value the index register can also serve as an auxiliary accumulator for temporary stor- age.the index register is unaffected by a reset of the device. 3.4 stack pointer (sp) the stack pointer shown in figure 3-1 is a 16-bit register internally. in devices with memory maps less than 64 kbytes the unimplemented upper address lines are ignored. the stack pointer contains the address of the next free location on the stack. during a reset or the reset stack pointer (rsp) instruction, the stack pointer is set to $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. the six least signi?ant register bits are appended to these ten ?ed bits to produce an address within the range of $00c0 to $00ff. subroutines and interrupts may use up to 64 ($40) locations. if 64 locations are exceeded, the stack pointer wraps around and writes over the previously stored information. a subroutine call occupies two locations on the stack; and an interrupt uses ?e locations. 3.5 program counter (pc) the program counter shown in figure 3-1 is a 16-bit register internally. in devices with memory maps less than 64 kbytes the unimplemented upper address lines are ignored. the program counter contains the address of the next instruction or operand to be fetched. february 12, 1997 general release specification mc68hc05cl4 central processing unit motorola rev 2.0 3-3 normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 condition code register (ccr) the ccr shown in figure 3-1 is a 5-bit register in which four bits are used to indi- cate the results of the instruction just executed. the ?th bit is the interrupt mask. these bits can be individually tested by a program, and speci? actions can be taken as a result of their state. the condition code register should be thought of as having three additional upper bits that are always ones. only the interrupt mask is affected by a reset of the device. the following paragraphs explain the functions of the lower ?e bits of the condition code register. 3.6.1 half carry bit (h-bit) when the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last add or adc (add with carry) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. 3.6.2 interrupt mask (i-bit) when the interrupt mask is set, the internal and external interrupts are disabled. interrupts are enabled when the interrupt mask is cleared. when an interrupt occurs, the interrupt mask is automatically set after the cpu registers are saved on the stack, but before the interrupt vector is fetched. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the interrupt is processed as soon as the interrupt mask is cleared. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. after any reset, the interrupt mask is set and can only be cleared by the clear i-bit (cli), stop, or wait instructions. 3.6.3 negative bit (n-bit) the negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (bit 7 of the result was a logical one.) the negative bit can also be used to check an often-tested ?g by assigning the ?g to bit 7 of a register or memory location. loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the ?g. 3.6.4 zero bit (z-bit) the zero bit is set when the result of the last arithmetic operation, logical opera- tion, data manipulation, or data load operation was zero. general release specification february 12, 1997 motorola central processing unit mc68hc05cl4 3-4 rev 2.0 3.6.5 carry/borrow bit (c-bit) the carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. the carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. this bit is not set by an inc or dec instruction. february 12, 1997 general release specification mc68hc05cl4 interrupts motorola rev 2.0 4-1 section 4 interrupts this section describes the interrupt structure of the mc68hc05cl4. 4.1 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are con- sidered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is clear) and the corresponding inter- rupt enable bit is set the processor will proceed with interrupt processing. other- wise, the next instruction is fetched and executed. if an interrupt occurs the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and ?ally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 4-1 will be serviced ?st. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed the cpu fetches the address of the appro- priate interrupt software service routine from the vector table at locations $1ff0 thru $1fff as de?ed in table 4-1 . general release specification february 12, 1997 motorola interrupts mc68hc05cl4 4-2 rev 2.0 table 4-1. vector address for interrupts and reset an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. register flag interrupt cpu int vector address n/a n/a reset reset $1ffe - $1fff n/a n/a software swi $1ffc - $1ffd n/a n/a external interrupt/ key board interrupt irq/kbi $1ffa - $1ffb n/a n/a low voltage lvi $1ff8 - $1ff9 clcsr1 rdf ring detect rdi $1ff6 - $1ff7 clcsr1 cdf carrier detect cdi $1ff4 - $1ff5 ctcsr ctof rtif core timer ctimer $1ff2 - $1ff3 tsr tof ocf icf timer timer $1ff0 - $1ff1 february 12, 1997 general release specification mc68hc05cl4 interrupts motorola rev 2.0 4-3 figure 4-1. interrupt processing flowchart n n n n y y y y y from reset is i-bit set? load interrupt vectors to pc set i-bit in ccr pc -> (sp,sp-1) x -> (sp-2) a -> (sp-3) cc -> (sp-4) clear irq latch restore registers from stack cc, a, x, pc irq external interrupt? rdi interrupt ? execute instruction fetch next instruction rti instruction ? swi instruction ? n n y lvi interrupt ? n y core timer int ? y timer interrupt ? n y cdi interrupt ? n general release specification february 12, 1997 motorola interrupts mc68hc05cl4 4-4 rev 2.0 4.2 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low level input on the reset pin or internal generated reset signal causes the program to vector to its starting address which is speci?d by the contents of memory locations $1ffe and $1fff. the i-bit in the condition code register is also set. the mcu is con?ured to a known state during this type of reset as described in section 5 . 4.3 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is exe- cuted regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupts enabled), the swi instruction executes after interrupts which were pending before the swi was fetched, or before interrupts generated after the swi was fetched. the interrupt service routine address is speci?d by the contents of memory loca- tions $1ffc and $1ffd 4.4 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. the hardware interrupts are explained in the following sections. 4.5 external interrupt (irq) if the interrupt mask bit (i bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts (subject to their individual interrupt enable control ?g status). irq now has an independent inter- rupt mask bit in the interrupt status and control register (iscr) which must also be cleared to enable its corresponding interrupt. the interrupt mask bit operates by inhibiting the interrupt signal after the appropri- ate interrupt request latch. this feature allows the interrupt to be recognized and latched even if the mask is set. when the irq input goes to the active level for at least one t ilih , a logic one is latched internally to signify an interrupt has been requested. when the mcu com- pletes its current instruction, the interrupt latch is tested. if the interrupt latch con- tains a logic one, and the interrupt mask bit (i bit) in the condition code register and the irq mask bit (irqm) in the iscr are both clear, then the mcu can begin the interrupt sequence. the state of the interrupt latch is re?cted in the interrupt request bit (req) in the iscr, and is automatically cleared during interrupt pro- cessing. see figure 4-2 . irq interrupt requests are automatically acknowledged and cleared during inter- rupt processing. it may also be cleared through software by setting the acknowl- edge bit in the iscr. setting this bit is a ?ne-shot operation and will not effect subsequent interrupt operation. the action of clearing the acknowledge bit will february 12, 1997 general release specification mc68hc05cl4 interrupts motorola rev 2.0 4-5 clear the request bit. this allows the programmer the option to cancel spurious interrupts which occur while the interrupt mask bits are set. this may be neces- sary in systems where it is desirable to prevent redundant (ghost) entries to the interrupt service routine (where the interrupt mask is eventually cleared). note that the irqm is cleared (enabled) during reset, though no interrupts can occur until the interrupt mask bit (i-bit) of the ccr is cleared (it is set during reset). the interrupt request latches are also cleared during reset. figure 4-2. interrupt status and control register irqm - irq enable mask the irqm bit is a read/write bit which will disable the irq interrupt when set. irqm is cleared by reset. 1 = irq interrupt request disabled 0 = irq interrupt request enabled irqs - irq sensitivity the irqs bit is a read/write bit which will select whether the irq interrupt is edge-sensitive only or both edge-sensitive and level-sensitive. irqs is cleared by reset. 1 = both edge-sensitive and level-sensitive 0 = edge-sensitive only edge - irq active edge select the edge bit is a read/write bit which allows the user to select which edge, ris- ing or falling, of the signal at the irq pin will generate an interrupt. both rising and falling edge sensitivity may be achieved in software by toggling the edge bit from within the irq service routine. edge is cleared by reset. 1 = rising edge irq interrupt 0 = falling edge irq interrupt req - irq interrupt request the req bit is a read-only bit. the irq interrupt request bit and latch are cleared during irq exception processing. therefore, one external irq interrupt pulse can be latched and subsequently serviced as soon as the i bit is cleared. req will be cleared by reset. 1 = irq interrupt request pending 0 = no irq interrupt request pending iscr $000f 7 w r 6543210 ack req edge irqm 0 00000000 reset t 0 0 irqs 0 general release specification february 12, 1997 motorola interrupts mc68hc05cl4 4-6 rev 2.0 ack - irq interrupt request acknowledge this bit is write only - it will always read as a zero. writing a one to this bit will acknowledge the interrupt by clearing the corresponding interrupt request bit. note the use of separate request and acknowledge bits allows the safe use of read- modify-write instructions (e.g. bset, bclr) on the iscr register. note when the edge and level-sensitive mask option is selected, the voltage applied to the irq pin must return to the inactive state before the rti instruction in the interrupt service routine is executed. if the irq pin remains in at the active level, the interrupt service routine will be re-entered after the rti is executed. setting the ack bit will have no effect under these circumstances. 4.5.1 keyboard interrupt (kbi) the kbi interrupt is generated by the keyboard interrupt circuit in porta as described in section 7 . the interrupt enable bit for the kbi interrupt is located at bit 4-7 of keyboard interrupt register (kbir) at $0011. the i-bit in the ccr must be clear in order for the kbi interrupt to be enabled. this address for the interrupt vector is shared with the irq located at $1ffa and $1ffb. 4.5.2 low voltage interrupt the lvi is generated by the low voltage detect circuit when the supply voltage falls below the lvi threshold (lvi th ). enable and ?g bits for this interrupt are located in the lvscr register located at address $0010. the i-bit in the ccr must be clear in order for the lvi interrupt to be enabled. this interrupt will vector to the interrupt service routine located at the address speci?d by the contents of memory loca- tions $1ff8 and $1ff9. the user is required to set the lvre bit in the option register before enabling the lvie bit in the lvscr register . kbe5 0 7 0000000 6543210 kbe4 kbe6 w r kbir $0011 reset kbe7 kbif 0 kbic 0 kedge february 12, 1997 general release specification mc68hc05cl4 interrupts motorola rev 2.0 4-7 4.5.3 lvi control register lvie ?low voltage reset enable low voltage interrupt enable bit, when set will enable an interrupt to be gener- ated when lvif, the low voltage interrupt ?g bit is set. this bit should only be enabled after lvre bit in the option register has been set. lvif ?low voltage reset flag this bit is set when vdd drops below the threshold voltage of lvi th . when set this bit will generate an interrupt provided the lvi enable bit (lvie) is set. it can be reset by writing a ? to lvif, provided vdd is above lvi th . lvis ?low voltage interrupt status this bit is set when vdd drops below the threshold voltage of lvi th .. the user can read this bit to check if the lv interrupt is true or if it is just a glitch. the dif- ference between lvis and lvif is that lvif is latched while lvis is not. 4.5.4 ring/carrier detect interrupts (rdi/cdi) this interrupt is caused by the caller id module when a valid ring signal or a car- rier is detected. the enable and ?g bits for the ring detect and the carrier detect are located in clcsr1 register. these two interrupts will vector to separate inter- rupt service routines located at the addresses speci?d by the contents of mem- ory locations $1ff6-$1ff7 and $1ff4-$1ff5 respectively. these interrupts will wake the mcu from the wait mode. see section 10 . 4.5.5 ctimer interrupt (core timer) the ctimer interrupt is generated by the core timer when a core timer over?w, or real time interrupt has occurred as described in section 8 . the interrupt enable bits and ?gs for the core timer interrupts are located in the core timer control and status register (ctcsr) located at $0008. the i-bit in the ccr must be clear in order for the ctimer interrupt to be enabled. these two interrupts will vector to the same interrupt service routine located at the address speci?d by the contents of memory locations $1ff2 and $1ff3. 4.5.6 timer interrupt (timer) the timer interrupt is generated by the multi-function timer when a timer over- ?w, output compare or input capture has occurred as described in section 8 . the interrupt enable bits and ?gs for the timer interrupts are located in the timer control register (tcr) and timer status register (tsr) located at $0012 & $0013. the i-bit in the ccr must be clear in order for the timer interrupt to be 76543210 lvscr $0010 read lvis lvif lvie write 0 reset uuuuuu0 0 general release specification february 12, 1997 motorola interrupts mc68hc05cl4 4-8 rev 2.0 enabled. these three interrupts will vector to the same interrupt service routine located at the address speci?d by the contents of memory locations $1ff0 and $1ff1. february 12, 1997 general release specification mc68hc05cl4 resets motorola rev 2.0 5-1 section 5 resets the mcu can be reset from four sources: power-on reset (por) cop watchdog reset (copr) low-voltage reset (lvr) external reset pin all the internal peripheral modules which drive external pins will be reset by the synchronous reset signal (rst) coming from a latch, which is synchronized to the internal bus clock and set by the any of the four reset sources. 5.1 external reset (reset ) the reset pin has an schmitt trigger stage and is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. this exter- nal reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the rst signal and reset the cpu and peripherals. termi- nation of the external reset input can alter the operating mode of the mcu. note activation of the rst signal is generally referred to as reset of the device, unless otherwise speci?d. the reset pin can also be pulled to a low state by an internal pull-down that is activated by the internal cop watchdog, power-on resets and low voltage reset. this reset pin pull-down device will only be activated for four cycles of the inter- nal clock, t cyc , when a cop watchdog reset occurs; or will remain activated as long as counting the power-on reset cycles or the low voltage is detected. 5.2 internal resets the three internally generated resets are the power-on reset , the cop watchdog timer reset, and the low-voltage reset. general release specification february 12, 1997 motorola resets mc68hc05cl4 5-2 rev 2.0 5.2.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabi- lize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064t cyc after the oscillator becomes active. the reset pin will be pulled down internally during these cycles. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of this 4064 cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end. 5.2.2 computer operating properly reset (copr) the internal copr reset is generated automatically (if enabled) by a time-out of the cop watchdog timer. this time-out occurs if the counter in the cop watch- dog timer is not reset (cleared) within a speci? time by a program reset sequence. the cop watchdog reset will activate the internal pull-down device connected to the reset pin for four cycle of the internal clock. the cop watchdog timer is enabled or disabled by a mask option. refer to section 8 for more information on cop watchdog. 5.2.3 low voltage reset (lvr) the internal lvr is generated automatically when the vdd drops below a certain level lvr th . the vdd level which will trigger the lvr is speci?d in section 12 . the lvr will activate the internal pull-down device connected to the reset pin as long as low voltage is detected. the lvr function is enabled or disabled by a mask option. february 12, 1997 general release specification mc68hc05cl4 low power modes motorola rev 2.0 6-1 section 6 low power modes the mc68hc05cl4 has two low-power operational modes. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the stop and wait instructions are not normally used if the cop watchdog timer is enabled. the ?w of the stop and wait modes is shown in figure 6-1 . 6.1 stop instruction execution of the stop instruction, places the mcu in its lowest power consump- tion mode. in the stop mode the internal oscillator is turned off, halting all inter- nal processing, including the cop watchdog timer. when the cpu enters stop mode the i-bit in the condition code register will be cleared automatically, so that any hardware interrupt (irq, rdi & kbi) can wake up the mcu. all other registers and memory remain unaltered. all input/output lines remain unchanged. the mcu can be brought out of the stop mode only by a hardware interrupt or an externally generated reset. when exiting the stop mode the internal oscilla- tor will resume after a 4064 internal processor clock cycle oscillator stabilization delay. 6.2 wait instruction the wait instruction places the mcu in a low-power mode, which consumes more power than the stop mode. in the wait mode the internal processor clock is halted, suspending all processor and internal bus activity. other internal clocks remain active, permitting interrupts to be generated from the core timer or a reset to be generated from the cop watchdog timer. the core timer may be used to generate a periodic exit from the wait mode. in the wait mode, the carrier detect and the ring detect circuit can be kept active by writing to the enable bit in the clcsr2 register before the wait instruction is executed. execution of the wait instruction automatically clears the i-bit in the condition code register, so that any hardware interrupt can wake up the mcu. all other registers, memory, and input/output lines remain in their previous states. general release specification february 12, 1997 motorola low power modes mc68hc05cl4 6-2 rev 2.0 6.3 data-retention mode the contents of ram and cpu registers are retained at supply voltages as low as 2.0 vdc. this is called the data-retention mode where the data is held, but the device is not guaranteed to operate. the reset pin must be held low during data-retention mode. 6.4 cop watchdog timer considerations if the cop watchdog timer is selected by setting the enable bit, any execution of the stop instruction (either intentional or inadvertent due to the cpu being dis- turbed) will be executed as a wait instruction. it is because, if a stop instruction could be executed, while the cop was enabled. the stop instruction will cause the oscillator to halt and prevent the cop watchdog timer from timing out. there- fore, the stop instruction will put the mcu into wait mode, insted of stop mode, if cop is enabled. if the cop watchdog timer is selected, the cop will reset the mcu when it times out. therefore, it is recommended that the cop watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the cop time-out period. february 12, 1997 general release specification mc68hc05cl4 low power modes motorola rev 2.0 6-3 figure 6-1. stop/halt/wait flowcharts n y y n n n n y y y y y 1.fetch reset vector or 2.service interrupt a.stack b.set i-bit c.vector to interrupt routine external reset? internal cop interrupt? stop external oscillator, stop internal timer clock, stop callerid module, and reset start-up delay restart external oscillator, and stabilization delay stop internal processor clock, clear i-bit in ccr end of start-up delay internal cop reset? external oscillator active, and internal timer clock active restart internal processor clock stop internal processor clock, clear i-bit in ccr external h/w interrupt? external reset? stop wait n internal interrupt? y n n external h/w interrupt? n internal interrupt? y general release specification february 12, 1997 motorola low power modes mc68hc05cl4 6-4 rev 2.0 february 12, 1997 general release specification mc68hc05cl4 input/output ports motorola rev 2.0 7-1 section 7 input/output ports in the single-chip mode there are 30 i/o lines fourteen of which are arranged as one 8-bit i/o port (port a) and one 6-bit i/o port (port b). the remaining sixteen lines arranged as two 8-bit ports, port c and port d. the individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (ddrs). when port c and d are con?ured as outputs, they are the lcd frontplanes. also, if enabled by software, pa4 to pa7 will have additional functions for keyboard interrupt. 7.1 parallel ports a and b port a, is 8-bit bidirectional port and port b is a 6-bit bidirectional port. each port pin is controlled by the corresponding bits in a data direction register and a data register as shown in figure 7-1 . the functions of the i/o pins are summarized in table 7-1 . figure 7-1. port i/o circuitry i/o pin read data write data data register bit internal hc05 data bus reset (rst) read/write ddr data direction register bit output general release specification february 12, 1997 motorola input/output ports mc68hc05cl4 7-2 rev 2.0 table 7-1. port a & b i/o functions 7.1.1 port a and b data registers each port i/o pin has a corresponding bit in the port data register. when a port pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. when a port pin is programmed as an input, any read of the port data register will return the logic state of the corre- sponding i/o pin. the locations of the data registers for port a & b are at $0000, $0001. the port data registers are unaffected by reset. 7.1.2 port a and b data direction registers each port i/o pin may be programmed as an input by clearing the corresponding bit in the ddr, or programmed as an output by setting the corresponding bit in the ddr. if keyboard interrupt enable bits are set for any of pa4 to pa7 (see section 7.2.3 ), these bits are not affect by ddr. the ddrs for port a and port b are located at $0004 and $0005 respectively. the ddrs are cleared by reset. note a ?litch can be generated on an i/o pin when changing it from an input to an output unless the data register is ?st pre-conditioned to the desired state before changing the corresponding ddr bit from a zero to a one. 7.2 ports c and d port c and d are 8-bit ports shared with lcd frontplanes fp29 - fp44. each port pin is controlled by the corresponding bits in a port con?uration register as shown in figure 7-2 . the functions of these pins are summarized in table 7-2 . r/w ddr i/o pin functions 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read. february 12, 1997 general release specification mc68hc05cl4 input/output ports motorola rev 2.0 7-3 figure 7-2. port c/d circuitry table 7-2. port c and d pin functions 7.2.1 port c and d data registers when a port pin is con?ured as an input, any read of the port data register will return the logic state of the corresponding i/o pin. the locations of the data reg- isters for port c & d are at $0002, $0003. the port data registers are unaffected by reset. when the port is con?ured as lcd output any read of the port will return a zero value. 7.2.2 port c and d con?uration registers each port c and d pin may be con?ured as an input by clearing the correspond- ing bit in the cfg, or programmed as an lcd output by setting the corresponding bit in the cfg. the cfg for port c & d are located at $0006, $0007. the cfgs are cleared by reset. 7.2.3 keyboard interrupt keyboard interrupt function is associated with bit 4 to bit 7 of port a. the function is enabled by setting the keyboard interrupt enable bits kbie4 - kbie7 (bits 4 - 7 in kbi register at $0011).when a kbie bit is set, the corresponding port a pin r/w cfg i/o pin functions 0 0 the i/o pin is in input mode. 1 0 the state of the i/o pin is read. 0 1 pin is an lcd frontplane output controlled by the lcd module 1 1 pin is an lcd frontplane output controlled by the lcd module i/o pin read data internal hc05 data bus reset (rst) read/write cfg configuration register bit output lcd data general release specification february 12, 1997 motorola input/output ports mc68hc05cl4 7-4 rev 2.0 will be con?ured into an input pin , and a pull-up resistor is connected to the pin. when a high to low transition is sensed on the pin, a keyboard interrupt will be generated, provided the i-bit in the ccr is cleared. the interrupt signal is latched, and it should be cleared by writing a? to the kbic bit (bit 0 of kbi register) in the interrupt service routine. this should be cleared after the key is debounced, or unwanted keyboard interrupt signal will be gener- ated. the keyboard interrupt can be con?ured to be either negative-edge sensitive or level sensitive. the interrupt vector address is shared with the irq and the inter- rupt service routine is speci?d by the contents of the memory locations $1ffa and $1ffb. 7.2.4 kbi register kbic?eyboard interrupt clear writing a? to this bit will clear the keyboard interrupt ?g latch. this bit should be cleared in the keyboard interrupt service routine, or the cpu will keep on serving this interrupt. this bit always reads?? kbif?eyboard interrupt flag key board interrupt ?g, this bit is set when a port a pin pa4-pa7 is pulled low provided the corresponding kbie bit is set. when this bit is set an interrupt is generated. this bit should be cleared in the keyboard interrupt service routine, or the cpu will keep on serving this interrupt. kedge?eyboard interrupt edge when this bit is set the key board interrupt is negative edge sensitive and when this bit is clear the interrupt is level sensitive/edge sensitive. kbe7-4?eyboard interrupt enables 7-4 port a i/o lines selected by kbe4-kbe7 will be con?ured as input lines with an internal pull-up resistor of 50 k w . once a high to low transition is sensed on any of the input lines of pa4-pa7 selected by the kbi register, provided the interrupt mask bit of the condition code register is cleared, a keyboard interrupt is generated. power-on or external reset will clear these bits. kbe5 0 7 0000000 6543210 kbe4 kbe6 w r kbir $0011 reset kbe7 kbif 0 kbic 0 kedge february 12, 1997 general release specification mc68hc05cl4 timers motorola rev 2.0 8-1 section 8 timers the mcu has two independent timers, the multi-functional timer and the core timer. 8.1 multi-functional timer the timer consists of a 16-bit free-running counter driven by a ?ed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. refer to figure 8-1 for a timer block diagram. because the timer has a 16-bit architecture, each speci? functional segment (capability) is represented by two registers. these registers contain the high and low byte of that functional segment. generally, accessing the low byte of a speci? timer function allows full control of that function; however, an access of the high byte inhibits that speci? timer function until the low byte is also accessed. note the i-bit in the ccr should be set while manipulating both the high and low byte register of a speci? timer function to ensure that an interrupt does not occur. 8.1.1 counter the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1a-$1b (counter alternate register). a read from only the least signi?ant byte (lsb) of the free-running counter ($19, $1b) receives the count value at the time of the read. if a read of the free-running counter or counter alternate register ?st addresses the most signi?ant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains ?ed after the ?st msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter general release specification february 12, 1997 motorola timers mc68hc05cl4 8-2 rev 2.0 alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb must also be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer over?w ?g (tof). there- fore, the counter alternate register can be read at any time without the possibility of missing timer over?w interrupts due to clearing of the tof. february 12, 1997 general release specification mc68hc05cl4 timers motorola rev 2.0 8-3 figure 8-1. timer block diagram mc68hc05 internal bus interrupt circuit internal timer clock (ntf1) ocf tof icf ocie olvl iedg icie toie ? 4 8-bit buffer 16-bit free running counters input capture register output compare register alternate counter register output compare circuit overflow detect circuit edge detect circuit interrupt logic tcr tsr reset tcmp tcap high byte low byte $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b d ck q general release specification february 12, 1997 motorola timers mc68hc05cl4 8-4 rev 2.0 figure 8-2. timer state timing diagram for reset figure 8-3. timer state timing diagram for timer over?w $fffc $fffd $fffe $ffff internal processor clock internal reset t00 t01 t10 t11 counter (16 bit) reset (external, lvr or por) internal timer clocks note: the counter register and timer control register are the only ones affected by reset $fffe $0000 $0001 $0002 internal processor clock t00 t01 t10 t11 counter (16 bit) timer overflow flag (tof) internal timer clocks note: the tof bit is set at timer state t11 (transition of counter from $ffff to $0000). it is cleared by read of the timer status register during the internal processor clock high time followed by a read of the counter low register. $ffff february 12, 1997 general release specification mc68hc05cl4 timers motorola rev 2.0 8-5 the free-running counter is con?ured to $fffc during reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator start-up delay. because the free-running counter is 16 bits preceded by a ?ed divide-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. when the counter rolls over from $ffff to $0000, the tof bit is set. an interrupt can also be enabled when counter roll over occurs by setting its interrupt enable bit (toie). in some particular timing control applications it may be desirable to reset the 16- bit free running counter under software control. when the low byte of the counter ($19 or $1b) is written to, the counter is con?ured to its reset value ($fffc). the divide-by-4 prescaler is also reset and the counter resumes normal counting operation. all of the ?gs and enable bits remain unaltered by this operation. if access has previously been made to the high byte of the free running counter ($18 or $1a), then the reset counter operation terminates the access sequence. 1 7 1 11 1 111 6543210 w r cnth $0018 reset cnt15 cnt14 cnt13 cnt12 cnt11 cnt10 cnt9 cnt8 1 7 1 11 1 100 6543210 w r cntl $0019 reset cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 counter reset 1 7 1 11 1 111 6543210 w r acnth $001a reset acnt15 acnt14 acnt13 acnt12 acnt11 acnt10 acnt9 acnt8 1 7 1 11 1 100 6543210 w r acntl $001b reset acnt7 acnt6 acnt5 acnt4 acnt3 acnt2 acnt1 acnt0 counter reset general release specification february 12, 1997 motorola timers mc68hc05cl4 8-6 rev 2.0 8.1.2 output compare register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for several pur- poses, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. the output compare register contents are compared with the contents of the free- running counter continually, and if a match is found, the corresponding output compare ?g (ocf) bit is set and the corresponding output level (olvl) bit is clocked to an output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written ?st. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare ?g (ocf) is set or clear. x 7 x xx x xxx 6543210 w r ocmph $0016 reset oc15 oc14 oc13 oc12 oc11 oc10 oc9 oc8 x 7 x xx x xxx 6543210 w r ocmpl $0017 reset oc7 oc6 oc5 oc4 oc3 oc2 oc1 oc0 february 12, 1997 general release specification mc68hc05cl4 timers motorola rev 2.0 8-7 figure 8-4. timer state timing diagram for output compare $ffeb $ffed $ffee $ffef internal processor clock t00 t01 t10 t11 counter(16 bit) output compare flag (ocf) internal timer clocks 1. the cpu writes to the compare register may take place at any time, but a compare only occurs at timer state t01. thus, a 4-cycle different may exist between the write to the compare register and the actual compare. 2. internal compare takes place during timer state t01. 3. ocf is set at timer state t11 which follows the comparison match ($ffed in this example). $ffec compare register compare register latch 1 2 3 cpu writes $ffed $ffed general release specification february 12, 1997 motorola timers mc68hc05cl4 8-8 rev 2.0 8.1.3 input capture register two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a de?ed transition. the level transition which triggers the counter transfer is de?ed by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture ?g (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register ($14) msb, the counter transfer is inhib- ited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. x 7 x xx x xxx 6543210 w r icaph $0014 reset ic15 ic14 ic13 ic12 ic11 ic10 ic9 ic8 x 7 x xx x xxx 6543210 w r icapl $0015 reset ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 february 12, 1997 general release specification mc68hc05cl4 timers motorola rev 2.0 8-9 figure 8-5. timer state timing diagram for input capture 8.1.4 timer control register (tcr) the tcr is a read/write register containing six control bits. three bits control inter- rupts associated with each of the three ?g bits found in the timer status register. the other two bits control: 1) which edge is signi?ant to the input capture edge detector (i.e., negative or positive), and 2) the next value to be clocked to the out- put level register in response to a successful output compare. the timer control register and the free running counter are the only sections of the timer affected by reset. the tcmp pin is forced low during external reset and stays low until a valid compare changes it to high. the timer control register is illustrated below by a def- inition of each bit. $ffeb $ffed $ffee $ffef internal processor clock t00 t01 t10 t11 counter(16 bit) input capture flag (icf) internal timer clocks note: if the input edge occurs in the shaded area from one timer state t10 to the other timer state t10 the input capture ?g is set during the next state t11. $ffec capture register internal capture latch $???? $ffed note input edge 0 icie 0 7 iedg 0 0000 x 1 6543210 0 0 olvl w r tcr $0012 reset toie ocie general release specification february 12, 1997 motorola timers mc68hc05cl4 8-10 rev 2.0 icie if the input capture interrupt enable (icie) bit is set, a timer interrupt is enable when the icf status ?g is set, provided the i bit in ccr is cleared. if the icie bit is cleared, the interrupt is inhibited. the icie bit is cleared by reset. ocie if the output compare interrupt enable (ocie) bit is set, a timer interrupt is enabled whenever the ocf status ?g is set, provided the i bit in ccr is cleared. if the ocie bit is cleared, the interrupt is inhibited. the ocie bit is cleared by reset. toie if the timer over?w interrupt enable (toie) bit is set, a timer interrupt is enabled whenever the tof status ?g is set, provided the i bit in ccr is cleared. if the toie bit is cleared, the interrupt is inhibited. the toie bit is cleared by reset. iedg the value of the input edge (iedg) bit determines which level transition on tcap pin will trigger a free running counter transfer to the input capture regis- ter. reset does not affect the iedg bit. 0 = negative edge 1 = positive edge olvl the value of the output level (olvl) bit is clocked into the output level register by the next successful output compare and will appear at tcmp pin. this bit and the output level register are cleared by reset. 0 = low output 1 = high output 8.1.5 timer status register (tsr) the timer status register is a read-only register and is illustrated below followed by a de?ition of each bit. refer to timing diagrams shown in figure 8-2 , figure 8-3 and figure 8-4 for timing relationship to the timer status register bits. x 7 x x0 0 000 6543210 0 0 0 0 0 tof ocf icf w r tsr $0013 reset february 12, 1997 general release specification mc68hc05cl4 timers motorola rev 2.0 8-11 icf?nput capture flag the input capture ?g (icf) is set when a proper edge has been sensed by the input capture edge detector. it is cleared by a processor access of the timer status register (with icf set) followed by accessing the low byte ($15) of the input capture register. reset does not affect the input compare ?g. ocf?utput compare flag the output compare ?g (ocf) is set when the output compare register con- tents matches the contents of the free running counter. the ocf is cleared by accessing the timer status register (with ocf set) and then accessing the low byte ($17) of the output compare register. reset does not affect the output compare ?g. tof?imer over?w flag the timer over?w ?g (tof) bit is set by transition of the free run from $ffff to $0000. it is cleared by accessing the timer status register (with tof set) fol- lowed by an access of the free running counter least signi?ant byte ($19). reset does not affect the tof bit. accessing the timer status register satis?s the ?st condition required to clear status bits. the remaining step is to access the register corresponding to the sta- tus bit. a problem can occur when using the timer over?w function and reading the free- running counter at random times to measure an elapsed time. without incorporat- ing the proper precautions into software, the timer over?w ?g could unintention- ally be cleared if: 1)the timer status register is read or written when tof is set, and 2)the lsb of the free-running counter is read but not for the purpose of ser- vicing the ?g. the counter alternate register at address $1a and $1b contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer over?w ?g in the timer status register. 8.1.6 operation during low power mode during the wait and stop modes, the timer stops and holds at its current state, retaining all data, and resumes operation from this point when external interrupt (irq), or internal interrupt is received. general release specification february 12, 1997 motorola timers mc68hc05cl4 8-12 rev 2.0 8.2 core timer the core timer (or ctimer) for this device is a 15-stage multi-functional ripple counter. the features include timer over flow, power-on reset (por), real time interrupt, and cop watchdog timer as seen in figure 8-6 , the timer is driven by the internal bus clock divided by four with a ?ed prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the ctimer counter register (ctcr) at address $08. a timer over?w function is imple- mented on the last stage of this counter, giving a possible interrupt at the rate of e/1024. two additional stages produce the por function at e/4064. the timer counter bypass circuitry (available only in test mode) is at this point in the timer chain. this circuit is followed by two more stages, with the resulting clock (e/ 16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1 of 4 selector. the output of the rti circuit is further divided by eight to drive the optional cop watchdog timer circuit. the rti rate selector bits, and the rti and ctof enable bits and ?gs are located in the ctimer control and status register(ctcsr) at location $1a. 8.2.1 computer operating properly (cop) watchdog reset the cop watchdog timer function is implemented on this device by using the out- put of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 8-1 . if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. preventing a cop time-out is done by writing a ? to bit 0 of address $1ff0. this location is shared with user rom byte. and reading this location will return the user rom data. when the cop is cleared, only the ?al divide by eight stage (output of the rti) is cleared.if the cop (computer operating properly) watchdog timer circuit times out, an internal reset is generated and the reset vector is fetched. note cop watchdog reset function is enabled or disabled by a mask option. february 12, 1997 general release specification mc68hc05cl4 timers motorola rev 2.0 8-13 figure 8-6. core timer block diagram cop clear internal bus $09b ctcr 7-bit counter interrupt circuit $08 ctcsr rti select circuit overflow circuit detect cop watchdog resetable timer ( ? 8) to reset logic to interrupt logic 8 8 f op f op /2 2 f op /2 10 por tcbp tcsr tcr internal processor clock ctof rtif ctofe rtie rt1 rt0 ctimer control & status register core timer counter register (tcr) ? 4 general release specification february 12, 1997 motorola timers mc68hc05cl4 8-14 rev 2.0 8.2.2 ctimer control and status register (ctcsr) the tcsr contains the timer interrupt ?g, the timer interrupt enable bits, and the real time interrupt rate select bits. ctof?ore timer over?w flag core timer over flow bit is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $ff to $00. clearing the tof is done by writ- ing a ? to it. writing a ? to ctof has no effect on the bit s value. reset clears ctof. rtif?eal time interrupt flag the real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. the clock frequency that drives the rti circuit is e/2 13 with three addi- tional divider stages. real time interrupt flag is a clearable, read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. clearing the rtif is done by writing a ? to it. writing a ? to rtif has no effect on this bit. reset clears rtif. ctofe?ore timer over?w enable when the core timer over flow enable bit is set, a cpu interrupt request is generated when the tof bit is set, provided the i bit in ccr is cleared. reset clears this bit. rtie?eal time interrupt enable when the real time interrupt enable bit is set, a cpu interrupt request is gen- erated when the rtif bit is set, provided the i bit in the ccr is cleared. reset clears this bit. rt1:rt0?eal time interrupt select bits these two real time interrupt rate select bits select one of four taps from the real time interrupt circuit. the settings for rti is listed in table 8-1 . reset sets these rt0 and rt1, selecting the lowest periodic rate and therefore the maxi- mum time in which to alter these bits if necessary. ctof 0 7 rt1 0 0000 1 1 6543210 0 0 rtie rt0 w r ctcsr $0008 reset ctofe rtif february 12, 1997 general release specification mc68hc05cl4 timers motorola rev 2.0 8-15 note care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modi?d during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing rti taps. 8.2.3 ctimer counter register (ctcr) the core timer counter register is a read-only register which contains the cur- rent value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions includ- ing a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted anytime during operation (other than por), the counter chain will be cleared. 8.2.4 operation during low power mode the timer is cleared when going into stop mode. when stop is exited by an external interrupt or an external reset, the internal oscillator will resume, fol- lowed by 4064 cycles internal processor stabilization delay. the timer is then cleared and operation resumes. the cpu clock halts during the wait mode, but the timer remains active. if the interrupts are enabled, the timer interrupt will cause the processor to exit the wait mode. 0 7 0 00 0 000 6543210 ct0 ct2 ct1 ct3 ct4 ct5 ct6 ct7 w r ctcr $0009 reset general release specification february 12, 1997 motorola timers mc68hc05cl4 8-16 rev 2.0 table 8-1. rti and cop rates rt1:rt0 rti rate 00 15.6 ms 01 31.2 ms 10 62.5 ms 11 7.81 ms div. ratio 2 15 2 16 2 17 2 14 cop rate (rti 7) 109 ms 219 ms 438 ms 54.7 ms bus frequency = 2.10 mhz february 12, 1997 general release specification mc68hc05cl4 lcd driver motorola rev 2.0 9-1 section 9 lcd driver the lcd driver module supports a 45 frontplane by 8 backplane or 49 frontplane by 4 backplane display. this allows a maximum of 360 lcd segments to be driven. each segment is controlled by a corresponding bit in the lcd ram. on reset or on power-up, the drivers are disabled via a display on (dison) bit in the lcd control (lcdctr) register, and all the port pins which are shared with this subsystem are con?ured as inputs. table 9-1 shows a block diagram of the lcd subsystem. figure 9-1. lcd block diagram. 9.1 lcd ram. the data to be displayed by the lcd is written to a 45 byte display ram located at $20 in the memory map. the bits are organized according to section 9-1 . with a 1 stored in a given location resulting in the corresponding display segment being 8 13 internal signals 8 bp(0:7) display ram lcd data latch segment driver fp(0:44) backplane driver control logic internal data bus internal address bus voltage generator 45x8 general release specification february 12, 1997 motorola lcd driver mc68hc05cl4 9-2 rev 2.0 activated. the lcd ram is a dual port ram that interfaces with the internal address and data buses of the mcu. it is possible to read from lcd ram loca- tions for scrolling purposes. when the display is con?ured to operate with four backplanes only bit0-bit4 of each byte in the display ram are used expect for the four bytes at $0020-$0023 where bit4-bit7 are used for the extra frontplanes which replace backplanes 4-7 on the pins. when the display is disabled, the lcd ram can be used as on-chip ram. table 9-1. lcd ram organization. 9.2 lcd operation table 9-2 shows the backplane waveforms and some examples of frontplane waveforms which are dependent on the lcd segments to be driven as de?ed in the lcd ram. the lcd driver module hardware uses the data in the lcd ram to construct the frontplane waveform to meet this criterion. the backplane wave- forms are continuous and repetitive (every 2 frames); they are ?ed and not affected by the data in the lcd ram.during wait mode the lcd drivers function as normal and will keep the display active if the dison bit (bit0 of $0a) is set. the lcd drivers can be con?ured to operate with either 8 backplanes or 4 back- planes under software control. the bias ratio is 1/4 for a 8 backplane lcd. the voltage levels required are gener- ated internally by a resistive divider between vdd and vss. addr data 0123 4 5 6 7 $0020 fp0-bp0 fp0-bp1 fp0-bp2 fp0-bp3 fp0-bp4 fp45-bp0 fp0-bp5 fp45-bp1 fp0-bp6 fp45-bp2 fp0-bp7 fp45-bp3 $0021 fp1-bp0 fp1-bp1 fp1-bp2 fp1-bp3 fp1-bp4 fp46-bp0 fp1-bp5 fp46-bp1 fp1-bp6 fp46-bp2 fp1-bp7 fp46-bp3 $0022 fp2-bp0 fp2-bp1 fp2-bp2 fp2-bp3 fp2-bp4 fp47-bp0 fp2-bp5 fp47-bp1 fp2-bp6 fp47-bp2 fp2-bp7 fp47-bp3 $0023 fp3-bp0 fp3-bp1 fp3-bp2 fp3-bp3 fp3-bp4 fp48-bp0 fp3-bp5 fp48-bp1 fp4-bp6 fp48-bp2 fp4-bp7 fp48-bp3 . $n fpn-bp0 fpn-bp1 fpn-bp2 fpn-bp3 fpn-bp4 fpn-bp5 fpn-bp6 fpn-bp7 . . $004b fp43- bp0 fp43- bp1 fp43- bp2 fp43- bp3 fp43-bp4 fp43-bp5 fp43-bp6 fp43-bp7 $004c fp44- bp0 fp44- bp1 fp44- bp2 fp44- bp3 fp44-bp4 fp44-bp5 fp44-bp6 fp44-bp7 february 12, 1997 general release specification mc68hc05cl4 lcd driver motorola rev 2.0 9-3 figure 9-2. lcd waveforms with 8 back planes. frame one vlcd v2 v0 v1 v0 bp0 bp1 bp2 bp7 fp x fp y fp z v3 vlcd v2 v1 v3 v0 vlcd v2 v1 v3 v0 vlcd v2 v1 v3 vlcd v2 v1 v3 v0 vlcd v2 v1 v3 v0 vlcd v2 v1 v3 v0 general release specification february 12, 1997 motorola lcd driver mc68hc05cl4 9-4 rev 2.0 9.3 lcd voltage generation figure 9-3. voltage generation shows the resistive divider chain network that is used to produce the various lcd waveforms outlined in the previous section. the lcd system can be disabled by setting the dison bit to 0. the voltage levels of the lcd drive waveforms and hence the contrast of the lcd can be altered by selecting appropriate resistors by setting the corresponding values to the cc1 to cc3 bits in the lcdctr register. figure 9-3. voltage generation v3 v2 dison r2 r1 r0 vdd v0 vlcd cc1 cc2 cc3 rc1=4r rc2=2r rc3=r v1 r3 february 12, 1997 general release specification mc68hc05cl4 lcd driver motorola rev 2.0 9-5 9.4 lcd control register (lcdctr) dison?isplay on the display is on when this bit is ? and off when this bit is ?? setting this bit to ? also disconnects the voltage generator resistor chain from vdd, thus reduc- ing power. lc, fc if the quality of the display is not critical, the lcd block on the device can be put into a low current mode using the fc and lc bits in the lcd register. by select- ing the appropriate values for each bit, as shown in table 9-2 , an extra resistor can be added to the divider chain, hence reducing the current consumption. when normal quality is required for the display, the fast charge option should be used which resumes default resister values for a pre-determined period in each frame. the default value of these resistors is approximately 30 k w . mx4 when this bit is set the system operates with 49 frontplanes and 4 backplanes, when cleared the system operates with 45 frontplanes and 8 backplanes. cc1 - cc3?ontrast control these bits can be used to select the values of the contrast control resistors. when set to 1 the corresponding resistor will be shorted. on reset these bits are set to 0. 76543210 lcdctr1 $000a read cc3 cc2 cc1 mx4 fc lc dison write reset 0 0 0 u 0000 u = unaffected table 9-2. voltage divider resistor options lc fc action 0 0 default value of ? 30k w 0 1 no action 1 0 resistor value ? 30k w per resistor selected 11 fast-charge, for a period lcdclk/128 in each time slot the resistor values are reduced to default general release specification february 12, 1997 motorola lcd driver mc68hc05cl4 9-6 rev 2.0 february 12, 1997 general release specification mc68hc05cl4 caller id motorola rev 2.0 10-1 section 10 caller id this section describes the caller id module of the mc68hc05cl4. 10.1 introduction. the caller id module demodulates the bell 202 1200 baud fsk asynchronous data. this module consists of four major building blocks fsk demodulator, carrier detect, ring detect and the power management circuit. the block diagram of this module is shown in figure 10-1 . figure 10-1. clid block diagram tip ring + ring 202 demod detect circuit bpf valid data detect power management carrier detect circuit carrier detect interface ring detect interface demod data tcap tcmp control/status register 1 control/status register 2 serial data select interrupt circuit mcu data bus sdsl cpu interrupt ring det 1 ring det 2 ring time power ctl from cpu general release specification february 12, 1997 motorola caller id mc68hc05cl4 10-2 rev 2.0 10.1.1 fsk demodulator the demodulator recovers the fsk data transmitted over the telephone line. it ?st band limits the incoming signal with a bandpass ?ter whose output is fed to the carrier detect threshold comparator as well as to the differential detector for demodulation. the recovered signal consists of both the channel seizure informa- tion and the message words. the original serial raw data is made available via the mcu registers. see section 10.2.2 . 10.1.2 carrier detector the carrier detect block will validate the carrier signal from the filter section. the asynchronous carrier signal is considered valid if present for a minimum of 25ms. a carrier dropout is con?med if it is silent for more than 8ms. the carrier detect signal will remain low until a dropout condition is detected. the carrier detect out- put is available in a read-only register (cd ) in control/status register 2 (clcsr2). it can also be overwritten by writing to cdo (carrier detect override) in the control/status register(clcsr1) when enabled by writing a ? to cdoe (carrier detect override enable) in the clcsr3 register. a valid carrier can also produce an interrupt to the cpu when enabled by the cdie bit in clcsr1. see section 10.2.1 and section 10.2.2 . 10.1.3 ring detector the ring detect circuit validates the input ring signal (rd2) and the ring detect out- put is available in a read-only register (rd ) in control/status register 2 (clcsr2). it can also be overwritten by writing to rdo (ring detect override) in the control/status register (clcsr1) when enabled by writing a ? to rdoe (ring detect override enable) in the clcsr3 register. a valid ring signal can also produce an interrupt to the cpu when enabled by the rdie bit in clcsr1. see section 10.2.1 and section 10.2.2 . if the ring detect feature is not required it can be disabled by writing to rdpw bit in the clcsr2 register. see section 10.2.1 and section 10.2.2 10.1.4 power management if the ring detect module is used, it should be enabled by setting the rdpw bit before executing the stop instruction. when the r t signal is below the threshold, r d2 v t (see figure 10-5 ) the oscillator circuit is forced on and the ring signal is validated. if the r t rises above the threshold before the ring signal is validated the oscillator will stop and the mcu will stay in the stop mode. however, if a valid ring is detected an interrupt is generated provided the ring detect interrupt enable bit (rdie) is set. the interrupt will wake the mcu from the stop mode and the clocks to all enabled modules will start. at this time if the cpu is not required the wait mode can be entered. february 12, 1997 general release specification mc68hc05cl4 caller id motorola rev 2.0 10-3 if the carrier detect module is enabled before entering the wait mode by cdpw bit, it will start processing the incoming data. when a valid carrier is detected an interrupt is generated if enabled by the cdie bit. the interrupt will take the cpu out of the wait mode. figure 10-2. cpu-clid power-up sequence from stop mode cpu stop mode rdpw? power on rdie? rd interrupt/ yes yes cpu wait mode cdpw? power on cdie? cd interrupt yes yes wake up cpu valid yes no no ring detect start osc no no no rt? carrier detect general release specification february 12, 1997 motorola caller id mc68hc05cl4 10-4 rev 2.0 figure 10-3. cpu-clid power-up sequence from wait mode 10.1.5 data interface the demodulated data from this module is available in serial. the serial data can be read from cidsd (bit 2) of the clcsr2 register. this data includes the alter- nate 0 and 1 pattern, 150 ms marking which precedes data. at all other times the demodulator output bit is high. cpu wait mode cdpw? power on cdie? cd interrupt yes yes wake up cpu no no carrier detect february 12, 1997 general release specification mc68hc05cl4 caller id motorola rev 2.0 10-5 10.2 caller id register 10.2.1 control/status register1 (clcsr1) cdo ?carrier detect override when enabled by the cdoe bit in the clcsr3 register, the carrier detect can be forced by writing a zero to this bit. on reset this bit is set to one. rdo ?ring detect override when enabled by rdoe in the clcsr3 register, the ring detect can be forced by writing a zero to this bit. on reset this bit is set to one. cdie?arrier detect interrupt enable when enabled (set) an interrupt will be generated when a carrier is detected or forced by writing to cdo. cdif?arrier detect interrupt flag provided the carrier detect interrupt is enabled by setting the cdie, this bit is set when the carrier is detected. when this ?g is one an interrupt is generated. the cdif bit must be cleared by writing a zero. rdie?ing detect interrupt enable when enabled (set) an interrupt will be generated when a carrier is detected or forced by writing to rdo. rdif?ing detect interrupt flag provided the ring detect interrupt is enabled by setting the rdie, this bit is set when the ring is detected. when this ?g is one an interrupt is generated. the rdif bit must be cleared by writing a zero. 76543210 clcsr1 $000c read rdif rdie cdif cdie rdo cdo write 0 0 reset 0000uu11 u = unaffected general release specification february 12, 1997 motorola caller id mc68hc05cl4 10-6 rev 2.0 10.2.2 control/status register 2 (clcsr2) cd ?arrier detect this read only bit returns the value of the carrier detect signal which goes low when a valid carrier is detected and remains low while the carrier remains valid. rd ?ing detect this read only bit returns the value of the ring detect signal which goes low when a valid ringing signal is detected and remains low as long as the ringing signal remains valid. cidsd?aller id serial data this read only bit returns the value of the caller id serial data (output of the on chip demodulator) whenever the cd is low. this data includes the alternate 0 and 1 pattern, 150 ms marking which precedes the data. at all other times the demodulator output is high. the source of this data bit is selected by bit 7 in this register. cdpw?arrier detect power up carrier detection is enabled when this bit is set. an interrupt will be generated when a valid carrier is detected provided the cdie bit in the clcsr1 register is set. rdpw?ing detect power up ring detection is enabled when this bit is set. an interrupt will be generated when a valid ring is detected provided the rdie bit in the clcsr1 register is set. 10.2.3 control/status register 3 (clcsr3) cdoe - carrier detect override enable setting this bit allows the user to force the carrier detect signal by writing a zero to cdo, bit 0 in the clcsr1 register. 76543210 reg $000d read rdpw cdpw cidsd rd cd write reset u 0 0 uuuuu u = unaffected 76543210 reg $000d read sdsl rdedg cdedg rdoe cdoe write reset 0 u u u 0000 u = unaffected february 12, 1997 general release specification mc68hc05cl4 caller id motorola rev 2.0 10-7 rdoe ?ring detect override enable setting this bit allows the user to force the ring detect signal by writing a zero to rdo, bit 1 in the clcsr1 register. cdedg when this bit is set, the carrier detect interrupt flag (bit 5 of clcsr1) will be triggered at the falling edge of the carrier detect signal and will be cleared by pulling reset low. if cdedg is kept low, the interrupt flag is active for as long as the carrier detect signal is valid. rdedg when this bit is set, the ring detect interrupt flag (bit 7 of clcsr1) will be triggered at the falling edge of the ring detect signal and will be cleared by pull- ing reset low. if rdedg is kept low, the interrupt flag is active for as long as the ring detect signal is valid. sdsl?erial data select when this bit is zero, the cidsd bit is the output of the on-chip demodulator. when this bit is set it disconnects the demodulator output from the cidsd which appears at the tcmp pin and the tcap pin now becomes the input for the cidsd bit. this allows the external caller id device to interface directly with the mcu. on reset this bit is cleared. general release specification february 12, 1997 motorola caller id mc68hc05cl4 10-8 rev 2.0 10.3 design parameters the data signalling interface conforms to the recommended operating ranges of the physical layer test parameters for type 1 cpe as described in bellcore publication sr-nwt-003004. table 10-1. typical input parameters table 10-2. critical design characteristics parameters operating range units mark frequency 1188 to 1212 hz space frequency 2178 to 2222 hz mark level ?2 to ?2 dbm space level ?2 to ?6 dbm carrier frequency 1700 hz twist immunity 10 dbm baud rate 1188 to 1212 baud ringing frequency 20 hz noise immunity (signal to noise ratio) ?0 (for noise below 200 and above 3200 hz) db 25 (for noise between 200 and 3200 hz) channel seizure delay 250 to 3600 ms input impedance 500 k w immunity to cs and ms 10 ms characteristics typical unit input tip/ring sensitivity ?0 dbm bandpass filter (bpf) frequency response (relative to 1700 hz @ 0 db) 60 hz 1000 hz 2400 hz 3 3300 hz ?8 ? ? ?4 db db db db carrier detect sensitivity ?0 dbm february 12, 1997 general release specification mc68hc05cl4 caller id motorola rev 2.0 10-9 table 10-3. switching characteristics (v dd = 5v; t a =25 c) the transmission level from the terminating ?entral of?e will be ?3.5 dbm 1.0. the expected worst case attenuation through the loop is expected to be 20db. the receiver therefore, should have a sensitivity of approximately ?4.5 db to handle the worst case installations. 10.4 message format figure 10-4. single message format description symbol minimum typical maximum unit osc start-up t dosc 2 ms carrier detect acquisition t daq 14 25 ms end of carrier detect t dch 8 ? ms 0101 1 data 2 sec 4 sec 2 sec 0.5ssec 0.5 sec channel seizure mark message message message chk sum signal type word length word word(s) word mark bits (0-10) general release specification february 12, 1997 motorola caller id mc68hc05cl4 10-10 rev 2.0 figure 10-5. clid timing diagram 0101 1 data 2 sec 4 sec 2 sec 0.5 sec 0.5 sec data word ring input ring detect ring detect interrupt flag carrier detect carrier detect interrupt flag demodulated serial data ring time r d2 v t flag cleared by software flag cleared by software february 12, 1997 general release specification mc68hc05cl4 instruction set motorola rev 2.0 11-1 section 11 instruction set this section describes the addressing modes and instruction types. 11.1 addressing modes the cpu uses eight addressing modes for ?xibility in accessing data. the addressing modes de?e the manner in which the cpu ?ds the data required to execute an instruction. the eight addressing modes are the following: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 11.1.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry ?g (sec) and increment accumulator (inca). inher- ent instructions require no memory address and are one byte long. 11.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no memory address and are two bytes long. the opcode is the ?st byte, and the immediate data value is the second byte. 11.1.3 direct direct instructions can access any of the ?st 256 memory addresses with two bytes. the ?st byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. brset and brclr are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. general release specification february 12, 1997 motorola instruction set mc68hc05cl4 11-2 rev 2.0 11.1.4 extended extended instructions use only three bytes to access any address in memory. the ?st byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 11.1.5 indexed, no offset indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the ?st 256 memory locations. the index register contains the low byte of the conditional address of the operand. the cpu auto- matically uses $00 as the high byte, so these instructions can address locations $0000?00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 11.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the ?st 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the conditional address of the operand. these instructions can access locations $0000?01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the ?st 256 memory loca- tions and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte fol- lowing the opcode. 11.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the conditional address of the operand. the ?st byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. these instructions can address any location in memory. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. february 12, 1997 general release specification mc68hc05cl4 instruction set motorola rev 2.0 11-3 11.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu ?ds the conditional branch destination by adding the signed byte follow- ing the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two s com- plement byte that gives a branching range of ?28 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and veri?s that it is within the span of the branch. 11.1.9 instruction types the mcu instructions fall into the following ?e categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions general release specification february 12, 1997 motorola instruction set mc68hc05cl4 11-4 rev 2.0 11.1.10register/memory instructions most of these instructions use two operands. one operand is in either the accu- mulator or the index register. the cpu ?ds the other operand in memory. table 11-1 lists the register/memory instructions. table 11-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub february 12, 1997 general release specification mc68hc05cl4 instruction set motorola rev 2.0 11-5 11.1.11read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modi?d value back to the memory location or to the register. the test for negative or zero instruction (tst) is an exception to the read-modify-write sequence because it does not write a replacement value. table 11-2 lists the read-modify-write instructions. 11.1.12jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump to subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. all branch instructions use relative addressing. bit test and branch instructions cause a branch based on the state of any read- able bit in the ?st 256 memory locations. these three-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu ?ds the conditional branch destination by adding the third byte to the program counter if the speci?d bit tests true. the bit to be tested table 11-2. read-modify-write instructions instruction mnemonic arithmetic shift left asl arithmetic shift right asr clear bit in memory bclr set bit in memory bset clear clr complement (one? complement) com decrement dec increment inc logical shift left lsl logical shift right lsr negate (two? complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst general release specification february 12, 1997 motorola instruction set mc68hc05cl4 11-6 rev 2.0 and its condition (set or clear) is part of the opcode. the span of branching is from ?28 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. table 11-3 lists the jump and branch instructions. table 11-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr february 12, 1997 general release specification mc68hc05cl4 instruction set motorola rev 2.0 11-7 11.1.13bit manipulation instructions the cpu can set or clear any writable bit in the ?st 256 bytes of memory. port registers, port data direction registers, timer registers, and on-chip ram locations are in the ?st 256 bytes of memory. the cpu can also test and branch based on the state of any bit in any of the ?st 256 memory locations. bit manipulation instructions use direct addressing. table 11-4 lists these instructions. 11.1.14control instructions these register reference instructions control cpu operation during program exe- cution. control instructions, listed in table 11-5 , use inherent addressing. table 11-4. bit manipulation instructions instruction mnemonic clear bit bclr branch if bit clear brclr branch if bit set brset set bit bset table 11-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait general release specification february 12, 1997 motorola instruction set mc68hc05cl4 11-8 rev 2.0 11.1.15instruction set summary table 11-6 is an alphabetical list of all m68hc05 instructions and shows the effect of each instruction on the condition code register. table 11-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles h i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 c b0 b7 0 b0 b7 c february 12, 1997 general release specification mc68hc05cl4 instruction set motorola rev 2.0 11-9 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff p 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 table 11-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc general release specification february 12, 1997 motorola instruction set mc68hc05cl4 11-10 rev 2.0 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ?(m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one? complement) m ? ( ) = $ff ?(m) a ? ( ) = $ff ?(m) x ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ?(m) 1 imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 11-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc m a x m m february 12, 1997 general release specification mc68hc05cl4 instruction set motorola rev 2.0 11-11 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? conditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two? complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix 30 40 50 60 70 ii ff 5 3 3 6 5 nop no operation inh 9d 2 table 11-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 0 b0 b7 c 0 general release specification february 12, 1997 motorola instruction set mc68hc05cl4 11-12 rev 2.0 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 6 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 table 11-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 b0 b7 c february 12, 1997 general release specification mc68hc05cl4 instruction set motorola rev 2.0 11-13 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) ?(m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ?$00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (two? complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit not affected table 11-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc motorola instruction set mc68hc05cl4 11-14 rev 2.0 table 11-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 tax 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb february 12, 1997 general release specification mc68hc05cl4 electrical specification motorola rev 2.0 12-1 section 12 electrical specification 12.1 maximum ratings (voltages referenced to v ss ) this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either v ss or v dd ). 12.2 thermal characteristics rating symbol value unit supply voltage v dd ?.3 to +7.0 v input voltage normal operation self-check mode (irq pin only) v in v ss ?.3 to v dd +0.3 v ss ?.3 to 2v dd +0.3 v v current drain per pin excluding vdd and vss i 25 ma operating temperature range t a 0 to 70 c storage temperature range t stg t l to t h ?5 to +150 c characteristic symbol value unit thermal resistance 80-pin pqfp q ja 60 c/w general release specification february 12, 1997 motorola electrical specification mc68hc05cl4 12-2 rev 2.0 12.3 dc electrical characteristics (v dd = 5.0 vdc 10%, vss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) notes: 1. all values shown re?ct average measurements. 2. typical values at midpoint of voltage range, 25 c only. 3. wait i dd : timer system active, carrier detect and ring detect circuit active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc =4.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l =20 pf on osc2. 5. wait, stop i dd : all ports con?ured as inputs, v il = 0.2 vdc, v ih = v dd ?.2 vdc. 6. stop i dd measured with osc1=v ss . 7. wait i dd is affected linearly by the osc2 capacitance. characteristic symbol min typ max unit output high voltage (i load = ?.8 ma) pa0-pa7, pb0-pb5, tcmp v oh v dd ?.8 v output low voltage (i load = +1.6 ma) pa0-pa7, tcmp, v ol 0.4 v input high voltage pa0-pa7, pb0-pb5, tcap, reset , irq , osc1 v ih 0.7 x v dd ? dd v input low voltage pa0-pa7, pb0-pb5, pc0-pc7, pd0-pd7, tcap, reset , irq , osc1 v il v ss 0.2 x v dd v supply current (see notes) run wait stop 25?c 0?c to +70?c (standard) i dd 7 4.5 36 40 8 5 50 50 ma ma m a m a i/o ports hi-z leakage current pa0-pa7, pb0-pb5 i il 10 m a input current reset , irq , osc1, tcap i in 1 m a capacitance ports (as input or output), reset , irq , osc1, osc2, tcap, c out c in 12 8 pf pf lcd voltage input v lcd v ss ? dd v low voltage interrupt threshold voltage v lvi 4.5 v low voltage reset threshold voltage v lvr 4.0 (100mv hysteresis) v input threshold voltage (caller id) positive going: vdd = 5v (rdi1, rt ) v t+ 2.5 2.75 3.0 v input threshold voltage (caller id) negative going: vdd = 5v (rdi1, rt ) v t 2.0 2.3 2.6 v rdi2 threshold (caller id) r d2 v t 0.9 1.0 1.1 v tip/ring input dc resistance (caller id) r in 500 k w february 12, 1997 general release specification mc68hc05cl4 electrical specification motorola rev 2.0 12-3 12.4 control timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) notes: 1. v dd = 5.0 v dc 10%, v ss = 0 vdc, t a = t l to t h 2. the 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. the minimum period t tltl, t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . characteristic symbol min max units frequency of operation crystal oscillator option external clock source f osc f osc 3.58 3.68 mhz mhz internal operating frequency crystal oscillator (f osc /2) external clock (f osc /2) f op f op 1.79 1.84 mhz mhz cycle time (1/f op )t cyc 540 560 ns crystal oscillator start-up time (crystal oscillator option) t oxon 100 ms stop recovery start-up time (crystal oscillator option) t ilch 100 ms reset pulse width low t rl 1.5 t cyc power-on reset output width 4064 cycle t porl 4064 t cyc watchdog reset output pulse width t dogl ?t cyc watchdog time-out t dog 6144 t cyc timer resolution (note 2) input capture pulse width input capture pulse period t resl t th t tl t tltl 4 540 note 3 4 t cyc ns t cyc irq interrupt pulse width low (edge-triggered) t ilih 125 ns irq interrupt pulse period t ilil note 3 t cyc pa4 to pa7 interrupt pulse period t ihih note 3 t cyc osc1 pulse width t 270 280 ns general release specification february 12, 1997 motorola electrical specification mc68hc05cl4 12-4 rev 2.0 february 12, 1997 general release specification mc68hc05cl4 mechanical specification motorola rev 2.0 13-1 section 13 mechanical specification this section describes the dimensions of the 80-pin qfp package. general release specification february 12, 1997 motorola mechanical specification mc68hc05cl4 13-2 rev 2.0 13.1 80-pin quad-flat-package (case 841b-01) * ( ( ( ( * * * ( ( ( ( ( * ( * ( "! ! " ! ' " ! " "# )) ! " " "" ! " %" " % " &"! " !" ' " " "" " " "# ! )) )) )) " " " "# )) ! ! ! $ " " " !" )) ! ! " # " #! % " #! ! ! ! ! # ! " " " "# )) ! ! " # " #! % " #! ! " " &!! " ! " & # " " " " " % #! " " p -a,b,d- b b detail a f d n section b-b j -h- detail c k q r t w x u -h- 60 61 80 120 21 40 41 detail c -c- m c h m g -b- -a- -d- b a l s v l e detail a ! ! ! ! ! ! ! ! ! ! ! ! ! ! !! february 12, 1997 general release specification mc68hc05cl4 motorola rev 2.0 a-1 appendix a mc68hc705cl4 this section describes the differences between the mc68hc705cl4 and the mc68hc05cl4. a.1 introduction the mc68hc705cl4 is an eprom version of the mc68hc05cl4, and is available for user system evaluation and debugging. the mc68hc705cl4 is functionally identical to the mc68hc05cl4 with the exception of the eprom feature and the self-check routine is replaced by a bootstrap routine. also, the mask option for cop and lvr in the mc68hc05cl4 is replaced by an option register in the mc68hc705cl4. a.2 memory the mc68hc705cl4 has an 8k-byte memory map (see figure a-1 ) consisting of user eprom, ram, bootstrap rom, and i/o. a.2.1 option register ($1d) this register can only be written once following a power-on or external reset, but can be read at any time. lvre?ow voltage reset enable 1 = low-voltage-reset enabled. 0 = low-voltage-reset disabled. cop?omputer operating properly 1 = cop watchdog reset enabled. 0 = cop watchdog reset disabled. refer to section 8 for detailed information on cop watchdog. 76543210 opt $001d read cop lvre write poru0uuu0uu u = unaffected general release specification february 12, 1997 motorola mc68hc05cl4 a-2 rev 2.0 figure a-1. mc68hc705cl4 memory map port a data register port b data register port a direction register port b direction register timer status register timer control register input capture high register input capture low register output compare high register eprom program control register $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f $0000 $001f $0020 $00bf $00c0 $00ff $0100 $044f $0450 $1fef $1fff $1ff0 user registers 32 bytes ram 1k bytes stack 64 bytes ram user vectors 16 bytes ctimer irq swi reset $1ff0 $1ff2 $1ff4 $1ff6 $1ff8 $1ffa $1ffc $1ffe $1ff1 $1ff3 $1ff5 $1ff7 $1ff9 $1ffb $1ffd $1fff user eprom 6k bytes bootstrap vectors 16 bytes 0 31 32 1103 1104 8191 8175 8176 191 192 255 256 core timer control & status register core timer register cdi lcd ram $004c $0050 76 80 output compare low register counter high register counter low register alternate counter high register alternate counter low register reserved $1fdf $1fe0 8159 8160 $07ff $0800 bootstrap rom 512 bytes 2047 2048 $05ff $0600 1535 1536 not used irq status/control register lcd control register rdi lvi port c data register port d data register port c configuration register port d configuration register lvi control register clid control/status register 1 clid control/status register 2 option register timer keyboard interrupt register clid control/status register 3 reserved reserved february 12, 1997 general release specification mc68hc05cl4 motorola rev 2.0 a-3 a.3 eprom the user eprom consists of 6112 bytes from $0800 to $1fdf and 16 bytes of user vectors from $1ff0 to $1fff. the bootstrap rom is located from $0600 to $07ff. the bootstrap vectors are located from $1fe0 to $1fef. a.4 bootstrap mode bootstrap mode is entered upon the rising edge of reset if the irq /v pp pin is at v tst and the pb5 pin is at logic one. the bootstrap program is mask in the rom area from $0600 to $07ff. this program handles copying of user code from an external eprom into the on-chip eprom. the user code must be a one-to-one correspondence with the internal eprom addresses. a.5 eprom programming programming the on-chip eprom is achieved by using the program control register located at address $1c. please contact motorola for programming board availability. a.5.1 program control register (pcr) this register is provided for programming the on-chip eprom in the mc68hc705cl4 . elat?prom latch control 0 = eprom address and data bus con?ured for normal reads 1 = eprom address and data bus con?ured for programming (writes to eprom cause address and data to be latched). eprom is in programming mode and cannot be read if elat is 1. this bit should not be set when no programming voltage is applied to the v pp pin. pgm?prom program command 0 = programming power is switched off from eprom array. 1 = programming power is switched on to eprom array. if elat 1 1, then pgm = 0. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcr r elat pgm $001c w reset 00000000 general release specification february 12, 1997 motorola mc68hc05cl4 a-4 rev 2.0 a.5.2 programming sequence the eprom programming sequence is: 1. set the elat bit 2. write the data to the address to be programmed 3. set the pgm bit 4. delay for a time t pgmr 5. clear the pgm bit 6. clear the elat bit the last two steps must be performed with separate cpu writes. caution it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but it should be equal to v dd during normal operations. figure a-2 shows the ?w required to successfully program the eprom. february 12, 1997 general release specification mc68hc05cl4 motorola rev 2.0 a-5 figure a-2. eprom programming sequence write additional byte? end elat=1 write eprom byte epgm=1 wait 1 ms elat=0 epgm=0 y n start general release specification february 12, 1997 motorola mc68hc05cl4 a-6 rev 2.0 a.6 maximum ratings (voltages referenced to v ss ) a.7 dc electrical characteristics (v dd = 5.0 vdc 10%, vss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) notes: 1. all values shown re?ct average measurements. 2. typical values at midpoint of voltage range, 25 c only. 3. wait i dd : only timer system active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc =4.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l =20 pf on osc2. 5. wait, stop i dd : all ports con?ured as inputs, v il = 0.2 vdc, v ih = v dd ?.2 vdc. 6. stop i dd measured with osc1=v ss . 7. wait i dd is affected linearly by the osc2 capacitance. a.8 control timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) rating symbol value unit bootstrap mode (irq /v pp pin only) v in v ss ?.3 to 2v dd +0.3 v characteristic symbol min typ max unit eprom programming voltage v pp 14.0 v supply current (see notes) run wait stop 25?c 0?c to +70?c (standard) i dd 7.5 5 22 23 9 6 50 50 ma ma m a m a characteristic symbol min max units eprom byte programming time t eprom 10.0 ms motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. how to reach us: mfax: rmfax0@email.sps.mot.com ?touchtone 602-244-6609 internet: http://design-net.com usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 303-675-2140 or 1-800-441-2447 japan: nippon motorola ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 03-81-3521-8315 asia/pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 HC05CL4GRS/h |
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