 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? motorola, inc., 1998 HC05LJ5GRS/h rev 1 68hc05lj5 specification (general release) november 10, 1998 semiconductor products sector motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part.
november 10, 1998 general release specification mc68hc05lj5 motorola rev 1 i table of contents section page section 1 general description 1.1 features ...................................................................................................... 1-1 1.2 mask options.............................................................................................. 1-2 1.3 mcu structure.......................................................................................... 1-2 1.4 pin assignments ........................................................................................ 1-3 1.5 functional pin description.................................................................. 1-4 1.5.1 v dd and v ss .............................................................................................. 1-4 1.5.2 osc1, osc2/r............................................................................................ 1-4 1.5.3 reset ......................................................................................................... 1-6 1.5.4 irq .............................................................................................................. 1-6 1.5.5 pa0-pa7 ...................................................................................................... 1-6 1.5.6 pb0-pb5 ...................................................................................................... 1-7 section 2 memory 2.1 memory map ................................................................................................ 2-1 2.2 i/o and control registers ................................................................... 2-2 2.3 ram ................................................................................................................. 2-2 2.4 rom................................................................................................................. 2-2 2.5 i/o registers summary ........................................................................... 2-3 section 3 central processing unit 3.1 registers .................................................................................................... 3-1 3.2 accumulator (a)........................................................................................ 3-2 3.3 index register (x) ..................................................................................... 3-2 3.4 stack pointer (sp) .................................................................................... 3-2 3.5 program counter (pc) ........................................................................... 3-2 3.6 condition code register (ccr) ........................................................... 3-3 3.6.1 half carry bit (h-bit) .................................................................................... 3-3 3.6.2 interrupt mask (i-bit) .................................................................................... 3-3 3.6.3 negative bit (n-bit) ...................................................................................... 3-3 3.6.4 zero bit (z-bit) ............................................................................................. 3-3 3.6.5 carry/borrow bit (c-bit) ............................................................................... 3-4 section 4 interrupts 4.1 cpu interrupt processing ................................................................... 4-1 4.2 reset interrupt sequence .................................................................. 4-2 4.3 software interrupt (swi) ..................................................................... 4-3 4.4 hardware interrupts ............................................................................ 4-3 4.5 external interrupt (irq)....................................................................... 4-3 general release specification november 10, 1998 motorola mc68hc05lj5 ii rev 1 table of contents section page 4.5.1 irq , pa0, pa1, pa2, and pa3 pins ............................................................ 4-3 4.5.2 pa7 pin........................................................................................................ 4-4 4.5.3 irq control/status register (icsr), $0a.................................................... 4-4 4.5.4 optional external interrupts (pa0-pa3)....................................................... 4-6 4.6 timer interrupt (timer).......................................................................... 4-6 section 5 resets 5.1 external reset (reset).......................................................................... 5-1 5.2 internal resets ........................................................................................ 5-1 5.2.1 power-on reset (por) ............................................................................... 5-1 5.2.2 computer operating properly reset (copr).............................................. 5-2 5.2.3 low voltage reset (lvr) ............................................................................ 5-2 5.2.4 illegal address reset (iladr)..................................................................... 5-2 section 6 low power modes 6.1 stop instruction...................................................................................... 6-1 6.1.1 stop mode ................................................................................................. 6-1 6.1.2 halt mode.................................................................................................. 6-3 6.2 wait mode .................................................................................................... 6-3 6.3 data-retention mode.............................................................................. 6-3 6.4 cop watchdog timer considerations ............................................. 6-4 section 7 input/output ports 7.1 slow output falling-edge transition............................................. 7-1 7.2 port a............................................................................................................ 7-1 7.2.1 port a data register.................................................................................... 7-2 7.2.2 port a data direction register..................................................................... 7-2 7.2.3 port a pull-down/up register....................................................................... 7-3 7.2.4 port a drive capability................................................................................. 7-3 7.2.5 port a i/o pin interrupts............................................................................... 7-3 7.3 port b............................................................................................................ 7-4 7.3.1 port b data register.................................................................................... 7-5 7.3.2 port b data direction register..................................................................... 7-5 7.3.3 port b pull-down/up register....................................................................... 7-6 7.4 i/o port programming ............................................................................ 7-6 7.4.1 pin data direction........................................................................................ 7-6 7.4.2 output pin.................................................................................................... 7-6 7.4.3 input pin....................................................................................................... 7-7 7.4.4 i/o pin transitions ....................................................................................... 7-7 7.4.5 i/o pin truth tables..................................................................................... 7-7 november 10, 1998 general release specification mc68hc05lj5 motorola rev 1 iii table of contents section page section 8 multi-function timer 8.1 timer registers ........................................................................................ 8-2 8.1.1 timer counter register (tcr), $09............................................................. 8-2 8.1.2 timer control/status register (tcsr), $08................................................. 8-3 8.2 cop watchdog timer............................................................................... 8-4 8.3 operation during stop mode .............................................................. 8-5 8.4 operation during wait/halt mode..................................................... 8-5 section 9 instruction set 9.1 addressing modes ................................................................................... 9-1 9.1.1 inherent........................................................................................................ 9-1 9.1.2 immediate .................................................................................................... 9-1 9.1.3 direct ........................................................................................................... 9-2 9.1.4 extended...................................................................................................... 9-2 9.1.5 indexed, no offset....................................................................................... 9-2 9.1.6 indexed, 8-bit offset .................................................................................... 9-2 9.1.7 indexed, 16-bit offset .................................................................................. 9-3 9.1.8 relative........................................................................................................ 9-3 9.1.9 instruction types ......................................................................................... 9-3 9.1.10 register/memory instructions ...................................................................... 9-4 9.1.11 read-modify-write instructions ................................................................... 9-5 9.1.12 jump/branch instructions ............................................................................ 9-5 9.1.13 bit manipulation instructions........................................................................ 9-7 9.1.14 control instructions...................................................................................... 9-7 9.1.15 instruction set summary ............................................................................. 9-8 section 10 electrical specifications 10.1 maximum ratings..................................................................................... 10-1 10.2 thermal characteristics ................................................................... 10-1 10.3 dc electrical characteristics........................................................ 10-2 10.4 control timing ........................................................................................ 10-4 section 11 mechanical specifications 11.1 16-pin pdip (case #648) ............................................................................ 11-1 11.2 20-pin pdip (case #738) ............................................................................ 11-2 11.3 20-pin soic (case #751d) ......................................................................... 11-2 general release specification november 10, 1998 motorola mc68hc05lj5 iv rev 1 table of contents section page november 10, 1998 general release specification mc68hc05lj5 motorola rev 1 v list of figures figure title page 1-1 mc68hc05lj5 block diagram ........................................................................ 1-2 1-2 pin assignment for 16-pin package................................................................. 1-3 1-3 pin assignment for 20-pin package................................................................. 1-3 1-4 oscillator connections ..................................................................................... 1-5 2-1 mc68hc05lj5 memory map........................................................................... 2-1 2-2 i/o registers memory map .............................................................................. 2-2 2-3 i/o registers $0000-$000f.............................................................................. 2-3 2-4 i/o registers $0010-$001f.............................................................................. 2-4 3-1 mc68hc05 programming model ..................................................................... 3-1 4-1 interrupt processing flowchart ........................................................................ 4-2 4-2 irq status & control register ......................................................................... 4-4 6-1 stop/halt/wait flowcharts......................................................................... 6-2 7-1 port b data direction register ......................................................................... 7-1 7-2 port a i/o circuitry ........................................................................................... 7-2 7-3 port b i/o circuitry ........................................................................................... 7-4 8-1 multi-function timer block diagram ................................................................ 8-1 8-2 timer counter register.................................................................................... 8-2 8-3 timer control/status register (tcsr)............................................................. 8-3 8-4 cop watchdog timer location ....................................................................... 8-5 11-1 16-pin pdip mechanical dimensions ............................................................ 11-1 11-2 20-pin pdip mechanical dimensions ............................................................ 11-2 11-3 20-pin soic mechanical dimensions ............................................................ 11-2 general release specification november 10, 1998 motorola mc68hc05lj5 vi rev 1 list of figures figure title page november 10, 1998 general release specification mc68hc05lj5 motorola rev 1 vii list of tables table title page 1-1 mc68hc05lj5 mask options.......................................................................... 1-2 4-1 vector address for interrupts and reset.......................................................... 4-1 6-1 cop watchdog timer recommendations ....................................................... 6-4 7-1 port a i/o pin functions................................................................................... 7-7 7-2 port b i/o pin functions................................................................................... 7-7 8-1 rti and cop rates at f op =3.0mhz................................................................ 8-4 9-1 register/memory instructions .......................................................................... 9-4 9-2 read-modify-write instructions ....................................................................... 9-5 9-3 jump and branch instructions.......................................................................... 9-6 9-4 bit manipulation instructions ............................................................................ 9-7 9-5 control instructions .......................................................................................... 9-7 9-6 instruction set summary ................................................................................. 9-8 9-7 opcode map................................................................................................... 9-14 10-1 dc electrical characteristics.......................................................................... 10-2 10-2 control timing................................................................................................ 10-4 general release specification november 10, 1998 motorola mc68hc05lj5 viii rev 1 list of tables table title page november 10, 1998 general release specification mc68hc05lj5 general description motorola rev 1 1-1 section 1 general description the mc68hc05lj5 hcmos microcontroller is a member of the mc68hc05 family of low-cost single-chip 8-bit microcontroller units (mcus). the mc68hc05lj5 is an enhanced version of the mc68hc05j5, which includes high sink current port pins, slow output transition port pins, an extra interrupt on a port pin, low-voltage-reset, and a tight tolerance rc oscillator option. the mc68hc05lj5 is available in 16-pin and 20-pin packages. the 16-pin version has four less i/o port lines than the 20-pin version. although the mc68hc05lj5 is an enhanced version of the mc68hc05j5, pin assignments are different. 1.1 features industry standard m68hc05 cpu core fully static operation with no minimum clock speed 1296 bytes of user rom including 16 bytes user vector 64 bytes of user ram 14 bidirectional i/o pins (10 bidirectional i/o pins for 16-pin package) on-chip oscillator: crystal/resonator oscillator or rc oscillator with only one external resistor required hardware mask and ?g for external interrupts 15-bit multi-function timer power saving stop and wait modes computer operating properly (cop) watchdog low voltage reset (lvr) illegal address reset (iladr) available in 16-pin pdip, 20-pin pdip, and 20-pin soic packages general release specification november 10, 1998 motorola general description mc68hc05lj5 1-2 rev 1 1.2 mask options the following mask options are available: table 1-1. mc68hc05lj5 mask options 1.3 mcu structure figure 1-1. mc68hc05lj5 block diagram mask option on-chip oscillator [crystal/resonator] or [rc] crystal/resonator feedback resistor [connected] or [disconnected] stop instruction convert to wait [enabled] or [disabled] pa0-pa3 external interrupt capability [enabled] or [disabled] external interrupt pins (irq , pa0-pa3) [edge-triggered] or [edge and level triggered] port a and port b pull-down/pull-up resistors [connected] or [disconnected] cop watchdog timer [enabled] or [disabled] low voltage reset [enabled] or [disabled] 64 bytes ram 1296 bytes rom osc ? 2 reset and irq power supply port a data direction reg. a port b data direction reg. b cpu control alu 68hc05 cpu accum index reg. cpu registers program counter cond code reg. 0 0 0 0 000 11 stk pntr 0 111hi nzc pa0 ? pa1 ? pa2 ? pa3 ? pa4 - pa5 - pa6 a pa7 ? vdd vss reset irq osc1 osc2/r - : 8ma current sink ? : external edge interrupt capability a : 8ma current sink, open-drained pb0 pb1 ? pb2 ?? pb4 ? pb5 ? pb3 ? ? : 25ma current sink, open-drained ? : pins not available on 16-pin package mft cop lvr with internal pull-up ? : 8ma current sink, open-drained with internal pull-up, external interrupt capability with internal pull-up november 10, 1998 general release specification mc68hc05lj5 general description motorola rev 1 1-3 1.4 pin assignments figure 1-2. pin assignment for 16-pin package figure 1-3. pin assignment for 20-pin package osc2/r osc1 reset pa7 pa6 pa5 pa4 pb0 pb1 vdd vss irq pa0 pa1 pa2 pa3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc2/r osc1 reset pa7 pa6 pa5 pa4 pb0 pb1 vdd vss irq pa0 pa1 pa2 pa3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 20 19 18 17 pb3 pb4 pb2 pb5 general release specification november 10, 1998 motorola general description mc68hc05lj5 1-4 rev 1 1.5 functional pin description the following paragraphs give a description of the general function of each pin assigned in figure 1-2 and figure 1-3 . 1.5.1 v dd and v ss power is supplied to the mcu through v dd and v ss . v dd is the positive supply, and v ss is ground. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care should be taken to provide good power supply bypassing at the mcu by using bypass capacitors with good high-frequency char- acteristics that are positioned as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 1.5.2 osc1, osc2/r the osc1 and osc2/r pins are the connections for the on-chip oscillator. the osc1 and osc2/r pins can accept the following sets of components: 1. a crystal as shown in figure 1-4 (a) 2. a ceramic resonator as shown in figure 1-4 (a) 3. an external resistor as shown in figure 1-4 (b) 4. an external clock signal as shown in figure 1-4 (c) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . the type of oscillator is selected by a mask option. an internal 2m w resistor may be selected between osc1 and osc2/r by a mask option (crystal/ceramic resonator mode only). if the rc oscillator option is selected, osc1 pin should be connected to a known logic level, either one or zero. crystal oscillator the circuit in figure 1-4 (a) shows a typical oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturer s recommendations should be fol- lowed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an internal start-up resistor of approximately 2 m w is provided between osc1 and osc2/r for the crystal type oscillator as a mask option. november 10, 1998 general release specification mc68hc05lj5 general description motorola rev 1 1-5 figure 1-4. oscillator connections ceramic resonator oscillator in cost-sensitive applications, a ceramic resonator can be used in place of the crystal. the circuit in figure 1-4 (a) can be used for a ceramic resonator. the res- onator manufacturer s recommendations should be followed, as the resonator parameters determine the external component values required for maximum sta- bility and reliable starting. the load capacitance values used in the oscillator cir- cuit design should include all stray capacitances. the ceramic resonator and components should be mounted as close as possible to the pins for start-up stabi- lization and to minimize output distortion. an internal start-up resistor of approxi- mately 2 m w is provided between osc1 and osc2/r for the ceramic resonator type oscillator as a mask option. rc oscillator the lowest cost oscillator is the rc oscillator con?uration. with this option an external resistor is connected between osc2/r pin and the v ss pin as shown in figure 1-4 (b). the typical operating frequency f osc is set at 4 mhz with the exter- nal r tied to v ss . the internal start-up resistor of approximately 2 m w is not con- nected between osc1 and osc2/r for the mask option of the rc type oscillator. the tolerance of this rc oscillator is guaranteed to be no greater than 15% at the speci?d conditions of 0 c to 40 c and 5v 10% v dd providing that the tol- erance of the external resistor r is at most 1% and the center frequency range is from 3.8mhz to 4.2mhz. the center frequency is the nominal operating frequency of the rc oscillator and can be adjusted by adjusting the external r value to change the internal vco charging current. in order to obtain an oscillator clock with the best possible tolerance, the external resistor connected to the osc2/r pin should be grounded as close to the vss pin as possible and the other terminal of this external resistor should be connected as close to the osc2/r pin as possible. mcu 37pf osc1 osc2/r 37 pf 2m w r unconnected external clock osc1 osc2/r mcu osc1 osc2/r mcu (a) crystal or ceramic resonator connection (b) rc oscillator connection (c) external clock source connection general release specification november 10, 1998 motorola general description mc68hc05lj5 1-6 rev 1 external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2/r input not connected, as shown in figure 1-4 (c). this con?uration is possible only when the crystal/ceramic resonator mask option is selected. 1.5.3 reset this is an i/o pin. this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains a steering diode to discharge any voltage on the pin to v dd , when the power is removed. an internal pull-up is also connected between this pin and v dd . the reset pin con- tains an internal schmitt trigger to improve its noise immunity as an input. this pin is an output pin if lvr triggers an internal reset. 1.5.4 i rq this input pin drives the asynchronous irq interrupt function of the cpu. the irq interrupt function has a mask option to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for "wired-or" operation, if desired. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. note each of the pa0 to pa3 i/o pins may be connected as an or function with the irq interrupt function by a mask option. this capability allows keyboard scan applications where the transitions or levels on the i/o pins will behave the same as the irq pin, except for the inverted phase. the edge or level sensitivity selected by a separate mask option for the irq pin also applies to the i/o pins or?d to create the irq signal. besides, pa7 also has falling-edge only interrupt capability whose functionality is controlled by another set of register bits. 1.5.5 pa0-pa7 these eight i/o lines comprise port a. pa6 and pa7 are open-drained pins with pull-up devices whereas pa0 to pa5 are push-pull pins with pull-down devices. pa4 to pa7 are also capable of sinking 8 ma. the state of any pin is software programmable and all port a lines are con?ured as inputs during power-on or reset. the lower four i/o pins (pa0 to pa3) can be connected via an internal or gate to the irq interrupt function enabled by a mask option. another independent interrupt source comes from the falling edge on pa7. pa7 interrupt source is associated with a second set of interrupt control/status bits. all port a pins except pa6 and pa7 have software programmable pull-down devices also provided by a mask option. pa6 and pa7 pins have software pro- grammable pull-up devices also provided by the same mask option. pull-up november 10, 1998 general release specification mc68hc05lj5 general description motorola rev 1 1-7 devices on pa6 and pa7 once enabled are always enabled regardless of pin direc- tion con?uration, unlike pull-down devices on pa0 to pa5 which are activated only when these pins are con?ured as input pins. pa6 and pa7 pins, when con?ured as output pins, also have slow output falling- edge transition feature to reduce emi. the falling-edge transition time is tentatively set at 250ns typical at a speci?d load of 500pf, assuming the bus rate is 2mhz. the slow transition output feature of pa6 and pa7, along with that of pb1 and pb2, can be enabled or disabled by software. both pa6 and pa7 pins have schmitt trigger input for better noise immunity. v ih and v il are speci?d at 2.4v and 0.8v, respectively. the slow transition feature of pa6 and pa7 pins can be enabled or disabled by software. once enabled, slow transition feature is applied to both pins while in out- put mode. 1.5.6 pb0-pb5 note i/o lines pb2 to pb5 are not available on the 16-pin package. these six i/o lines comprise port b. pb0, pb3 to pb5 are push-pull i/o lines with pull-down resistor. pb1 and pb2 are open-drain i/o lines with pull-up resistor. the state of any line is software programmable and is con?ured as an input dur- ing power-on or reset. i/o lines pb1 and pb2 have software programmable pull-up device whereas pb0, pb3 to pb5 have software programmable pull-down device, by a mask option. pull-up devices on pb1 and pb2 lines once enabled are always enabled regardless of pin direction con?uration; unlike pull-down devices on pb0, pb3-pb5 lines, which are activated only when the pin is con?ured as input pin. similar to pa6 and pa7, pb1 also has a slow output falling transition feature when con?ured as an output line. pb1 has 25ma sink capability at 0.5v v ol . pb2 output is one clock cycle (250ns if bus rate is 2mhz) late than other i/o pins if slow output transition feature is enabled. pb2 has 25ma sink capability at 0.5v v ol . note for the 16-pin package, pb1 and pb2 are bonded to the same pin and is labelled pb1. this pb1 has 50ma sink capability is slow transition feature is enabled and if they are written with the same value at the same write cycle. the falling transition time of pb1 is set at 250ns typical at a speci?d load of 50pf, assuming that the bus rate is 2mhz. the slow transition feature on this pb1 pin is longer than pb1 pin for the 20-pin package. general release specification november 10, 1998 motorola general description mc68hc05lj5 1-8 rev 1 note if port data register pb1 and pb2 are not written with the same value, pb1 pin on the 16-pin package will sink 25 ma only and the output transition time will be shorter. november 10, 1998 general release specification mc68hc05lj5 memory motorola rev 1 2-1 section 2 memory 2.1 memory map the mc68hc05lj5 has 4k-bytes of addressable memory consisting 32 bytes of i/o, 64 bytes of user ram, and 1296 bytes of user rom, as shown in figure 2-1 . figure 2-1. mc68hc05lj5 memory map 4095 4088 3840 4087 3839 4080 4079 rom reserved for test 8 bytes user vectors (rom) 8 bytes unimplemented 160 bytes 0768 0767 stack user ram 64 bytes reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) timer vector (low byte) timer vector (high byte) $0ff7 $0ff8 $0ff9 $0ffa $0ffb $0ffc $0ffd $0ffe $0fff $001f $0000 $0100 $00ff 0255 0256 i/o 32 bytes 0032 0031 0000 $0fff $0f00 $0eff $0300 $02ff $00c0 $00bf $0020 $001f $0000 user rom 1280 bytes i/o registers 32 bytes (see figure 2-2 ) 0192 0191 unimplemented 512 bytes $0ff6 $0ff3 $0ff4 $0ff5 $0ff2 $0ff1 $0ff0 cop watchdog timer* $07ff $0800 test rom 240 bytes rom * writing a 0 to bit 0 of $0ff0 clears the cop timer. reading $0ff0 returns user rom data. reserved for test reserved for test reserved for test reserved for test reserved for test reserved for test reserved for test $0ff8 $0ff7 2047 2048 $0ff0 $0fef unimplementd 1792 bytes general release specification november 10, 1998 motorola memory mc68hc05lj5 2-2 rev 1 2.2 i/o and control registers the i/o and control registers reside in locations $0000-$001f. the overall orga- nization of these registers is shown in figure 2-2 . the bit assignments for each register are shown in figure 2-3 and figure 2-4 . reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. figure 2-2. i/o registers memory map 2.3 ram the user ram consists of 64 bytes (including the stack), located from $00c0 to $00ff. the stack begins at address $00ff and proceeds down to $00c0. using the stack area for data storage or temporary work locations requires care to pre- vent it from being overwritten due to stacking from an interrupt or subroutine call. 2.4 rom there are a total of 1296 bytes of user rom on-chip. this includes 1280 bytes of user rom from locations $0300 to $07ff for user program storage and 16 bytes for user vectors from locations $0ff0 to $0fff. there are a total of 240 bytes of internal test rom on chip at locations $0f00 to $0fef. port a data register $0000 port b data register $0001 port a data direction register $0004 port b data direction register $0005 timer control & status register $0008 timer counter register $0009 reserved $001f unimplemented (2 bytes) unimplemented (2 bytes) unimplemented (5 bytes) unimplemented (13 bytes) irq control & status register $000a port a pull-down/up register $0010 port b pull-down/up register $0011 november 10, 1998 general release specification mc68hc05lj5 memory motorola rev 1 2-3 2.5 i/o registers summary addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 port a data r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta w $0001 port b data r 0 0 pb5 pb4 pb3 pb2 pb1 pb0 portb w $0002 unimplemented r w $0003 unimplemented r w $0004 port a data direction r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 ddra w $0005 port b data direction r slowe 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 ddrb w $0006 unimplemented r w $0007 unimplemented r w $0008 mft ctrl/status r tof rtif tofe rtie 00 rt1 rt0 tcsr w tofr rtifr $0009 mft counter r tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 tcnt w $000a irq control/status r irqe irqe1 0 0 irqf irqf1 0 0 icsr w irqr irqr1 $000b unimplemented r w $000c unimplemented r w $000d unimplemented r w $000e unimplemented r w $000f unimplemented r w unimplemented bits reserved bits figure 2-3. i/o registers $0000-$000f general release specification november 10, 1998 motorola memory mc68hc05lj5 2-4 rev 1 addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 port a pull-down/up r pdura w pura7 pura6 pdra5 pdra4 pdra3 pdra2 pdra1 pdra0 $0011 port b pull-down/up r pdurb w pdrb5 pdrb4 pdrb3 purb2 purb1 pdrb0 $0012 unimplemented r w $0013 unimplemented r w $0014 unimplemented r w $0015 unimplemented r w $0016 unimplemented r w $0017 unimplemented r w $0018 unimplemented r w $0019 unimplemented r w $001a unimplemented r w $001b unimplemented r w $001c unimplemented r w $001d unimplemented r w $001e unimplemented r w $001f unimplemented r w unimplemented bits reserved bits figure 2-4. i/o registers $0010-$001f november 10, 1998 general release specification mc68hc05lj5 central processing unit motorola rev 1 3-1 section 3 central processing unit the mc68hc05lj5 has an 4k-bytes memory map. the stack has only 64 bytes. therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00c0 and then wrap-around to $00ff. all other instructions and registers behave as described in this chapter. 3.1 registers the mcu contains ?e registers which are hard-wired within the cpu and are not part of the memory map. these ?e registers are shown in figure 3-1 and are described in the following paragraphs. figure 3-1. mc68hc05 programming model condition code register i accumulator 60 a index register 71 x 4 52 3 stack pointer sp 14 8 15 9 12 13 10 11 pc cc 111 11 0 0 0 0 0 0 0 0 program counter h nzc half-carry bit (from bit 3) interrupt mask negative bit zero bit carry bit general release specification november 10, 1998 motorola central processing unit mc68hc05lj5 3-2 rev 1 3.2 accumulator (a) the accumulator is a general purpose 8-bit register as shown in figure 3-1 . the cpu uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. the accumulator is not affected by a reset of the device. 3.3 index register (x) the index register shown in figure 3-1 is an 8-bit register that can perform two functions: indexed addressing temporary storage in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu ?ds the operand address by adding the index register content to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu ?ds the operand address by adding the index register content to a 16-bit immediate value. the index register can also serve as an auxiliary accumulator for temporary storage. the index register is not affected by a reset of the device. 3.4 stack pointer (sp) the stack pointer shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. the stack pointer contains the address of the next free location on the stack. during a reset or the reset stack pointer (rsp) instruction, the stack pointer is set to $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. the six least signi?ant register bits are appended to these ten ?ed bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64($c0) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack and an interrupt uses ?e locations. 3.5 program counter (pc) the program counter shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. the program counter contains the address of the next instruction or operand to be fetched. november 10, 1998 general release specification mc68hc05lj5 central processing unit motorola rev 1 3-3 normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 condition code register (ccr) the ccr shown in figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. the ?th bit is the interrupt mask. these bits can be individually tested by a program, and speci? actions can be taken as a result of their states. the condition code register should be thought of as having three additional upper bits that are always ones. only the interrupt mask is affected by a reset of the device. the following paragraphs explain the functions of the lower ?e bits of the condition code register. 3.6.1 half carry bit (h-bit) when the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last add or adc (add with carry) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. 3.6.2 interrupt mask (i-bit) when the interrupt mask is set, the internal and external interrupts are disabled. interrupts are enabled when the interrupt mask is cleared. when an interrupt occurs, the interrupt mask is automatically set after the cpu registers are saved on the stack, but before the interrupt vector is fetched. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the interrupt is processed as soon as the interrupt mask is cleared. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. after any reset, the interrupt mask is set and can only be cleared by the clear i-bit (cli), or wait instructions. 3.6.3 negative bit (n-bit) the negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (bit 7 of the result was a logical one.) the negative bit can also be used to check an often tested ?g by assigning the ?g to bit 7 of a register or memory location. loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the ?g. 3.6.4 zero bit (z-bit) the zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. general release specification november 10, 1998 motorola central processing unit mc68hc05lj5 3-4 rev 1 3.6.5 carry/borrow bit (c-bit) the carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. the carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. this bit is neither set by an inc nor by a dec instruction. november 10, 1998 general release specification mc68hc05lj5 interrupts motorola rev 1 4-1 section 4 interrupts the cpu can be interrupted in ?e different ways: non-maskable software interrupt instruction (swi) external asynchronous interrupt (irq ) optional external interrupt on pa0-pa3 (mask option) external interrupt on pa7 internal timer interrupt 4.1 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are con- sidered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is clear) and the corresponding inter- rupt enable bit is set the processor will proceed with interrupt processing. other- wise, the next instruction is fetched and executed. if an interrupt occurs the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and ?ally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 4-1 will be serviced ?st. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed the cpu fetches the address of the appro- priate interrupt software service routine from the vector table at locations $07f8 to $07ff as de?ed in table 4-1 . table 4-1. vector address for interrupts and reset n/a n/a irqf/irqf1 tof rtif register n/a n/a icsr tcsr tcsr flag name interrupts reset software external interrupt timer overflow real time interrupt cpu interrupt reset swi irq timer timer vector address $0ffe-$0fff $0ffc-$0ffd $0ffa-$0ffb $0ff8-$0ff9 $0ff8-$0ff9 general release specification november 10, 1998 motorola interrupts mc68hc05lj5 4-2 rev 1 an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. figure 4-1. interrupt processing flowchart 4.2 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low level input on the reset pin or an internally generated rst signal causes the program to vector to its start- ing address which is speci?d by the contents of memory locations $0ffe and $0fff. the i-bit in the condition code register is also set. execute instruction from reset is i-bit set? load pc from: swi: $07fc, $07fd irq: $07fa-$07fb timer: $07f8-$07f9 set i-bit in ccr stack pc, x, a, cc clear irq request latch if irqe1 is cleared restore registers from stack cc, a, x, pc y n irq external interrupt? y n timer internal interrupt? y n fetch next instruction rti instruction ? y n swi instruction ? y n november 10, 1998 general release specification mc68hc05lj5 interrupts motorola rev 1 4-3 4.3 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is exe- cuted regardless of the state of the i-bit in the ccr. as with any instruction, inter- rupts pending during the previous instruction will be serviced before the swi opcode is fetched. the interrupt service routine address is speci?d by the con- tents of memory locations $0ffc and $0ffd. 4.4 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. there are two types of hardware inter- rupts which are explained in the following sections. 4.5 external interrupt (irq ) interrupts from external pins are available on: irq pin pa0 to pa3 pins (enabled by mask option) pa7 pin 4.5.1 irq , pa0, pa1, pa2, and pa3 pins if ?dge-only sensitivity is chosen by mask option, the irq interrupt is sensitive to the following cases: 1. falling edge on the irq pin. 2. rising edge on any pa0-pa3 pin with irq enabled (via mask option). if ?dge-and-level sensitivity is chosen, the irq interrupt is sensitive to the follow- ing cases: 1. low level on the irq pin. 2. falling edge on the irq pin. 3. high level on any pa0-pa3 pin with irq enabled (via mask option). 4. rising edge on any pa0-pa3 pin with irq enabled (via mask option). the irqe enable bit controls whether an active irqf ?g can generate an irq interrupt sequence. this interrupt is serviced by the interrupt service routine located at the address speci?d by the contents of $0ffa and $0ffb. the irq latch is automatically cleared by entering the interrupt service routine if irqe1 enable bit is cleared. if irqe1 enable bit is also set, the only way of clear- ing irqf is by writing a logic one to the irqr acknowledge bit. writing a logic one to the irqr acknowledge bit in the icsr is the other way of clearing irqf ?g, regardless of the status of the irqe1 bit, besides irq vector fetch. this condi- tional reset of irqf ?g provides a way for the user to differentiate the interrupt sources from irq and irq1 latches and also to make it hc05j1a compatible if general release specification november 10, 1998 motorola interrupts mc68hc05lj5 4-4 rev 1 pa7 interrupt is not used. as long as the output state of the irqf ?g bit is active the cpu will continuously re-enter the irq interrupt sequence until the active state is removed or the irqe enable bit is cleared. 4.5.2 pa7 pin pa7 interrupt source, if enabled by irqe1 enable bit, triggers irq interrupt on pa7 falling edge only. the irq1 latch (irqf1 ?g) can only be cleared by writing a logic one to the irqr1 acknowledge bit in the icsr. irq vector fetch can not clear irqf1 ?g. irq interrupt caused by pa7 falling edge also vectors to $0ffa and $0ffb. 4.5.3 irq control/status register (icsr), $0a the irq interrupt function is controlled by the icsr located at $000a. all unused bits in the icsr will read as logic zeros. the irqf, irqf1, irqe1 bits are cleared and irqe bit is set by reset. figure 4-2. irq status & control register irqr 1 - pa7 interrupt acknowledge the irqr1 acknowledge bit clears an irq interrupt triggered by a falling edge on pa7 by clearing the irq1 latch. the irqr1 acknowledge bit will always read as a logic zero. 1 = writing a logic one to the irqr1 acknowledge bit will clear the irq1 latch. 0 = writing a logic zero to the irqr1 acknowledge bit will have no effect on the irq1 latch. irqr - irq interrupt acknowledge the irqr acknowledge bit clears an irq interrupt by clearing the irq latch. the irqr acknowledge bit will always read as a logic zero. 1 = writing a logic one to the irqr acknowledge bit will clear the irq latch. 0 = writing a logic zero to the irqr acknowledge bit will have no effect on the irq latch. 0 irqr1 icsr $000a 1 7 w r 0000000 reset t 6543210 irqe irqf 0 irqr 0 irqf1 irqe1 0 reserved for test november 10, 1998 general release specification mc68hc05lj5 interrupts motorola rev 1 4-5 irqf1 - pa7 interrupt request flag writing to the irqf1 ?g bit will have no effect on it. if the additional setting of irqf1 ?g bit is not cleared in the irq service routine and the irqe1 enable bit remains set the cpu will re-enter the irq interrupt sequence continuously until either the irqf1 ?g bit or the irqe1 enable bit is cleared. the irqf1 latch is cleared by reset. 1 = indicates that an irq request triggered by a falling edge on pa7 is pending. 0 = indicates that no irq request triggered by a falling edge on pa7 is pending. the irqf1 ?g bit can only be cleared by writing a logic one to the irqr1 acknowledge bit. doing so before exiting the service routine will mask out additional occurrences of the irqf1. irqf - irq interrupt request flag writing to the irqf ?g bit will have no effect on it. if the additional setting of irqf ?g bit is not cleared in the irq service routine and the irqe enable bit remains set the cpu will re-enter the irq interrupt sequence continuously until either the irqf ?g bit or the irqe enable bit is clear. the irqf latch is cleared by reset. 1 = indicates that an irq request is pending. 0 = indicates that no irq request triggered by pins pa0-3 or irq is pending. the irqf ?g bit is cleared once the irq vector is fetched and if irqe1 is also cleared. if irqe1 is set, then the only way of clearing irqf ?g is by writing a logic one to irqr bit. the irqf ?g bit can be cleared, regardless of the status of the irqe1 bit, by writing a logic one to the irqr acknowledge bit to clear the irq latch and also conditioning the external irq sources to be inactive (if the level sensitive interrupts are enabled via mask option). doing so before exiting the service routine will mask out additional occurrences of the irqf. irqe1 - pa7 interrupt enable the irqe1 bit enables/disables the irqf1 ?g bit to initiate an irq interrupt sequence. 1 = enables irqf1 interrupt, that is, the irqf1 ?g bit can generate an interrupt sequence. execution of the stop or wait instructions will leave the irqe1 bit to be unaffected. 0 = the irqf1 ?g bit cannot generate an interrupt sequence. reset clears the irqe1 enable bit, thereby disabling pa7 interrupts. general release specification november 10, 1998 motorola interrupts mc68hc05lj5 4-6 rev 1 irqe - irq interrupt enable the irqe bit enables/disables the irqf ?g bit to initiate an irq interrupt sequence. 1 = enables irqf interrupt, that is, the irqf ?g bit can generate an interrupt sequence. reset sets the irqe enable bit, thereby enabling irq interrupts once the i-bit is cleared. execution of the stop or wait instructions causes the irqe bit to be set in order to allow the external irq to exit these modes. 0 = the irqf ?g bit cannot generate an interrupt sequence. 4.5.4 optional external interrupts (pa0-pa3) the irq interrupt can also be triggered by the inputs on the pa0 to pa3 port pins if enabled by a single mask option. if enabled, the lower four bits of port a can activate the irq interrupt function, and the interrupt operation will be the same as for inputs to the irq pin. this mask option of pa0-3 interrupt allow all of these input pins to be or?d with the input present on the irq pin. all pa0 to pa3 pins must be selected as a group as an additional irq interrupt. all the pa0-3 interrupt sources are also controlled by the irqe enable bit. note the bih and bil instructions will only apply to the level on the irq pin itself, and not to the output of the logic or function with the pa0 to pa3 pins. the state of the individual port a pins can be checked by reading the appropriate port a pins as inputs. note if enabled, the pa0 to pa3 and pa7 pins will cause an irq interrupt regardless of whether these pins are con?ured as inputs or outputs. 4.6 timer interrupt (timer) the timer interrupt is generated by the multi-function timer when either a timer over?w or a real time interrupt has occurred as described in section 8 . the inter- rupt ?gs and enable bits for the timer interrupts are located in the timer control/ status register (tcsr) located at $0008. the i-bit in the ccr must be clear in order for the timer interrupt to be enabled. either of these two interrupts will vec- tor to the same interrupt service routine located at the address speci?d by the contents of memory locations $0ff8 and $0ff9. november 10, 1998 general release specification mc68hc05lj5 resets motorola rev 1 5-1 section 5 resets the mcu can be reset from ?e sources: one external input and four internal restart conditions. initial power up of device (power on reset) a logic zero applied to the reset pin (external reset). timeout of the cop watchdog (cop reset) low voltage applied to the device (lvr reset) fetch of an opcode from an address not in the memory map (illegal address reset) 5.1 external reset (reset ) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage sepa- rated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the rst signal and reset the cpu and peripherals. this pin is also an output pin whenever the lvr triggers an internal reset. termination of the external reset input or the internal cop watchdog reset or lvr are the only reset sources that can alter the operating mode of the mcu. 5.2 internal resets the four internally generated resets are the initial power-on reset function, the cop watchdog timer reset, the illegal address detector reset and the low voltage reset (lvr). termination of the external reset input or the internal cop watch- dog timer or lvr are the only reset sources that can alter the operating mode of the mcu. the other internal resets will not have any effect on the mode of opera- tion when their reset state ends. 5.2.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabi- lize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064 internal processor bus clock cycles (ph2) after the oscillator becomes active. general release specification november 10, 1998 motorola resets mc68hc05lj5 5-2 rev 1 the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of this 4064 cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end. 5.2.2 computer operating properly reset (copr) the internal copr reset is generated automatically (if the cop is enabled) by a time-out of the cop watchdog timer. this time-out occurs if the counter in the cop watchdog timer is not reset (cleared) within a speci? time by a software reset sequence. the cop watchdog timer can be disabled by a mask option. refer to section 8.2 for more information on this time-out feature. cop reset also forces the reset pin low the copr will generate the rst signal which will reset the cpu and other peripherals. also, the copr will establish the mode of operation based on the state of the irq pin at the time the copr signal ends. if the voltage on the irq pin is at the v tst level, the state of the pb0 pin during the last rising edge of the reset pin will determine which test mode (internal or expanded) the mcu will be in. if the voltage at the irq pin is in the normal operating range (v ss to v dd ), the mcu will enter single-chip mode when the copr signal ends. if any other reset function is active at the end of the copr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. 5.2.3 low voltage reset (lvr) the internal lvr reset is generated when v dd falls below the speci?d lvr trig- ger value v lv r for at least one t cyc . in typical applications, the power supply decoupling circuit will eliminate negative-going voltage glitches of less than one t cyc . this reset will hold the mcu in the reset state until v dd rises above v lv r . whenever v dd is above v lvr and below 4.5v, the mcu is guaranteed to operate although not within speci?ation. the output from the lvr is connected directly to the internal reset circuitry and also forces the reset pin low. the internal reset will be removed once the power supply voltage rises above v lv r , at which time a normal power-on-reset sequence occurs. 5.2.4 illegal address reset (iladr) the internal iladr reset is generated when an instruction opcode fetch occurs from an address which is not implemented in the ram ($00c0 - $00ff) nor rom ($0300-$07ff). the iladr will generate the rst signal which will reset the cpu and other peripherals. if any other reset function is active at the end of the iladr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. notice that iladr also forces the reset pin low november 10, 1998 general release specification mc68hc05lj5 low power modes motorola rev 1 6-1 section 6 low power modes the mc68hc05lj5 is capable of running in one of several low-power operating modes. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the stop and wait instructions are not normally used if the cop watchdog timer is enabled. a mask option is provided to convert the stop instruction to a halt, which is a wait-like instruction that does not halt the cop watchdog timer but has a recovery delay. the ?w of the stop, halt, and wait modes are shown in figure 6-1 . 6.1 stop instruction the stop instruction can result in one of two modes of operation depending on the stop mask option chosen. one option is for the stop instruction to operate like the stop in normal mc68hc05 family members and place the device in the stop mode. the other option is for the stop instruction to behave like a wait instruction (except that the restart time will involve a delay) and place the device in the halt mode. 6.1.1 stop mode execution of the stop instruction in this mode (as chosen by a mask option) places the mcu in its lowest power consumption mode. in the stop mode the internal oscillator is turned off, halting all internal processing, including the cop watchdog timer. when the cpu enters stop mode the interrupt ?gs (tof and rtif) and the interrupt enable bits (tofe and rtie) in the tcsr are cleared by internal hard- ware to remove any pending timer interrupt requests and to disable any further timer interrupts. execution of the stop instruction automatically clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/sta- tus register so that the irq external interrupt is enabled. all other registers, including the other bits in the tcsr, and memory remain unaltered. all input/out- put lines remain unchanged. the mcu can be brought out of the stop mode only by an irq external interrupt or an externally generated reset or an lvr reset. when exiting the stop mode the internal oscillator will resume after a 4064 internal processor clock cycle oscil- lator stabilization delay. general release specification november 10, 1998 motorola low power modes mc68hc05lj5 6-2 rev 1 note execution of the stop instruction with the stop mode mask option will cause the oscillator to stop and therefore disable the cop watchdog timer. if the cop watchdog timer is to be used, the stop mode should be changed to the halt mode by choosing the appropriate mask option. see section 6.4 for more details. figure 6-1. stop/halt/wait flowcharts 1. fetch reset vector or 2. service interrupt a. stack b. set i-bit c. vector to interrupt routine wait stop conversion to halt? y n external reset? y n irq external interrupt? y n stop external oscillator, stop internal timer clock, reset start-up delay restart external oscillator, start stabilization delay stop internal processor clock, clear i-bit in ccr, and set irqe in icsr end of stabilization delay? y n irq external interrupt? y n external oscillator active and internal timer clock active restart internal processor clock timer internal interrupt? y n external reset? y n stop halt external reset ? y n irq external interrupt? y n external oscillator active and internal timer clock active timer internal interrupt? y n cop internal reset? y n cop internal reset? y n stop internal processor clock, clear i-bit in ccr, and set irqe in icsr stop internal processor clock, clear i-bit in ccr, and set irqe in icsr november 10, 1998 general release specification mc68hc05lj5 low power modes motorola rev 1 6-3 6.1.2 halt mode execution of the stop instruction in this mode (as chosen by a mask option) places the mcu in a low-power mode, which consumes more power than the stop mode. in the halt mode the internal processor clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permit- ting interrupts to be generated from the timer or a reset to be generated from the cop watchdog timer. execution of the stop instruction automatically clears the i-bit in the condition code register and sets the irqe enable bit in the irq con- trol/status register so that the irq external interrupt is enabled. all other regis- ters, memory, and input/output lines remain in their previous states. the halt mode may be exited when a timer interrupt, an external irq, an lvr reset, or external reset occurs. when exiting the halt mode the internal pro- cessor clock will resume after a delay of one to 4064 internal processor clock cycles. this varied delay time is due to the halt mode testing the oscillator stabi- lization delay timer (a feature of the stop mode) which has been free-running (a feature of the wait mode). note the halt mode is not intended for normal use, but is provided to keep the cop watchdog timer active should the stop instruction opcode be inadvertently executed. 6.2 wait mode the wait instruction places the mcu in a low-power mode, which consumes more power than the stop mode. in the wait mode the internal processor clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the cop watchdog timer. execution of the wait instruction auto- matically clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/status register so that the irq external interrupt is enabled. all other registers, memory, and input/output lines remain in their previous states. if timer interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode and resume normal operation. the timer may be used to gener- ate a periodic exit from the wait mode. the wait mode may also be exited when an external irq or an lvr reset or an external reset occurs. 6.3 data-retention mode if the lvr mask option is selected and since lvr kicks in whenever v dd is below the speci?d lvr trigger voltage which is higher than that required of the data retention mode, the data retention mode will not exist. data retention mode is only meaningful if lvr mask option is not selected. general release specification november 10, 1998 motorola low power modes mc68hc05lj5 6-4 rev 1 the contents of ram and cpu registers are retained at supply voltages as low as 2.0 vdc. this is called the data-retention mode where the data is held, but the device is not guaranteed to operate. the reset pin must be held low during data-retention mode. 6.4 cop watchdog timer considerations the cop watchdog timer is active in all modes of operation if enabled by a mask option. however, regardless of the mask option chosen, the cop watchdog timer will be disabled if the voltage on the irq pin equals or exceeds the v tst voltage level. thus, emulation of applications that do not service the cop should only be done with devices that have the cop mask option disabled. this prevents the voltage level on the irq pin from enabling the cop which would cause a reset and possibly change the operating mode of the device. if the cop watchdog timer is selected by the mask option, any execution of the stop instruction (either intentional or inadvertent due to the cpu being dis- turbed) will cause the oscillator to halt and prevent the cop watchdog timer from timing out unless the stop to halt conversion feature is enabled. therefore, it is recommended that the stop instruction should be converted to a halt instruc- tion if the cop watchdog timer is enabled. if the cop watchdog timer is selected by the mask option, the cop will reset the mcu when it times out. therefore, it is recommended that the cop watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the cop time-out period. the recommended interactions and considerations for the cop watchdog timer, stop instruction, and wait instruction are summarized in table 6-1 . table 6-1. cop watchdog timer recommendations less than v tst wait time less than cop time-out voltage on irq pin stop instruction wait time then the cop watchdog timer should be as follows: less than v tst disable cop by mask option converted to halt by mask option enable or disable cop by mask option wait time more than cop time-out any length wait time acts as stop less than v tst disable cop by mask option converted to halt by mask option if the following conditions exist: november 10, 1998 general release specification mc68hc05lj5 input/output ports motorola rev 1 7-1 section 7 input/output ports in the normal operating mode there are 14 usable bidirectional i/o lines arranged as one 8-bit i/o port (port a), and one 6-bit i/o port (port b). the individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (ddr s). also, if enabled by a single mask option all port a and port b i/o pins may have individual software programmable pull-down or pull-up devices. also, pa4-pa7 and pb1-pb2 pins have properties of sinking higher current; pa0-pa3 may function as additional irq interrupt input sources. note that both pa6 and pa7 pins have schmitt trigger input for better noise immu- nity. v ih and v il speci?d at 2.4v and 0.8v, respectively. 7.1 slow output falling-edge transition figure 7-1. port b data direction register slowe - slow transition enabled the slow transition feature is controlled by the slowe bit of ddrb (port b data direction register). 1 = enables the slow falling-edge output transition feature on the four i/ o lines: pa6, pa7, pb1, and pb2. if the pin is con?ured as an output pin. 0 = disables slow falling-edge output transition feature on the four i/o lines: pa6, pa7, pb1, and pb2. default value of slowe bit is cleared. 7.2 port a port a is an 8-bit bi-directional port which shares ?e of its pins with the irq inter- rupt system as shown in figure 7-2 . note that both pa6 and pa7 pins have schmitt trigger input for better noise immunity. only pa6 and pa7 are of open- drained type with slow output transition feature. each port a pin is controlled by the corresponding bits in a data direction register, a data register, and a pull-down/ up register. the port a data register is located at address $0000. the port a 0 ddrb0 ddrb $0005 0 7 w r 0000000 reset t 6543210 slowe ddrb1 ddrb2 ddrb3 ddrb4 ddrb5 general release specification november 10, 1998 motorola input/output ports mc68hc05lj5 7-2 rev 1 data direction register (ddra) is located at address $0004. the port a pull- down/up register (pdura) is located at address $0010. reset clears the ddra and the pdura. the port a data register is unaffected by reset. figure 7-2. port a i/o circuitry 7.2.1 port a data register each port a i/o pin has a corresponding bit in the port a data register. when a port a pin is programmed as an output the state of the corresponding data regis- ter bit determines the state of the output pin. when a port a pin is programmed as an input, any read of the port a data register will return the logic state of the cor- responding i/o pin. the port a data register is unaffected by reset. 7.2.2 port a data direction register each port a i/o pin may be programmed as an input by clearing the correspond- ing bit in the ddra, or programmed as an output by setting the corresponding bit in the ddra. the ddra can be accessed at address $0004. the ddra is cleared by reset. if con?ured as output pins, pa6 and pa7 have slow output falling-edge transition feature. the slow transition feature is controlled by the slowe bit of ddrb. slowe bit, if set and if the pin is con?ured as an output pin, enables the slow falling-edge output transition feature of all three i/o lines, pa6, pa7, and pb1. write $0010 read $0000 write $0000 read $0004 write $0004 internal hc05 data bus 100 m a pull-down data register bit output mask option (software pull-down/up inhibit) reset (rst) data direction register bit pulldown/up register bit vdd 5k pull-up note: each i/o port pin can have either pull-up or pull-down device, but not both. pa6 and pa7 output drivers are of open-drain type i/o pin 8 ma sink capability (bits 4-7 only) pa0-pa3 and pa7 only: to irq interrupt system november 10, 1998 general release specification mc68hc05lj5 input/output ports motorola rev 1 7-3 7.2.3 port a pull-down/up register all port a i/o pins may have software programmable pull-down/up devices enabled by the applicable mask option. if the pull-down/up mask option is selected, the pull-down/up is activated whenever the corresponding bit in the pdura is clear. if the corresponding bit in the pdura bit is set or the mask option for pull-down/up is not chosen, the pull-down/up will be disabled. a pull- down on an i/o pin is activated only if the i/o pin is programmed as an input whereas a pull-up device on an i/o pin is always activated whenever enabled, regardless of port direction. the pdura is a write-only register. any reads of location $0010 will return unde- ?ed results. since reset clears both the ddra and the pdura, all pins will ini- tialize as inputs with the pull-down active and pull-up devices active (if enabled by mask option). typical value of port a pull-up is 5k w . 7.2.4 port a drive capability the outputs for the upper four bits of port a (pa4, pa5, pa6 and pa7) are capable of sinking approximately 8 ma of current to v ss . 7.2.5 port a i/o pin interrupts the inputs to pa0, pa1, pa2, pa3 may be connected to the irq input of the cpu if enabled by a mask option. the input to pa7 is also connected to the irq input of the cpu, yet it is only enabled or disabled by software, not by mask option. pa7 interrupt capability is controlled by a set of control and status bits (irqe1, irqf1, irqr1), different from the set of control and status bits for that of pa0-pa3 and irq pin (irqe, irqf, irqr) in the same icsr (interrupt control and status reg- ister). when connected as an alternate source of an irq interrupt, pa0-3 input pins will behave the same as the irq pin itself, except that their active state is a logical one or a rising edge. the irq pin has an active state that is a logical zero or a falling edge. pa7 interrupt occurs, if enabled, only upon the falling edge at the input. if mask options for both level and edge sensitivity interrupts are chosen, the pres- ence of a logic one or occurrence of a rising edge on any one of the lower four port a pins will cause an irq interrupt request. if the edge-only sensitivity is selected, the occurrence of a rising edge on any one of the lower four port a pins will cause an irq interrupt request. as long as any one of the lower four port a irq inputs remains at a logic one level, the other of the lower four port a irq inputs are effectively ignored. general release specification november 10, 1998 motorola input/output ports mc68hc05lj5 7-4 rev 1 note the bih and bil instructions will only apply to the level on the irq pin itself, and not to the internal irq input to the cpu. therefore bih and bil cannot be used to test the state of the lower four port a input pins as a group nor that of pa7. 7.3 port b port b is a 6-bit bidirectional port which functions as shown in figure 7-3 . each port b pin is controlled by the corresponding bits in a data direction register, a data register, and a pull-down/up register. the port b data register is located at address $0001. the port b data direction register (ddrb) is located at address $0005. the port b pull-down/up register (pdurb) is located at address $0011. reset clears the ddrb and the pdurb. the port b data register is unaffected by reset. pb1 and pb2 are open-drained type i/os, capable of typically sinking 25ma cur- rent each, at v ol 0.5v max. for the 16-pin package, pb1 and pb2 are connected together to form the pin labelled pb1 on the package. this pb1 pin will have a maximum sink current of 50ma if both pb1 and pb2 are written with the same value at the same write cycle. figure 7-3. port b i/o circuitry write $0011 read $0001 write $0001 read $0005 write $0005 internal hc05 data bus 100 m a pull-down data register bit output mask option (software pull-down/up inhibit) reset (rst) data direction register bit pulldown/up register bit vdd 30k pull-up note: each i/o port pin can have either pull-up or pull-down device, but not both. pb1 and pb2 output drivers are of open-drain type i/o pin november 10, 1998 general release specification mc68hc05lj5 input/output ports motorola rev 1 7-5 7.3.1 port b data register all port b i/o pins have a corresponding bit in the port b data register. when a port b pin is programmed as an output the state of the corresponding data regis- ter bit determines the state of the output pin. when a port b pin is programmed as an input, any read of the port b data register will return the logic state of the cor- responding i/o pin. the port b data register is unaffected by reset. unused bits 6 and 7 will always read as logic zeros, and any write to these bits will be ignored. the port b data register is unaffected by reset. 7.3.2 port b data direction register port b i/o pins may be programmed as an input by clearing the corresponding bit in the ddrb, or programmed as an output by setting the corresponding bit in the ddrb. the ddrb can be accessed at address $0005. unused bits 6 and 7 will always read as logic zeros, and any write to these bits will be ignored.the ddrb is cleared by reset. if con?ured as output pins, pb1 and pb2 have slow output falling-edge transition feature. the slow transition feature is controlled by the slowe bit of ddrb. slowe bit, if set and if the pin is con?ured as an output pin, enables the slow falling-edge output transition feature of all four i/o lines, pa6, pa7, pb1 and pb2. for the 16-pin package type, care should be taken in using pb1 pin, which is bonded to two internal port b i/o lines pb1 and pb2, to constitute a 50 ma current sinking driver. both pb1 and pb2 i/o lines are capable of sinking 25 ma. if they are written with the same logic 0 value in the same write cycle, pb1 pin will sink 50 ma. if they are written with different values in the same write cycle, pb1 pin will sink only 25 ma. for the 20-pin package type, i/o lines pb1 and pb2 are not bonded to the same pin. hence, to constitute a 50ma current sinking driver, pb1 and pb2 pins have to be tied together externally and controlled in the same way as in the16-pin pack- age type case. also, if the slow transition feature of pin pb1 is enabled, a combination of i/o lines pb1 and pb2, is also a combination of slow transition features of i/o lines pb1 and pb2. pb2 line falling-edge output transition occurs t cyc /2 after the write cycle, with a standard i/o edge transition time. whereas for pb1 line, the falling- edge transition occurring immediately after the write cycle, but with an edge tran- sition time slower than standard i/os, similar to pa6 and pa7 pins. the net result is, for the 16-pin package type, since both pb1 and pb2 i/o lines are bonded to the same pb1 pin, the combination of delayed pb1 line sharp-edge output and the non-delayed slow transition output yields the desired slow output falling-edge transition. for the 20-pin package, pb1 and pb2 pins should be tied externally to create a driver with the desired slow output falling-edge transition feature. if slowe is set and pb2 pin is not tied to pb1 pin, be advised that the output at pb2 changes state t cyc /2 after the write cycle. general release specification november 10, 1998 motorola input/output ports mc68hc05lj5 7-6 rev 1 7.3.3 port b pull-down/up register all port b i/o pins may have software programmable pull-down/up devices enabled by a mask option. if the pull-down/up mask option is selected, the pull- down/up is activated whenever the corresponding bit in the pdurb is clear. a pull-down on an i/o pin is activated only if the i/o pin is programmed as an input whereas a pull-up device on an i/o pin is always activated whenever enabled, regardless of port direction. the pdurb is a write-only register. any reads of location $0011 will return unde- ?ed results. since reset clears both the ddrb and the pdurb, all pins will ini- tialize as inputs with the pull-down devices active and pull-up devices active (if chosen via mask option). typical value of port b pull-up is 30k w . 7.4 i/o port programming all i/o pins can be programmed as inputs or outputs, with or without pull-down/up devices. 7.4.1 pin data direction the direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (ddr). a pin is con?ured as an output if its corresponding ddr bit is set to a logic one. a pin is con?ured as an input if its corresponding ddr bit is cleared to a logic zero. the data direction bits ddrb0 to ddrb2 and ddra0 to ddra7 are read/write bits which can be manipulated with read-modify-write instructions. at power-on or reset, all ddrs are cleared which con?ures all port pins as inputs. if the pull- down/up mask option is chosen, all pins will initially power-up with their software programmable pull-downs/ups enabled. 7.4.2 output pin when an i/o pin is programmed as an output pin, the state of the corresponding data register bit will determine the state of the pin. the state of the data register bits can be altered by writing to address $0000 for port a and address $0001 for port b. reads of the corresponding data register bit at address $0000 or $0001 will return the state of the data register bit (not the state of the i/o pin itself). therefore bit manipulation is possible on all pins programmed as outputs. if the corresponding bit in the pull-down/up register is clear (and the pull-down/up mask option is chosen), only output pins with pull-ups have an activated pull-up device connected to the pin. for those pins with pull-downs and con?ured as out- put pins, the pull-downs will be inactivated regardless of the state of the corre- sponding pull-down/up register bit. since the pull-down/up register bits are write- only, bit manipulation should not be used on these register bits. november 10, 1998 general release specification mc68hc05lj5 input/output ports motorola rev 1 7-7 7.4.3 input pin when an i/o pin is programmed as an input pin, the state of the pin can be deter- mined by reading the corresponding data register bit. any writes to the corre- sponding data register bit for an input pin will be ignored in the sense that the written value will not be re?cted on the pin, rather it is only re?cted in the port data register. please refer to table 7-1 and table 7-2 for details. if the corresponding bit in the pull-down/up register is clear (and the pull-down/up mask option is chosen) the input pin will also have an activated pull-down/up device. since the pull-down/up register bits are write-only, bit manipulation should not be used on these register bits. 7.4.4 i/o pin transitions a "glitch" can be generated on an i/o pin when changing it from an input to an out- put unless the data register is ?st preconditioned to the desired state before changing the corresponding ddr bit from a zero to a one. if pull-downs are enabled by mask option, a ?ating input can be avoided by clear- ing the pull-down/up register bit before changing the corresponding ddr from a one to a zero. this will insure that the pull-down device will be activated before the i/o pin changes from a driven output to a pulled low/high input. 7.4.5 i/o pin truth tables every pin on port a and port b may be programmed as an input or an output under software control as shown in table 7-1 and table 7-2 . all port i/o pins may also have software programmable pull-down/up devices if selected by the appro- priate mask option. table 7-1. port a i/o pin functions table 7-2. port b i/o pin functions accesses to pdura at $0010 accesses to data register @ $0000 0 1 in, hi-z out pdura0-7 pdura0-7 ddra0-7 ddra0-7 i/o pin pa0-7 * pa0-7 u u i/o pin mode ddra read/write accesses to ddra @ $0004 read write read write * does not affect input, but stored to data register u is undefined accesses to pdurb at $0011 accesses to data register @ $0001 0 1 in, hi-z out pdurb0-2 pdurb0-2 ddrb0-2 ddrb0-2 i/o pin pb0-2 * pb0-2 u u i/o pin mode ddra read/write accesses to ddrb @ $0005 read write read write * does not affect input, but stored to data register u is undefined general release specification november 10, 1998 motorola input/output ports mc68hc05lj5 7-8 rev 1 november 10, 1998 general release specification mc68hc05lj5 multi-function timer motorola rev 1 8-1 section 8 multi-function timer the mc68hc05lj5 timer is a 15-stage multi-function ripple counter. the features include timer over flow (tof), power-on reset (por), real time interrupt (rti), and cop watchdog timer. figure 8-1. multi-function timer block diagram as shown in figure 8-1 , the timer is driven by the timer clock, ntf1, divided by four (4). ntf1 has the same phase and frequency as the processor bus clock, ph2, but is not stopped by the wait or halt modes. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer counter register (tcr) at address $09. a timer over- rti select circuit overflow circuit detect 88 f op ? 2 ? 10 internal timer clock (ntf1) tof rtif tofe rtie rt1 rt0 rtifr tofr timer control & status register ($08) timer counter register ($09) interrupt circuit cop watchdog resetable timer (?) 7-bit counter mcu internal bus to cpu interrupt ? 14 ? 15 ? 17 ? 16 ? to reset logic cop clear general release specification november 10, 1998 motorola multi-function timer mc68hc05lj5 8-2 rev 1 ?w function is implemented on the last stage of this counter, giving a possible interrupt at the rate of f op /1024. this circuit is followed by four more stages, with the resulting clock (f op /16384) driving the real time interrupt circuit. the rti cir- cuit consists of three divider stages with a 1 of 4 selector. the output of the rti circuit is further divided by eight to drive the optional cop watchdog timer circuit, which can be enabled by a mask option. the rti rate selector bits, and the rti and tof enable bits and ?gs are located in the timer control and status regis- ter at location $08. the real time interrupt circuit consists of a three stage divider and a 1 of 4 selec- tor. the clock frequency that drives the rti circuit is f op /2 14 (or f op /16384) with three additional divider stages giving a maximum interrupt period of f op /2 17 (or f op / 131072). the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. if reset is asserted at any time during operation the counter chain will be cleared. 8.1 timer registers the 15-stage multi-function timer contains two registers: a timer counter regis- ter and a timer control/status register. 8.1.1 timer counter register (tcr), $09 the timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions including a soft- ware input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. the value of each bit of the tcr is shown in figure 8-2 . this reg- ister is cleared by reset. figure 8-2. timer counter register tcr $09 0 7 w r 0000000 reset t 6543210 tmr0 tmr2 tmr1 tmr3 tmr4 tmr5 tmr6 tmr7 november 10, 1998 general release specification mc68hc05lj5 multi-function timer motorola rev 1 8-3 8.1.2 timer control/status register (tcsr), $08 the tcsr contains the timer interrupt ?g bits, the timer interrupt enable bits, and the real time interrupt rate select bits. bit 2 and bit 3 are write-only bits which will read as logical zeros. figure 8-3 shows the value of each bit in the tcsr follow- ing reset. figure 8-3. timer control/status register (tcsr) tof - timer over?w flag the tof is a read-only ?g bit. 1 = set when the 8-bit ripple counter rolls over from $ff to $00. a timer interrupt request will be generated if tofe is also set. 0 = reset by writing a logical one to the tof acknowledge bit, tofr. writing to the tof ?g bit has no effect on its value. this bit is cleared by reset. rtif - real time interrupt flag the rtif is a read-only ?g bit. 1 = set when the output of the chosen (1 of 4 selections) real time interrupt stage goes active. a timer interrupt request will be generated if rtie is also set. 0 = reset by writing a logical one to the rtif acknowledge bit, rtifr. writing to the rtif ?g bit has no effect on its value. this bit is cleared by reset. tofe - timer over?w enable the tofe is an enable bit that allows generation of a timer interrupt upon over?w of the timer counter register. 1 = when set, the timer interrupt is generated when the tof ?g bit is set. 0 = when cleared, no timer interrupt caused by tof bit set will be generated. this bit is cleared by reset. rtie - real time interrupt enable the rtie is an enable bit that allows generation of a timer interrupt by the rtif bit. 1 = when set, the timer interrupt is generated when the rtif ?g bit is set. 0 = when cleared, no timer interrupt caused by rtif bit set will be generated. this bit is cleared by reset. rtif tofe 0 7 tof rt1 w r 0000011 6543210 tcsr $08 reset t 0 rtifr 0 tofr rtie rt0 general release specification november 10, 1998 motorola multi-function timer mc68hc05lj5 8-4 rev 1 tofr - timer over?w acknowledge the tofr is an acknowledge bit that resets the tof ?g bit. this bit is unaf- fected by reset. reading the tofr will always return a logical zero. 1 = clears the tof ?g bit. 0 = does not clear the tof ?g bit. rtifr - real time interrupt acknowledge the rtifr is an acknowledge bit that resets the rtif ?g bit. this bit is unaf- fected by reset. reading the rtifr will always return a logical zero. 1 = clears the rtif ?g bit. 0 = does not clear the rtif ?g bit. rt1:rt0 - real time interrupt rate select the rt0 and rt1 control bits select one of four taps for the real time interrupt circuit. table 8-1 shows the available interrupt rates for two f op values. both the rt0 and rt1 control bits are set by reset, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modi?d during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared just prior to changing rti taps. 8.2 cop watchdog timer the cop (computer operating properly) watchdog timer function is imple- mented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset times are listed in table 8-1 . if the cop circuit times out, an internal reset is generated and the reset vector is fetched. prevent- ing a cop time-out is done by writing a logical zero to bit 0 of address $0ff0 as shown in figure 8-4 . the cop register is shared with a test rom byte. this address location is not affected by any reset signals. reading this location will return the test rom byte. when the cop is cleared, only the ?al divide by eight stage (output of the rti) is cleared. the cop watchdog timer can be enabled/ disabled by a mask option. table 8-1. rti and cop rates at f op =3.0mhz bus frequency, f bus =f op =2.0 mhz rt1 rt0 divide ratio rti rate cop reset period (rti x 8) 00 2 14 8.912ms 66ms 01 2 15 16.384ms 131ms 10 2 16 32.768ms 262ms 11 2 17 65.536ms 524ms november 10, 1998 general release specification mc68hc05lj5 multi-function timer motorola rev 1 8-5 figure 8-4. cop watchdog timer location 8.3 operation during stop mode the timer system is cleared when going into stop mode. when stop is exited by an external interrupt or an lvr reset or an external reset , the internal oscilla- tor will resume, followed by a 4064 internal processor oscillator stabilization delay. the timer system counter is then cleared and operation resumes. if chosen by a mask option, the stop instruction will initiate halt mode and the effects on the timer are as described in section 8.4 . 8.4 operation during wait/halt mode the cpu clock halts during the wait/halt mode, but the timer remains active. if interrupts are enabled, a timer interrupt or custom periodic interrupt will cause the processor to exit the wait/halt mode. 7 w r 6543210 cop $0ff0 copr reading $0ff0 returns the contents of rom. unimplemented general release specification november 10, 1998 motorola multi-function timer mc68hc05lj5 8-6 rev 1 november 10, 1998 general release specification mc68hc05lj5 instruction set motorola rev 1 9-1 section 9 instruction set this section describes the addressing modes and instruction types. 9.1 addressing modes the cpu uses eight addressing modes for ?xibility in accessing data. the addressing modes de?e the manner in which the cpu ?ds the data required to execute an instruction. the eight addressing modes are the following: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 9.1.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry ?g (sec) and increment accumulator (inca). inherent instructions require no memory address and are one byte long. 9.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no memory address and are two bytes long. the opcode is the ?st byte, and the immediate data value is the second byte. general release specification november 10, 1998 motorola instruction set mc68hc05lj5 9-2 rev 1 9.1.3 direct direct instructions can access any of the ?st 256 memory addresses with two bytes. the ?st byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. brset and brclr are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 9.1.4 extended extended instructions use only three bytes to access any address in memory. the ?st byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 9.1.5 indexed, no offset indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the ?st 256 memory locations. the index register contains the low byte of the conditional address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000?00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 9.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the ?st 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the conditional address of the operand. these instructions can access locations $0000?01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the ?st 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. november 10, 1998 general release specification mc68hc05lj5 instruction set motorola rev 1 9-3 9.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the conditional address of the operand. the ?st byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. these instructions can address any location in memory. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 9.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu ?ds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two s complement byte that gives a branching range of ?28 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and veri?s that it is within the span of the branch. 9.1.9 instruction types the mcu instructions fall into the following ?e categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions general release specification november 10, 1998 motorola instruction set mc68hc05lj5 9-4 rev 1 9.1.10 register/memory instructions most of these instructions use two operands. one operand is in either the accumulator or the index register. the cpu ?ds the other operand in memory. table 9-1 lists the register/memory instructions. table 9-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub november 10, 1998 general release specification mc68hc05lj5 instruction set motorola rev 1 9-5 9.1.11 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modi?d value back to the memory location or to the register. the test for negative or zero instruction (tst) is an exception to the read-modify-write sequence because it does not write a replacement value. table 9-2 lists the read-modify-write instructions. 9.1.12 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump to subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. all branch instructions use relative addressing. bit test and branch instructions cause a branch based on the state of any readable bit in the ?st 256 memory locations. these three-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu ?ds the conditional branch destination by adding the table 9-2. read-modify-write instructions instruction mnemonic arithmetic shift left asl arithmetic shift right asr clear bit in memory bclr set bit in memory bset clear clr complement (one? complement) com decrement dec increment inc logical shift left lsl logical shift right lsr negate (two? complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst general release specification november 10, 1998 motorola instruction set mc68hc05lj5 9-6 rev 1 third byte to the program counter if the speci?d bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?28 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. table 9-3 lists the jump and branch instructions. table 9-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr november 10, 1998 general release specification mc68hc05lj5 instruction set motorola rev 1 9-7 9.1.13 bit manipulation instructions the cpu can set or clear any writable bit in the ?st 256 bytes of memory. port registers, port data direction registers, timer registers, and on-chip ram locations are in the ?st 256 bytes of memory. the cpu can also test and branch based on the state of any bit in any of the ?st 256 memory locations. bit manipulation instructions use direct addressing. table 9-4 lists these instructions. 9.1.14 control instructions these register reference instructions control cpu operation during program execution. control instructions, listed in table 9-5 , use inherent addressing. table 9-4. bit manipulation instructions instruction mnemonic clear bit bclr branch if bit clear brclr branch if bit set brset set bit bset table 9-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait general release specification november 10, 1998 motorola instruction set mc68hc05lj5 9-8 rev 1 9.1.15 instruction set summary table 9-6 is an alphabetical list of all m68hc05 instructions and shows the effect of each instruction on the condition code register. table 9-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles h i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 c b0 b7 0 b0 b7 c november 10, 1998 general release specification mc68hc05lj5 instruction set motorola rev 1 9-9 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff p 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc general release specification november 10, 1998 motorola instruction set mc68hc05lj5 9-10 rev 1 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ?(m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one? complement) m ? ( ) = $ff ?(m) a ? ( ) = $ff ?(m) x ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ?(m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc m a x m m november 10, 1998 general release specification mc68hc05lj5 instruction set motorola rev 1 9-11 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? conditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two? complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix 30 40 50 60 70 ii ff 5 3 3 6 5 nop no operation inh 9d 2 table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 0 b0 b7 c 0 general release specification november 10, 1998 motorola instruction set mc68hc05lj5 9-12 rev 1 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 b0 b7 c november 10, 1998 general release specification mc68hc05lj5 instruction set motorola rev 1 9-13 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) ?(m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ?$00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (two? complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit not affected table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc motorola instruction set mc68hc05lj5 9-14 rev 1 table 9-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 tax 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb m s b lsb msb november 10, 1998 general release specification mc68hc05lj5 electrical specifications motorola rev 1 10-1 section 10 electrical specifications this section provides the electrical and timing speci?ations for the mc68hc05lj5. 10.1 maximum ratings note maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip. the device is not intended to operate at these conditions. the mcu contains circuitry that protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range from v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . 10.2 thermal characteristics (voltages referenced to v ss ) rating symbol value unit supply voltage v dd 0.3 to +7.0 v test mode (irq pin only) v in v ss ?0.3 to 2v dd + 0.3 v current drain per pin excluding pb1, pb2, v dd and v ss i25ma operating junction temperature t j +150 c operating temperature range mc68hc05lj5 (standard) mc68hc05lj5 (extended) t a t a t l to t h 0 to +70 40 to +85 c c storage temperature range t stg 65 to +150 c characteristic symbol value unit thermal resistance pdip soic q ja q ja 60 60 c/w c/w general release specification november 10, 1998 motorola electrical specifications mc68hc05lj5 10-2 rev 1 10.3 dc electrical characteristics table 10-1. dc electrical characteristics (v dd = 5.0vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) characteristic symbol min typ max unit output voltage i load = 10.0 m a v ol v oh v dd ?0.1 0.1 v output high voltage (i load = 0.8 ma) pa0-5, pb0, pb3-5 v oh v dd ?0.8 v output low voltage (i load = 1.6ma) pa0-3, pb0, pb3-5 (i load = 8ma) pa4-7 (i load = 25ma) pb1, pb2 (see note 8) v ol 0.4 0.4 0.5 v input high voltage pa0-5, pb0-5, irq , reset , osc1 v ih 0.7 v dd ? dd v input low voltage pa0-5, pb0-5, i rq , reset , osc1 v il v ss 0.2 v dd v positive-going input threshold voltage pa6, pa7 v t+ 1.7 v negative-going input threshold voltage pa6, pa7 v t 1.15 v supply current (see notes) run wait stop (lvr on) 25 c ?0 c to +85 c stop (lvr off) 25 c ?0 c to +85 c i dd 5.5 2 160 tbd 8 4 300 tbd ma ma m a m a m a m a i/o ports hi-z leakage current pa0-7, pb0-5 (without individual pull-down/up activated) i z 10 m a input pull-down current pa0-5, pb0, pb3-5 (with individual pull-down activated) i il 50 100 200 m a input current reset , irq , osc1 i in 1 m a november 10, 1998 general release specification mc68hc05lj5 electrical specifications motorola rev 1 10-3 notes: 1. all values shown re?ct average measurements. 2. typical values at midpoint of voltage range, 25 c only. 3. wait i dd : only mft active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 2.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on osc2/r. 5. wait, stop i dd : all ports con?ured as inputs, v il = 0.2 vdc, v ih = v dd 0.2 vdc. 6. stop i dd measured with osc1 = v ss . 7. wait i dd is affected linearly by the osc2/r capacitance. 8. t a = 0 c to +40 c. 9. input voltage level on pa6 or pa7 higher than 2.4v is guaranteed to be recognized as logical one and as logic zero if lower than 0.8v. 10. pa6 and pa7 pull-up resistor values are speci?d under the condition that pin voltage ranges from 0v to 2.4v. capacitance ports (as input or output) rese t , irq , osc1, osc2/r c out c in 12 8 pf pf crystal/ceramic resonator oscillator mode internal resistor osc1 to osc2/r r osc 2 3 4 m w pull-up resistor pa6, pa7 (see note 10) pb1, pb2 r pullup 2 15 5 30 10 60 k w k w lvr trigger voltage v lvri 2.52 2.8 v table 10-1. dc electrical characteristics (v dd = 5.0vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) characteristic symbol min typ max unit general release specification november 10, 1998 motorola electrical specifications mc68hc05lj5 10-4 rev 1 10.4 control timing notes: 1. the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . 2. effects of processing, temperature, and supply voltage (excluding tolerances of external r and c) 3. rc oscillator: typical center frequency is 4mhz. for the speci?d range of the operating center fre- quency from 3.8mhz (min.) to 4.2mhz (max.), the frequency tolerance is guaranteed to be more than ?5% under the conditions that vdd=5vdc 10%, ta = 0 c to +40 c and the tolerance of the external r is at most 1%. table 10-2. control timing (v dd = 5.0vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) characteristic symbol min max units frequency of operation rc oscillator option (see note 3) crystal oscillator option external clock source f osc f osc f osc 3.8 dc 4.2 4.2 4.2 mhz mhz mhz internal operating frequency rc oscillator (f osc ? 2) crystal oscillator (f osc ? 2) external clock (f osc ? 2) f op f op f op 1.9 dc 2.1 2.1 2.1 mhz mhz mhz cycle time (1 ? f op )t cyc 475 ns reset pulse width low t rl 1.5 t cyc irq interrupt pulse width low (edge-triggered) t ilih 0.5 t cyc irq interrupt pulse period t ilil see note 1 t cyc pa0 to pa3 interrupt pulse width high (edge-triggered) t ihil 0.5 t cyc pa0 to pa3 interrupt pulse period t ihih see note 1 t cyc pa7 interrupt pulse width low t ilih 0.5 t cyc osc1 pulse width t oh , t ol 200 ns output high to low transition period pa6, pa7, pb1 t slow 0.5 (typical) t cyc november 10, 1998 general release specification mc68hc05lj5 mechanical specifications motorola rev 1 11-1 section 11 mechanical specifications this section provides the mechanical dimensions for the three available packages for mc68hc05lj5. 11.1 16-pin pdip (case #648) figure 11-1. 16-pin pdip mechanical dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. style 1: pin 1. cathode 2. cathode 3. cathode 4. cathode 5. cathode 6. cathode 7. cathode 8. cathode 9. anode 10. anode 11. anode 12. anode 13. anode 14. anode 15. anode 16. anode style 2: pin 1. common drain 2. common drain 3. common drain 4. common drain 5. common drain 6. common drain 7. common drain 8. common drain 9. gate 10. source 11. gate 12. source 13. gate 14. source 15. gate 16. source a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 general release specification november 10, 1998 motorola mechanical specifications mc68hc05lj5 11-2 rev 1 11.2 20-pin pdip (case #738) figure 11-2. 20-pin pdip mechanical dimensions 11.3 20-pin soic (case #751d) figure 11-3. 20-pin soic mechanical dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application o r use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, i ncluding "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor th e rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1-800-441-2447 or 1-303-675-2140 japan: nippon motorola ltd. spd, strategic planning of?e 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141, japan. 03-5487-8488 asia/pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 mfax tm , motorola fax back system: rmfax0@email.sps.mot.com; http://sps.motorola.com/mfax/; touchtone 1-602-244-6609; us and canada only 1-800-774-1848 home page: http://motorola.com/sps/ mfax is a trademark of motorola, inc. ?motorola, inc., 1998 |
Price & Availability of HC05LJ5GRS
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |