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1 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller features c ustomer p rocurement s pecifica tion n low power consumption - 750 mw n 32 input/output lines n digital inputs nmos levels with internal pull-up resistors n 4 kbytes rom n four direct connect led drive pins n 124 bytes of ram n hardware watch-dog timer (wdt) n two programmable 8-bit counter/timers, each with 6-bit programmable prescaler n six vectored, priority interrupts from six different sources n on-chip rc oscillator n clock frequency: up to 5mhz n low emi emission general description the Z08617 keyboard controller is a member of the z8 ? single-chip microcontroller family with 4 kbytes of rom. the device is housed in a 40-pin dip package, and is manufactured in nmos technology. the Z08617 microcontroller offers fast execution, efficient use of memory, sophisticated interrupt, input/output bit- manipulation capabilities, and easy hardware/soft- ware system expansion along with low cost and low power consumption. the Z08617 architecture is characterized by a flex- ible i/o scheme, an efficient register, i/o, and a number of ancillary features that are useful in many industrial and advanced scientific applications. for applications which demand powerful i/o capabili- ties, the Z08617 provides 32 pins dedicated to input and output. these lines are grouped into four ports, each port consists of 8 lines, and are configurable under software control to provide timing, status signals, and serial or parallel i/o ports. the Z08617 offers low emi emission which is achieved by means of several modifications in the output drivers and clock circuitry of the device. there are two basic address spaces which are avail- able to support this wide range of configurations: program memory and 124 general-purpose registers. the Z08617 offers two on-chip counter/timers with a large number of user-selectable modes. this unbur- dens the program from coping with real-time prob- lems such as counting/timing (figure 1). notes: all signals with a preceding front slash, "/", are active low, e.g., b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss ds96key0300 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 2 general description (continued) port 3 counter/ timers (2) interrupt control port 2 i/o (bit programmable) alu flags register pointer register file 124 x 8-bit machine timing & instruction control program memory program counter vcc gnd output input port 0 port 1 i/o output open-drain (nibble programmable) i/o output open-drain (byte programmable) 44 8 wdt por /wdtout /reset xtal2 xtal1 figure 1. Z08617 functional block diagram
3 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller pin identification figure 2. 40-pin dip pin configuration pin # symbol function direction 1v cc power supply input 2 clk out clock out output 3 rc in z8 clock input 4 p37 port 3, pin 7 output 5 p30 port 3, pin 0 input 6 /reset reset input *7 gnd ground *8 n/c not connected 9 /wdtout watch-dog timer output 10 p35 port 3, pin 5 output pin # symbol function direction 11 gnd ground 12 p32 port 3, pin 2 input 13-20 p07-p00 port 0, pins 0,1,2,3,4,5,6,7 in/output 21-28 p17-p10 port 1, pins 0,1,2,3,4,5,6,7 in/output 29 p34 port 3, pin 4 output 30 p33 port 3, pin 3 input 31-38 p27-p20 port 2, pins 0,1,2,3,4,5,6,7 in/output 34-38 p24-p20 port 2, pins 0, 1, 2, 3, 4 in/output 39 p31 port 3, pin 1 input 40 p36 port 3, pin 6 output table 1. 40-pin dip pin identification 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vcc clk out rc in p37 p30 /reset *gnd *n/c /wdtout p35 gnd p32 p00 p01 p02 p03 p04 p05 p06 p07 p36 p31 p27 p26 p25 p24 p23 p22 p21 p20 p33 p34 p17 p16 p15 p14 p13 p12 p11 p10 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Z08617 dip note: * pin 8 is connected to the chip, although used only for testing. this pin must float. pin 7 is a test pin and must be grounded.
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 4 absolute maximum ratings symbol description min max units v cc supply voltage* C0.3 +7.0 v t stg storage temp C 6 5 +150 c t a oper ambient temp ? ? notes: * voltage on all pins with respect to gnd. ? see ordering information stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliabil- ity. standard test conditions the characteristics listed here apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (figure 17). from output under test 150 pf figure 17. test load diagram standard test conditions t a = 25 c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to ground. parameter max input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf
5 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller dc characteristics v cc = 4.75v to 5.25v @ 0 c to -55 c sym parameter min max typ* unit condition v ih input high voltage 2.0 v cc v v il input low voltage C0.3 0.8 v v rh reset input high voltage 3.8 v cc v v rl reset input low voltage C0.3 0.8 v v oh output high voltage 2.0 v i oh = C250 m a (port 2 only) output high voltage 2.4 v i oh = C250 m a (port 3 only) v ol output low voltage 0.8 v i ol = 10.0 ma (see note [1] below.) i il input leakage C10 10 m av in = 0v, 5.25v (see note [3] below.) i ol output leakage C10 10 m av in = 0v, 5.25v (see note [2] below.) i ir reset input current C335 C775 C477 m av in = 0v, 5.25v i r1 input current C335 C775 m a pull-up resistor=10.4 kohms, v in =0.0v i r2 input current C1.6 C2.9 ma pull-up resistor = 2.4 kohms, v in =0.0v i cc v cc supply current 160 ma wdt watch-dog timer 2.0 ma v ol =0.4 volt notes: * typical @ 25 c [ 1 ] ports p37-p34 may be used to sink 12 ma. these may be used for leds or as general-purpose outputs requiring high sink current. [ 2 ] p00-p07, p10-p17, p20-p25, p30-p33 as output mode open- drain as a logic one. [ 3 ] p00-p07, p10-p17, p20-p25, p30-p33 as output mode open- drain as a logic one.
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 6 pin functions rcin this pin is connected between a precision resistor on the power supply from the precision rc oscillator. clk out this pin is the syste m clock of the z8 and runs at the frequency of the rc oscillator. any load on this pin will effect the rc oscillator frequency. port 0 (p07-p00). port 0 is an 8-bit, nibble program- mable, bi-directional, nmos compatible i/o port. these eight i/o lines can be configured under software control as a nibble input port, or as a nibble open-drain output port. when used as an i/o port, inputs are standard nmos (figure 5). port p03-p00 has 10.4 kohms ( 35%) pull-up resistors when configured as inputs. figure 5. port 0 configuration port 0 i/o (open-drain output) z8615 4 4 input output pad oen 10.4 kohms (a) port p00-p03 input output pad oen (b) port p04-p07
7 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller pin functions (continued) port 1 (p17-p10). port 1 is an 8-bit, byte programmable, bidirectional, nmos compatible i/o port. these eight i/o lines are configured under software control program as a byte input port or as an open-drain output port. when used as an i/o port, inputs are standard nmos (figure 6). port 1 i/o (open-drain output) z8615 8 input output pad oen figure 6. port 1 configuration
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 8 port 2 (p27-p20). port 2 is an 8-bit, bit programmable, bi- directional, nmos compatible i/o port. these eight i/o lines are configured under the software control program for i/o. port 2 can be programmed as bit-by-bit indepen- dently, as input or output, or configured to provide open- drain outputs (figure 7). p26 and p27 have 2.4 kohms ( 25%) pull-up resistors and are capable of sourcing 2.4 ma. p24 and p25 have 10.4 kohms ( 35%) pull-up when configured as inputs. open-drain out oen in pad input (a) ports p20-p23 port 2 (i/o) z8615 open-drain out oen in pad 10.4 kohms input (b) ports p24-p25 open-drain out oen in pad 2.4 kohms input (c) ports p26-p27 figure 7. port 2 configuration
9 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller pin functions (continued) port 3 (p37-p30). port 3 is an 8-bit, nmos compatible four- fixed-input and four-fixed-output i/o port. these eight i/o lines have four-fixed-input (p33-p30) and four-fixed-out- put (p37-p34) ports. port 3 inputs have 10.4 kohms ( 35%) pull-up resistors and port 3 outputs are capable of driving up to four leds. port 3 is configured under software control to provide the following control functions: four external interrupt request signals (irq3-irq0); timer input and output signals (t in and t out - figure 8). /reset (input, active low). when activated, /reset initializes the Z08617. when /reset is deactivated, program execution begins from the internal program location at 000ch. reset pin has a 10.4 kohms pull- up resistor. once this pin is pulled low, it takes about 150 ms for microcon-troller initialization. figure 8. port 3 configuration port 3 (i/o or control) z8615 input pad output pad (a) port 3 p34-p37 (b) port 3 p30-p33 10.4 kohms
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 10 functional description the device incorporates special functions to enhance zilog's z8 applications as a keyboard controller, scien- tific research and advanced technologies applications. program memory. the 16-bit program counter ad- dresses 4 kbytes of program memory space at inter- nal locations (figure 9). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations have six 16-bit vectors that correspond to the six available interrupts. byte 12 to byte 4095 consists of on-chip, mask programmed rom. addresses 4096 and greater are reserved. 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 65535 4096 4095 reserved figure 9. program memory map
11 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller functional description (continued) register file. the register file (figure 10) consists of four i/o port registers, 124 general-purpose registers and 16 control and status registers (r3-r0, r127-r4, and r255- r240, respectively). the instructions can access registers directly or indirectly through an 8-bit address field. this allows short, 4-bit register addressing using the register pointer (figure 11). in the 4-bit mode, the register file is divided into nine working-register groups, each occupy- ing 16 continuous locations. the register pointer ad- dresses the starting location of the active working-register group. figure 10. register file configuration figure 11. register pointer configuration stack pointer (bits 7-0) r255 general-purpose register (bits 7-0) register pointer program control flags interrupt mask register interrupt request register interrupt priority register ports 1-0 mode port 3 mode port 2 mode t0 prescaler timer/counter0 t1 prescaler timer/counter1 timer mode reserved not implemented general-purpose registers port 3 port 2 port 1 port 0 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 r127 r3 r2 r1 r0 spl gpr rp flags imr irq ipr p01m p3m p2m preq t0 pre1 t1 tmr p3 p2 p1 p0 r4 location identifiers the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports specified working register group the lower nibble of the register file address provided by the instruction points to the specified register. r3 r2 r1 r0 register group 1 register group 0 r15 to r0 register group f r15 to r4 r3 to r0 r15 to r0 ? ? ? ? ? ff f0 0f 00 1f 10 2f 20 ? ? ? ? ? ? ? ? ?
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 12 stack. the Z08617 internal register files are used for the stack. an 8-bit stack pointer (r255) is used for the internal stack that resides within the 124 general-purpose regis- ters. counter/timers. there are two 8-bit programmable counter/timers (t0-t1), each driven by its own 6-bit programmable prescaler. the t1 prescaler can be driven by internal or external clock sources, however, the t0 prescaler is driven by the internal clock only (figure 12). the 6-bit prescalers can further divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its own counter, which decrements the value (1 to 256) that has been loaded into the counter. when both the counter and prescaler reach the end of count, a timer interrupt request, irq4 (t0) or irq5 (t1), is generated. the counter can be programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo- n continuous mode). the counters, but not the prescalers, are read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and are either the internal microprocessor clock divided by four, or an external signal input through port 3. the timer mode register configures the external timer input as an external clock, a trigger input that can be retriggerable or non-triggerable, or as a gate input for the internal clock. the counter/timers can be pro- grammable cascaded by connecting the t0 output to the input of t1. port 3 lines p36 also serves as a timer output (t out ) through which t0, t1 or the internal clock are output. figure 12. counter/timers block diagram pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter ? 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register clock logic irq4 t p36 out irq5 internal data bus write write read internal clock gated clock triggered clock t p31 write write read internal data bus external clock internal clock ? 4 ? 2 in clk out rc osc ? 2
13 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller functional description (continued) interrupts. the Z08617 has six different interrupts from six different sources. these interrupts are maskable and prioritized (figure 13). the six sources are divided as follows: four sources are claimed by port 3 lines p33-p30, and two are claimed by the counter/timers. the interrupt masked register globally or individually enables or dis- ables the six interrupts requests. when more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the interrupt priority register. all inter- rupts are vectored through locations in the program memory. when an interrupt machine cycle is activated an interrupt request is granted. this disables all of the subse- quent interrupts, saves the program counter and status flags, and then branches to the program memory vector location reserved for that interrupt. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt request needs service. irq imr ipr priority logic 6 global interrupt enable vector select interrupt request 6 irq0-irq5 figure 13. interrupt block diagram
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 14 rc oscillator. the Z08617 provides an internal capacitor to accommodate an rc oscillator configuration. a 1% precision resistor is necessary to achieve 10% accurate frequency oscillation. figure 14. oscillator configuration emi. the Z08617 offers low emi emission due to circuit modifications to improve emi performance. the inter- nal divide-by-two circuit has been removed to improve emi performance. rc oscillator xtal1 nc 1% precision xtal2 5v
15 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller functional description (continued) watch-dog timer. the Z08617 is equipped with a hard- ware watch-dog timer which will be turned on automati- cally by power-on (figure 15). the watch-dog timer must be refreshed at least once every 50 ms by executing the instruction wdt (opcode = %5f), otherwise the Z08617 will reset itself if /wdtout pin 9 is connected to /reset (pin 6). figure 16 shows the block diagram of wdt. the watch-dog timer is automatically enabled upon power-up of the microcontroller and /reset going high. the /wdtout pin can be connected to the /reset pin to provide an automatic reset upon wdt time-out. dur- ing wdt time-out, the /wdtout pin goes low for approximately 8-15 m s. wdt hot bit. bit 7 of the interrupt request register (irr register fah) determines whether a hot start or cold start occurred. a cold start is defined as a rest occurring from the power-up of the Z08617 (bit 7 is set to zero upon power-up). a hot start occurs when a wdt time- out has occurred (bit 7 is set to 1). bit 7 of the irq register is read-only and is automatically reset to 0 when accessed. power-on reset. upon power-up of the microcontroller, a reset condition is enabled. a delay of 150 ms 20% is used to assist in initializing the microcontroller. /reset vcc /wdt output internal reset por 8-15 m s reset delay * reset delay = por 150 ms 20% figure 15. wdt turn-on timing after reset reset internal reset counter reset logic 50 ms 10.4 kohms internal rc wdt 150 ms figure 16. wdt block diagram
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 16 z8 ? control register diagrams d7 d6 d5 d4 d3 d2 d1 d0 0 = disable t0 count 1 = enable t0 count 0 = no function 1 = load t0 0 = no function 1 = load t1 0 = disable t1 count 1 = enable t1 count tin modes 00 = external clock input 01 = gate input 10 = trigger input (non-retriggerable) 11 = trigger input (retriggerable) tout mode 00 = not used 01 = t0 out 10 = t1 out 11 = internal clock out r241 tmr figure 18. timer mode register (f1h: read/write) d7 d6 d5 d4 d3 d2 d1 d0 t1 initial value (when write) (range 1-256 decimal 01-00 hex) t1 current value (when read) r242 t1 figure 19. counter timer 1 register (f2h: read/write) d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 = t1 single pass 1 = t1 modulo n clock source 1 = t0 internal 0 = t0 external timing input (tin) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 figure 20. prescaler 1 register (f3h: write only) d7 d6 d5 d4 d3 d2 d1 d0 t0 initial value (when write) (range: 1-256 decimal 01-00 hex) t0 current value (when read) r244 t0 figure 21. counter/timer 0 register (f4h: read/write) d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 = t0 single pass 1 = t0 modulo n reserved (must be 0) prescaler modulo (range: 1-64 decimal 01-00 hex) r245 pre0 d7 d6 d5 d4 d3 d2 d1 d0 p20-p27 i/o definition 0 defines bit as output 1 defines bit as input r246 p2m figure 22. prescaler 0 register (f5h: write only) figure 23. port 2 mode register (f6h: write only) figure 24. port 3 mode register (f7h: write only) d7 d6 d5 d4 d3 d2 d1 d0 0 port 2 pull-ups open-drain 1 port 2 pull-ups active reserved (must be 0) r247 p3m
17 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller d7 d6 d5 d4 d3 d2 d1 d0 p00 - p03 mode 00 = output 01 = input r248 p01m stack selection 1 = internal (must be 1) p10-p17 mode 0 = byte output 1 = byte input reserved (must be 0) p04 - p07 mode 00 = output 01 = input figure 25. port 0 and 1 mode register (f8h: write only) d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority reserved = 000 c > a > b = 001 a > b > c = 010 a > c > b = 011 b > c > a = 100 c > b > a = 101 b > a > c = 110 reserved = 111 irq3, irq5 priority (group a) 0 = irq5 > irq3 1 = irq3 > irq5 irq0, irq2 priority (group b) 0 = irq2 > irq0 1 = irq0 > irq2 irq1, irq4 priority (group c) 0 = irq1 > irq4 1 = irq4 > irq1 reserved (must be 0) r249 ipr figure 26. interrupt priority register (f9h: write only) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) 1 enables irq0-irq5 (d0 = irq0) 1 enables interrupts r251 imr figure 28. interrupt mask register (fbh: read/write) figure 27. interrupt request register (fah: read/write) z8 ? control register diagrams (continued) d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input (d0 = irq0) irq1 = p33 input irq2 = p31 input irq3 = p30 input irq4 = t0 irq5 = t1 reserved (must be 0) r250 irq wdt hot bit 0 = por* 1 = wdt time out * default setting after setup.
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 18 d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag r252 flags figure 29. flag register (fch: read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) r4 r253 rp r5 r6 r7 register pointer figure 30. register pointer (fdh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 gpr r254 gpr figure 31. general-purpose register (feh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp0-sp7) r255 spl figure 32. stack pointer (ffh: read/write)
19 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller instruction set notation addressing modes. the following notation is used to describe the addressing modes and instruction opera- tions as shown in the instruction summary. symbol meaning irr indirect register pair or indirect work- ing- register pair address irr indirect working-register pair only x indexed address da direct address ra relative address im immediate r register or working-register address r working-register address only ir indirect-register or indirect working-register address ir indirect working-register address only rr register pair or working register pair address symbols. the following symbols are used in describing the instruction set. symbol meaning dst destination location or contents src source location or contents cc condition code @ indirect address prefix sp stack pointer pc program counter flags flag register (control register 252) rp register pointer (r253) imr interrupt mask register (r251) flags. control register (r252) contains the following six flags: symbol meaning c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag affected flags are indicated by: 0 clear to zero 1 set to one * set to clear according to operation - unaffected x undefined
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 20 condition codes value mnemonic meaning flags set 1000 always true 0111 c carry c = 1 1111 nc no carry c = 0 0110 z zero z = 1 1110 nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 eq equal z = 1 1110 ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than [z or (s xor v)] = 0 0010 le less than or equal [z or (s xor v)] = 1 1111 uge unsigned greater than or equal c = 0 0111 ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 0000 f never true (always false)
21 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller instruction formats instruction summary note: assignment of a value is indicated by the symbol ? . for example: dst ? dst + src indicates that the source data is added to the desti- nation data and the result is stored in the destination location. the notation addr (n) is used to refer to bit (n) of a given operand location. mode dst/src opc dst opc mode opc src dst opc value opc opc mode src/dst dst/src opc src/dst dst/src opc value dst opc ra dst/cc 7fh ffh 6fh opc dst dst/src 1 1 1 0 dst 1 1 1 0 src 1 1 1 0 mode src opc dst mode dst opc value opc src mode dst opc mode address x dst/src opc dau cc dal dau dal opc src 1 1 1 0 dst 1 1 1 0 dst 1 1 1 0 src 1 1 1 0 dst 1 1 1 0 clr, cpl, da, dec, decw, inc, incw, pop, push, rl, rlc, rr, rrc, sra, swap jp, call (indirect) or or or or or or or srp adc, add, and, cp, or, sbc, sub, tcm, tm, xor ld, lde, ldei, ldc, ldci ld ld djnz, jr stop/halt ld ld jp call adc, add, and, cp, ld, or, sbc, sub, tcm, tm, xor adc, add, and, cp, ld, or, sbc, sub, tcm, tm, xor one-byte instructions two-byte instructions three-byte instructions ccf, di, ei, iret, nop, rcf, ret, scf or
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 22 instruction summary (continued) address flags instruction mode opcode affected and operation dst src byte (hex) c z s v d h adc dst, src ? 1[ ] [[[[ 0 [ dst ? dst + src + c add dst, src ? 0[ ] [[[[ 0 [ dst ? dst + src and dst, src ? 5[ ] [[ 0CC dst ? dst and src call dst da d6 CCCCCC sp ? sp C 2 irr d4 @sp ? pc, pc ? dst ccf ef [ CCCCC c ? not c clr dst r b0 CCCCCC dst ? 0irb1 com dst r 6 0 C [[ 0CC dst ? not dst ir 6 1 cp dst, src ? a[ ] [[[[ CC dst C src da dst r 4 0 [[[ xC C dst ? da dst ir 4 1 dec dst r 0 0 C [[[ CC dst ? dst C 1 ir 0 1 decw dst rr 8 0 C [[[ CC dst ? dst C 1 ir 8 1 di 8f CCCCCC imr(7) ? 0 djnz r, dst ra ra CCCCCC r ? r C 1 r = 0 C f if r 1 0 pc ? pc + dst range: +127,C128 ei 9f CCCCCC imr(7) ? 1 address flags instruction mode opcode affected and operation dst src byte (hex) c z s v d h inc dst r re C [[[ CC dst ? dst + 1 r = 0 C f r20 ir 2 1 incw dst rr a 0 C [[[ CC dst ? dst + 1 ir a 1 iret bf [[[[[[ flags ? @sp; sp ? sp + 1 pc ? @sp; sp ? sp + 2; imr(7) ? 1 jp cc, dst da cd CCCCCC if cc is true c = 0 C f pc ? dst irr 3 0 jr cc, dst ra cb CCCCCC if cc is true, c = 0 C f pc ? pc + dst range: +127,C128 ld dst, src r im rc CCCCCC dst ? src r r r 8 rr r9 r = 0 C f rx c7 xr d7 rir e3 ir r f3 rr e4 rir e5 rim e6 ir im e 7 ir r f 5 ldc dst, src r irr c2 CCCCCC ldci dst, src ir irr c3 CCCCCC dst ? src r ? r + 1; rr ? rr + 1
23 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller address opcode flags instruction mode byte affected and operation dst src (hex) c z s v d h sub dst, src ? 2[ ] [[[[1[ dst ? dst C src swap dst r f 0 x [[ xC C ir f 1 tcm dst, src ? 6[ ]C [[ 0CC (not dst) and src tm dst, src ? 7[ ]C [[ 0CC dst and src wdt 5f C xxxC C xor dst, src ? b[ ]C [[ 0CC dst ? dst xor src instruction summary (continued) address opcode flags instruction mode byte affected and operation dst src (hex) c z s v d h nop ff CCCCCC or dst, src ? 4[ ] C [[ 0CC dst ? dst or src pop dst r 50 CCCCCC dst ? @sp; ir 5 1 sp ? sp + 1 push src r 70 CCCCCC sp ? sp C 1; ir 7 1 @sp ? src rcf cf 0CCCCC c ? 0 ret af CCCCCC pc ? @sp; sp ? sp + 2 rl dst r 9 0 [[[[ CC ir 9 1 rlc dst r 1 0 [[[[ CC ir 1 1 rr dst r e0 [[[[ CC ir e 1 rrc dst r c0 [[[[ CC ir c 1 sbc dst, src ? 3[ ] [[[[ 1 [ dst ? dst src C c scf df 1CCCCC c ? 1 sra dst r d0 [[[ 0CC ir d 1 srp src im 31 CCCCCC rp ? src c 70 c 70 c 70 c 70 c 70 ? these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13. address mode lower dst src opcode nibble r r [2] r ir [3] r r [4] r ir [5] r im [6] ir im [7] 7430
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 24 6.5 dec r1 6.5 dec ir1 6.5 add r1, r2 6.5 add r1, ir2 10.5 add r2, r1 10.5 add ir2, r1 10.5 add r1, im 10.5 add ir1, im 0123456789 abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) bytes per instruction 23 231 6.5 rlc r1 6.5 rlc ir1 6.5 adc r1, r2 6.5 adc r1, ir2 10.5 adc r2, r1 10.5 adc ir2, r1 10.5 adc r1, im 10.5 adc ir1, im 6.5 inc r1 6.5 inc ir1 6.5 sub r1, r2 6.5 sub r1, ir2 10.5 sub r2, r1 10.5 sub ir2, r1 10.5 sub r1, im 10.5 sub ir1, im 10.5 decw rr1 10.5 decw ir1 6.5 rl r1 6.5 rl ir1 10.5 incw rr1 10.5 incw ir1 6.5 cp r1, r2 6.5 cp r1, ir2 10.5 cp r2, r1 10.5 cp ir2, r1 10.5 cp r1, im 10.5 cp ir1, im 6.5 clr r1 6.5 clr ir1 6.5 xor r1, r2 6.5 xor r1, ir2 10.5 xor r2, r1 10.5 xor ir2, r1 10.5 xor r1, im 10.5 xor ir1, im 6.5 rrc r1 6.5 rrc ir1 12.0 ldc r1, irr2 18.0 ldci ir1, irr2 10.5 ld r1,x,r2 6.5 sra r1 6.5 sra ir1 20.0 call* irr1 20.0 call da 10.5 ld r2,x,r1 6.5 rr r1 6.5 rr ir1 6.5 ld r1, ir2 10.5 ld r2, r1 10.5 ld ir2, r1 10.5 ld r1, im 10.5 ld ir1, im 8.5 swap r1 8.5 swap ir1 6.5 ld ir1, r2 10.5 ld r2, ir1 6.5 ld r1, r2 6.5 ld r2, r1 12/10.5 djnz r1, ra 12/10.0 jr cc, ra 6.5 ld r1, im 12.10.0 jp cc, da 6.5 inc r1 6.1 di 6.1 ei 14.0 ret 16.0 iret 6.5 rcf 6.5 scf 6.5 ccf 6.0 nop 10.5 cp r , r 12 4 a lower opcode nibble pipeline cycles mnemonic second operand execution cycles upper opcode nibble first operand legend: r = 8-bit address r = 4-bit address r1 or r1 = dst address r2 or r2 = src address sequence: opcode, first operand, second operand note: blank areas not defined. * 2-byte instruction appears as a 3-byte instruction 8.0 jp irr1 6.1 srp im 6.5 sbc r1, r2 6.5 sbc r1, ir2 10.5 sbc r2, r1 10.5 sbc ir2, r1 10.5 sbc r1, im 10.5 sbc ir1, im 8.5 da r1 8.5 da ir1 6.5 or r1, r2 6.5 or r1, ir2 10.5 or r2, r1 10.5 or ir2, r1 10.5 or r1, im 10.5 or ir1, im 10.5 pop r1 10.5 pop ir1 6.5 and r1, r2 6.5 and r1, ir2 10.5 and r2, r1 10.5 and ir2, r1 10.5 and r1, im 10.5 and ir1, im 6.5 com r1 6.5 com ir1 6.5 tcm r1, r2 6.5 tcm r1, ir2 10.5 tcm r2, r1 10.5 tcm ir2, r1 10.5 tcm r1, im 10.5 tcm ir1, im 10/12.1 push r2 12/14.1 push ir2 6.5 tm r1, r2 6.5 tm r1, ir2 10.5 tm r2, r1 10.5 tm ir2, r1 10.5 tm r1, im 10.5 tm ir1, im 6.0 wdt opcode map
25 Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller package information 40-pin dip package diagram
Z08617 nmos z8 ? 8-b it mcu k eyboard c ontroller 26 ordering information 5 mhz Z0861705psc for fast results, contact your local zilog sales office for assistance in ordering the part desired. package p = plastic dip v = plastic leaded chip carrier speed 05 = 5 mhz environmental c = plastic standard temperature s = 0 c to +70 c (standard temp for the z8615 is 0 to C55 c) example: z 8615 05 p s* c environmental flow temperature (standard temp for the z8615 is 0 to C55 c) package speed product number zilog prefix is a z8615, 5 mhz, dip, 0 c to C55 c, plastic standard flow

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