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" for more information + ! " increased clock speeds and faster initial burst access on am29bdd160g application note publication number 27384 revision a amendment 0 issue date december 12, 2002
publication# 27384 rev: a amendment/ 0 issue date: december 12, 2002 1 increased clock speeds and faster initial burst access modification to burst initial access delay control and cfi device geometry definition? revision 4a versus revisions 4 and earlier application note introduction this application note discusses design improvements to the am29bdd160g. technology and application developers are increasingly requiring flash memory with higher clock speeds and faster access times. this is particularly true for the automotive market in anti-lock braking, engine control, and transmission control appli- cations. one of the factors affecting system performance is the interface between the flash mem- ory and the microprocessor. flash memory in burst mode (synchronous) requires a longer access time for the initial access than subsequent accesses (as fast as one clock cycle at 66 mhz). flash burst initial access delay is therefore an important factor influencing sys- tem performance. amd is the world leader in flash memory design, de- velopment and production, and is committed to continuous improvement of flash memory capability. the am29bdd160g 16 megabit flash memory is a prime example of how this commitment is driving de- sign modifications. improvements to the am29bdd160g have resulted in significantly de- creased the burst initial access delay. the number of wait states associated with the burst initial access in revision 4a (versus all previous revisions) has been decreased by one state across all frequencies. the am29bdd160g now provides for a 66 mhz operation with a burst initial access time of five clock cycles and subsequent burst access time of one clock cycle (also known as 5-1-1-1? at 56 mhz and 66 mhz). design improvements require changes to both the sili- con revision level (incremented from 4 to 4a) and the am29bdd160g datasheet revision level (incremented from b to c). there are three areas of discussion: initial access delay control user configurable control register determines the ini- tial access delay in burst mode i.e., initial access delay control (burst control configuration). allows for proper configuration of the flash memory to match the micro- processor interface. cfi device geometry definition fixed configuration information in common flash memory interface i.e., cfi device geometry definition containing details about memory size, word?size, and erase block configuration. summary of silicon revision 4 and 4a differ- ences discussion of differences between silicon revision 4 from 4a with respect to external attributes (such as part number, part marking) and internally through interroga- tion of flash configuration registers (software). this third section also discusses issues that should be con- sidered when different revision level devices are used.
2 increased clock speeds and faster initial burst access december 12, 2002 burst initial access delay control (burst control configuration) design modifications have decreased the burst initial access delay by one clock cycle for all control register configuration values and for frequencies up to 66 mhz. configuration registers cr13 through cr10 deter- mine the burst initial access delay. the burst initial access delay is defined as the number of clk cycles that must elapse from the first valid clock edge after adv# assertion (or the rising edge of adv#) until the first valid clk edge when the data is valid. figure 1 and table 1 are valid for the majority of applications, and have the following operating conditions: 1. burst initial access starts with the first clk rising edge after adv# assertion. 2. configuration register 6 is set to 1 (cr[6] = 1). burst starts and data outputs on rising clk edge. for a complete discussion of this and other operating conditions see the am29bdd160g datasheet (publi- cation# 24960 rev: c or later). for example, revision 4 control register setting cr[13- 10] = 0010 results in a burst initial access delay of five clock cycles; while revision 4a the same control regis- ter setting results in a burst initial access delay with four clock cycles. . notes: 1. burst access process starts when rising clk edge after adv# assertion. 2. configuration register 6 is set to 1 (rc[6] = 1). burst starts and data outputs on rising clk edge. figure 1. burst initial access delay control table 1. burst initial access delay control configuration register setting burst initial access delay (clk cycles) cr13 cr12 cr11 cr10 rev. 4 rev. 4a 00 0 0 3 2 00 0 1 4 3 00 1 0 5 4 00 1 1 6 5 01 0 0 7 6 01 0 1 8 7 01 1 0 9 8 01 1 1 10 9 burst initial access delay 1 3 2 clk adv# a18-a0 dq31-dq0 valid 3 clk cycles burst initial access delay d0 d1 d2 d3
december 12, 2002 increased clock speeds and faster initial burst access 3 cfi device geometry definition the am29bdd160g datasheet (publication number 24960) table 13 through table 16 details the cfi de- vice information. these tables outline the flash device and host system software interrogation handshake that allows specific vendor-specific software algorithms to be used for entire families of devices. table 15 details the cfi device geometry such as memory size (ca- pacity), interface description (8,16, 32 bit word size), and erase block region information. the quantity of erase blocks regions is stored in memory location 2ch for a 32 bit wide word (or 58h for a 16 bit wide word). revision 4 has a value of 4h while for revision 4a has a value of 3h. a query returns a correct result in both cases. table 2 shows the valid configuration informa- tion for the number of erase block regions within the device. all devices have three usable erase blocks. revisions 4 and earlier have a fourth erase block; however, that erase block has a size of 0 x 0 kb. this is a zero length block and is effectively not present. revision 4a re- moved the fourth erase block and modified the cfi device geometry definition accordingly. see table 3. this change allows for a distinction of the two revisions by querying the cfi information table. table 2. cfi geometry data table 3. erase block region configurations address (x32 mode) address (x16 mode) data description 2ch 58h 3h or 4h number of erase block regions within device 3h for flash part numbers: am29bdd160gx54cyz, am29bdd160gx65dyz, am29bdd160gx64cyz, and am29bdd160gx65ayz, where x, y, and z reflect user selectable options, i.e. x = boot sector, y = package, z = temperature 4h for flash part numbers: am29bdd160gx80cyz, am29bdd160gx90ayz, and am29bdd160gb? ds3/4/5/6/7, where x, y, and z reflect user selectable options, i.e. x = boot sector, y = package, z = temperature. these part numbers are obsolete and are replaced by the above parts erase block region revisons 4 and earlier revision 4a description 1 8 x 8 kb 8 x 8 kb same size 2 30 x 64 kb 30 x 64 kb same size 3 8 x 8 kb 8 x 8 kb same size 4 0 x 0 kb none block of 0 x 0 is unusable and is effectively not present
4 increased clock speeds and faster initial burst access december 12, 2002 summary of silicon revision 4 and 4a differences hardware/physical considerations burst initial access delay control revision 4 and 4a differ by one clock cycle for a partic- ular setting. see burst initial delay access discussion above for details. cfi device geometry definition, number if erase block regions, memory location 2ch while in x32 mode) revision 4 has a value of 4h while revision 4a has a value of 3h. software considerations cfi device geometry definition the cfi device geometry definition change between revisions provides software/firmware to determine of the revision level of a given flash device by interrogat- ing the cfi information. software/firmware can then program the device appropriately for proper operation by programming the burst initial access delay. this assumes that the flash device has a speed rating (d, c, or a) compatible with the microprocessor. datasheet/part number considerations device speed and clock rate information the product selector guide and ordering information sections in the datasheet have details on device speed and clock rate. revisions 4 and earlier have options for 80c and 90a while revision 4a has options for 54d, 64c, and 65a. the 80c and 90a options for revisions 4 are obsolete with revision 4a. ordering information (part number) revisions 4 and earlier have the following valid combi- nations, which are obsolete with revision 4a: am29bdd160gx80cyz, am29bdd160gx90ayz, and am29bdd160gb-ds3/4/5/6/7 revision 4a has the following valid combinations: am29bdd160gx54dyz, am29bdd160gx64cyz, am29bdd160gx65ayz,and am29bdd160gy65dyz note: x, y, and z reflect user selectable options, i.e. x = boot sec- tor, y = package, z = temperature additional considerations it is important that each user understand that the micro- processor of choice must be paired to a flash device with a compatible speed and clock rate. achieving in- tended operation of the system is not just a matter of interrogating the cfi device geometry definition to de- termine the revision level and configuring the flash device. for example: a flash device must meet or exceed the microproces- sor clock speed. assume that a revision 4 (or earlier revision) flash device with a device speed and clock rate of 80c (80 ns, 56 mhz) is used. then later, when a revision 4a device replaces the revision 4 device, a flash device speed and clock rate 65a (65 ns, 40 mhz) cannot be used. the reason is the 65a part has a maximum clock rate of 40 mhz, which is less than the 80c revision 4 device. the example above demonstrates that simply interro- gating the cfi device geometry definition to determine the revision level is not sufficient. there is no way to determine that an a (40 mhz) device is in a system clocked at a c s peed (56 mhz). the device must be capable of operating properly at the micropro- cessor clock speed. trademarks copyright ? 2002 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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