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low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 1 of 13 http://www.cypress.com approved product fs781/82/84 features ? spread spectrum clock generator (sscg) with 1x, 2x and 4x outputs ? 6 to 82 mhz operating frequency range. ? modulates external clocks including crystals, crystal oscillators and ceramic resonators. ? programmable modulation with simple r-c external loop filter (lf) ? center spread modulation. ? 3 - 5 volt power supply. ? ttl/cmos compatible outputs. ? low short term jitter. ? low power dissipation; 3.3 vdc = 37 mw - typical 5.0 vdc = 115 mw - typical ? available in 8 pin soic and tssop packages. applications ? desktop/notebook computers ? printers, copiers and mfp ? scanners and fax ? lcd displays and monitors ? cd-rom, vcd and dvd ? automotive and embedded systems ? networking, lan/wan ? digital cameras and camcorders ? modems benefits ? programmable emi reduction ? fast time to market ? lower cost of compliance ? no degradation in rise/fall times ? lower component and pcb layer count product description the cypress fs781/2/4 are spread spectrum clock generator ics (sscg) designed for the purpose of reducing electro magnetic interference (emi) found in today?s high-speed digital systems. the fs781/2/4 sscg clocks use an imi proprietary technology to modulate the input clock frequency, fs out by modulating the frequency of the digital clock. by modulating the reference clock the measured emi at the fundamental and harmonic frequencies of fsout is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements without degrading digital waveforms. the cypress fs781/2/4 clocks are very simple and versatile devices to use. by programming the two range select lines, s0 and s1, any frequency from 6 to 82 mhz operating range can be selected. the fs781/2/4 are designed to operate over a very wide range of input frequencies and provides 1x, 2x and 4x modulated clock outputs. the fs78x devices have a simple frequency selection table that allows operation from 6 mhz to 82 mhz in four separate ranges. the bandwidth of the frequency spread at fsout is determined by the values of the loop filter components. the modulation rate is determined internally by the input frequency and the selected input frequency range. the bandwidth of these products can be programmed from as little as 0.6% up to as much as 4.0% by selecting the proper loop filter value. refer to the loop filter selection chart on page 6 for recommended values. due to a wide range of application requirements, an external loop filter (lf) is used on the fs78x products. the user can select the exact amount of frequency modulation suitable for the application. using a fix internal loop filter would severely limit the use of a wide range of modulation bandwidths (spread %) to a few discrete values. refer to fs791/2/4 products for applications requiring 80 to 140 mhz frequency range.
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 2 of 13 http://www.cypress.com approved product fs781/82/84 block diagram figure 1. block diagram ordering information product number fm-out scaling package type production flow fs781bzb 1xfin 8 pin 150 mil soic commercial, 0 to 70 c fs782bzb 2xfin 8 pin 150 mil soic commercial, 0 to 70 c fs784bzb 4xfin 8 pin 150 mil soic commercial, 0 to 70 c fs781bt 1xfin 8 pin 169 mil tssop commercial, 0 to 70 c fs781bt 2xfin 8 pin 169 mil tssop commercial, 0 to 70 c fs781bt 4xfin 8 pin 169 mil tssop commercial, 0 to 70 c marking example: date code fs781bzb lot number fs78xbzb flow ( ? b ? flow not indicated on tssop package) packages z = soic (150 mil) t = tssop (169 mil) revisions device number phase detector vco 1(3) 2(4) xin xout 10 pf. reference divider 8 pf 8 pf 250 k vco / n modulation control input control logic output divider and mux power contol logic 3(5) 7(1) 8(2) 5(7) 4(6) vdd s0 s1 fsout loop filter vss 6(8) vss vdd (tssop pin #)
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 3 of 13 http://www.cypress.com approved product fs781/82/84 pin configuration pin description pin no. pin name i/o type description 1/2 xin / xout i/o analog pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal. xin may be connected to ttl/cmos external clock source. if xin connected to external clock other than crystal, leave xout (pin 2) unconnected. 7/3 s0 / s1 i cmos/ttl digital control inputs to select input frequency range and output frequency scaling. refer to tables 7 & 8 for selection. s0 has internal pulldown. s1 has internal pullup. 4 lf i analog loop filter. single ended tri-state output of the phase detector. a two-pole passive loop filter is connected to loop filter (lf). 6 fsout o cmos/ttl modulated clock frequency output. the center frequency is the same as the input reference frequency for fs781. input frequency is multiplied by 2x and 4x for fs782 and fs784 respectively. 8 vdd p power positive power supply. 5 vss p power power supply ground table 1 output frequency selection product number fsout frequency scaling description fs781 1x 1x modulated frequency of input clock fs782 2x 2x modulated frequency of input clock fs784 4x 4x modulated frequency of input clock table 2. fsout sscg (modulated output clock) product selection 1 2 3 4 8 7 6 5 s0 vdd xin xout fsout vss lf s1 fs78x 8 pin tssop package 1 2 3 4 8 7 6 5 xin xout s1 lf vdd s0 fsout vss fs78x 8 pin soic package
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 4 of 13 http://www.cypress.com approved product fs781/82/84 this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range, vss < (vin or vout) < vdd. all digital inputs are tied high or low internally. refers to electrical specifications for operating supply range. absolute maximum ratings item symbol min max units operating voltage vdd 3.0 6.0 vdc input, relative to vss virvss -0.3 vdd +0.3 vdc output, relative to vss vorvss -0.3 vdd +0.3 vdc avdd relative to dvdd ? vpp -100 +100 mv avss relative to dvss ? vss -100 +100 mv temperature, operating top 0 + 70 0 c temperature, storage tst - 65 + 150 0 c table 3 electrical characteristics characteristic symbol min typ max units input low voltage vil - - 0.3 * vdd vdc input high voltage vih 0.7 * vdd - - vdc input low current iil - - 100 a input high current iih - - 100 a output low voltage iol= 10ma, vdd = 5v vol - - 0.4 vdc output high voltage ioh = 10ma, vdd = 5v voh vdd-1.0 - - vdc output low voltage iol= 6ma, vdd = 3.3v vol - - 0.4 vdc output high voltage ioh = 5ma,vdd = 3.3v voh 2.4 - - vdc resistor, pull down (pin-7) rpd 60k 125k 200k ? resistor, pull up (pin-3) rpu 60k 125k 200k ? input capacitance (pin-1) c xin -8 - pf output capacitance (pin-2) c xout -10 - pf 5 volt dynamic supply current (c l = no load) icc - 38 - ma 3.3 volt dynamic supply current (c l = no load) icc - 20 - ma short circuit current (fsout) isc - 25 - ma bw% variations, 3.30v** bw -20 0 +20 % bw% variations, 5.00v** bw -30 0 +30 % test measurements performed at vdd = 3.3v and 5.0v 10%, xin = 48 mhz, ta = 0 c to 70 c **bw% variations in % from the bw% values give in loop filter value tables. table 4
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 5 of 13 http://www.cypress.com approved product fs781/82/84 timing characteristics characteristic symbol min typ max units output rise time measured at 10% - 90% @ 5 vdc ttlh 2.0 2.2 2.5 ns output fall time measured at 10% - 90% @ 5 vdc tthl 1.7 2.0 2.2 ns output rise time measured at 0.8v - 2.0v @ 5 vdc ttlh 0.50 0.65 0.75 ns output fall time measured at 0.8v - 2.0 v @ 5 vdc tthl 0.50 0.65 0.75 ns output rise time measured at 10% - 90% @ 3.3 vdc ttlh 2.6 2.65 2.9 ns output fall time measured at 10% - 90% @ 3.3 vdc tthl 2.0 2.1 2.2 ns output rise time measured at 0.8v - 2.0v @ 3.3 vdc ttlh 0.8 0.95 1.1 ns output fall time measured at 0.8v - 2.0 v @ 3.3 vdc tthl 0.78 0.85 0.9 ns output duty cycle tsymf1 45 50 55 % fsout, cycle to cycle jitter, 48 mhz @ 3.30 vdc (pin 6) ccj - 320 370 ps fsout, cycle to cycle jitter, 48 mhz @ 5.0 vdc (pin 6) ccj - 310 360 ps fsout, cycle to cycle jitter, 72 mhz @ 3.30 vdc (pin 6) ccj - 270 325 ps fsout, cycle to cycle jitter, 72 mhz @ 5.0 vdc (pin 6) ccj - 390 440 ps measurements performed at vdd = 3.3 and 5.0v 10%, ta = 0 c to 70 c, cl = 15pf, xin = 48 mhz. table 5 range selection table s1 (pin 3) s0 (pin 7) fin (mhz) (pin 2/3) modulation rate fs781 fsout (pin 6) fs782 fsout (pin 6) fs784 fsout (pin 6) 0 0 6 - 16 fin/120 6 ? 16 mhz 12 ? 32 mhz 32 ? 64 mhz 0 1 16 - 32 fin/240 16 ? 32 mhz 32 ? 64 mhz 64 ? 82 mhz 1 0 32 - 66 fin/480 32 ? 66 mhz 64 ? 82 mhz n/a 1 1 66 - 82 fin/720 66 ? 82 mhz n/a n/a table 6
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 6 of 13 http://www.cypress.com approved product fs781/82/84 loop filter selection chart the following table provides a list of recommended loop filter values for the fs781/2/4. the fs78x is divided into 4 ranges and operates at both 3.3 and 5.0 vdc. the loop filter at the right is representative of the loop filter components in the table below. fs781/2/4 recommended loop filter values. c7 (pf.) @ +3.3 vdc +/- 5% (r6 = 3.3k) input (mhz) s 1 s 0 bw = 1.0% (note 3) bw = 1.5% (note 3) bw = 2.0% (note 3) bw = 2.5% (note 3) bw = 3.0% (note 3) bw = 3.5% (note 3) bw = 4.0% (note 3) 6 0 0 10,000/1000 1550 910 780 700 640 560 8 0 0 10,000/330 990 820 640 520 450 400 10 0 0 1040 680 460 360 300 240 210 12 0 0 830 420 300 220 200 190 170 14 0 0 580 230 200 160 140 100 80 16 0 1 10000 980 760 580 470 410 385 20 0 1 1000 730 470 390 320 220 190 22 0 1 960 640 410 270 230 200 180 24 0 1 920 400 250 210 180 160 150 26 0 1 660 300 220 180 150 140 120 28 0 1 470 230 180 150 130 100 70 30 0 1 470 180 140 120 100 80 60 32 0 1 330 170 120 100 82 68 47 34 1 0 10000 860 640 520 430 380 330 36 1 0 2200 820 620 470 400 330 290 38 1 0 1500 690 520 410 340 290 240 40 1 0 960 600 420 340 280 220 160 42 1 0 940 620 380 275 230 210 180 44 1 0 950 680 400 250 210 190 170 46 1 0 900 580 270 220 190 180 165 48 1 0 790 440 260 210 180 160 140 52 1 0 470 325 220 185 155 135 120 54 1 0 470 270 200 170 140 130 100 56 1 0 445 250 185 150 120 85 47 58 1 0 430 210 165 130 100 65 33 60 1 0 295 185 150 120 100 90 82 62 1 0 270 220 150 120 100 82 68 64 1 1 1180 860 560 410 340 290 230 66 1 1 1180 760 560 350 260 220 210 68 1 1 1180 750 500 320 260 230 210 70 1 1 1120 740 470 370 300 240 170 72 1 1 1160 780 470 300 250 220 190 74 1 1 1110 770 470 280 230 210 190 76 1 1 1000 720 440 240 210 190 170 78 1 1 910 670 270 210 190 170 160 80 1 1 900 620 260 210 190 170 156 82 1 1 900 540 250 210 190 170 150 notes: 1. if the value selected from the above chart is not a standard, use the next available larger value. 2. all bandwidth ? s indicated above are total peak-to-peak spread. 1% = +0.5% to ? 0.5%. 4% = +2.0% to ? 2.0%. 3. if c8 is not listed in the chart for a particular bw and freq., it is not used in the loop filter. 4. contact factory for lf (loop filter) values less than 1.0 % bw. table 7 c8 r6 c7 lf (pin 4)
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 7 of 13 http://www.cypress.com approved product fs781/82/84 fs781/2/4 recommended loop filter values. c7 (pf.) @ +5.0 vdc +/- 5% (r6 = 3.3k) input (mhz) s 1 s 0 bw = 1.0% (note 3) bw = 1.5% (note 3) bw = 2.0% (note 3) bw = 2.5% (note 3) bw = 3.0% (note 3) bw = 3.5% (note 3) bw = 4.0% (note 3) 6 0 0 1140 1030 930 830 710 610 510 8 0 0 1170 970 740 570 460 400 280 10 0 0 1030 660 430 350 280 210 130 12 0 0 760 340 230 200 180 160 130 14 0 0 450 240 180 140 100 70 50 16 0 1 2490 970 730 590 480 430 370 20 0 1 1360 680 480 370 280 190 250 22 0 1 990 560 330 260 230 200 190 24 0 1 820 360 250 200 180 160 150 26 0 1 530 270 210 170 150 110 90 28 0 1 430 230 180 150 110 100 90 30 0 1 250 200 150 110 100 90 80 32 10 note 4. 1000 740 570 470 410 370 36 10 note 4. 970 670 480 380 310 230 38 10 note 4. 880 560 380 310 270 220 40 10 note 4. 800 460 290 240 230 220 42 1 0 1030 680 360 260 220 200 190 44 1 0 790 560 260 220 200 190 170 46 1 0 1110 420 280 210 180 170 140 48 1 0 1110 280 200 190 170 140 120 50 1 0 830 330 200 180 160 130 110 52 1 0 560 340 205 170 140 120 90 54 1 0 510 280 180 140 110 110 90 56 1 0 470 210 160 120 100 90 90 58 1 0 450 220 250 110 90 80 80 60 1 0 430 240 120 90 80 80 70 62 11 note 4. 800 580 430 330 250 180 66 11 note 4. 630 400 320 240 150 100 68 11 note 4. 690 365 285 225 170 140 70 11 note 4. 650 330 250 210 190 180 72 11 note 4. 575 340 250 210 190 170 74 11 note 4. 500 355 245 205 180 165 76 11 note 4. 550 330 230 200 175 160 78 11 note 4. 600 290 220 190 170 155 80 11 note 4. 570 240 210 185 165 150 82 11 note 4. 540 250 200 180 160 140 notes: 1. if the value selected from the above chart is not a standard value, use the next available larger value. 2. all bandwidths indicated are total peak-to-peak spread. 1% = +0.5% to ? 0.5%. 4% = +2.0% to ? 2.0%. 3. if c8 is not listed in the chart for a particular bw and freq., it is not used in the loop filter. 4. contact factory for these loop filter values and bandwidths less than 1.0%. table 8
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 8 of 13 http://www.cypress.com approved product fs781/82/84 sscg modulation profile the digital control inputs s0 and s1 determine the modulation frequency of fs781/2/4 products. the input frequency is divided by a fixed number, depending on the operating range that is selected. the modulation frequency of the fs78x can be determined from the table 8. to compute the modulation frequency enter to table 8 with selected s0 and s1 values to obtain modulation divider number, and divide the input frequency by this fix number. s1 s0 input frequency range (mhz) modulation divider number 0 0 6 to 16 120 0 1 16 to 32 240 1 0 32 to 66 480 1 1 66 to 82 720 table 9 figure 5. frequency profile in time domain with the correct loop filter connected to pin 4, the following profile will provide the best emi reduction. this profile can be seen on a time domain analyzer. theory of operation the fs781/2/4 devices are phase lock loop (pll) type clock generators using direct digital synthesis (dds). by precisely controlling the bandwidth of the output clock, the fs781/2/4 products become a low emi clock generator. the theory and detailed operation of these products will be discussed in the following sections. emi all clocks generate unwanted energy in their harmonics. conventional digital clocks are square waves with a duty cycle that is very close to 50 %. because of the 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e.; 3 rd , 5 th , 7 th etc. it is possible to reduce the amount of energy contained in the fundamental and harmonics by increasing the bandwidth of the fundamental clock frequency. conventional digital xin + .5% - .5% time (microseconds) 1.0% total
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 9 of 13 http://www.cypress.com approved product fs781/82/84 fc = 20 mhz fmin = 19.8 mhz fmax = 20.2 mhz clocks have a very high q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. by reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for electro-magnetic interference (emi). conventional methods of reducing emi have been to use shielding, filtering, multi-layer pcb ? s etc. these fs781/2 and 4 use the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the q of the clock. sscg the fs781/2/4 products use a unique method of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak to peak and cycle to cycle. the fs78x products take a narrow band digital reference clock in the range 6 - 82 mhz and produce a clock that sweeps between a controlled start and stop frequency and precise rate of change. to understand what happens to an sscg clock, consider that we have a 20 mhz clock with a 50 % duty cycle. from a 20 mhz clock we know the following; clock frequency = fc = 20 mhz. clock period = tc = 1/20 mhz=50 ns consider that this 20 mhz clock is applied to the xin input of the fs78x, either as an externally driven clock or as the result of a parallel resonant crystal connected to pins 1 and 2 of the fs78x. also consider that the products are operating from a 5-volt dc power supply and the loop filter is set for a total bandwidth spread of 2%. refer to table 6 on page 6. from the above parameters, the output clock at fsout will be sweeping symmetrically around a center frequency of 20 mhz. the minimum and maximum extremes of this clock will be +200 khz and -200 khz. so, we have a clock that is sweeping from 19.8 mhz to 20.2 mhz and back again. if we were to look at this clock on a spectrum analyzer we would see the picture in figure 7. keep in mind that this is a drawing of a perfect clock with no noise. figure 7. 50% 50% tc = 50 ns. 20 mhz unmodulated clock figure 6.
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 10 of 13 http://www.cypress.com approved product fs781/82/84 tc = 50.50 tc =49.50 ns. we see that the original 20 mhz reference clock is at the center frequency, cf, and the minimum and maximum extremes are positioned symmetrically about the center frequency. this type of modulation is called center-spread . figure 8 shows a 20 mhz clock, as it would be seen on an oscilloscope. the top trace is the non-modulated reference clock,. the bottom trace is the modulated clock at pin 6. from this comparison chart you can see that the frequency is decreasing and the period of each successive clock is increasing. the tc measurements on the left and right of the bottom trace indicate the max. and min. extremes of the clock. intermediate clock changes are small and accumulate to achieve the total period deviation. the reverse of this figure would show the clock going from minimum extreme back to the high extreme. figure 8. period comparison chart looking at figure 7, you will note that the peak amplitude of the 20 mhz non-modulated clock is higher than the wideband modulated clock. this difference in peak amplitudes between modulated and unmodulated clocks is the reason why sscg clocks are so effective in digital systems. this figure refers to the fundamental frequency of a clock. a very important characteristic of the sscg clock is that the bandwidth of the fundamental frequency is multiplied by the harmonic number. in other words, if the bandwidth of a 20 mhz clock is 200 khz, the bandwidth of the 3 rd harmonic will be 3 times 200, or 600 khz. the amount of bandwidth is relative to the amount of energy in the clock. consequently, the wider the bandwidth, the greater the energy reduction of the clock. most applications will not have a problem meeting agency specifications at the fundamental frequency. it is the higher harmonics that usually cause the most problems. with an sscg clock, the bandwidth and peak energy reduction increases with the harmonic number. consider that the 11 th harmonic of a 20 mhz clock is 220 mhz. with a total spread of 200 khz at 20 mhz, the spread at the 11 th harmonic would be 2.20 mhz which greatly reduces the peak energy content. it is typical to see as much as 12 to 18 db. reduction at the higher harmonics, due to a modulated clock. the difference in the peak energy of the modulated clock and the non-modulated clock in typical applications will see a 2 - 3 db. reduction at the fundamental and as much as 8 - 10 db. reduction at the intermediate harmonics, 3 rd , 5 th , 7 th etc. at the higher harmonics, it is quite possible to reduce the peak harmonic energy, compared to the unmodulated clock, by as much as 12 to 18 db.
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 11 of 13 http://www.cypress.com approved product fs781/82/84 application notes and schematic the schematic at the right is configured for the following parameters; package selected = fs781 xin = 20 mhz crystal fsout = 20 mhz (s0=1 and s1=0) bandwidth of the fsout clock is determined by the values of the loop filter connected to pin 4. ** ** occasionally, c8 is used to create a second pole f or this loop f ilter. ref er to loop filter selection table. mount loop f ilter components as close to lf pin as possible. . crystal is 20 mhz is 1st order w ith 18 pf load capacitance. if crystal load capacitance is dif f erent than 18 pf, c1 and c2 must be re-calculated. for third overtone crystals, a parallel or series resonant trap is required. r6 c1 0.1 uf c2 27 pf c3 27 pf y1 20 m hz c8 c7 fs781 xi n 1 xout 2 s1 3 lf 4 vss 5 fsout 6 s0 7 vdd 8 vdd fsout
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 12 of 13 http://www.cypress.com approved product fs781/82/84 package drawing and dimensions 8 pin soic outline dimensions inches millimeters symbol min nom max min nom max a 0.053 - 0.069 1.35 - 1.75 a 1 0.004 - 0.010 0.10 - 0.25 a2 0.047 - 0.059 1.20 - 1.50 b 0.013 - 0.020 0.33 - 0.51 c 0.007 - 0.010 0.19 - 0.25 d 0.189 - 0.197 4.80 - 5.00 e 0.150 - 0.157 3.80 - 4.00 e 0.050 bsc 1.27 bsc h 0.228 - 0.244 5.80 - 6.20 l 0.016 - 0.050 0.40 - 1.27 a0 o -8 o 0 o -8 o 8 pin tssop outline dimensions inches millimeters symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a2 0.031 0.039 0.041 0.80 1.00 1.05 b 0.007 - 0.012 0.19 - 0.30 c 0.004 - 0.008 0.09 - 0.20 d 0.114 0.118 0.122 2.90 3.00 3.10 e 0.169 0.173 0.177 4.30 4.40 4.50 e 0.026 bsc 0.65 bsc h 0.244 0.252 0.260 6.20 6.40 6.60 l 0.018 0.024 0.030 0.45 0.60 0.75 a0 o -8 o 0 o -8 o cypress semiconductor corporation disclaimer cypress semiconductor corporation reserves the right to change or modify the information contained in this data sheet, without notice. cypress semiconductor corporation does not assume any liability arising out of the application or use of any product or circuit described herein cypress semiconductor corporation does not convey any license under its patent rights nor the rights of others. cypress semiconductor corporation does not authorize its products for use as critical components in life-support systems or critical me dical instruments, where a malfunction or failure may reasonably be expected to result in significant injury to the user. a b e a a 1 a 2 d e h l c
low emi spectrum spread clock cypress semiconductor corporation 525 los coches st. document#: 38-07029 rev. ** 05/07/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 13 of 13 http://www.cypress.com approved product fs781/82/84 document title: fs781/82/84 low emi spectrum spread clock document number: 38-07029 rev. ecn no. issue date orig. of change description of change ** 106957 06/11/01 ika convert from imi to cypress

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