? semiconductor components industries, llc, 2008 december, 2008 ? rev. 0 1 publication order number: NB7L1008M/d NB7L1008M 2.5v / 3.3v 1:8 cml fanout multi ? level inputs w/ internal termination description the NB7L1008M is a high performance differential 1:8 clock/data fanout buffer . the NB7L1008M produces eight identical output copies of clock or data operating up to 6 ghz or 10.7 gb/s, respectively. as such, the NB7L1008M is ideal for sonet, gige, fiber channel, backplane and other clock/data distribution applications. the differential inputs incorporate internal 50 termination resistors that are accessed through the vt pin. this feature allows the NB7L1008M to accept various logic standards, such as lvpecl, cml, lvds, lvcmos or lvttl logic levels. the v refac reference output can be used to rebias capacitor ? coupled differential or single ? ended input signals. the 1:8 fanout design was optimized for low output skew applications. the NB7L1008M is a member of the gigacomm ? family of high performance clock products. features ? input data rate > 12 gb/s typical ? data dependent jitter < 20 ps ? maximum input clock frequency > 8 ghz typical ? random clock jitter < 0.8 ps rms ? low skew 1:8 cml outputs, < 25 ps max ? multi ? level inputs, accepts lvpecl, cml, lvds ? 160 ps typical propagation delay ? 45 ps typical rise and fall times ? differential cml outputs, 400 mv peak ? to ? peak, typical ? operating range: v cc = 2.375 v to 3.6 v, gnd = 0 v ? internal input termination resistors, 50 ? v refac reference output ? qfn ? 32 package, 5 mm x 5 mm ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices qfn32 mn suffix case 488am see detailed ordering and shipping information on page 9 of this data sheet. ordering information marking diagram http://onsemi.com 32 1 nb7l 1008m awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package simplified logic diagram q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 q5 q5 v refac in vt in q6 q6 q7 q7 32 (note: microdot may be in either location) 50 50
NB7L1008M http://onsemi.com 2 vcc 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 vcc vrefac vcc gnd vcc q4 q4 q3 q3 gnd vcc in vt in gnd gnd figure 1. 32 ? lead qfn pinout (top view) NB7L1008M exposed pad (ep) q7 q7 q6 q6 q5 q5 vcc vcc q0 q0 q1 q1 q2 q2 vcc table 1. pin description pin name i/o description 3, 6 in, in lvpecl, cml, lvds input non ? inverted / inverted differential clock/data input. note 1 4 vt internal 50 termination pin for in and in 2, 7 17,24 gnd negative supply voltage, note 2 1, 8, 9, 16, 18, 23, 25, 32 v cc positive supply voltage, note 2 31, 30, 29, 28, 27, 26, 22, 21, 20, 19, 15, 14, 13, 12, 11, 10 q0, q0 , q1, q1 , q2, q2 , q3, q3 , q4, q4 , q5, q5 , q6, q6 , q7, q7 cml non ? inverted / inverted differential output. note 1 5 vrefac output voltage reference for capacitor ? coupled inputs, only ? ep ? the exposed pad (ep) on the qfn ? 24 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be at- tached to a heat ? sinking conduit. the pad is electrically connected to gnd and is recommended to be electrically connected to gnd on the pc board. 1. in the dif ferential configuration when the input termination pin (v t ) is connected to a common termination voltage or left open, and if no signal is applied on in/in , then the device will be susceptible to self ? oscillation. qn/qn outputs have internal 50 source termination resistors. 2. all v cc and gnd pins must be externally connected to the same power supply voltage to guarantee proper device operation.
NB7L1008M http://onsemi.com 3 table 2. attributes characteristics value esd protection human body model machine model > 2 kv > 200 v moisture sensitivity (note 3) indefinite time of the drypack qfn ? 32 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 263 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, refer to application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 4.0 v v in input voltage gnd = 0 v ? 0.5 to v cc v v inpp differential input voltage |in ? in | 1.89 v i in input current through r t (50 resistor) 40 ma i out output current continuous surge 34 40 ma i vfrefac v refac sink/source current 1.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) tgsd 51 ? 6 (2s2p multilayer test board) with filled thermal vias 0 lfpm 500 lfpm qfn ? 32 qfn ? 32 31 27 c/w c/w jc thermal resistance (junction ? to ? case) standard board qfn ? 32 12 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB7L1008M http://onsemi.com 4 table 4. dc characteristics ? cml output v cc = 2.375 v to 3.6 v; gnd = 0v ta = ? 40 c to 85 c (note 6) symbol characteristic min typ max unit power supply v cc power supply voltage v cc = 3.3 v v cc = 2.5 v 3.0 2.375 3.3 2.5 3.6 2.625 v power supply current i cc power supply current, inputs and outputs open 265 315 ma cml outputs (note 5, figures 10 and 11) v oh output high voltage v cc = 3.3v v cc = 2.5v v cc ? 30 3270 2470 v cc ? 10 3290 2490 v cc 3300 2500 mv v ol output low voltage v cc = 3.3v v cc = 2.5v v cc ? 600 2700 1900 v cc ? 400 2900 2100 v cc ? 350 2950 2150 mv differential inputs driven single ? ended (notes 7 and 8) (figures 6 and 8) v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v th input threshold reference voltage range 1100 v cc ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 1200 mv v refac v refac output reference voltage @ 100 a for capacitor ? coupled inputs, only v cc = 3.3 v v cc = 2.5 v v cc ? 1375 v cc ? 1325 v cc ? 1200 v cc ? 1200 v cc ? 1100 v cc ? 1075 mv differential inputs driven differentially (in, in ) (note 9) (figures 4 and 7) v ihd differential input high voltage 1100 v cc mv v ild differential input low voltage gnd v ihd ? 100 mv v id differential input voltage (v ihd ? v ild ) 100 1200 mv i ih input high current ? 150 40 +150 a i il input low current ? 150 5 +150 a termination resistors r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. cml outputs loaded with 50 to v cc for proper operation. 6. input and output parameters vary 1:1 with v cc . 7. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 8. v th is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously.
NB7L1008M http://onsemi.com 5 table 5. ac characteristics v cc = 2.375 v to 3.6 v; gnd = 0v ta = ? 40 c to 85 c (note 10) symbol characteristic min typ max unit f data maximum operating input data rate 10 12 gb/s f inclk maximum input clock frequency, v outpp 200 mv 6 8 ghz v outpp output voltage amplitude (see figures 2 and 5, note 11) f in 4 ghz f in 6 ghz 200 200 400 350 mv v cmr input common mode range (differential configuration, note 12, figure 9) 1050 v cc ? 50 mv t plh , t phl propagation delay to output differential, in/in to qn/qn 100 160 250 ps t plh tc propagation delay t emperature coefficient ? 40 c to +85 c 35 fs/ c t dc output clock duty cycle f in 6 ghz 45 49/51 55 % t skew duty cycle skew (note 13) within device skew (note 14) device to device skew (note 15) 0.15 7 25 1 25 70 ps t jitter clock jitter rms, 1000 cycles (note 16) f in 6 ghz data dependent jitter (ddj) (note 17) 10 gb/s 0.2 3 0.8 20 ps v inpp input voltage swing (differential configuration) (note 18) (figure 5) 100 1200 mv t r , t f output rise/fall times (20% ? 80%) qn, qn 20 45 70 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. measured using a 400 mv source, 50% duty cycle 1 ghz clock source. all outputs must be loaded with external 50 to v cc . input edge rates 40 ps (20% ? 80%). 11. output voltage swing is a single ? ended measurement operating in differential mode. 12. v cmr min varies 1:1 with gnd, v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 13. duty cycle skew is measured between differential outputs using the deviations of the sum of t pw ? and t pw + @ 1 ghz. 14. within device skew compares coincident edges. 15. device to device skew is measured between outputs under identical transition 16. additive clock jitter with 50% duty cycle clock signal. 17. additive peak ? to ? peak jitter with input nrz data at prbs23. 18. input voltage swing is a single ? ended measurement operating in differential mode. figure 2. output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typical) 500 450 400 350 300 250 200 0 1.0 2.0 3.0 8.0 7.0 6.0 5.0 4.0 . f out , clock output frequency (ghz) output voltage amplitude (mv) q output amplitude (mv) figure 3. input structure 50 50 v t v cc in in
NB7L1008M http://onsemi.com 6 in in q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (in) ? v il (in) figure 4. differential inputs driven differentially figure 5. ac reference measurement v ihd v ild v id = |v ihd(in) ? v ild(in)| in in figure 6. differential input driven single ? ended figure 7. differential inputs driven differentially figure 8. v th diagram figure 9. v cmr diagram in v cc gnd v ih v ihmin v ihmax v thmax v th v th v thmin v cmmin v cmmax in v cmr v cc gnd in in v th v th in in v ilmax v il v ilmin in v ildmax v ihdmax v id = v ihd ? v ild v ildtyp v ihdtyp v ildmin v ihdmin v ih v il
NB7L1008M http://onsemi.com 7 figure 10. typical termination for output driver and device evaluation (see application note and8173/d) driver device receiver device qd q d z o = 50 z o = 50 50 50 v cc figure 11. typical cml output structure and termination v cco 50 50 16 ma 50 50 v cc (receiver) gnd q q NB7L1008M
NB7L1008M http://onsemi.com 8 lvpecl driver v cc gnd z o = 50 v t = v cc ? 2 v z o = 50 NB7L1008M in 50 50 in gnd figure 12. lvpecl interface lvds driver v cc gnd z o = 50 v t = open z o = 50 NB7L1008M in 50 50 in gnd figure 13. lvds interface v cc v cc cml driver v cc gnd z o = 50 v t = v cc z o = 50 NB7L1008M in 50 50 in gnd v cc figure 14. standard 50 load cml interface differential driver v cc gnd z o = 50 vt = v refac * z o = 50 NB7L1008M in 50 50 in gnd v cc figure 15. capacitor ? coupled differential interface (v t connected to v refac ) *v refac bypassed to ground with a 0.01 f capacitor differential driver v cc gnd z o = 50 vt = v refac * NB7L1008M in 50 50 in gnd v cc figure 16. capacitor ? coupled single ? ended interface (v t connected to v refac )
NB7L1008M http://onsemi.com 9 ordering information device package shipping NB7L1008Mmng qfn32 (pb ? free) 74 units / rail NB7L1008Mmnr4g qfn32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB7L1008M http://onsemi.com 10 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NB7L1008M/d gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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