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order # 1394 node controller core technical manual august 2001 preliminary
ii rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. this document is preliminary. as such, it contains data derived from functional simulations and performance estimates. lsi logic has not veri?d either the functional descriptions, or the electrical and mechanical speci?ations using production parts. this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?er of lsi logic corporation. document db14-000075-02, third edition (august 2001) this document describes the lsi logic corporation 1394 node controller core and will remain the of?ial reference source for all revisions/releases of this product until rescinded by an update. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright 2000, 2001 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, coreware, g10, gigablaze, flexstream, and right-first-time are trademarks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. eh to receive product literature, visit us at http://www.lsilogic.com. for a current list of our distributors, sales of?es, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/na_salesof?es.html
1394 node controller core technical manual iii rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. preface this book is the primary reference and technical manual for the 1394 node controller core. it contains preliminary information regarding the functional description of the 1394 node controller core. audience this document assumes that you have some familiarity with the ieee 1394 high-performance serial bus and related support devices. the people who bene? from this book are: ? engineers and managers who are evaluating the 1394 node controller core for possible use in a system ? engineers who are designing the 1394 node controller core into a system organization this document has the following chapters: ? chapter 1, introduction , summarizes the key features and applications of the 1394 node controller core. ? chapter 2, data formats , describes the different data formats that the 1394 node controller core sends and receives. ? chapter 3, signal descriptions , describes the signals that comprise the external interface of the 1394 node controller core. ? chapter 4, registers , describes the internal registers of the 1394 node controller core. ? chapter 5, operation overview , provides functional waveforms, which show the operation of the core.
iv preface rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. ? chapter 6, application operation , describes transmit and receive operations from the viewpoint of the application. related publications 1394 physical layer (phy) core technical manual, document no. db14-000036-01 ieee standard for a high performance serial bus (ieee standard 1394-1995 ) p1394a draft standard for a high performance serial bus (supplement) conventions used in this manual 1. all signals have the module name as pre?. for example: llc_lreq: this signal is part of the llc module. 2. all signals ending with ? are low-asserted signals. for example: app_rstn: reset is an active-low signal. abbreviations: abuf asynchronous buffer block appif application interface module av/c audio video control (iec-61883) chf cip header field (iec-61883) cip common isochronous packet (iec-61883) cmp connection management procedures (iec-61883) csr command and status register (iso/iec-13213) csu control and status unit crc cyclic redundancy check code dbuf dma buffer block dvcr digital video cassette recorder eoh end of cip header (iec-61883)
preface v rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. the ?st time a word or phrase is de?ed in this manual, it is italicized. the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre? ?x ?or example, 0x32cf. binary numbers are indicated by the pre? ?b ?or example, 0b0011.0010.1100.1111. fcp function control protocol (iec-61883) iec-61883 standard for consumer digital av equipment using 1394 impr input master plug register ipcr input plug control register (iec-61883) llc link layer controller mpeg motion picture experts group opcr output plug control register ompr output master plug register orb operation request block pcr plug control register pht packet header transformation sbp-2 serial bus protocol 2 sph source packet header (iec-61883) ubuf universal asynchronous buffer urf universal receive fifo utf universal transmit fifo
vi preface rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved.
1394 node controller core technical manual vii rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. contents chapter 1 introduction 1.1 lsi logic coreware program 1-2 1.2 1394 node controller core overview 1-3 1.3 block diagram description 1-4 1.4 features 1-5 1.4.1 general 1-5 1.4.2 application interface 1-6 1.4.3 asynchronous operation 1-6 1.4.4 isochronous operation 1-6 1.4.5 bus management 1-7 1.5 applications 1-7 chapter 2 data formats 2.1 asynchronous data formats 2-1 2.1.1 asynchronous transmit data formats 2-1 2.1.2 asynchronous receive data formats 2-9 2.2 isochronous dma data formats 2-17 2.2.1 isochronous transmit data formats 2-17 2.2.2 isochronous receive data formats 2-20 2.3 phy packet data formats 2-21 2.3.1 phy packet transmit data format 2-21 2.3.2 phy packet receive data format 2-22 2.4 miscellaneous packet data formats 2-22 2.4.1 self-id packet receive data format 2-22 2.4.2 unformatted data transmit format 2-23 chapter 3 signal descriptions 3.1 application interface 3-3 3.2 universal buffer fifo interface 3-4
viii contents rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 3.3 phy interface 3-6 3.4 dma 0 interface 3-8 3.5 dma 1 interface 3-10 3.6 dma 0 fifo interface 3-12 3.7 dma 1 fifo interface 3-14 3.8 miscellaneous 3-15 chapter 4 registers 4.1 ordering conventions 4-1 4.2 control and status registers (csrs) 4-2 4.2.1 node id register (0x000) 4-2 4.2.2 cycle time register (0x004) 4-3 4.3 1394 registers 4-5 4.3.1 control 0 register (0x008) 4-7 4.3.2 control 1 register (0x00c) 4-11 4.3.3 control 2 register (0x010) 4-12 4.3.4 phy access register (0x014) 4-13 4.3.5 interrupt 0 register (0x020) 4-14 4.3.6 interrupt 0 mask register (0x024) 4-19 4.3.7 interrupt 1 register (0x028) 4-21 4.3.8 interrupt 1 mask register (0x02c) 4-22 4.3.9 interrupt 2 register (0x030) 4-23 4.3.10 interrupt 2 mask register (0x034) 4-23 4.3.11 dma space register (0x038) 4-24 4.3.12 acknowledge status register (0x03c) 4-25 4.3.13 ubuf transmit next (0x040) 4-25 4.3.14 ubuf transmit last (0x044) 4-25 4.3.15 ubuf transmit clear (0x048) 4-26 4.3.16 ubuf receive clear (0x04c) 4-26 4.3.17 ubuf receive (0x050) 4-26 4.3.18 ubuf receive level (0x054) 4-26 4.3.19 encoded interrupt priority (0x058) 4-26 4.3.20 pht control and status register 0 (0x080) 4-28 4.3.21 pht split time-out/empty cip interval register 0 (0x084) 4-35 4.3.22 pht request/response/cip receive header 0 register 0 (0x088) 4-37
contents ix rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.23 pht request/response/cip receive header 1 register 0 (0x08c) 4-39 4.3.24 pht request header 2/stream sph receive register 0 (0x090) 4-42 4.3.25 stream receive channel/nodeid selection 0 register 0 (0x094) 4-43 4.3.26 stream receive channel/nodeid selection 1 register 0 (0x098) 4-44 4.3.27 stream receive channel header register 0 (0x09c) 4-44 4.3.28 stream transmit channel header register 0 (0x0a0) 4-45 4.3.29 data transfer control register 0 (0x0a4) 4-47 4.3.30 cip header transmit 0 register 0 (0x0a8) 4-48 4.3.31 cip header transmit 1 register 0 (0x0ac) 4-49 4.3.32 stream transmit time stamp offset register 0 (0x0b4) 4-50 4.3.33 dma control and status register 0 (0x0b8) 4-52 4.3.34 dma transfer threshold register 0 (0x0bc) 4-53 4.3.35 dbuf fifos level register 0 (0x0c0) 4-54 4.3.36 dbuf tx data register 0 (0x0c4) 4-54 4.3.37 dbuf rx data register 0 (0x0c8) 4-55 4.3.38 dbuf fifos watermark level register 0 (0x0cc) 4-56 4.3.39 dbuf fifos size register 0 (0x0d0) 4-57 4.3.40 pht control and status register 1 (0x100) 4-57 4.3.41 pht split time-out/empty cip interval register 1 (0x104) 4-64 4.3.42 pht request/response/cip receive header 0 register 1 (0x108) 4-66 4.3.43 pht request/response/cip receive header 1 register 1 (0x10c) 4-68 4.3.44 pht request header 2/stream sph receive register 1 (0x110) 4-71 4.3.45 stream receive channel/nodeid selection 0 register 1 (0x114) 4-73 4.3.46 stream receive channel/nodeid selection 1 register 1 (0x118) 4-73
x contents rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.47 stream receive channel header register 1 (0x11c) 4-74 4.3.48 stream transmit channel header register 1 (0x120) 4-75 4.3.49 data transfer control register 1 (0x124) 4-76 4.3.50 cip header transmit 0 register 1 (0x128) 4-77 4.3.51 cip header transmit 1 register 1 (0x12c) 4-78 4.3.52 stream transmit time stamp offset register 1 (0x134) 4-79 4.3.53 dma control and status register 1 (0x138) 4-81 4.3.54 dma transfer threshold register 1 (0x13c) 4-82 4.3.55 dbuf fifos level register 1 (0x140) 4-83 4.3.56 dbuf tx data register 1 (0x144) 4-84 4.3.57 dbuf rx data register 1 (0x148) 4-84 4.3.58 dbuf fifos watermark level register 1 (0x14c) 4-85 4.3.59 dbuf fifos size register 1 (0x150) 4-86 chapter 5 operation overview 5.1 link layer controller 5-1 5.1.1 transmitter 5-1 5.1.2 receiver 5-2 5.1.3 phy interface 5-4 5.1.4 single-phase retry mechanism 5-8 5.2 application interface module 5-9 5.2.1 read accesses 5-9 5.2.2 write accesses 5-10 5.3 packet header transformation modules (phts) 5-11 5.3.1 isochronous transmission 5-11 5.3.2 isochronous reception 5-12 5.3.3 tight isochronous cycles 5-12 5.3.4 loose isochronous packets 5-12 5.3.5 asynchronous request transmission 5-13 5.3.6 asynchronous request reception 5-13 5.3.7 scheduling of packets for transmission 5-13 5.4 interrupt mechanism 5-14 5.4.1 setting up the interrupt mask registers 5-14 5.4.2 determining and clearing the interrupt 5-15
contents xi rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. chapter 6 application operation 6.1 asynchronous packet reception 6-1 6.2 asynchronous packet transmission 6-2 6.3 asynchronous stream packet transmission 6-3 6.4 example register con?urations 6-3 6.4.1 automatic asynchronous write request packet generation 6-3 6.4.2 automatic asynchronous read request packet generation 6-4 6.4.3 cip format isochronous packet reception 6-5 6.4.4 simultaneous cip format isochronous packet reception and transmission 6-6 6.4.5 automatic asynchronous request packet processing 6-7 6.4.6 asynchronous write request packet generation writing dma transmit fifo through the application interface 6-8 6.4.7 asynchronous read request packet generation reading dma receive fifo through the application interface 6-9 6.4.8 cip format isochronous packet transmission with syt time stamps using programmable frame synchronization 6-10 customer feedback figures 1.1 1394 node controller core block diagram 1-4 2.1 read request for data quadlet packet transmit format 2-2 2.2 write response packet transmit format 2-2 2.3 write request for data quadlet packet transmit format 2-4 2.4 read response for quadlet data packet transmit format 2-4 2.5 read request for block data packet transmit format 2-4 2.6 lock/write request for data block packet transmit format 2-6 2.7 lock/read response for block data packet transmit format 2-6
xii contents rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 2.8 read request receive format for data quadlet 2-9 2.9 write response packet receive format 2-9 2.10 write quadlet request receive format 2-11 2.11 read quadlet response packet receive format 2-11 2.12 read block request packet receive format 2-12 2.13 lock/write request for data block receive format 2-14 2.14 lock/read response for block data receive format 2-15 2.15 isochronous transmit format 1 2-17 2.16 isochronous transmit format 2 2-17 2.17 isochronous transmit format 3 2-19 2.18 isochronous receive format 1 2-20 2.19 isochronous receive format 2 2-21 2.20 phy packet transmit data format 2-22 2.21 phy packet receive data format 2-22 2.22 self-id receive format 2-23 2.23 unformatted data transmit format 2-23 3.1 1394 node controller core logic diagram 3-2 4.1 interior bit signi?ance 4-1 4.2 interior byte signi?ance 4-2 4.3 internal quadlet order 4-2 5.1 block diagram of the phy interface block 5-5 5.2 bus request using llc_lreq 5-5 5.3 status timing 5-6 5.4 transmit timing 5-7 5.5 receive timing 5-8 5.6 read from the application 5-10 5.7 write from application 5-11 6.1 write quadlet request receive format 6-1 6.2 write quadlet response packet transmit format 6-2 tables 4.1 csr registers 4-2 4.2 1394 register summary 4-5 5.1 tcodes 5-2 5.2 speed codes 5-8
1394 node controller core technical manual 1-1 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. chapter 1 introduction this chapter contains the following sections: ? section 1.1, ?si logic coreware program ? section 1.2, ?394 node controller core overview ? section 1.3, ?lock diagram description ? section 1.4, ?eatures ? section 1.5, ?pplications the 1394 node controller core conforms with the requirements of the ieee 1394-1995 standard for high performance serial bus and the 1394a supplement. it provides full link layer functionality and easily interfaces to the lsi logic 1394 physical layer core or any other standard 1394a-compliant phy device. the core uses a dma interface to reduce cpu utilization for large data transfers. the core can process incoming 1394 read/write requests to a programmable 4 gbyte range without cpu intervention using dma transfers. this feature is useful when the core is used in sbp-2 (serial bus protocol) initiator applications or dpp (direct print protocol) receiver mode. the core can generate automatic and sequential 1394 read/write requests. this feature is useful when the core is used in sbp-2 target applications or dpp sender mode. isochronous transfers use the dma interface. cip (common isochronous packet) headers can be generated automatically when transmitting. the core supports hardware-assisted transmit data ?w control (for example, dv empty cip packet generation). the core also supports simultaneous transmission and reception of one iec-61883 format talk stream and two listen streams. for unformatted streams (1394 tag equals zero), the core supports any combination of simultaneous talk and listen channels.
1-2 introduction rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. when the core is a 1394 cycle master, it supports external 1394 cycle timer control by using the cycle clock input signal. the core provides a clock output signal that is based on a 1394 cycle timer for application synchronization when the core is a 1394 cycle slave. 1.1 lsi logic coreware program an lsi logic core is a fully de?ed, optimized, and reusable block of logic. it supports industry-standard functions and has prede?ed timing and layout. the core is also an encrypted rtl simulation model for a wide range of vhdl and verilog simulators. the coreware library contains an extensive set of complex cores for the communications, consumer, and computer markets. the library consists of high-speed interconnect functions such as the gigablaze g10 core, mips embedded microprocessors, a usb core, a pci core, and many more. the library also includes megafunctions or building blocks , which provide useful functions for developing a system on a chip. through the coreware program, you can create a system on a chip uniquely suited to your applications. each core has an associated set of deliverables, including: ? rtl simulation models for both verilog and vhdl environments ? a system veri?ation environment (sve) for rtl-based simulation ? synthesis and timing shells ? netlists for full timing simulation ? complete documentation ? lsi logic flexstream software support the lsi logic flexstream software provides seamless connectivity between products from leading electronic design automation (eda) vendors and lsi logic manufacturing environment. standard interfaces for formats and languages such as vhdl, verilog, waveform generation language (wgl), physical design exchange format (pdef), and standard delay format (sdf) allow a wide range of tools to interoperate within the lsi logic flexstream environment. in addition to design
1394 node controller core overview 1-3 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. capabilities, full scan automatic test pattern generation (atpg) tools and lsi logic specialized test solutions can be combined to provide high-fault coverage test programs that assure a fully functional design. because your design requirements are unique, lsi logic is ?xible in working with you to develop your system-on-a-chip coreware design. three different work relationships are available: ? you provide lsi logic with a detailed speci?ation and lsi logic performs all design work. ? you design some functions while lsi logic provides you with the cores and megafunctions, and lsi logic completes the integration. ? you perform the entire design and integration, and lsi logic provides the core and associated deliverables. whatever the work relationship, the lsi logic advanced coreware methodology and asic process technologies consistently produce right-first-time silicon. 1.2 1394 node controller core overview the 1394 node controller core is targeted for embedded asic designs using the ieee 1394 serial bus. the core provides full link layer functionality. the link layer provides a one-way data transfer with con?mation of request to the transaction layer. the link layer also provides addressing, data checking, and data framing for transmitting and receiving of packets. the 1394 node controller core supports asynchronous and isochronous transfers. you can con?ure a wide range of isochronous support capabilities, including transmission and reception of several isochronous channels in parallel. the 1394 node controller core seamlessly connects to the lsi logic 1394 physical layer core or any other phy device that conforms to the 1394a speci?ation. the con?urable core design is ideal for a wide range of embedded applications, from basic low-cost devices to sophisticated high- performance asics. the core design consists of the link layer controller (llc), control and status unit, llc arbiter, ubuf, appif, two phts, and two dmatf, dmarf, and dma interfaces. the packet header
1-4 introduction rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. transformation (pht) module is capable of large isochronous or asynchronous dma transfers. the universal asynchronous buffer is primarily intended for protocol (sbp-2, dpp, av/c, iicp, etc.) command and status transfers. 1.3 block diagram description figure 1.1 shows a block diagram of the 1394 node controller core. figure 1.1 1394 node controller core block diagram the link layer controller (llc) implements the complete functionality of the link layer in the 1394 node controller core. this block interfaces dmatf1 dma dmarf1 appif ubuf utf link layer controller to phy control and status unit register and control csrs cycle timer/ phy crc tx rx monitor if interface urf llc arbiter dmatf0 dma dmarf0 interface packet header transformation (pht) 0 packet header transformation (pht) 1 0 1
features 1-5 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. to the phy, the arbiter, the packet header transformation module (pht), and the control and status unit. the phy interface (phyif) handles all the protocols between the phy and the llc. the universal asynchronous buffer (ubuf) block contains a set of fifos for transmitting and receiving asynchronous packets. only one packet is allowed in each of the ubuf transmit fifo (utf). the packet header transformation (pht) modules handle the communication between the llc and the dma interfaces. the application interface (appif) module connects the application with the 1394 for nonautomated asynchronous packet transfers. the application uses this interface to access the 1394 register space. the control and status unit (csu) implements the node controller registers. the dma buffer block (dbuf) contains a set of fifos for isochronous data transmission and reception for different channels or automated asynchronous transfers. 1.4 features the features of the 1394 node controller core are summarized in the following subsections. 1.4.1 general ? supports ieee standard 1394-1995 and the 1394a supplement ? implements full link layer ? reduces cpu utilization by use of dma transfers ? provides automatic asynchronous request packet generation for sequential data buffer accesses ? generates response to received requests in a designated 4 gbyte address range without cpu involvement ? supports 1394 cycle time synchronization with application modules
1-6 introduction rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. ? generates iec-61883 cip header for isochronous transmission ? provides hardware-assisted isochronous data ?w control ? provides full packet handling, and packing and unpacking for asynchronous and isochronous packet transmission and reception ? supports 100/200/400 mbits/s bus speeds ? contains a standard phy interface with up to eight data lines for 400 mbits/s operation ? provides 32-bit crc generation and error detection ? is con?urable to application requirements by optional module selection, compilation parameters (fifo sizes), and programmable con?uration registers ? connects to the lsi logic 1394 phy core or any other standard 1394a-compliant phy device 1.4.2 application interface ? application interface for both control and data transfers to be used with a microcontroller or a hardwired controller ? application interface module with 32-bit wide bus (1394 node controller core is bus slave) in burst mode as well as nonburst mode ? controller interface provides access to all csrs and control register set ? extensive maskable interrupt register set provides status reporting 1.4.3 asynchronous operation ? supports full link layer for asynchronous transmission and reception ? provides con?urable asynchronous buffer bank size during compilation; size allocation among the asynchronous fifos con?urable by the end-user ? supports single-phase retry sequence 1.4.4 isochronous operation ? supports isochronous bandwidth of the ieee-1394 bus (up to 400 mbits/s implementation) ? transmits and receives multiple isochronous channels
applications 1-7 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. ? provides programmable isochronous data routing with header insertion for transmission and separation for reception ? supports external dma controller for isochronous data transmit or receive ? provides dma transmit and/or receive fifo units whose total size is con?ured during compilation. size allocation among the fifos is con?urable by the end-user. ? provides a byte pack/unpack module for dma interface 1.4.5 bus management ? transaction and isochronous capable node ? cycle master capable node ? bus manager capable node 1.5 applications some applications for the 1394 node controller core include: ? digital still cameras ? video conferencing cameras ? printers ? storage devices ? scanners ? digital audio devices (consumer and professional) ? digital vcr/tv ? digital set-top box
1-8 introduction rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved.
1394 node controller core technical manual 2-1 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. chapter 2 data formats this chapter describes the data formats that the 1394 node controller core accepts for transmission and reception over the 1394 bus. this chapter contains the following sections: ? section 2.1, ?synchronous data formats ? section 2.2, ?sochronous dma data formats ? section 2.3, ?hy packet data formats ? section 2.4, ?iscellaneous packet data formats in this chapter, the term quadlet refers to a 32-bit data size. 2.1 asynchronous data formats this section describes the asynchronous data formats for the transmit and receive fifo operations. 2.1.1 asynchronous transmit data formats asynchronous data is transmitted in one of three basic formats: 1. 3 quadlet (used for quadlet read requests and quadlet/block write responses) 2. 4 quadlet (used for block read requests, quadlet write requests, and quadlet read responses) 3. n quadlet (used for block write requests, lock requests and responses, and block read responses)
2-2 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 2.1.1.1 3-quadlet transmit format the 3-quadlet data format is shown in figures 2.1 and 2.2 . the ?st quadlet contains the packet control information. the second and third quadlets contain the 16-bit destination id and either the 48-bit quadlet aligned destination offset (used for read requests) or the response code (used for write responses). the ?ld names and their descriptions are described below. pri priority this four-bit ?ld is the priority level for the current packet. this ?ld should always be zero. tcode transaction code this four-bit ?ld is the transaction code for the current packet. the following table lists valid encoding for this ?ld. rt retry code this two-bit ?ld contains the valid retry code for the current packet as listed in the following table. figure 2.1 read request for data quadlet packet transmit format reserved spd tl rt tcode pri destinationid destinationoffsethigh destinationoffsetlow figure 2.2 write response packet transmit format rcvdbusid res spd tl rt tcode pri destinationid rcode reserved reserved tcode description 0100 read request for data quadlet 0010 write response rt retry code 01 retry_x
asynchronous data formats 2-3 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. tl transaction label these six bits indicate the transaction label for the packet. they are used for tracking requests with responses. ubuf transmitted requests should never use 0x3f, 0x3e (reserved for use by the pht modules). rcvdbusid received bus id this 10-bit ?ld contains the destination bus id used in the write request. this value is used as the source bus id in the write response. spd speed this three-bit ?ld indicates the speed at which the current packet is to be sent. destinationid destination id this 16-bit ?ld speci?s the destination id, which is the concatenation of the 10-bit destination bus id with the 6-bit destination node id. destinationoffset destination offset the 48-bit destination offset ?ld is the quadlet-aligned destination address. rcode response code this ?ld contains the four-bit response code to an earlier corresponding request. 2.1.1.2 4-quadlet transmit format this data format is shown in figures 2.3 through 2.5 . the ?st quadlet contains the packet control information. the second and third quadlets contain the 16-bit destination id and either the 48-bit quadlet aligned destination offset (used for read/write requests) or the response code (used for read responses). the fourth quadlet contains the quadlet data for read responses and quadlet write requests or the data length for the block read request. spd speed 000 100 mbits/s 010 200 mbits/s 100 400 mbits/s all others reserved
2-4 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. the ?ld names and descriptions are described below. pri priority this four-bit ?ld is the priority level for the current packet. this ?ld should always be zero. tcode transaction code this four-bit ?ld is the transaction code for the current packet. the following table lists the valid encoding for this ?ld. figure 2.3 write request for data quadlet packet transmit format reserved spd tl rt tcode pri destinationid destinationoffsethigh destinationoffsetlow quadlet_data figure 2.4 read response for quadlet data packet transmit format rcvdbusid res spd tl rt tcode pri destinationid rcode reserved reserved quadlet_data figure 2.5 read request for block data packet transmit format reserved spd tl rt tcode pri destinationid destinationoffsethigh destinationoffsetlow data_length reserved tcode description 0000 write request for data quadlet 0110 read response for data quadlet 0101 read request for data block
asynchronous data formats 2-5 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. rt retry code this two-bit ?ld contains the valid retry code for the current packet as listed in the following table. tl transaction label these six bits indicate the transaction label for the packet. they are used for tracking requests with responses. ubuf transmitted requests should never use 0x3f, 0x3e (reserved for use by the pht modules). rcvdbusid received bus id this 10-bit ?ld contains the destination bus id used in the read request. this value is used as the source bus id in the read response. spd speed this three-bit ?ld indicates the speed at which the current packet is to be sent. destinationid destination id this 16-bit ?ld speci?s the destination id, which is the concatenation of the 10-bit destination bus id with the 6-bit destination node id. destinationoffset destination offset the 48-bit destination offset ?ld is the quadlet-aligned destination address. rcode response code this ?ld contains the four-bit response code to an earlier corresponding request. quadlet_data quadlet data this 32-bit ?ld contains the quadlet data to be transmitted for either a read response or a write request. rt retry code 01 retry_x spd speed 000 100 mbits/s 010 200 mbits/s 100 400 mbits/s all others reserved
2-6 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. data_length data length the 16-bit data length ?ld speci?s the length of the data block size in bytes for block-data read requests. 2.1.1.3 n-quadlet transmit format the n-quadlet data format is shown in figures 2.6 through 2.7 . the ?st quadlet contains the packet control information. the second and third quadlets contain the 16-bit destination id and either the 48-bit quadlet aligned destination offset (used for read/write requests) or the response code (used for read/lock responses). the fourth quadlet contains the data length and the extended transaction code for the block write/read/lock. the block data, if any, follows the extended code. block data must be quadlet aligned; that is, you might have to append zeros to the block data for the last quadlet. the ?ld names and their descriptions are described below. figure 2.6 lock/write request for data block packet transmit format reserved spd tl rt tcode pri destinationid destinationoffsethigh destinationoffsetlow data_length extended_tcode data_?ld padding (if necessary) figure 2.7 lock/read response for block data packet transmit format rcvdbusid res spd tl rt tcode pri destinationid rcode reserved reserved data_length extended_tcode data_?ld padding (if necessary)
asynchronous data formats 2-7 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. pri priority this four-bit ?ld is the priority level for the current packet. this ?ld should always be zero. tcode transaction code this four-bit ?ld is the transaction code for the current packet. the following table lists valid encoding for this ?ld. rt retry code this two-bit ?ld contains the valid retry code for the current packet as listed in the following table. tl transaction label these six bits indicate the transaction label for the packet. they are used for tracking requests with responses. ubuf transmitted requests should never use 0x3f, 0x3e (reserved for use by the pht modules). rcvdbusid received bus id this 10-bit ?ld contains the destination bus id used in the read request. this value is used as the source bus id in the read response. spd speed this three-bit ?ld indicates the speed at which the current packet is to be sent. tcode description 0001 write request for data block 1001 lock request 1011 lock response 0111 read response for data block rt retry code 01 retry_x spd speed 000 100 mbits/s 010 200 mbits/s 100 400 mbits/s all others reserved
2-8 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. destinationid destination id this 16-bit ?ld speci?s the destination id, which is the concatenation of the 10-bit destination bus id with the 6-bit destination node id. destinationoffset destination offset the 48-bit destination offset ?ld is the quadlet-aligned destination address. rcode response code this ?ld contains the four-bit response code to an earlier corresponding request. data_length data length the 16-bit data length ?ld speci?s the length of the data block size in bytes for block-data read requests. data_?ld data field this ?ld contains block data that needs to be transmitted. its length is speci?d by the data_length ?ld. if data_length is zero, there is no data_?ld. if the value in the data_length ?ld is not a multiple of four, the data ?ld must be padded with zeros to make it quadlet aligned. extended_tcode extended transaction code the extended transaction code is used only for lock transactions. the following table lists the encoding of this ?ld. refer to the ieee-1394 document for detailed explanations of this decoding. extended_tcode description 0x0 reserved (reads and writes) 0x1 mask_swap 0x2 compare_swap 0x3 fetch_add 0x4 little_add 0x5 bounded_add 0x6 wrap_add 0x7 vendor_dependent 0x8?xf reserved
asynchronous data formats 2-9 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 2.1.2 asynchronous receive data formats asynchronous data is received in the receive fifo in one of four basic formats: 1. 4 quadlet (used for read requests for data quadlets and write responses) 2. 5 quadlet (used for read requests for block data, write requests for data quadlets, and read responses for data quadlets) 3. n quadlet (used for write requests for data blocks, lock requests and responses, and read responses for data blocks) 4. self-id data packets 2.1.2.1 4-quadlet receive format these data formats are shown in figures 2.8 and 2.9 . the ?st quadlet contains the destination node id and the rest of the packet header information. the second and third quadlets contain the 16-bit source id and either the 48-bit quadlet-aligned destination offset (used for read requests) or the response code (used for write responses). the ?ld names and their descriptions are described below. figure 2.8 read request receive format for data quadlet destinationid tl rt tcode pri sourceid destinationoffsethigh destinationoffsetlow reserved spd reserved figure 2.9 write response packet receive format destinationid tl rt tcode pri sourceid rcode reserved reserved reserved spd reserved
2-10 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. pri priority this four-bit ?ld is the priority level for the current packet. this ?ld should always be zero. tcode transaction code this four-bit ?ld is the transaction code for the current packet. the following table lists the valid encoding for this ?ld. rt retry code this two-bit ?ld contains the retry code for the current packet as listed in the following table. tl transaction label these six bits indicate the transaction label for the packet. they are used for tracking requests with responses. spd speed this three-bit ?ld indicates the speed at which the current packet was received. destinationid destination id this 16-bit ?ld speci?s the destination id, which is the concatenation of the 10-bit destination bus id with the 6-bit destination node id. destinationoffset destination offset the 48-bit destination offset ?ld is the quadlet-aligned destination address. tcode description 0100 read request for data quadlet 0010 write response rt retry code 01 retry_x spd speed 000 100 mbits/s 010 200 mbits/s 100 400 mbits/s all others reserved
asynchronous data formats 2-11 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. rcode response code this ?ld contains the four-bit response code to an earlier corresponding request. sourceid source id this 16-bit ?ld indicates the node id and bus id of the sender. 2.1.2.2 5-quadlet receive format these data formats are shown in figures 2.10 through 2.12 . the ?st quadlet contains the destination id and the rest of the packet header information. the second and third quadlets contain the 16-bit source id and either the 48-bit quadlet-aligned destination offset (used for read/write requests) or the response code (used for read responses). the fourth quadlet contains either the quadlet data for read responses and quadlet write requests or the data length for the block read request. the last quadlet contains the packet reception status. figure 2.10 write quadlet request receive format destinationid tl rt tcode pri sourceid destinationoffsethigh destinationoffsetlow quadlet_data reserved spd reserved figure 2.11 read quadlet response packet receive format destinationid tl rt tcode pri sourceid rcode reserved reserved quadlet_data reserved spd reserved
2-12 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. the ?ld names and their descriptions are described below. pri priority this four-bit ?ld is the priority level for the current packet. this ?ld should always be zero. tcode transaction code this four-bit ?ld is the transaction code for the current packet. the following table lists the valid encoding for this ?ld. rt retry code this two-bit ?ld contains the retry code for the current packet as listed in the following table. tl transaction label these six bits indicate the transaction label for the packet. they are used for tracking requests with responses. figure 2.12 read block request packet receive format destinationid tl rt tcode pri sourceid destinationoffsethigh destinationoffsetlow data_length reserved reserved spd reserved tcode description 0100 read request for data quadlet 0010 write response rt retry code 01 retry_x
asynchronous data formats 2-13 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. spd speed this three-bit ?ld indicates the speed at which the current packet was received. destinationid destination id this 16-bit ?ld speci?s the destination id, which is the concatenation of the 10-bit destination bus id with the 6-bit destination node id. destinationoffset destination offset the 48-bit destination offset ?ld is the quadlet-aligned destination address. rcode response code this ?ld contains the four-bit response code to an earlier corresponding request. sourceid source id this 16-bit ?ld indicates the node id and bus id of the sender. quadlet_data quadlet data this 32-bit ?ld contains the quadlet data to be transmitted for either a read response or a write request. data_length data length the 16-bit data length ?ld speci?s the length of the data block size in bytes for block-data read requests. 2.1.2.3 n-quadlet receive format these data formats are shown in figures 2.13 and 2.14 . the ?st quadlet contains the destination id and the rest of the packet header information. the second and third quadlets contain the 16-bit source id and either the 48-bit quadlet-aligned destination offset (used for read/write requests) or the response code (used for read/lock responses). the spd speed 000 100 mbits/s 010 200 mbits/s 100 400 mbits/s all others reserved
2-14 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. fourth quadlet contains the data length and the extended transaction code for the block write/read/lock. the block data, if any, follows the extended code. block data must be quadlet aligned; that is, there may be appended zeros to the block data for the last quadlet of the data ?ld. the ehdr and ihdr bits in the pht control and status register 0 affect the format of the data written to the dbuf transmit and receive fifos when endmas is asserted. if ihdr is not set, only the data ?ld portion of the incoming request is written to the dbuf receive fifo. if ihdr is set and ehdr is not set, the 1394 header is written to the dbuf receive fifo in addition to the data ?ld. if ihdr and ehdr are set, in addition to the 1394 header and data ?ld, a quadlet containing the speed of the received request is written to the dbuf receive fifo. note: if ihdr and ehdr are set, the format of the data in the dbuf is as shown in figure 2.13 (write request for data block receive format). the maximum data ?ld size that can be received is the dbuf receive fifo size less 20 bytes. if ehdr is not set, the dbuf transmit fifo must contain only the data ?ld for read response packets to be sent in response to received read requests. if ehdr is set, the format followed is that of figure 2.4 or figure 2.7 . an appropriate setting for ehdr and ihdr depends on the capability of the external dma controller. figure 2.13 lock/write request for data block receive format destinationid tl rt tcode pri sourceid destinationoffsethigh destinationoffsetlow data_length extended_tcode data_?ld padding (if necessary) reserved spd reserved
asynchronous data formats 2-15 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. . the ?ld names and their descriptions are described below. pri priority this four-bit ?ld is the priority level for the current packet. this ?ld should always be zero. tcode transaction code this four-bit ?ld is the transaction code for the current packet. the following table lists valid encoding for this ?ld. rt retry code this two-bit ?ld contains the valid retry code for the current packet as listed in the following table. tl transaction label these six bits indicate the transaction label for the packet. they are used for tracking requests with responses. ubuf transmitted requests should never use 0x3f, 0x3e (reserved for use by the pht modules). figure 2.14 lock/read response for block data receive format destinationid tl rt tcode pri sourceid rcode reserved reserved data_length extended_tcode reserved spd reserved tcode description 0001 write request for data block 1001 lock request 1011 lock response 0111 read response for data block rt retry code 01 retry_x
2-16 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. spd speed this three-bit ?ld indicates the speed at which the current packet is to be sent. destinationid destination id this 16-bit ?ld speci?s the destination id, which is the concatenation of the 10-bit destination bus id with the 6-bit destination node id. sourceid source id this 16-bit ?ld indicates the node id and bus id of the sender. destinationoffset destination offset the 48-bit destination offset ?ld is the quadlet-aligned destination address. rcode response code this ?ld contains the four-bit response code to an earlier corresponding request. data_length data length the 16-bit data length ?ld speci?s the length of the data block size in bytes for block-data read requests. data_?ld data field this ?ld contains block data that needs to be transmitted. its length is speci?d by the data_length ?ld. if data_length is zero, there is no data_?ld. if the value in the data_length ?ld is not a multiple of four, the data ?ld must be padded with zeros to make it quadlet aligned. extended_tcode extended transaction code the extended transaction code is used only for lock transactions. the following table lists the encoding of this spd speed 000 100 mbits/s 010 200 mbits/s 100 400 mbits/s all others reserved
isochronous dma data formats 2-17 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. ?ld. refer to the ieee-1394 document for detailed explanations of this decoding. 2.2 isochronous dma data formats this section describes the isochronous data transmit/receive formats. the data formats for the transmits and receives are described separately. 2.2.1 isochronous transmit data formats the data formats for an isochronous transmit using the dma transmit fifo are shown from figure 2.15 through figure 2.17 . data_?ld data field this ?ld contains the isochronous data. extended_tcode description 0x0 reserved (reads and writes) 0x1 mask_swap 0x2 compare_swap 0x3 fetch_add 0x4 little_add 0x5 bounded_add 0x6 wrap_add 0x7 vendor_dependent 0x8?xf reserved figure 2.15 isochronous transmit format 1 data_?ld padding (if necessary) figure 2.16 isochronous transmit format 2 reserved cycle_end cycle_skip 1110 spd fs data_?ld padding (if necessary)
2-18 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. reserved reserved this 19-bit ?ld is reserved and should be zeros. cycle_end cycle end this one-bit ?ld determines whether this is the last packet for which an isochronous request should be made during the current isochronous cycle (this bit must be set if hardware-generated cip headers are enabled). if hardware-generated cip headers are not enabled, this bit can be used to group several packets (with different isochronous channel numbers) that are to be transmitted during the same isochronous cycle. if n packets with different channel numbers are to be transmitted during the same isochronous cycle, the ?st n ? 1 packets would have cycle end equal to zero and the nth packet would have cycle end equal to one. thus n packets are transmitted during the same isochronous cycle. cycle_skip cycle skip this four-bit ?ld is used for ow rate control. once the core has queued and is ready to transmit the packet, the core waits n isochronous cycles before requesting the 1394 bus (where n is the value in the cycle skip ?ld), if gencip is not set. if gencip is set, the core sends empty cips for n isochronous cycles before requesting the 1394 bus to send the data_?ld following the embedded control quadlet. spd speed this three-bit ?ld is the speed at which the packet is to be sent. note: if cip format isochronous data with hardware-generated cip headers is being transmitted, in addition to setting the spd ?ld in the embedded control quadlet, the speed ?ld in the stream transmit channel header register must be set to the same value. fs frame start when set, this one-bit ?ld causes an syt time stamp to be generated when the packet is dmaed to the core if certain pht module control bits are set. data_?ld data field this ?ld contains the isochronous data.
isochronous dma data formats 2-19 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. note: cip format isochronous data with hardware-generated cip headers is not supported when using isochronous transmit format 3. reserved reserved this 19-bit ?ld is reserved and must be zeros. ce cycle end this one-bit ?ld determines whether this is the last packet for which an isochronous request should be made during the current isochronous cycle. this bit can be used to group several packets (with different isochronous channel numbers) that are to be transmitted during the same isochronous cycle. if n packets with different channel numbers were desired to be transmitted during the same isochronous cycle, the ?st n ? 1 packets would have cycle end equal to zero and the nth packet would have cycle end equal to one. this would result in the n packets being transmitted during the same isochronous cycle. cycle_skip cycle skip this four-bit ?ld is used for ow rate control. once the core has queued and is ready to transmit the packet, the core waits n isochronous cycles before requesting the 1394 bus (where n is the value in the cycle skip ?ld). spd speed this three-bit ?ld is the speed at which the packet is to be sent. fs frame start this one-bit ?ld when set causes an syt time stamp to be generated when the packet is dmaed to the core, if certain pht module control bits are set. figure 2.17 isochronous transmit format 3 reserved ce cycle_skip 1110 spd fs data_length tag channel 1010 sy data_?ld padding (if necessary)
2-20 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. data_length data length this ?ld contains the 16-bit data length for isochronous data. tag tag this ?ld contains the two-bit isochronous tag data format. channel channel this ?ld contains the six-bit isochronous channel number. sy synchronization code this four-bit synchronization code is application dependent. data_?ld data field this ?ld contains the isochronous data. 2.2.2 isochronous receive data formats the data formats for isochronous receives are shown in figure 2.18 and figure 2.19 . the ?st quadlet in figure 2.18 contains the isochronous channel number, data length, and synchronization code. subsequent quadlets contain the isochronous data received. the ?ld names and their descriptions are described below. data_length data length this ?ld contains the 16-bit data length for isochronous data. tag description 00 data field unformatted 01 iec-61883 format 10 ?1 reserved figure 2.18 isochronous receive format 1 data_length tag channel tcode sy data_?ld padding (if necessary)
phy packet data formats 2-21 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. tag tag this ?ld contains the two-bit isochronous tag data format. channel channel this ?ld contains the six-bit isochronous channel number. tcode transaction code this four-bit ?ld is the transaction code for the current packet. sy synchronization code this four-bit synchronization code is application dependent. data_?ld data field this ?ld contains the isochronous data. the ?ld names and their descriptions are described below. data_?ld data field this ?ld contains the isochronous data. 2.3 phy packet data formats this section describes the phy packet data transmit/receive formats. the data formats for the transmit and receive are described separately. 2.3.1 phy packet transmit data format the data formats for phy packet transmissions are shown in figure 2.20 . the least signi?ant eight bits of the ?st quadlet are ?ed tag description 00 data field unformatted 01 iec-61883 format 10 ?1 reserved figure 2.19 isochronous receive format 2 data_?ld padding (if necessary)
2-22 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. at 0b1110.0000. the second quadlet contains the phy packet data. the third quadlet is the inverse of the second quadlet. 2.3.2 phy packet receive data format the data formats for phy packet receptions are shown in figure 2.21 . the least signi?ant eight bits of the ?st quadlet are ?ed at 0b1110.0000. the second quadlet contains the phy packet data. 2.4 miscellaneous packet data formats this section describes the remaining packet data formats that the 1394 node controller core receives. the core, if programmed, will receive the self-id packets. 2.4.1 self-id packet receive data format the data format for the self-id packets is shown in figure 2.22 . the ?st quadlet contains the packet header information with tcode equal to 0b1110. the remaining quadlets contain the data that is received from the time the bus is reset to the ?st subaction gap. this data is the concatenation of all the self-id packets received. the sidf bit in the pdc control register determines whether or not the inverse quadlet of the phy packet is stored in addition to the phy packet quadlet itself. figure 2.20 phy packet transmit data format reserved 1110 0000 phy packet quadlet inverse of phy packet quadlet figure 2.21 phy packet receive data format reserved 1110 0000 phy packet quadlet
miscellaneous packet data formats 2-23 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. the resultcode ?ld is either 0xe (an error occurred) or 0x1 (no error occurred). if the last quadlet in the universal receive fifo does not follow this format, it indicates that an over?w condition occurred. 2.4.2 unformatted data transmit format the unformatted data transmit format is shown in figure 2.23 . it is sent as is without any crcs. the ?st quadlet is not included in the transmission. no ack is expected. figure 2.22 self-id receive format reserved 1110 0001 self-id packet data reserved result code figure 2.23 unformatted data transmit format reserved 1110 0001 unformatted packet data
2-24 data formats rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved.
1394 node controller core technical manual 3-1 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. chapter 3 signal descriptions this chapter describes the signals for the 1394 node controller core. the signals are categorized according to interface. they are described in alphabetical order by mnemonic. the mnemonic for an active low signal ends in an ?? the mnemonic for an active high signal ends in a ?. in the following descriptions, the verb assert means to drive true or active. the verb deassert means to drive false or inactive. this chapter contains the following sections: ? section 3.1, ?pplication interface ? section 3.2, ?niversal buffer fifo interface ? section 3.3, ?hy interface ? section 3.4, ?ma 0 interface ? section 3.5, ?ma 1 interface ? section 3.6, ?ma 0 fifo interface ? section 3.7, ?ma 1 fifo interface ? section 3.8, ?iscellaneous figure 3.1 is a logic diagram of the 1394 node controller core.
3-2 signal descriptions rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. figure 3.1 1394 node controller core logic diagram aint_int0p aint_int1p aint_int2p aint_intp aint_rddatap[31:0] aint_waitp app_addrp[15:0] app_readp app_selp app_wrdatap[31:0] app_writep application interface urfc_rdaddrp[0:10] urf_rddatap[0:31] urf_sizep[0:10] urfc_rdclkp urfc_wep urfc_wraddrp[0:10] urfc_wrclkp urfc_wrdata[0:31] utfc_rdaddrp[0:10] utfc_wraddrp[0:10] utf_rddatap[0:31] utf_sizep[0:10] utfc_rdclkp utfc_wep utfc_wrclkp utfc_wrdatap[0:31] universal buffer fifo interface directp llc_ctloep[0:1] llc_ctloutp[0:1] llc_doep[0:7] llc_doutp[0:7] llc_linkonp llc_lpsp llc_lreqoep llc_lreqp phy_ctlinp[0:1] phy_dinp[0:7] phy_linkonp phy_sclkp phy interface dint_cyctimep[24:0] dintx_dreqp dintx_dreqwp dintx_fsyncoutp dintx_rddatap[31:0] dintx_cipquadp dmacx_dackp dmacx_dackwp dmacx_fsyncinp dmacx_readp dmacx_wrdatap[31:0] dmacx_writep dma interface dbufx_aadr[0:10] dbufx_badr[0:10] dbufx_clka dbufx_clkb dbufx_dia[0:31] dbufx_dib[0:31] dbufx_doa[0:31] dbufx_dob[0:31] dbufxwea dbufx_web drfx_initsizep[0:10] dtfx_initsizep[0:10] dma fifo interface clk8kinp gscan_enablelp gscan_inp gscan_outp gtest_enablep llc_clk8koutp powerdownn resetp syscllk_isslowp sysclkp testmodep 1394 node controller core miscellaneous
application interface 3-3 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 3.1 application interface this interface is used for application software device access. the 1394 node controller core is a slave on this bus. aint_int0p interrupt register 0 interrupt o the core asserts this signal high to indicate an ?nterrupt register 0 interrupt occurred. aint_int1p interrupt register 1 interrupt o the core asserts this signal high to indicate an ?nterrupt register 1 interrupt occurred. aint_int2p interrupt register 2 interrupt o the core asserts this signal high to indicate an ?nterrupt register 2 interrupt occurred. aint_intp interrupt register interrupt o the core asserts this signal high to indicate an interrupt in interrupt register 0, 1, or 2 occurred. aint_rddatap[31:0] data read port to application o the 1394 node controller core puts the data on this bus when the application device is reading an internal register or fifo. aint_waitp wait cycle request o the 1394 node controller core asserts this signal high to indicate that the current application interface transaction is not ?ished. when asserted, this signal tells the application device to continue the current read/write from/to the core. app_addrp[15:0] address bus i the application device puts the address on this bus when it wants to read or write a 1394 node controller cores internal register or fifo. app_readp application data read from registers/fifo i the application device asserts this signal and app_selp high when it wants to read the 1394 node controller cores internal registers or fifos.
3-4 signal descriptions rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. app_selp select signal i when this control signal is asserted high, access to the registers and fifos is enabled. app_wrdatap[31:0] data write port i the application device puts the data on this bus for a write to a 1394 node controller core internal register or fifo. app_writep application data write to registers/fifo i the application device asserts this signal and app_selp high when it wants to write the 1394 node controller cores internal registers or fifos. 3.2 universal buffer fifo interface urfc_rdaddrp[0:10] receive fifo read address port o when reading the ubuf receive fifo, the core places the read address on this bus. urf_rddatap[0:31] receive fifo read data port i the 1394 node controller core receives data from the ubuf receive fifo on this bus. urf_sizep[0:10] size of receive fifo connected i this bus indicates to the core the size (in quadlets) of the ubuf receive fifo. urfc_rdclkp receive fifo read clock o this signal is the read clock for the ubuf receive fifo. urfc_wep receive fifo write enable signal o the 1394 node controller core asserts this signal high to request a write to the ubuf receive fifo.
universal buffer fifo interface 3-5 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. urfc_wraddrp[0:10] receive fifo write address port o when writing to the ubuf receive fifo, the core places the write address on this bus. urfc_wrclkp receive fifo write clock o this signal is the write clock for the connected ubuf receive fifo. urfc_wrdatap[0:31] receive fifo write data port o the core places data to be written to the ubuf receive fifo on this bus. utfc_rdaddrp[0:10] transmit fifo read address port o the 1394 node controller core places the address for a read of the ubuf transmit fifo on this bus. utfc_wraddrp[0:10] transmit fifo write address port o the 1394 node controller core places the address for a write of the ubuf transmit fifo on this bus. utf_rddatap[0:31] transmit fifo read data port i data read from the ubuf transmit fifo is input to the core on this bus. utf_sizep[0:10] size of transmit fifo connected i this bus indicates to the core the size (in quadlets) of the ubuf transmit fifo. utfc_rdclkp transmit fifo read clock o this signal is the read clock for the ubuf transmit fifo. utfc_wep transmit fifo write enable signal o the core asserts this signal high to perform a write to the ubuf transmit fifo.
3-6 signal descriptions rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. utfc_wrclkp receive fifo write clock o this signal is the write clock for the connected ubuf transmit fifo. utfc_wrdatap[0:31] transmit fifo write data port o the core places data to be written to the ubuf transmit fifo on this bus. 3.3 phy interface the phy interface connects to a phy device. this interface conforms to ieee 1394a, revision 2.0. directp nondifferentiated phy interface i drive this signal low when an isolation barrier is present. llc_ctloep[0:1] phy control enable o in designs that use 3-state buffers for llc_ctloutp, use these signals to enable the 3-state buffers. llc_ctloutp[0:1] phy control out o llc_ctloutp[0:1] are the control lines from the core to the phy device. llc_ctloutp[0:1] description 00 idle. transmission complete, bus released. 01 hold. the core is either holding the bus while preparing data or indicating that it wants to reacquire the bus without arbitrating to send another packet. 10 transmit. the core is sending a packet to the phy device. 11 reserved.
phy interface 3-7 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. llc_doep[0:7] phy data enable o in designs that use 3-state buffers for llc_doutp, use these signals to enable the 3-state buffers. llc_doutp[0:7] phy data out o the core places data to be written to the phy device on this bus. llc_doutp0 is the most-signi?ant bit; llc_doutp7 is the least-signi?ant bit. llc_linkonp llc link on o the core asserts this signal to indicate it has received a link on indication from the phy device. llc_lpsp link power status o the core asserts this signal to indicate the core is active. llc_lreqoep link request enable o in designs that use a 3-state buffer for llc_lreqp, use this signal to enable the 3-state buffer. when directp is not asserted, llc_lreqoep acts as a digital differentiator that enables the 3-state buffer only when llc_lreqp changes. llc_lreqp link request o the 1394 node controller core asserts this signal high to request access to the phy device. phy_ctlinp[0:1] phy control in i these signals are the control lines from the phy device to the 1394 node controller core. phy_ctlinp[0:1] description 00 idle. no activity. 01 status. the phy device is sending status information to the core. 10 receive. a packet is being transferred from the phy device to the core. 11 grant. the core has been granted the bus and can send a packet.
3-8 signal descriptions rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. phy_dinp[0:7] phy data in i this bus receives data from the phy device. phy_dinp0 is the most-signi?ant bit; phy_dinp7 is the least-signi?ant bit. phy_linkonp phy link on i when this signal is asserted, another node is requesting activation of the core. phy_sclkp phy clock i this input connects to the 49.152 mhz input clock from the phy device. 3.4 dma 0 interface this interface is used for dma data transfers. data paths can be con?ured as 8, 16, or 32 bits wide. dint_cyctimep[24:0] cycle time o these signals re?ct the least signi?ant 25 bits of the cycle time register synchronized to sysclkp. bit 24 is the most signi?ant bit of the cycle count ?ld. dint0_dreqp dma read request for transmit and receive channels o when the ractl bit in the dma control and status register is set, packets read from the pht0 dbuf use dint0_dreqp while packets written to the pht0 dbuf use dint0_dreqwp. if simultaneous read/write access is not required, ractl can be reset to zero. in this case, packets read from or written to the pht0 dbuf use dint0_dreqp. dint0_dreqwp dma write request for transmit and receive channels o when the ractl bit in the dma control and status register is set, packets read from the pht0 dbuf use
dma 0 interface 3-9 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dint0_dreqp while packets written to the pht0 dbuf use dint0_dreqwp. if simultaneous read/write access is not required, ractl can be reset to zero. in this case, packets read from or written to the pht0 dbuf use dint0_dreqp. dint0_fsyncoutp fsync output o if the core is receiving a cip format stream containing syt time stamps, then, when an syt time stamp is detected, dint0_fsyncoutp is asserted during the read of the quadlet following the syt time stamp. dint0_rddatap[31:0] data read port o the 1394 node controller core places data from the dbuf receive fifo on this bus. dint0_cipquadp cip quadlet o the quadlet output on dint0_rddatap is a iec-61883 cip quadlet. dmac0_dackp dma read acknowledge i when the ractl bit in the dma control and status register is set, packets read from the pht0 dbuf use dmac0_dackp while packets written to the pht0 dbuf use dmac0_dackwp. if simultaneous read/write access is not required, ractl can be reset to zero. in this case, packets read from or written to the pht0 dbuf use dmac0_dackp. dmac0_dackwp dma write acknowledge i when the ractl bit in the dma control and status register is set, packets read from the pht0 dbuf use dmac0_dackp while packets written to the pht0 dbuf use dmac0_dackwp. if simultaneous read/write access is not required, ractl can be reset to zero. in this case, packets read from or written to the pht0 dbuf use dmac0_dackp.
3-10 signal descriptions rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dmac0_fsyncinp frame sync input i when the fssel bit of the pht control and status register is set, the fsyncin input signal is used to control time stamping when the gencip bit is set and the most-signi?ant bit of the fmt ?ld of the stream control transmit 1 register is 0 (dvcr). this input should be asserted during the ?st write strobe of a packet in which an syt time stamp is generated by the core. dmac0_readp edmac data read from fifo i the external dma controller asserts this signal high when it wants to read the dbuf receive fifo. dmac0_wrdatap[31:0] data write port i the dma device places data to be written to the dbuf transmit fifo on this bus. dmac0_writep edmac data write to fifo i the external dma controller asserts this signal high to request a write to the dbuf transmit fifo. 3.5 dma 1 interface this interface is used for dma data transfers. data paths can be con?ured as 8, 16, or 32 bits wide. dint1_dreqp dma read request for transmit and receive channels o when the ractl bit in the dma control and status register is set, packets read from the pht1 dbuf use dint1_dreqp while packets written to the pht1 dbuf use dint1_dreqwp. if simultaneous read/write access is not required, ractl can be reset to zero. in this case, packets read from or written to the pht1 dbuf use dint1_dreqp.
dma 1 interface 3-11 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dint1_dreqwp dma write request for transmit and receive channels o when the ractl bit in the dma control and status register is set, packets read from the pht1 dbuf use dint1_dreqp while packets written to the pht1 dbuf use dint1_dreqwp. if simultaneous read/write access is not required, ractl can be reset to zero. in this case, packets read from or written to the pht1 dbuf use dint1_dreqp. dint1_fsyncoutp fsync output o if the core is receiving a cip format stream containing syt time stamps, then, when an syt time stamp is detected, dint1_fsyncoutp is asserted during the read of the quadlet following the syt time stamp. dint1_rddatap[31:0] data read port o the 1394 node controller core places data from the dbuf receive fifo on this bus. dint1_cipquadp cip quadlet o the quadlet output on dint1_rddatap is a iec-61883 cip quadlet. dmac1_dackp dma read acknowledge i when the ractl bit in the dma control and status register is set, packets read from the pht1 dbuf use dmac1_dackp while packets written to the pht1 dbuf use dmac1_dackwp. if simultaneous read/write access is not required, ractl can be reset to zero. in this case, packets read from or written to the pht1 dbuf use dmac1_dackp. dmac1_dackwp dma write acknowledge i when the ractl bit in the dma control and status register is set, packets read from the pht1 dbuf use dmac1_dackp while packets written to the pht1 dbuf use dmac1_dackwp.
3-12 signal descriptions rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. if simultaneous read/write access is not required, ractl can be reset to zero. in this case, packets read from or written to the pht1 dbuf use dmac1_dackp. dmac1_fsyncinp frame sync input i when the fssel bit of the pht control and status register is set, the fsyncin input signal is used to control time stamping when the gencip bit is set and the most-signi?ant bit of the fmt ?ld of the stream control transmit 1 register is 0 (dvcr). this input should be asserted during the ?st write strobe of a packet in which an syt time stamp is generated by the core. dmac1_readp edmac data read from fifo i the external dma controller asserts this signal high when it wants to read the dbuf receive fifo. dmac1_wrdatap[31:0] data write port i the dma device places data to be written to the dbuf transmit fifo on this bus. dmac1_writep edmac data write to fifo i the external dma controller asserts this signal high to request a write to the dbuf transmit fifo. 3.6 dma 0 fifo interface dbuf0_aadr[0:10] pht0 dma side fifo address port o the 1394 node controller core places the address on this bus for an access of the dma side of the dbuf transmit/receive fifo. dbuf0_badr[0:10] pht0 pht side fifo address port o the 1394 node controller core places the address on this bus for an access of the pht side of the dbuf transmit/receive fifo.
dma 0 fifo interface 3-13 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dbuf0_clka pht0 dma side fifo clock o clock for an access of the dma side of the dbuf transmit/receive fifo. dbuf0_clkb pht0 pht side fifo clock o this signal is the clock for an access of the pht side of the dbuf transmit/receive fifo. dbuf0_dia[0:31] pht0 transmit fifo write data port o data to be written from the 1394 node controller core to the transmit fifo is output on this bus. dbuf0_dib[0:31] pht0 receive fifo write data port o data to be written from the 1394 node controller core to the receive fifo is output on this bus. dbuf0_doa[0:31] pht0 receive fifo read data port i this 32-bit bus receives data from the receive fifo on this bus. dbuf0_dob[0:31] pht0 transmit fifo read data port i the 1394 node controller core receives data from the transmit fifo on this bus. dbuf0_wea pht0 transmit fifo write enable signal o the 1394 node controller core asserts this output to request a write of the transmit fifo. dbuf0_web pht0 receive fifo write enable signal o the 1394 node controller core asserts this signal to request a write to the receive fifo. drf0_initsizep[0:10] size of pht0 receive fifo i this bus indicates the size of the receive fifo. dtf0_initsizep[0:10] size of pht0 transmit fifo i this 11-bit bus indicates the size of the transmit fifo.
3-14 signal descriptions rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 3.7 dma 1 fifo interface dbuf1_aadr[0:10] pht1 dma side fifo address port o the 1394 node controller core places the address on this bus for an access of the dma side of the dbuf transmit/receive fifo. dbuf1_badr[0:10] pht1 pht side fifo address port o the 1394 node controller core places the address on this bus for an access of the pht side of the dbuf transmit/receive fifo. dbuf1_clka pht1 dma side fifo clock o this signal is the clock for accesses to the dma side of the dbuf transmit/receive fifo. dbuf1_clkb pht1 pht side fifo clock o this signal is the clock for accesses to the pht side of the dbuf transmit/receive fifo. dbuf1_dia[0:31] pht1 transmit fifo write data port o data to be written from the 1394 node controller core to the transmit fifo is output on this bus. dbuf1_dib[0:31] pht1 receive fifo write data port o data to be written from the 1394 node controller core to the receive fifo is output on this bus. dbuf1_doa[0:31] pht1 receive fifo read data port i this 32-bit bus receives data from the receive fifo. dbuf1_dob[0:31] pht1 transmit fifo read data port i the 1394 node controller core receives data from the transmit fifo on this bus.
miscellaneous 3-15 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dbuf1_wea pht1 transmit fifo write enable signal o the 1394 node controller core asserts this output to request a write of the transmit fifo. dbuf1_web pht1 receive fifo write enable signal o the 1394 node controller core asserts this signal to request a write to the receive fifo. drf1_initsizep[0:10] size of pht1 receive fifo i this bus indicates the size of the receive fifo. dtf1_initsizep[0:10] size of pht1 transmit fifo i this 11-bit bus indicates the size of the transmit fifo. 3.8 miscellaneous clk8kinp 8-khz clock input i this optionally selectable clock is used for the cycle timer. gscan_enablep scan enable i this input is used during manufacturers testing only. hold it low during normal operation. gscan_inp scan data in i this input is used during manufacturers testing only. during normal operation, it is ignored. gscan_outp scan data out o this output is used during manufacturers testing only. during normal operation, it is ignored. gtest_enablep test enable i this input is used during manufacturers testing only. hold it low during normal operation. llc_clk8koutp 8 khz clock output o this signal changes at the same rate as the cycle count ?ld of the cycle timer register (nominally 8 khz).
3-16 signal descriptions rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. powerdownn power down i when asserted, this signal causes the llc_lpsp signal to be deasserted. resetp system reset i this input is the core initialization signal. to reset the 1394 node controller core, assert this input high for a minimum of two sysclkp cycles. sysclk_isslowp sysclkp range i when asserted, this input indicates sysclkp is in the 11 to 2 mhz range. sysclkp application domain clock i sysclkp is the application interface clock. its frequency range is 2 to 50 mhz. testmodep test mode i this input is used during manufacturers testing only. hold it low during normal operation.
1394 node controller core technical manual 4-1 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. chapter 4 registers this chapter describes the 1394 node controller core registers. the control and status registers and the 1394 registers are directly accessible from the application interface. this chapter contains the following sections: ? section 4.1, ?rdering conventions ? section 4.2, ?ontrol and status registers (csrs) ? section 4.3, ?394 registers 4.1 ordering conventions the ordering conventions of the 1394 serial bus are used in the representation of data structures. in order to promote interoperability with memory buses that may have different ordering conventions, the de?ition of the order and signi?ance of bits within bytes, bytes within quadlets, and quadlets with octlets is in terms of their relative position and not their physically addressed position. within a byte, the most signi?ant bit, msb, is that which is transmitted ?st; the least signi?ant bit, lsb, is that which is transmitted last on the serial bus, as illustrated in figure 4.1 . the signi?ance of the interior bits uniformly decreases in progression from msb to lsb. figure 4.1 interior bit signi?ance msb interior bits (decreasing signi?ance left to right) lsb
4-2 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. within a quadlet, the most signi?ant byte (msb) is that which is transmitted ?st; the least signi?ant byte (lsb) is that which is transmitted last on the serial bus, as shown in figure 4.2 . within an octlet, the most signi?ant quadlet is that which is transmitted ?st, and the least signi?ant quadlet is that which is transmitted last on the serial bus, as figure 4.3 indicates. 4.2 control and status registers (csrs) this section describes the csrs. table 4.1 shows the implemented csrs in this block with their respective register space addresses. accesses from the 1394 bus to the csrs are served with split asynchronous subactions. 4.2.1 node id register (0x000) the node id register is used to identify and modify the 16-bit identi?r of this node. it identi?s the current bus id and physical id values, which directly affect the initial node address. one of the ?lds in this register is the offset_id ?ld, known as the physical-id value of the node. the phy figure 4.2 interior byte signi?ance msb second most signi?ant byte third least signi?ant byte lsb figure 4.3 internal quadlet order most signi?ant quadlet least signi?ant quadlet table 4.1 csr registers register space address (application side) register 0x000 node id 0x004 cycle timer
control and status registers (csrs) 4-3 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. determines the physical id after a bus reset during the selfid process. when the selfid process is complete, the physical id has been determined, and it is set in a register inside the phy. in addition, the phy automatically initiates a status transfer to the link, which includes the physical id. busid bus id [31:22] default: 0x03ff rw this read/write ?ld allows multiple bus con?urations to distinguish node addresses on one bus from those on another. the initial value of this ?ld is 0x03ff. offsetid offset id [21:16] default: 0x00 ro this read-only ?ld contains the physical id of the node. it is generated during the selfid process. the initial value of this ?ld is 0. res reserved [15:1] these bits are reserved and must be written as zeros. valid valid 0 this bit is cleared from when a bus reset is detected until the offset id has been automatically updated and from a power on reset until the offset id has been automati- cally updated. 4.2.2 cycle time register (0x004) the ?lds in this register specify the current time value. reception of a cycle start packet when the device is not cycle master and the cycle timer is enabled is treated as a write to the cycle start register. the register can also be modi?d using the application interface. 31 22 21 16 busid offset id 15 10 res valid
4-4 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. seccnt second count [31:25] default: 0x00 rw this ?ld increments on each carry from the cycle count. an increment from value 127 causes a wraparound to zero. cyccnt cycle count [24:12] default: 0x0000 rw this ?ld increments on each carry from the cycle offset ?ld when extcyc is zero or for each positive transition of the clk8kin input signal when extcyc and cmstr are one. an increment from value 7999 causes a wraparound to zero and carries into the second count ?ld (this ?ld has 125 s resolution). cycoff cycle offset [11:0] default: 0x000 rw this ?ld increments every other sclk from the phy. when extcyc is zero, an increment from when the cycoff ?ld matches the value in the offmatch ?ld of the control 1 register (default value 3071) causes a wraparound to zero and carries into the cycle count ?ld. each positive transition of clk8kin when extcyc and cmstr are one causes a wraparound to zero. 31 25 24 16 seccnt cyccnt 15 12 11 0 cyccnt cycoff
1394 registers 4-5 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3 1394 registers these registers control and monitor the operation of the 1394 node controller core. table 4.2 shows these registers with their respective address offsets. table 4.2 1394 register summary address offset register name page # 0x008 control 0 register page 4-7 0x00c control 1 register page 4-11 0x010 control 2 register page 4-12 0x014 phy access register page 4-13 0x020 interrupt 0 register page 4-14 0x024 interrupt 0 mask register page 4-19 0x028 interrupt 1 register page 4-21 0x02c interrupt 1 mask register page 4-22 0x030 interrupt 2 register page 4-23 0x034 interrupt 2 mask register page 4-23 0x038 dma space register page 4-24 0x03c acknowledge status register page 4-25 0x040 ubuf transmit next page 4-25 0x044 ubuf transmit last page 4-25 0x048 ubuf transmit clear page 4-26 0x04c ubuf receive clear page 4-26 0x050 ubuf receive page 4-26 0x054 ubuf receive level page 4-26 0x058 encoded interrupt priority page 4-26 0x080 packet header transformation control and status register 0 page 4-28 0x084 pht split time-out/empty cip interval register 0 page 4-35 0x088 pht request/response/cip receive header 0 register 0 page 4-37 0x08c pht request/response/cip receive header 1 register 0 page 4-39
4-6 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 0x090 pht request header 2/sph receive register 0 page 4-42 0x094 stream receive channel/nodeid selection 0 register 0 page 4-43 0x098 stream receive channel/nodeid selection 1 register 0 page 4-44 0x09c stream receive channel header register 0 page 4-44 0x0a0 stream transmit channel header register 0 page 4-45 0x0a4 data transfer control register 0 page 4-47 0x0a8 cip header transmit 0 register 0 page 4-48 0x0ac cip header transmit 1 register 0 page 4-49 0x0b4 stream transmit time stamp offset register 0 page 4-50 0x0b8 dma control and status register 0 page 4-52 0x0bc dma transfer threshold register 0 page 4-53 0x0c0 dbuf fifos level register 0 page 4-54 0x0c4 dbuf tx data register 0 page 4-54 0x0c8 dbuf rx data register 0 page 4-55 0x0cc dbuf watermarks register 0 page 4-56 0x0d0 dbuf fifo size register 0 page 4-57 0x100 packet header transformation control and status register 1 page 4-57 0x104 pht split time-out/empty cip interval register 1 page 4-64 0x108 pht request/response/cip receive header 0 register 1 page 4-66 0x10c pht request/response/cip receive header 1 register 1 page 4-68 0x110 pht request header 2/sph receive register 1 page 4-71 0x114 stream receive channel/nodeid selection 0 register 1 page 4-73 0x118 stream receive channel/nodeid selection 1 register 1 page 4-73 0x11c stream receive channel header register 1 page 4-74 0x120 stream transmit channel header register 1 page 4-75 0x124 data transfer control register 1 page 4-76 0x128 cip header transmit 0 register 1 page 4-77 0x12c cip header transmit 1 register 1 page 4-78 table 4.2 1394 register summary address offset register name page #
1394 registers 4-7 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.1 control 0 register (0x008) the bits within the control 0 register enable/disable various functions of the 1394 node controller core. all bits in this register can be read and written from the application interface. rcvselfid receive selfid 31 default: 0 rw when this bit is set, all selfid packets from phys during bus initialization are placed in the universal receive or dmarf0 fifo. when this bit is cleared, these packets are ignored. sidf selfid format 30 default: 0 rw when this bit is set, both quadlets of all selfid packets from phys during bus initialization are placed in the receive fifo. setting this bit is useful when selfid packets are received corrupted and determining suspect 0x134 stream transmit time stamp offset register 1 page 4-79 0x138 dma control and status register 1 page 4-81 0x13c dma transfer threshold register 1 page 4-82 0x140 dbuf fifos level register 1 page 4-83 0x144 dbuf tx data register 1 page 4-84 0x148 dbuf rx data register 1 page 4-84 0x14c dbuf watermarks register 1 page 4-85 0x150 dbuf fifo size register 1 page 4-86 table 4.2 1394 register summary address offset register name page # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rcv self id sidf delim txen rxen txrst rx rst busid rst cmstr cyc tmren ext- cyc root brde stardy loose- tight iso 15 12 11 6 5 4 3 0 retlim prilim rsp0 urcvm res
4-8 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. nodes is desired. when this bit is cleared, the ?st quadlet of all selfid packets from phys during bus initialization is placed in the universal receive fifo. delim data error retry limit [29:28] default: 0 rw the value in this ?ld determines how many automatic retry attempts are made for an asynchronous transmit packet when an ack_data_error is received in response to a transmission attempt. a value of zero means only the original transmission of the packet is made. txen transmitter enable 27 default: 0 rw when this bit is cleared, the transmitter does not arbitrate or send any packets. rxen receiver enable 26 default: 0 rw when this bit is cleared, the receiver stops receiving packets. txrst transmitter reset 25 default: 0 rw when this bit is set, the entire transmitter resets synchronously. this bit clears itself. rxrst receiver reset 24 default: 0 rw when this bit is set, the entire receiver resets synchronously. this bit clears itself. busidrst bus id reset 23 default: 0 rw when this bit is set, the bus id ?ld is cleared to 0x03ff, when a local bus reset is received. cmstr cycle master 22 default: 0 rw when this bit is set, the core transmits a cycle start packet subsequent to the cyccnt ?ld of the cycle timer register being incremented. subsequent to a bus reset, if the root bit is zero (as seen in the status from the phy), then this bit is automatically cleared.
1394 registers 4-9 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. cyctmren cycle timer enable 21 default: 1 rw when this bit is set, the cycle timers cycle offset ?ld is incremented. extcyc extcyc 20 default: 0 rw when this bit and the cmstr are set, the cycle timers cyccnt ?ld is incremented subsequent to each positive transition of the clk8kin input signal. root root 19 default: 0 ro a one on this bit indicates this node is the root on the bus. it automatically updates after the selfid phase. brde busy received data errors 18 default: 0 when this bit is set, the llc sends an ack_busy_x acknowledge to any rejected incoming packet with data crc or data length mismatch errors. setting this bit can improve the throughput from ohci links that are experiencing temporary conditions causing under?w of the ohci links transmit fifo. stardy send tardy 17 default: 0 rw when this bit is set, the receiver sends an ack tardy acknowledge to any incoming packet addressed to the core. loosetightiso loose iso cycles 16 default: 1 rw when this bit is reset to zero, loose iso cycles are supported. when this bit is one, tight iso cycles are supported. tight iso means that isochronous format packets are only accepted if received during the interval between a cycle start packet and a subaction gap. retlim retry limit [15:12] default: 0xf rw the value in this ?ld determines how many automatic retry attempts are made for an asynchronous transmit packet when a busy ack is received in response to a
4-10 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. transmission attempt. a value of zero means only the original transmission of a packet is made. prilim priority request limit [11:6] default: 0x00 rw the value in this ?ld determines how many priority requests the core can make in a fairness interval for phy packets and packets with the following asynchronous tcodes (0x0, 0x1, 0x4, 0x5, 0x9, 0xa). in addition asynchronous packets with tcodes of (0x2, 0x6, 0x7, 0xb, 0x8) can use priority requests without regard to this limit. at each arbitration reset gap indication from the phy, a decrementer is loaded with the value of this ?ld. as long as the counter is nonzero (it is decremented after each transmission of a packet subject to the limit) and a busy acknowledge has not been received subsequent to packet transmission, priority requests are used for the packets listed. if the decrementer reaches zero or a busy ack is received in response to a packet transmitted by the core, the core only uses fair arbitration requests (with the exception of cycle start packets) until reception of another arbitration reset gap indication from the phy. rsp0 route selfid packets to pht0 5 default: 0 when this bit is set, selfid packets are routed to pht0/dmarf0. setting this bit is useful when the total size of the selfid packets exceeds the size of the ubuf. when this condition occurs, the application can disable the dma interface (and also clear elis, endmas, erreq, ewreq, etalk), set this bit, and cause the phy to initiate a bus reset. once the subactgap interrupt occurs, this bit can be cleared by the application and the selfid packets can be read from the dmarf0 using dbuf rx fifo data register 0. urcvm ubuf receive multiple packets 4 default: 0 when this bit is set, the universal receive buffer accepts multiple packets. when this bit is cleared, the universal receive buffer will send busy acks in response to all incoming packets, if there is already a packet in the ubuf receive fifo. an exception is made for phy packets and selfid packets.
1394 registers 4-11 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. multiple selfid and phy packets are accepted if the previously accepted packets are phy or selfid packets. res reserved [3:0] default: 0 these bits are reserved and must be written as zeros. 4.3.2 control 1 register (0x00c) the settings within the control 1 register enable/disable various functions of the 1394 node controller core. res reserved [31:27], [15:12] these bits are reserved for future use. they must be written as zeros. ptime ping timer [26:16] default: 0x7ff ro each time the last bit of a phy packet is transmitted from the core to the phy, this ?ld is initialized to zero. ptime is incremented every other sclk until the core receives the ?st bit of the response to the phy packet. the bus manager uses the resulting value to optimize the gap count. offmatch offset match [11:0] default: 3071 rw this ?ld contains the value compared with the cycle offset ?ld of the cycle time register to determine carry generation for the cycle count ?ld of the cycle time register. 31 27 26 16 res ptime 15 12 11 0 res offset match
4-12 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.3 control 2 register (0x010) the settings within the control 2 register enable/disable various functions of the 1394 node controller core. all bits in this register can be read and written from the application interface. this registers clock is the application clock, unlike most of the other registers. res reserved [31:4] default: 0 these bits are reserved and must be written as zeros. sok sclk ok 3 default: 0 ro when this bit is set, the clock from the phy is opera- tional. this bit can be polled after asserting lpsen to determine when accesses to all sclk-based registers can be successfully made. srst sclk domain reset 2 default: 1 rw when this bit is set, all logic that runs off the clock from the phy (most of the core) is reset. this bit is automatically cleared after the reset has occurred (which can only occur while lpsen is set). reset the fifos before using them after this bit is set. lpsen link power status enable 1 default: 0 rw when this bit is set, the lps output is asserted (high in undifferentiated mode, pulsing in differentiated mode). note: sensible deassertion of this bit results in power savings due to the clock supplied from the phy (which is used for most of the link logic) stopping if this bit is not asserted. impor tant: only the control 2, interrupt 2, and interrupt 2 mask registers can be accessed when lpsen is deasserted. all 31 16 res 15 432 1 0 res sok srst lpsen lpsrst
1394 registers 4-13 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. other register accesses will not return the actual value in those registers when read and any writes will not affect the contents of those registers. after asserting lpsen, valid accesses to other registers cannot be immediately made because it is dependent upon the clock from the phy being restored. lpsrst link power status reset 0 default: 0 rw when this bit is set, the lps output is deasserted (low in either undifferentiated mode or differentiated mode) for at least 2.75 microseconds but no more than 24 microseconds. this bit is automatically cleared. do not set this bit during packet transmission in order to ensure compliance with section 5.1 of the 1394a standard with regards to phy/link interface signal conditioning. 4.3.4 phy access register (0x014) the phy access register provides access to the internal registers of the attached phy. when reading a phy register, the address of the register is written to the phyrgadr ?ld with the rdphy bit set. this bit is cleared once the request has been sent to the phy. the clearing of the bit does not mean that the data has been received in the register. when the phy returns the data for the read through status, the phy register received (phyrrx) interrupt is set, indicating that this register contains the data from the phy read access. when writing a phy register, the address and data of the phy register are written into phyrgadr and phyrgdat ?lds with the wrphy bit set. this bit is cleared once the write request has been sent to the phy. the application should not try to write into this register as long as rdphy or wrphy is set. when the read phy bit is set, the read data and the 31 30 29 28 27 24 23 16 rdphy wrphy res phyrgadr phyrgdat 15 12 11 8 7 0 res phyrxadr phyrxdat
4-14 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. address of the phy register are written into the phyrxdat and phyrxadr ?lds eventually and the phyrrx interrupt bit is set. all bits in this register can be read from and written into the application interface side except phyrxadr and phyrxdat, which are read only. rdphy read phy 31 default: 0 rw when this bit is set, the 1394 node controller core initiates a register read to the attached phy. wrphy write phy 30 default: 0 rw when this bit is set, the 1394 node controller core initiates a register write to the attached phy. res reserved [29:28], [15:12] these bits are reserved and must be written as zeros. phyrgadr phy access address [27:24] default: 0 rw this ?ld contains the address of the phy register to be accessed. phyrgdat write phy register data [23:16] default: 0 rw this ?ld contains the data to be written into the phy register indicated by phyrgadr ?ld. phyrxadr receive phy address [11:8] default: 0 ro this read-only ?ld contains the address of the register from which phyrxdat came. phyrxdat receive phy register data [7:0] default: 0 ro this read-only ?ld contains received register data from the phy. 4.3.5 interrupt 0 register (0x020) the ?lds within the interrupt 0 register inform the application when the state of the 1394 node controller core changes. when a bit is set in the interrupt 0 register and its corresponding bit in the interrupt 0 mask register is set, the 1394 node controller core generates an interrupt to
1394 registers 4-15 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. the application. the application acknowledges the request, and writes a one to the corresponding interrupt bit. this action resets the corresponding interrupt bit. the default value for this register is 0. phyint phy interrupt 31 a one on this bit indicates an interrupt status bit was received from the phy. phyrrx phy register received 30 a one on this bit indicates a register value has been transferred to the phy access register from the phy interface. phyrst phy reset 29 a one on this bit indicates the phy recon?uration has started (bus reset). the phy reset interrupt acts as a tx ubuf reset. the tx ubuf is reset as long as the interrupt bit is on (prevents sending ubuf packets when the intended destination node id might have changed). arbrstgap arbitration reset gap 28 a one on this bit indicates the serial bus has been idle for an arbitration reset gap. cmdrst command reset 27 a one on this bit indicates that the receiver has been sent a quadlet write request addressed to the reset_start csr register. sntbsyack sent busy/tardy acknowledge 26 a one on this bit indicates the receiver was forced to send the busy acknowledge to a packet addressed to this node because the receive fifo contains a previously received packet or a tardy ack was sent and the packet was not accepted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 phyint phyr rx phyrst arb rst gap cmd rst snt bsy ack hdrerr tcerr sub- act gap urx cyctl cyc sec cycst cyc dn cyc pend cyc lost 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cyc arbfl ack rcvd ack miss invack retex sto pb cntr uresp fmte txstk syttt syttr res ciphe drfo drfr
4-16 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. hdrerr header error 25 a one on this bit indicates the receiver detected a header crc error on an incoming packet that may have been addressed to this node. tcerr transaction code error 24 a one on this bit indicates the transmitter detected an invalid transaction code in the data at the transmit fifo interface. subactgap subaction gap 23 a one on this bit indicates the phy detected a subaction gap. urx ubuf packet received 22 a one on this bit indicates that an asynchronous packet has been received and is con?med in the ubuf. cyctl cycle too long 21 this bit is set, if after transmitting a cycle start packet, a subaction gap or bus reset is not detected within 116 microseconds. the cmstr bit is automatically cleared upon this bit being set. the cmstr bit cannot be set while this bit is set. cycsec cycle second 20 this bit is set whenever the cycle-second ?ld of the cycle timer register is updated. cycst cycle start 19 this bit is set whenever the cycle start packet has been sent or received. cycdn cycle done 18 this bit is set when an arbitration gap has been detected on the bus after the cycle-start packet. this bit indicates that the isochronous cycle is over. cycpnd cycle pending 17 this bit is set when a cycle start packet is expected to be sent or received. cyclost cycle lost 16 this bit is set when no cycle start packet is sent/received between two successive cycle sync events.
1394 registers 4-17 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. cycarbfl cycle arbitration failed 15 this bit is set if the arbitration to send the cycle-start packet has failed. ackrcvd acknowledge received 14 a one on this bit indicates the ack code and transaction label for the last request or response packet transmitted from the ubuf are received and are present in the ack status register. ackmiss acknowledge missing 13 after the core has transmitted an asynchronous packet, this bit is set if a subaction gap indication is received from the phy without an intervening acknowledge reception. this bit is not set after phy or broadcast packet transmission. invack invalid acknowledge 12 this bit is set upon receipt of an acknowledge that is reserved. retex retry attempts exhausted 11 this bit is set if a packet has been retransmitted retlim or delim number of times and received a busy/data-error ack each time. sto split time out 10 this bit is set when a pht request packet has been transmitted that received a pending ack that was not followed by a response packet before the split time out limit was reached (the pact bit is cleared). pbcntr packet/byte count reached 9 this bit is set if the pbcnt ?ld of the data transfer control register is decremented to zero, meaning a pbcnt number of request packets or pbcnt number of bytes has been transmitted successfully (the pact bit is cleared). for a series of read requests, the data from the last packet that caused the pbcntr to be set might still be in the dbuf receive fifo (the dact bit of the dma control and status register can be examined to determine when the ?al packet has been completely transferred).
4-18 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. uresp unexpected response 8 this bit is set when a bus reset occurs while the pact bit was set and a pht was in one of the asynchronous modes (ewreq or erreq, east or endmas set) or if a request packet generated by a pht module receives a ?al response other than ?omplete from the destination node (the pact bit is cleared). the pht control and status register can be read to determine the ?al response received to the request. fmte format error 7 this bit is set whenever the pht module enters the stuck state, because either it detected the control quadlet or the isochronous header that was expected to be prepended to the data ?ld of an isochronous packet from the dbuf transmit fifo contained an unexpected value (transmission stopped and pht stuck). txstk tx stuck 6 this bit is set whenever the tx enters the stuck state, because the transmit fifo becomes empty in the middle of a packet transmission. syttt syt time stamp transmitted 5 this bit is set whenever a packet containing an syt time stamp has been transmitted. syttr syt time stamp received 4 this bit is set whenever a packet containing an syt time stamp has been received. res reserved 3 these bits are reserved and must be written as zeros. ciphe cip header error 2 this bit is set whenever the eoh or form bits of a received cip header are unexpected (packet discarded). drfo dbuf receive fifo over?w 1 this bit is set when during an isochronous format packet reception the dbuf receive fifo over?ws. the packet that caused the over?w is removed from the fifo and reception continues.
1394 registers 4-19 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. drfr dbuf receive fifo reception 0 a one on this bit indicates a packet has been con?med into the dmarf. 4.3.6 interrupt 0 mask register (0x024) the interrupt 0 mask register determines whether the interrupts speci?d in the interrupt 0 register are activated or not. each bit in this register corresponds to an interrupt ?g bit in the interrupt 0 register. to mask a particular interrupt, clear its corresponding bit in the interrupt 0 mask register. the application interface can read and write all bits in this register. the default value for each bit in this register is zero. phyintm phy interrupt mask 31 clearing this bit masks the phy interrupt interrupt. phyrrxm phy register received mask 30 clearing this bit masks the phy register received interrupt. phyrstm phy reset mask 29 clearing this bit masks the phy reset interrupt. arbrstgapm arbitration reset gap mask 28 clearing this bit masks the arbitration reset gap interrupt. cmdrstm command reset mask 27 clearing this bit masks the command reset interrupt. sntbsyackm sent busy acknowledge mask 26 clearing this bit masks the sent busy acknowledge interrupt. hdrerrm header error mask 25 clearing this bit masks the header error interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 phy intm phyr- rxm phy rst m arb rst gapm cmd rstm snt bsy ackm hdr errm tc err m sub act gapm urxm cyc tlm cyc secm cyc stm cyc dnm cyc pendm cyc lostm 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cyc arb flm ack rcvd m ack missm inv ackm retex m stom pb cnt rm u resp m fmte m txstk m syt ttm syt trm res ciph em drfo m drfr m
4-20 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. tcerrm transaction code error mask 24 clearing this bit masks the transaction code error interrupt. subactgapm subaction gap mask 23 clearing this bit masks the subaction gap interrupt. urxm ubuf packet received mask 22 clearing this bit masks the ubuf packet received interrupt. cyctlm cycle too long mask 21 clearing this bit masks the cycle too long interrupt. cycsecm cycle second mask 20 clearing this bit masks the cycle second interrupt. cycstm cycle start mask 19 clearing this bit masks the cycle start interrupt. cycdnm cycle done mask 18 clearing this bit masks the cycle done interrupt. cycpndm cycle pending mask 17 clearing this bit masks the cycle pending interrupt. cyclostm cycle lost mask 16 clearing this bit masks the cycle lost interrupt. cycarbflm cycle arbitration failed mask 15 clearing this bit masks the cycle arbitration failed interrupt. ackrcvdm acknowledge received mask 14 clearing this bit masks the acknowledge received interrupt. ackmissm acknowledge missing mask 13 clearing this bit masks the acknowledge missing interrupt. invackm invalid acknowledge mask 12 clearing this bit masks the invalid acknowledge interrupt. retexm retry attempts exhausted mask 11 clearing this bit masks the retry attempts exhausted interrupt.
1394 registers 4-21 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. stom split time out mask 10 clearing this bit masks the split time out interrupt. pbcntrm packet/byte count reached mask 9 clearing this bit masks the packet/byte count reached interrupt. urespm unexpected response mask 8 clearing this bit masks the unexpected response interrupt. fmtem format error mask 7 clearing this bit masks the format error interrupt. txstkm tx stuck mask 6 clearing this bit masks the tx stuck interrupt. sytttm syt time stamp transmitted mask 5 clearing this bit masks the syt time stamp transmitted interrupt. syttrm syt time stamp received mask 4 clearing this bit masks the syt time stamp received interrupt. res reserved 3 this bit is reserved and must be written as zero. ciphem cip header error mask 2 clearing this bit masks the cip header error interrupt. drfom dbuf receive fifo over?w mask 1 clearing this bit masks the dbuf transmit fifo over?w interrupt. drfrm dbuf receive fifo reception mask 0 clearing this bit masks the dbuf receive fifo reception interrupt. 4.3.7 interrupt 1 register (0x028) the ?lds within the interrupt 1 register inform the application when the state of the 1394 node controller core changes. when a bit is set in both the interrupt 1 register and its corresponding bit in the interrupt 1 mask register, the 1394 node controller core generates an interrupt to the application. the application acknowledges the request, and writes a one
4-22 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. to the corresponding interrupt bit. this action resets the corresponding interrupt bit. the default value for this register is 0. res reserved [31:2] these bits are reserved and must be written as zeros. utd ubuf transmission done 1 this bit is set if transmission attempts of a packet in the ubuf transmit fifo are done (due to receipt of a pending, complete, or missing ack or busy/data error retries are exhausted, a bus reset is detected, a phy or broadcast packet is transmitted, etc.). dtfo dbuf transmit fifo over?w 0 this bit is set if during a transmission, the dbuf transmit fifo over?ws (pact is cleared (if elis not set) and pstk is set). 4.3.8 interrupt 1 mask register (0x02c) the interrupt 1 mask register determines whether the interrupts speci?d in the interrupt 1 register are activated or not. to mask a particular interrupt, clear its corresponding bit in the interrupt 1 mask register. the application interface can read and write all bits in this register. the default value for each bit in this register is zero. res reserved [31:2] these bits are reserved and must be written as zeros. 31 16 res 15 2 1 0 res utd dtfo 31 16 res 15 2 1 0 res utdm dtfom
1394 registers 4-23 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. utdm ubuf transmission done mask 1 clearing this bit masks the ubuf transmission done interrupt. dtfom dbuf transmit fifo over?w mask 0 clearing this bit masks the dbuf transmit fifo over?w interrupt. 4.3.9 interrupt 2 register (0x030) the ?lds within the interrupt 2 register inform the application when the state of the 1394 node controller core changes. when a bit is set in the interrupt 2 register and its corresponding bit is set in the interrupt 2 mask register, the 1394 node controller core generates an interrupt to the application. the application acknowledges the request and writes a one to the corresponding interrupt bit. this action resets the corresponding interrupt bit. the default value for this register is 0. the clock of this register is the application clock unlike most of the other registers. res reserved [31:1] these bits are reserved and must be written as zeros. linkon link on 0 this bit is set whenever the linkon input has been asserted. clear this bit only after setting lpsen or this bit will be set again because the linkon input will still be asserted. 4.3.10 interrupt 2 mask register (0x034) the interrupt 2 mask register determines whether the interrupts speci?d in the interrupt 2 register are activated or not. each bit in this register corresponds to an interrupt ?g bit in the interrupt 2 register. to mask a particular interrupt, clear its corresponding bit in the interrupt 2 31 16 res 15 10 res linkon
4-24 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. mask register. the application interface can read and write all bits in this register. the default value for each bit in this register is zero. the clock of this register is the application clock unlike most of the other registers. res reserved [31:1] these bits are reserved and must be written as zeros. linkonm link on mask 0 this bit is the mask bit for the linkon interrupt. 4.3.11 dma space register (0x038) this register contains information used in the transfer of a dma space response packet. this information is used for transfers to/from the dbuf only. dmar dma region [31:0] default: 0 rw this ?ld contains the value compared against the upper 32 bits of the destination offset ?ld of a received read or write request to determine if a dma space access is being made. a dma space access is being made if the upper 32 bits of the destination offset ?ld of a received read or write request is less than dmar. 31 16 res 15 10 res linkonm 31 16 dmar 15 0 dmar
1394 registers 4-25 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.12 acknowledge status register (0x03c) this register stores the acknowledge received for the last request or response packet transmitted from the utf fifo. this register also stores the transaction label for the last utf packet transmitted. the application can read this register, but cannot write to it. ack code acknowledge code [31:28] default: 0 ro this ?ld contains the acknowledge code received. this ?ld is not updated after transmissions of phy, broadcast, or any other transmitted packets for which an ack is not received. translabel transaction label [27:22] default: 0 ro this ?ld contains the transaction label. res reserved [21:0] these bits are reserved for future use. they must be written as zeros. 4.3.13 ubuf transmit next (0x040) this register is not physically within the 1394 node controller core. the core treats a write access to this register like a write to the utf fifo. the application writes a transmit packet into this fifo for the ?st (n ? 1) quadlets of the packet (packet size is n quadlets). 4.3.14 ubuf transmit last (0x044) this register is not physically within the 1394 node controller core. the core treats a write access to this register like a write to the utf fifo. the application writes the last quadlet for the transmit packet into this address, which con?ms that this address is the last quadlet of the 31 28 27 22 21 16 ackcode tr anslabel res 15 0 res
4-26 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. packet. once a quadlet is written into the location, the status signals are updated on the llc side of the fifo. 4.3.15 ubuf transmit clear (0x048) this register is not physically within the 1394 node controller core. the core treats a write access to this register like a request to initialize the utf fifo pointers. the application writes this location ?st to prepare the utf fifo before loading a packet into the utf fifo for transmission. 4.3.16 ubuf receive clear (0x04c) this register is not physically within the 1394 node controller core. the core treats a write access to this register like a request to initialize the urf fifo pointers. the application need not write to this location during normal operation. 4.3.17 ubuf receive (0x050) this register is not physically within the 1394 node controller core. the core treats a read to this register like a read of the urf fifo. 4.3.18 ubuf receive level (0x054) this register is the ubuf receive level, synchronized to the application interface clock. after a packet is received in the urf fifo, this register should be read to determine the size of the packet in quadlets before reading the packet from the urf fifo. 4.3.19 encoded interrupt priority (0x058) this register contains a code that indicates the highest priority unmasked interrupt that is set. 31 16 res 15 8 7 0 res ipcode
1394 registers 4-27 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. res reserved [31:8] these bits are reserved for future use. they must be written as zeros. ipcode interrupt priority code [7:0] default: 0 rw the ipcode ?ld contains the code associated with the highest priority unmasked interrupt that is set. the interrupts are prioritized as shown in the following table. interrupt priority code phyrst 0x84 cmdrst 0x80 hdrerr 0x7c tcerr 0x78 txstk 0x74 fmte 0x70 invack 0x6c ackmiss 0x68 retex 0x64 uresp 0x60 drfo 0x5c dfto 0x58 cyctl 0x54 cyclost 0x50 cycarbfl 0x4c phyint 0x48 phyrrx 0x44 urx 0x40 ciphe 0x3c sntbsyack 0x38 drfr 0x34 utd 0x30 ackrcvd 0x2c pcntr 0x28 syttt 0x24 syttr 0x20 arbrstgap 0x1c
4-28 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.20 pht control and status register 0 (0x080) the settings within the pht control register enable/disable various functions of the 1394 packet header transformation module. all bits in this register can be read and written from the application interface. note: program all pht con?uration bits in other registers before enabling one of (east, erreq, ewreq, endmas) or (elis and/or etalk). east enable asynchronous stream transmit 31 default: 0 rw when this bit is set, 1394 asynchronous stream packets (isochronous transmit format 1 packets sent during the asynchronous interval) are generated while epcnt is set and the pbcnt ?ld of the data transfer control register is not zero, and the threshold condition of the dfill ?ld of the data transfer control register has been met. when this bit is set, 1394 asynchronous stream packets are generated while epcnt is not set and the threshold condition of the dfill ?ld of the data transfer control register has been met. ewreq, erreq, endmas, and etalk must not be set when this bit is set. this bit is only sampled between transfers. if the prbr bit becomes set while this bit and the pact bit are set, the pact bit is subactgap 0x18 cycst 0x14 cycdn 0x10 sto 0x0c cycpnd 0x08 cycsec 0x04 no interrupt 0x00 interrupt priority code 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 east cch gts fssel strip ehdr ecq gen- cip ihdr pht rst epcnt etalk elis er req ew req 15 14 13 12 11 10 9 8 7 4 3 0 ebcnt eri syts endmas res pstk prbr pact rcvdack rrcode
1394 registers 4-29 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. cleared and the pstk bit is set because the channel number must be reallocated. cch check cip header 30 default: 0 rw when this bit is set, received isochronous packets are checked to determine if the eoh and form bits of the cip header conform to the two-quadlet cip header format. if the packet does not conform, the ciphe interrupt is set. gts generate time stamp 29 default: 0 rw when this bit, gencip, and etalk are set, then a time stamp is generated and is included in the transmitted packet. the most-signi?ant bit of the fmt ?ld of the cip header transmit 1 register determines if there is a syt time stamp. the sph bit of the cip header transmit 0 register determines if there is a source packet header time stamp. fssel frame sync select 28 default: 0 rw when this bit is set, the fsyncin input signal is used to control time stamping when gencip and the most-signi?ant bit of the fmt ?ld of the stream control transmit 1 register is 0 (for example, dvcr). the fsyncin input should be asserted during the ?st write strobe of a packet in which a syt time stamp should be generated by the core. if this bit is not set and syt time stamping is desired, the ecq bit must be set to enable the alternative method (syt time stamping occurs for each packet whose frame start bit is set in the application prepended embedded control quadlet).
4-30 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. strip strip cip header [27:26] default: 0 rw this ?ld controls how cip headers are handled when listening to an isochronous channel. ehdr embedded header 25 default: 0 rw when this bit is set, it is required that the header of the packet (as shown in isochronous transmit format 3 or the read response for block data packet transmit format) is prepended to the data ?ld of a packet to be transmitted. the header registers are not used. for unformatted isochronous data ?lds (tag = 0 in header), multichannel talk capability can be supported. when this bit is set and etalk is set, ecq should also be set. the embedded control quadlet is needed to determine the speed of transmission of the packet. ecq embedded control quadlet 24 default: 0 rw when this bit is set, it is required that a control quadlet is prepended to the data ?ld of an isochronous packet to be transmitted (the control quadlet enables software-controlled frame synchronization and hardware assisted isochronous data ?w control (useful for dv frame rate transmission control). when gencip and this bit are set and the cycle skip ?ld of the embedded control quadlet is n, n empty cip packets are transmitted before the packet containing the data_?ld after the embedded control quadlet. in addition, for unformatted data ?lds (tag = 0), multichannel talk capability can be supported if this bit is set in addition to the ehdr bit. strip description 00 unchanged. 01 strip all cip headers (also subtract 8 bytes from data packet length in received isochronous header sent to dbuf) 10 strip only empty cips (if ihdr is set, when an empty cip is encountered the header is not written to the dbuf) 11 reserved.
1394 registers 4-31 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. gencip generate cip header 23 default: 0 rw when this bit is set, a cip header is prepended to the data ?ld of each isochronous packet transmitted. do not set this bit if talking on more than one isochronous channel. if this bit is set, for each dma request assertion, the dma controller must write less than or equal to the number of source packets transmitted in a 1394 payload. ihdr include header 22 default: 0 rw when this bit is set, the header is written to the dbuf fifo in addition to the data ?ld of the 1394 packet (useful when listening to more than one isochronous channel or dma space requests enabled). phtrst pht reset 21 default: 0 rw if the pht becomes stuck, this bit should be set (this bit automatically clears itself). epcnt enable packet counter 20 default: 0 rw when this bit is set, pht packet transmissions stop when the pbcnt ?ld of the data transfer control register is decremented to zero. if neither this bit nor ebcnt is set and either erreq, ewreq, etalk, or east is set, 1394 packets are transmitted inde?itely. ebcnt and epcnt must not be set at the same time. etalk enable isochronous talk 19 default: 0 rw when this bit is set, isochronous packets are transmitted. east, erreq, endmas, and ewreq must not be set if this bit is set. when generating cips, set etalk before setting den (dma enable). this bit is only sampled between transfers. elis enable isochronous listen 18 default: 0 rw when this bit is set, isochronous packets transmitted on channels enabled in the stream receive channel selection registers are received. erreq and ewreq must not be set if this bit is set. this bit is only sampled between transfers.
4-32 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. erreq enable read requests 17 default: 0 rw when this bit is set, 1394 read requests are generated while epcnt or ebcnt is set and the pbcnt ?ld of the data transfer control register is not cleared. if this bit is set, 1394 read requests are generated inde?itely while neither epcnt nor ebcnt is set and the dbuf receive fifo has enough space to accept another response. east, ewreq, etalk, endmas, and elis must not be set if this bit is set. this bit is only sampled between transfers. if the prbr bit becomes set while this bit and the pact bit are set, the pact bit is cleared and the pstk bit is set because the node ids might have changed. ewreq enable write requests 16 default: 0 rw when this bit is set, 1394 write requests are generated while epcnt or ebcnt is set and the pbcnt ?ld of the data transfer control register is not cleared. if this bit is set, 1394 write requests are generated inde?itely while neither epcnt nor ebcnt is set. east, erreq, etalk, endmas, and elis must not be set when this bit is set. this bit is only sampled between transfers. if the prbr bit becomes set while this bit and the pact bit are set, the pact bit is cleared and the pstk bit is set because the node ids may have changed. ebcnt enable byte count 15 default: 0 rw if this bit is set, asynchronous pht packet transmissions stop when the pbcnt ?ld of the data transfer control register is decremented to zero. the data length ?ld of the transmitted 1394 header of the last packet transferred is adjusted appropriately if the pbcnt ?ld is not divisible by the programmed data length. if neither this bit nor epcnt is set and either erreq or ewreq is set, 1394 packets are transmitted inde?itely. both ebcnt and epcnt must not be set at the same time. this bit must not be set when etalk or east is set. eri enable request interval 14 default: 0 rw if this bit and ewreq or erreq are set, the time interval between consecutive pht requests as measured from the reception of an ack or response packet of ?omplete
1394 registers 4-33 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. or ?usy for the ?st packet is determined by the value programmed in the rqintrvl ?ld. syts syt start 13 default: 0 rw if this bit is set, incoming cip format isochronous packets are not written to the dbuf until a packet containing an syt time stamp is received (which indicates the start of a frame). endmas enable dma space 12 default: 0 rw when this bit is set, automatic handling of received read and write requests is enabled. the pht automatically handles a received request packet whose quadlet aligned address matches the dmar ?ld criteria. east, erreq, etalk, ewreq, and elis must not be set when this bit is set. this bit is only sampled between transfers. if the prbr bit becomes set while this bit and the pact bit are set, the pact bit is cleared and the pstk bit is set because the node ids might have changed. automatic handling of read and write requests occurs when the endmas bit is set, an incoming request packet's quadlet aligned address matches the dmar ?ld criteria, and the incoming request packet's source node id corresponds to a selected node for the pht (the corresponding bit in the stream receive channel/nodeid selection registers is set). the ehdr and ihdr bits in pht control and status register 0 affect the format of the data written to the dbuf transmit and receive fifos when endmas is asserted. if ihdr is not set, only the data ?ld portion of the incoming request is written to the dbuf receive fifo. if ihdr is set and ehdr is not set, the 1394 header is written to the dbuf receive fifo in addition to the data ?ld. if ihdr and ehdr are both set, in addition to the 1394 header and data ?ld, a quadlet containing the speed of the received request is written to the dbuf receive fifo. note: if ehdr is set, care must be taken to guarantee that all response packets have been sent prior to disabling endmas. one possibility would be to ?st clear the nodeid selection registers to disable further acceptance
4-34 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. of incoming requests by the pht. when it is determined that all previously accepted requests have been processed, endmas can be safely cleared. note: if ihdr and ehdr are set, the format of the data in the dbuf is as shown in figure 2.13 (write request for data block receive format). the maximum data ?ld size that can be received is the dbuf receive fifo size less 20 bytes. if ehdr is not set, the dbuf transmit fifo must contain only the data ?ld for read response packets to be sent in response to received read requests. if ehdr is set, the format followed is that of figure 2.4 or figure 2.7 . an appropriate setting for ehdr and ihdr depends on the capability of the external dma controller. res reserved 11 this bit is reserved and must be written as zero. pstk pht module stuck 10 default: 0 ro when this bit is set, software must set the phtrst bit to reinitialize the module. prbr pht received bus reset 9 default: 0 ro this bit is set when the pact bit is set and a bus reset is detected. pact pht active 8 default: 0 ro this bit is automatically set when the pht module is not in the idle or stuck state with the exception that if both etalk and elis are set and the pht transmitter becomes stuck, the pact bit remains set because the pht receiver never becomes stuck. rcvdack received acknowledge [7:4] default: 0xf ro this ?ld contains the ack code received for the last packet transmitted. it is initialized to 0xf when a request for transmission is made.
1394 registers 4-35 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. rrcode received response code [3:0] default: 0xf ro this ?ld contains the rcode in the last response packet received because of a request packet transmitted. it is initialized to 0xf when a request for transmission is made. 4.3.21 pht split time-out/empty cip interval register 0 (0x084) when erreq or ewreq is set, this register contains the maximum time allowed from reception of an ack pending in reply to a request initiated by the pht block until a response to that request is received. application software is responsible for split time-out detection for packets transmitted using the utf fifo. this detection can be done using the cycst and ackrcvd interrupts. dst disable split time-out 31 when this bit is set, the time limit ?ld is ignored and there is no hardware time-out. it might be useful to set this bit when it is known the destination node is not on the local 1394 bus. in such a bridged environment, the remote split time-out might be known to be longer than the maximum value to which the timelimit ?ld can be programmed, so other methods must be used for time-out detection. res reserved [30:16] these bits are reserved for future use. they must be written as zeros. timelimit time limit [15:0] default: 0x0000 rw bits [15:13] correspond to seconds. bits [12:0] correspond to fractional seconds with a 125 s resolution (that is, equivalent resolution to the cycle count ?ld of the cycle timer register). bits [12:0] must be 31 30 16 dst res 15 0 timelimit
4-36 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. programmed with a value less than 8000. the actual duration of time between reception of an ack pending and nonreception of a response packet that causes the sto interrupt to be set can differ as much as 125 microseconds less than the programmed value. when etalk is set, the register is de?ed as follows. eecipo enable empty cip override 31 default: 0 rw when this bit, gencip, and etalk, etc. are set, an empty cip packet is sent during the isochronous cycle subsequent to each time an internal counter increments to the same value as the ecipi ?ld. epfs enable programmable frame synchronization 30 default: 0 rw when this bit, gencip, etalk, etc. are set, an syt time stamp is generated for the ?st nonempty cip packet transmitted and every n+1 nonempty cip packets transmitted thereafter, where n is the value of the ppf ?ld. ppf packets per frame [29:21] default: 0 rw this ?ld is only used when the epfs bit is set. it is programmed with the number of packets per frame minus one (for example, for a 525-60 system, the value is 249 decimal). res reserved 20 these bits are reserved for future use. they must be written as zeros. 31 30 29 21 20 19 16 eecipo epfs ppf res ecipi 15 0 ecipi
1394 registers 4-37 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. ecipi empty cip interval [19:0] default: 0 rw this ?ld is compared against an internal counter that increments every other sclk (49.152 mhz clock) from the phy. the counter is reset to zero when a match occurs. 4.3.22 pht request/response/cip receive header 0 register 0 (0x088) this register contains information used in the transfer of a request packet if erreq or ewreq is set or a response packet if endmas is set or a received isochronous packet if elis is set. this information is used for transfers to/from the dbuf only. if erreq or ewreq is set, the register is de?ed as follows. did destination id [31:16] default: 0 rw this ?ld is the concatenation of the bus id and the node id of the destination. the broadcast node id of 0b111111 is not supported. doffhi destination offset hi [15:0] default: 0 rw this ?ld contains the most-signi?ant 16 bits of the destination offset address. this ?ld must not be programmed with a value that would result in an over?w when this ?ld is automatically updated during multipacket transmission. if endmas is set, the de?ition is as follows (note that if ehdr is not set, the contents of this register do not always re?ct the last request received and should not be relied on for that purpose). 31 16 destination id 15 0 destination offset hi
4-38 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. destid destination id [31:16] default: 0x0000 rw this ?ld is the concatenation of the bus id and the node id of the node that initiated the dma space request. dlen data length [15:0] default: 0 rw this ?ld contains the data length in bytes of the received dma space request, which is reused if a read response is generated. when elis is set, this register is de?ed as follows. eoh0 end of cip header 0 31 default: 0 ro a value of 0 means another header quadlet will follow (always zero for a standard two-quadlet cip). form0 form 0 30 default: 0 ro this ?ld is always zero for a standard two-quadlet cip. sid source id [29:24] default: 0 ro this ?ld contains the node id of the transmitter. dbs data block size [23:16] default: 0 ro this ?ld contains the data block size in quadlets. 31 16 destid 15 0 dlen 31 30 29 24 23 16 eoh0 form0 sid dbs 15 14 13 11 10 9 8 7 0 fn qpc sph res dbc
1394 registers 4-39 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. fn fraction number [15:14] default: 0 ro this ?ld contains the number of data blocks into which a source packet is divided. qpc quadlet padding count [13:11] default: 0 ro this ?ld contains the number of dummy quadlets padded to a source packet to equalize the size of divided data blocks. sph source packet header 10 default: 0 ro a value of one on this bit indicates that the source packet has its own header. res reserved [9:8] these bits are reserved for future use. dbc data block counter [7:0] default: 0 ro this ?ld contains the continuity counter of data blocks to detect a loss of data blocks. the counter value for the ?st data block in a bus packet is shown in this ?ld. 4.3.23 pht request/response/cip receive header 1 register 0 (0x08c) this register contains information used in the transfer of a request packet (if erreq or ewreq is set) or a response packet (if endmas is set), or a received isochronous packet (if elis is set). this information is used for transfers to/from the dbuf only. when erreq or ewreq is set, this register is de?ed as follows. 31 16 destination offset lo 15 0 destination offset lo
4-40 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dofflo destination offset lo [31:0] default: 0 rw this ?ld contains the least-signi?ant 32 bits of the destination offset address. if endmas is set, this register is de?ed as follows (note that if ehdr is not set, the contents of this register do not always re?ct the last request received and must not be relied on for that purpose). res reserved [31:23] these bits are reserved for future use. they must be written as zeros. tcode transaction code [22:19] default: 0 rw this ?ld contains the transaction code of the dma space read or write request. speed speed [18:16] default: 0 rw this ?ld contains the transmit speed of the dma space read or write request. rcvdbusid received bus id [15:6] default: 0 rw this ?ld contains the destination bus id used in a dma space read request. this value is used as the source bus id in the read response 31 23 22 19 18 16 res tcode speed 15 6 5 0 rcvdbusid tl speed[13:15] encoding 000 s100 speed 010 s200 speed 100 s400 speed
1394 registers 4-41 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. tl transaction label [5:0] default: 0x0000 rw this ?ld contains the transaction label of the received dma space read or write request. when elis is set, this register is de?ed as follows. eoh1 end of cip header 1 31 default: 0 ro a value of one on this bit means another header quadlet does not follow (should always be one for standard two-quadlet cip). form1 form 1 30 default: 0 ro this bit must always be zero for a standard two-quadlet cip. fmt format id [29:24] default: 0 ro the encoding for this ?ld is shown in the table below. fdf format dependent field [23:16] default: 0 ro this ?ld is de?ed for each format. syt synchronization time field [15:0] default: 0 ro for dvcr, this ?ld can contain a time stamp of the frame synchronization pulse. for mpeg2, this ?ld is 0. 31 30 29 24 23 16 eoh1 form1 fmt fdf 15 0 syt fmt description 0x00 when the most-signi?ant bit (bit 2) is zero, a time stamp may be in the syt ?ld (such as in the dvcr format). 0x20 when the most-signi?ant bit (bit 2) is one, a time stamp is not in the syt ?ld (such as in the mpeg format).
4-42 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.24 pht request header 2/stream sph receive register 0 (0x090) if erreq or ewreq is set, this register contains information used in the transfer of a request packet. this information is used for transfers to/from the dbuf only. res reserved [31:29] these bits are reserved for future use. rqintrvl request interval [28:25] this four-bit ?ld contains the minimum number of desired nominal 125 s cycles between reception of an ack or response of ?omplete or ?usy for a previous pht generated request and transmission of the next pht generated request. the actual observed time between any two requests can be as much as 125 s less than the programmed value (to guarantee at least a 125 s interval, the programmed value should be two). tl transaction label [24:19] default: 0x0 rw these six bits indicate the transaction label for the packet. they are used for tracking requests with responses. pht module 0 must be programmed with 0x3f. pht module 1 must be programmed with 0x3e. speed speed [18:16] default: 0 rw this ?ld contains the transmit speed of the dbuf read or write request as shown in the following table. 31 29 28 25 24 19 18 16 res rqintrvl tl speed 15 0 dlen speed[13:15] encoding 000 s100 speed 010 s200 speed 100 s400 speed
1394 registers 4-43 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dlen data length [15:0] default: 0 rw this ?ld contains the data length in bytes of the payload to be written or read. after an ack or rcode of ?omplete is received in response to a transmitted request, the destination offset ?ld of the pht request header register is updated with the addition of the data length ?ld. when elis is set, the register is de?ed as follows. this register contains the time stamp from the last received packet with an isochronous header tag ?ld of 0b01 and a cip header sph bit of 0b1. res reserved [31:25] these bits are reserved for future use. they must be written as zeros. tstmp time stamp [24:0] default: 0 rw this ?ld contains the time stamp of the packet. 4.3.25 stream receive channel/nodeid selection 0 register 0 (0x094) the settings within the stream receive channel selection registers enable/disable isochronous channel reception when elis is set or enable/disable dma space read/write requests from other nodes when endmas is set . 31 25 24 16 res tstmp 15 0 tstmp 31 16 channel select hi 15 0 channel select hi
4-44 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. chselhi channel select hi [31:0] default: 0 rw this ?ld contains the reception enable bits for stream channels 63 (bit 31) to 32 (bit 0) or the read/write request reception enable bits for broadcasts (bit 31) or nodes 62 (bit 30) to 32 (bit 0). 4.3.26 stream receive channel/nodeid selection 1 register 0 (0x098) the settings within the stream receive channel selection registers enable/disable isochronous channel reception when elis is set or enable/disable dma space read/write requests from other nodes when endmas is set . chsello channel select lo [31:0] default: 0 rw this ?ld contains the reception enable bits for stream channels 31 (bit 31) to 0 (bit 0) or the read/write request reception enable bits for nodes 31 (bit 31) to 0 (bit 0). 4.3.27 stream receive channel header register 0 (0x09c) this register contains the received information in the header quadlet of a stream packet (tcode equals 0xa isoch or async). 31 16 channel select lo 15 0 channel select lo 31 16 isodatalen 15 14 13 8 7 6 4 3 0 tag channelno res speed syn
1394 registers 4-45 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. isodatalen iso packet data length [31:16] default: 0 ro this ?ld indicates the number of data bytes in the current packet. transmission of zero data length packets are not supported. tag tag [15:14] default: 0 ro this ?ld contains the tag of the stream packet. channelno channel number [13:8] default: 0 ro this ?ld contains the channel number of the stream packet. res reserved 7 this bit is reserved for future use. it must be written as zero. speed speed [6:4] default: 0 ro this ?ld contains the speed at which the current packet was received as shown in the following table. syn sync [3:0] default: 0 ro this ?ld is the sync ?ld of the stream packet. 4.3.28 stream transmit channel header register 0 (0x0a0) this register contains the information in the header quadlet of a stream packet (tcode equals 0xa isoch or async). this information is used for stream transmits only if the embedded header bit is not enabled (otherwise the header information is obtained from the dbuf). this register is used for single stream transmit mode in which the dbuf contains isochronous transmit format 1 or 2 information to be transmitted. the speed ?ld generates speed bits when sending an lreq on the phy/link interface. speed[25:27] encoding 000 s100 speed 010 s200 speed 100 s400 speed
4-46 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. isodatalen iso packet data length [31:16] default: 0 rw this ?ld indicates the number of data bytes in the current packet. this device does not support transmission of zero data length packets. tag tag [15:14] default: 0 rw this ?ld contains the tag of the stream packet. channelno channel number [13:8] default: 0 rw this ?ld contains the channel number of the stream packet. res reserved 7 this bit is reserved for future use. it must be written as zero. speed speed [6:4] default: 0 rw this ?ld contains the speed at which the current isochronous packet has to be transmitted. syn sync [3:0] default: 0 rw this ?ld is the sync ?ld of the stream packet. 31 16 isodatalen 15 14 13 8 7 6 4 3 0 tag channelno res speed syn speed[25:27] encoding 000 s100 speed 010 s200 speed 100 s400 speed
1394 registers 4-47 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.29 data transfer control register 0 (0x0a4) this register contains information used in the transfer of packets. this information is used for outbound 1394 dbuf transfers only. res reserved [31:29] these bits are reserved for future use. they must be written as zeros. dfill dbuf threshold fill trigger [28:16] default: 0 rw the number of bytes in the dbuf transmit fifo must be greater than this value before a stream request is made. when in isochronous talk mode, if the dbuf transmit fifo level is not greater than this value, an empty cip packet is sent if gencip is set. no isochronous packet is sent in isochronous talk mode if gencip is not set and the dbuf transmit fifo level is not greater than this value. this ?ld is useful when the stream packet size or sum of simultaneous isochronous streams is greater than the fifo size, and it is known that the sustained dma data rate is suf?ient to prevent under?w once transmission starts. when the ecq bit is set, dfill must be programmed no higher than the total number of bytes to be read from the fifo per isochronous phase less ?e bytes. pbcnt packet/byte count [15:0] default: 0 rw this ?ld can be written with the desired packet/byte transmit count before enabling pht transfers. this ?ld is decremented after each packet transmission (when epcnt or ebcnt is set). when the ?ld reaches zero, the pbcntr interrupt is set and transfers stop. 31 29 28 16 res dfill 15 0 pbcnt
4-48 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.30 cip header transmit 0 register 0 (0x0a8) this register contains information used in the isochronous transfer of an iec-61883 format packet. this information is used for transfers from the dbuf only. this register must not be written while etalk is one. this register is not affected by phtrst. res reserved [31:29], [9:8] these bits are reserved and read as zeros. nsp number of source packets [28:24] default: 1 rw this ?ld speci?s the number of source packets transmitted when a nonempty cip packet is sent (used to control dbc ?ld incrementing). this value should be consistent with the isodatalen ?ld of the stream transmit control header register (for example, if ve 188-byte mpeg + 4-byte time stamp (core generated source packet header) packets are to be transmitted in one 1394 packet, then nsp should be 5 and isodatalen should be 5 x (4 + 188) + 8 = 968. nsp must be one or more. dbs data block size [23:16] default: 0 rw this ?ld contains the data block size in quadlets. 31 29 28 24 23 16 res nsp dbs 15 14 13 11 10 9 8 7 0 fn qpc sph res dbc
1394 registers 4-49 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. fn fraction number [15:14] default: 0 rw this ?ld contains the number of data blocks into which a source packet is divided. qpc quadlet padding count [13:11] default: 0 rw this ?ld contains the number of dummy quadlets padded to a source packet by the application to equalize the size of divided data blocks. sph source packet header 10 default: 0 rw a value of one on this bit indicates that the source packet has its own header. dbc data block counter [7:0] default: 0 ro this ?ld contains the continuity counter of data blocks to detect a loss of data blocks. the counter value for the ?st data block in a 1394 packet is shown in this ?ld. 4.3.31 cip header transmit 1 register 0 (0x0ac) this register contains information used in the transfer of a iec-61883 format packet. this information is used for transfers to the dbuf only. this register must not be written while etalk is one. this register is not affected by phtrst. fn description 0b00 not divided (for example, dvcr). the dbc lsb increments after every nonempty cip packet transmission. 0b11 1/8 source packet (for example, mpeg). the three lsbs of dbc are always 0b000 because an integer multiple of source packets is transmitted or an empty cip per cycle occurs. 31 30 29 24 23 16 res fmt fdf 15 0 syt
4-50 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. res reserved [31:30] these bits are reserved and read as zeros. fmt format id [29:24] default: 0 rw the value for this ?ld is application dependent. fdf format dependent field [23:16] default: 0 rw this ?ld is de?ed for each format. syt synchronization time field [15:0] default: 0 rw for dvcr format, the transmitted version of this ?ld is sometimes replaced with a pht-module-generated time stamp of the frame synchronization pulse. for mpeg2 format, this ?ld should be 0x0000. 4.3.32 stream transmit time stamp offset register 0 (0x0b4) this register contains the time stamp offset used for transmitting a packet with an isochronous header tag ?ld of 0b01, if the gts bit is set. this register is not affected by phtrst. sytc syt carry 31 when this bit is set, a carry occurred between the cycle offset and cycle count ?ld when generating syt time stamps (see the de?ition of the tsoff ?ld below). fmt description 0x00 (dvcr) if the most-signi?ant bit (bit 2) is a 0, it indicates that a time stamp may be generated by the pht module in the transmitted syt ?ld (such as dvcr format). 0x20 (mpeg) if the most-signi?ant bit (bit 2) is a 1, the bits in the syt ?ld are always transmitted unmodi?d (used for mpeg format). 31 30 29 28 16 sytc res sps 15 0 tsoff
1394 registers 4-51 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. res reserved [30:29] these bits are reserved for future use. they must be written as zeros. sps source packet size [28:16] this ?ld contains the size in bytes of a source packet less any source packet header. for example, in the case of mpeg2 transport stream packets, the appropriate value is 188 bytes. this ?ld is only used when transmitting iec-61883 format streams. tsoff time stamp offset [15:0] default: 0 rw this ?ld contains the time stamp offset added to the cycle time register to produce the time stamp. for syt time stamps (when the sytc bit of the pht control and status register is zero), bits [11:0] are added to the cycle_offset ?ld 1 and bits [15:12] are added to the four lsbs of the cycle_count ?ld to produce the time stamp. for syt time stamps (when the sytc bit of the pht control and status register is one), bits [11:0] are added to the cycle_offset ?ld 2 and bits [15:12] are added to the four lsbs of the cycle_count ?ld to produce the time stamp. for sph time stamps, bits [11:0] are added to the cycle_offset ?ld of the cycle timer. if the result is greater than 3071, the resulting sph cycle offset value transmitted is (cycle offset sum ? 3072). a carry of one is made to the addition of bits [15:12] and the cycle count ?ld of the cycle timer. if the sum of bits [15:12], the cycle count ?ld of the cycle timer, and the carry (if any) is greater than 7999, then the resulting sph cycle count value is (cycle count sum ? 8000). the cycle offset portion (bits [11:0]) of tsoff must not be programmed with a value greater than 3071. 1. there is no carry to the next signi?ant nibble of the time stamp, and the result is limited to 0xbff (any addition that would result in a value greater than 0xbff does not wrap to zero - the result is 0xbff). 2. carry to the next signi?ant nibble of the time stamp (any addition that would result in a value greater than 0xbff does wrap around).
4-52 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.33 dma control and status register 0 (0x0b8) the settings within the dma control register enable/disable various functions of the 1394 slave dma module. all bits in this register can be read and written from the application interface. res reserved [31:21], [15:1] these bits are reserved for future use. they must be written as zeros. lfirst least signi?ant first 20 default: 0 rw data is processed on a quadlet basis within the device. if this bit is not set, then on an 8-bit wide dma interface, the ?st byte output/input from/to the device is the most signi?ant byte. if the least signi?ant byte is output/input ?st, this bit must be set. similarly, on a 16-bit interface, the ?st two bytes output/input from/to the device are the two most-signi?ant bytes, if this bit is not set. den dma enable 19 default: 0 rw when this bit is set, the dma interface is enabled. dwidth dma width [18:17] default: 0b10 rw the following table lists the encoding for this ?ld. 31 21 20 19 18 17 16 res lfirst den dwidth ractl 15 10 res dact dwidth description 00 8-bit interface 01 16-bit interface 10 32-bit interface 11 reserved value
1394 registers 4-53 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. ractl request acknowledge control 16 default: 1 rw when this bit is cleared, all dma transfers use the dint0_dreqp and dmac0_dackp signals. when this bit is set, all packets read from the dbuf use dint0_dreqp and dmac0_dackp while packets written to the dbuf use dint0_dreqwp and dmac0_dackwp. dact dma active 0 default: 0 ro when this bit is set, the dma interface is active (due to data to be read by external controller or data needed to be written from external controller). 4.3.34 dma transfer threshold register 0 (0x0bc) this register contains information used in the transfer of packets. this information is used to control dma transfers. res reserved [31:29], [15:13] these bits are reserved for future use. they must be written as zeros. rdlvl read level [28:16] default: 0 rw the number of bytes in the dbuf receive fifo must be greater than this value before the appropriate dint_dreqp signal is asserted to notify the external dma controller to read the fifo. wrlvl write level [12:0] default: 0 rw the number of bytes empty in the dbuf transmit fifo must be greater than this value before the appropriate dint_dreqp signal is asserted to notify the external dma controller to write the fifo. 31 29 28 16 res rdlvl 15 13 12 0 res wrlvl
4-54 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.35 dbuf fifos level register 0 (0x0c0) this register contains the number of bytes in the dbuf fifos. drrst dbuf receive fifo reset 31 default: 0 rw when set, this bit clears the dbuf receive fifo pointers. this bit automatically clears itself. res reserved [30:29], [14:13] these bits are reserved for future use. they must be written as zeros. rcvlvl receive level [28:16] default: 0 ro this ?ld contains the number of bytes in the dbuf receive fifo. dxrst dbuf transmit fifo reset 15 default: 0 rw when set, this bit clears the dbuf transmit fifo pointers. this bit automatically clears itself. xmitlvl transmit level [12:0] default: 0 ro this ?ld indicates the number of bytes in the dbuf transmit fifo. 4.3.36 dbuf tx data register 0 (0x0c4) when the dma interface is disabled, the software writes to this register in order to perform writes to the tx dbuf fifo. the software uses this register to directly place data in the tx dbuf, which the pht can then transmit. 31 30 29 28 16 drrst res rcvlvl 15 14 13 12 0 dxrst res xmtlvl
1394 registers 4-55 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dmatfdata dma transmit fifo data [31:0] default: none wo this ?ld contains the data value to be written to the tx dbuf fifo. 4.3.37 dbuf rx data register 0 (0x0c8) when the dma interface is disabled, the software reads from this register in order to perform reads from the rx dbuf fifo. the software uses this register to directly read data that the pht has received. dmarfdata dma receive fifo data [31:0] default: none ro this ?ld contains the data value that is read from the rx dbuf fifo. 31 16 dmatfdata 15 0 dmatfdata 31 16 dmarfdata 15 0 dmarfdata
4-56 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.38 dbuf fifos watermark level register 0 (0x0cc) this register contains the highest number of bytes in the dbuf fifos. rcvmen dbuf receive fifo watermark enable 31 default: 0 rw when this bit is cleared, the rcvmrk ?ld is reset to 0. when this bit is set, the rcvmrk ?ld records the highest level of the receive fifo. res reserved [30:29], [14:13] these bits are reserved for future use. they must be written as zeros. rcvmrk receive watermark level [28:16] default: 0 ro this ?ld contains the highest number of bytes in the dbuf receive fifo since rcvmen was set. xmtmen dbuf transmit fifo watermark enable 15 default: 0 rw when this bit is cleared, the xmitmrk ?ld is reset to 0. when this bit is set, the xmitmrk ?ld records the highest level of the transmit fifo. xmitmrk transmit watermark level [12:0] default: 0 ro this ?ld indicates the highest number of bytes in the dbuf transmit fifo since xmtmen was set. 31 30 29 28 16 rcvmen res rcvmrk 15 14 13 12 0 xmtmen res xmtmrk
1394 registers 4-57 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.39 dbuf fifos size register 0 (0x0d0) this register contains the size in number of quadlets of the dbuf fifos. res reserved [31:27], [15:11] these bits are reserved for future use. they must be written as zeros. rcvsize receive dbuf size [26:16] default: based on the size inputs to the core at reset rw this ?ld contains the size in number of quadlets of the dbuf receive fifo. xmitsize transmit dbuf level [10:0] default: based on the size inputs to the core at reset rw this ?ld indicates the size in number of quadlets of the dbuf transmit fifo. 4.3.40 pht control and status register 1 (0x100) the settings within the pht control register enable/disable various functions of the 1394 packet header transformation module. all bits in this register can be read and written from the application interface. program all pht con?uration bits in other registers before enabling one of (east, erreq, ewreq, endmas) or (elis and/or etalk). 31 27 26 16 res rcvsize 15 11 10 0 res xmtsize 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 east cch gts fssel strip ehdr ecq gen cip ihdr pht rst epcnt e talk elis er req ew req 15 14 13 12 11 10 9 8 7 4 3 0 ebcnt eri syts endmas res pstk prbr pact rcvdack rrcode
4-58 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. east enable asynchronous stream transmit 31 default: 0 rw when this bit is set, 1394 asynchronous stream packets (isochronous transmit format 1 packets sent during the asynchronous interval) are generated while epcnt is set and the pbcnt ?ld of the data transfer control register is not zero, and the threshold condition of the dfill ?ld of the data transfer control register has been met. when this bit is set, 1394 asynchronous stream packets are generated while epcnt is not set and the threshold condition of the dfill ?ld of the data transfer control register has been met. ewreq, erreq, endmas, and etalk must not be set when this bit is set. this bit is only sampled between transfers. if the prbr bit becomes set while this bit and the pact bit are set, the pact bit is cleared and the pstk bit is set because the channel number must be reallocated. cch check cip header 30 default: 0 rw when this bit is set, received isochronous packets are checked to determine if the eoh and form bits of the cip header conform to the two-quadlet cip header format. if the packet does not conform, the ciphe interrupt is set. gts generate time stamp 29 default: 0 rw when this bit, gencip, and etalk are set, a time stamp is generated and included in the transmitted packet. the most-signi?ant bit of the fmt ?ld of the cip header transmit 1 register determines whether there is a syt time stamp. the sph bit of the cip header transmit 0 register determines if there is a source packet header time stamp. fssel frame sync select 28 default: 0 rw when this bit is set, the fsyncin input signal is used to control time stamping when gencip and the most-signi?ant bit of the fmt ?ld of the stream control transmit 1 register are 0s (for example, dvcr). the fsyncin input must be asserted during the ?st write strobe of a packet in which the core generates an syt time stamp. if this bit is not set and syt time stamping
1394 registers 4-59 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. is desired, the ecq bit must be set to enable the alternative method (syt time stamping occurs for each packet whose frame start bit is set in the application prepended embedded control quadlet). strip strip cip header [27:26] default: 0 rw this ?ld controls how cip headers are handled when listening to an isochronous channel. ehdr embedded header 25 default: 0 rw when this bit is set, the header of the packet (as shown in isochronous transmit format 3 or the read response for block data packet transmit format) must be prepended to the data ?ld of a packet to be transmitted. the header registers are not used. for unformatted isochronous data ?lds (tag = 0 in header), multichannel talk capability is supported. when this bit is set and etalk is set, ecq also must be set. the embedded control quadlet is needed to determine the speed of transmission of the packet. ecq embedded control quadlet 24 default: 0 rw when this bit is set, a control quadlet must be prepended to the data ?ld of an isochronous packet to be transmitted (the control quadlet enables software-controlled frame synchronization and hardware-assisted isochronous data ?w control (useful for dv frame rate transmission control). when gencip is set in addition to this bit and the cycle skip ?ld of the embedded control quadlet is n, n empty cip packets are transmitted before the packet containing the data_?ld strip description 00 unchanged. 01 strip all cip headers (also subtract 8 bytes from data packet length in received isochronous header sent to dbuf) 10 strip only empty cips (if ihdr is set, when an empty cip is encountered the header is not written to the dbuf) 11 reserved.
4-60 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. after the embedded control quadlet. in addition, for unformatted data ?lds (tag = 0), multichannel talk capability is supported if this bit is set in addition to the ehdr bit. gencip generate cip header 23 default: 0 rw when this bit is set, a cip header is prepended to the data ?ld of each isochronous packet transmitted. this bit must not be set when talking on more than one isochronous channel. if this bit is set, for each dma request assertion, the dma controller must write less than or equal to the number of source packets transmitted in a 1394 payload. ihdr include header 22 default: 0 rw when this bit is set, the header is written to the dbuf fifo in addition to the data ?ld of the 1394 packet (useful when listening to more than one isochronous channel or dma space requests enabled). phtrst pht reset 21 default: 0 rw if the pht becomes stuck, this bit must be set. this bit automatically clears itself. epcnt enable packet counter 20 default: 0 rw when this bit is set, pht packet transmissions stop when the pbcnt ?ld of the data transfer control register is decremented to zero. if neither this bit nor ebcnt is set and either erreq, ewreq, etalk, or east is set, 1394 packets are transmitted inde?itely. ebcnt and epcnt must not be set at the same time. etalk enable isochronous talk 19 default: 0 rw when this bit is set, isochronous packets are transmitted. east, erreq, endmas, and ewreq must not be set when this bit is set. when generating cips, set etalk before setting den (dma enable) in the dma status and control register. this bit is only sampled between transfers.
1394 registers 4-61 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. elis enable isochronous listen 18 default: 0 rw when this bit is set, isochronous packets transmitted on channels enabled in the stream receive channel selection registers are received. erreq and ewreq must not be set when this bit is set. this bit is only sampled between transfers. erreq enable read requests 17 default: 0 rw when this bit is set, 1394 read requests are generated while epcnt or ebcnt is set and the pbcnt ?ld of the data transfer control register is not zero. if this bit is set, 1394 read requests are generated inde?itely while neither epcnt nor ebcnt is set and the dbuf receive fifo has enough space to accept another response. east, ewreq, etalk, endmas, and elis must not be set when this bit is set. this bit is only sampled between transfers. if the prbr bit becomes set while this bit and the pact bit are set, the pact bit is cleared and the pstk bit is set because the node ids might have changed. ewreq enable write requests 16 default: 0 rw when this bit is set, 1394 write requests are generated while epcnt or ebcnt is set and the pbcnt ?ld of the data transfer control register is not zero. if this bit is set, 1394 write requests are generated inde?itely while neither epcnt nor ebcnt is set. east, erreq, etalk, endmas, and elis must not be set when this bit is set. this bit is only sampled between transfers. if the prbr bit becomes set while this bit and the pact bit are set, the pact bit is cleared and the pstk bit is set because the node ids might have changed. ebcnt enable byte count 15 default: 0 rw if this bit is set, asynchronous pht packet transmissions will stop when the pbcnt ?ld of the data transfer control register is decremented to zero. the data length ?ld of the transmitted 1394 header of the last packet transferred is adjusted appropriately if the pbcnt ?ld is not divisible by the programmed data length. if neither this bit nor epcnt is set and either erreq or ewreq is set, 1394 packets are transmitted inde?itely. both ebcnt and
4-62 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. epcnt must not be set. this bit must not be set when etalk or east is set. eri enable request interval 14 default: 0 rw if this bit and ewreq or erreq are set, the value programmed in the rqintrvl ?ld determines the time interval between consecutive pht requests as measured from the reception of an ack or response packet of ?omplete or ?usy for the ?st packet. syts syt start 13 default: 0 rw if this bit is set, incoming cip format isochronous packets are not written to the dbuf until a packet containing a syt time stamp is received (indicating the start of a frame). endmas enable dma space 12 default: 0 rw when this bit is set, automatic handling of received read and write requests is enabled. a received request packet whose quadlet aligned address matches the dmar ?ld criteria is handled automatically by the pht. east, erreq, etalk, ewreq, and elis must not be set when this bit is set. this bit is only sampled between transfers. if the prbr bit becomes set while this bit and the pact bit are set, the pact bit is cleared and the pstk bit is set because the node ids might have changed. automatic handling of read and write requests occurs when the endmas bit is set, an incoming request packet's quadlet aligned address matches the dmar ?ld criteria, and the incoming request packet's source node id corresponds to a selected node for the pht (the corresponding bit in the stream receive channel/nodeid selection registers is set). the ehdr and ihdr bits in pht control and status register 0 affect the format of the data written to the dbuf transmit and receive fifos when endmas is asserted. if ihdr is not set, only the data ?ld portion of the incoming request is written to the dbuf receive fifo. if ihdr is set and ehdr is not set, the 1394 header is written to the dbuf receive fifo in addition to the data ?ld. if ihdr and ehdr are set, in addition to the
1394 registers 4-63 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 1394 header and data ?ld, a quadlet containing the speed of the received request is written to the dbuf receive fifo. note: if ehdr is set, special care must be taken to guarantee that all response packets have been sent prior to disabling endmas. one possibility would be to ?st clear the nodeid selection registers to disable further acceptance of incoming requests by the pht. when it is determined that all previously accepted requests have been processed, endmas can be safely deasserted. note: if ihdr and ehdr are set, the format of the data in the dbuf is as shown in figure 2.13 (write request for data block receive format). the maximum data ?ld size that can be received is the dbuf receive fifo size less 20 bytes. if ehdr is not set, the dbuf transmit fifo must contain only the data ?ld for read response packets to be sent in response to received read requests. if ehdr is set, the format followed is that in figure 2.4 or figure 2.7 . an appropriate setting for ehdr and ihdr depends on the capability of the external dma controller. res reserved 11 this bit is reserved and must be written as zero. pstk pht module stuck 10 default: 0 ro when this bit is set, software must set the phtrst bit to reinitialize the module. prbr pht received bus reset 9 default: 0 ro this bit is set when the pact bit was set and a bus reset was detected. pact pht active 8 default: 0 ro this bit is automatically set when the pht module is not in the idle or stuck state with the exception that if both etalk and elis are set and the pht transmitter becomes stuck, the pact bit remains set because the pht receiver never becomes stuck.
4-64 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. rcvdack received acknowledge [7:4] default: 0xf ro this ?ld contains the ack code received for the last packet transmitted. it is initialized to 0xf when a request for transmission is made. rrcode received response code [3:0] default: 0xf ro this ?ld contains the rcode in the last response packet received because of a request packet transmitted. it is initialized to 0xf when a request for transmission is made. 4.3.41 pht split time-out/empty cip interval register 1 (0x104) when erreq or ewreq is set, this register contains the maximum time allowed from reception of an ack pending in reply to a request initiated by the pht block until a response to that request is received. application software is responsible for split time-out detection for packets transmitted using the utf fifo. this detection can be done using the cycst and ackrcvd interrupts. dst disable split time-out 31 when this bit is set, the time limit ?ld is ignored and there is no hardware time-out. it can be useful to set this bit when it is known the destination node is not on the local 1394 bus. in such a bridged environment the remote split time-out can be known to be longer than the maximum value that the timelimit ?ld can be programmed to and time-out detection must be handled by other means. res reserved [30:16] these bits are reserved for future use. they must be written as zeros. 31 30 16 dst res 15 0 timelimit
1394 registers 4-65 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. timelimit time limit [15:0] default: 0x0000 rw bits [16:18] correspond to seconds. bits [19:31] correspond to fractional seconds with a 125 s resolution (equivalent resolution to the cycle count ?ld of the cycle timer register). when etalk is set, this register is de?ed as follows. eecipo enable empty cip override 31 default: 0 rw when this bit, gencip, and etalk, etc. are set, an empty cip packet is sent during the isochronous cycle subsequent to each time an internal counter increments to the same value as the ecipi ?ld. epfs enable programmable frame synchronization 30 default: 0 rw when this bit, gencip, etalk, etc. are set, an syt time stamp is generated for the ?st nonempty cip packet transmitted and every n + 1 nonempty cip packets transmitted thereafter, where n is the value of the ppf ?ld. ppf packets per frame [29:21] default: 0 rw this ?ld is only used when the epfs bit is set and must be programmed with the number of packets per frame minus one (for example, for a 525-60 system, the value is 249 decimal). res reserved 20 this bit is reserved for future use. they must be written as zeros. 31 30 29 21 20 19 16 eecipo epfs ppf res ecipi 15 0 ecipi
4-66 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. ecipi empty cip interval [19:0] default: 0 rw this ?ld is compared against an internal counter that increments every other sclk (49.152 mhz clock) from the phy. the counter is reset to zero when a match occurs. 4.3.42 pht request/response/cip receive header 0 register 1 (0x108) this register contains information used in the transfer of: ? a request packet if erreq or ewreq is set ? a response packet if endmas is set, or ? a received isochronous packet if elis is set. this information is used for transfers to/from the dbuf only. if erreq or ewreq is set, the register is de?ed as follows. did destination id [31:16] default: 0 rw this ?ld is the concatenation of the bus id and the node id of the destination. the broadcast node id of 0b111111 is not supported. doffhi destination offset hi [15:0] default: 0 rw this ?ld contains the most-signi?ant 16 bits of the destination offset address. this ?ld must not be programmed with a value that would result in an over?w when this ?ld is automatically updated during multipacket transmission. 31 16 destination id 15 0 destination offset hi
1394 registers 4-67 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. if endmas is set, the de?ition is as follows (note that if ehdr is not set, the contents of this register do not always re?ct the last request received and must not be relied on for that purpose). destid destination id [31:16] default: 0x0000 rw this ?ld is the concatenation of the bus id and the node id of the node that initiated the dma space request. dlen data length [15:0] default: 0 rw this ?ld contains the data length in bytes of the received dma space request, which is reused if a read response is generated. when elis is set, this register is de?ed as follows. eoh0 end of cip header 0 31 default: 0 ro a value of 0 means another header quadlet will follow (always zero for a standard two-quadlet cip). form0 form 0 30 default: 0 ro this ?ld is always zero for a standard two-quadlet cip. sid source id [29:24] default: 0 ro this ?ld contains the node id of transmitter. 31 16 destid 15 0 dlen 31 30 29 24 23 16 eoh0 form0 sid dbs 15 14 13 11 10 9 8 7 0 fn qpc sph res dbc
4-68 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dbs data block size [23:16] default: 0 ro this ?ld contains the data block size in quadlets. fn fraction number [15:14] default: 0 ro this ?ld contains the number of data blocks into which a source packet is divided. qpc quadlet padding count [13:11] default: 0 ro this ?ld contains the number of dummy quadlets padded to a source packet to equalize the size of divided data blocks. sph source packet header 10 default: 0 ro a value of one on this bit indicates that the source packet has its own header. res reserved [9:8] these bits are reserved for future use. dbc data block counter [7:0] default: 0 ro this ?ld contains the continuity counter of data blocks to detect a loss of data blocks. the counter value for the ?st data block in a bus packet is shown in this ?ld. 4.3.43 pht request/response/cip receive header 1 register 1 (0x10c) this register contains information used in the transfer of: ? a request packet (if erreq or ewreq is set), ? a response packet (if endmas is set), or ? a received isochronous packet (if elis is set). this information is used for transfers to/from the dbuf only. when erreq or ewreq is set, this register is de?ed as follows.
1394 registers 4-69 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dofflo destination offset lo [31:0] default: 0 rw this ?ld contains the least-signi?ant 32 bits of the destination offset address. if endmas is set, this register is de?ed as follows (note that if ehdr is not set, the contents of this register do not always re?ct the last request received and must not be relied on for that purpose). res reserved [31:23] these bits are reserved for future use. they must be writ- ten as zeros. tcode transaction code [22:19] default: 0 rw this ?ld contains the transaction code of the dma space read or write request. speed speed [18:16] default: 0 rw this ?ld contains the transmit speed of the dma space read or write request. 31 16 destination offset lo 15 0 destination offset lo 31 23 22 19 18 16 res tcode speed 15 6 5 0 rcvdbusid tl speed[13:15] encoding 000 s100 speed 010 s200 speed 100 s400 speed
4-70 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. rcvdbusid received bus id [15:6] default: 0 rw this ?ld contains the destination bus id used in a dma space read request. this value is used as the source bus id in the read response. tl transaction label [5:0] default: 0x0000 rw this ?ld contains the transaction label of the received dma space read or write request. when elis is set, this register is de?ed as follows. eoh1 end of cip header 1 31 default: 0 ro a value of one on this bit means another header quadlet does not follow (must always be one for standard 2-quadlet cip). form1 form 1 30 default: 0 ro this bit must always be zero for a standard 2-quadlet cip. fmt format id [29:24] default: 0 ro the encoding for this ?ld is shown in the table below. fdf format dependent field [23:16] default: 0 ro this ?ld is de?ed for each format. 31 30 29 24 23 16 eoh1 form1 fmt fdf 15 0 syt fmt description 0x00 when the msb (bit 2) is zero, a time stamp might be in the syt ?ld (such as in the dvcr format). 0x20 when the msb (bit 2) is one, a time stamp is not in the syt ?ld (such as in the mpeg format).
1394 registers 4-71 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. syt synchronization time field [15:0] default: 0 ro for dvcr, this ?ld can contain a time stamp of the frame synchronization pulse. for mpeg2, this ?ld is zero. 4.3.44 pht request header 2/stream sph receive register 1 (0x110) if erreq or ewreq is set, this register contains information used in the transfer of a request packet. this information is used for transfers to/from the dbuf only. res reserved [31:29] these bits are reserved for future use. rqintrvl request interval [28:25] this four-bit ?ld contains the minimum number of desired nominal 125 s cycles between reception of an ack or response of ?omplete or ?usy for a previous pht generated request and transmission of the next pht generated request. the actual observed time between any two requests can be as much as 125 s less than the programmed value (to guarantee at least 125 s interval, the programmed value must be two). tl transaction label [24:19] default: 0x0 rw these six bits indicate the transaction label for the packet. they are used for tracking requests with responses. pht module 0 must be programmed with 0x3f. pht module 1 must be programmed with 0x3e. 31 29 28 25 24 19 18 16 res rqintrvl tl speed 15 0 dlen
4-72 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. speed speed [18:16] default: 0 rw this ?ld contains the transmit speed of the dbuf read or write request as shown in the following table. dlen data length [15:0] default: 0 rw this ?ld contains the data length in bytes of the payload to be written or read. after an ack or rcode of ?omplete is received in response to a transmitted request, the destination offset ?ld of the pht request header register is updated with the addition of the data length ?ld. when elis is set, the register is de?ed as follows. this register contains the time stamp from the last received packet with an isochronous header tag ?ld of 0b01 and a cip header sph bit of 0b1. res reserved [31:25] these bits are reserved for future use. they must be written as zeros. tstmp time stamp [24:0] default: 0 rw this ?ld contains the time stamp of the packet. speed[13:15] encoding 000 s100 speed 010 s200 speed 100 s400 speed 31 25 24 16 res tstmp 15 0 tstmp
1394 registers 4-73 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.45 stream receive channel/nodeid selection 0 register 1 (0x114) the settings within the stream receive channel selection registers enable/disable isochronous channel reception when elis is set or enable/disable dma space read/write requests from other nodes when endmas is set. chselhi channel select hi [31:0] default: 0 rw this ?ld contains the reception enable bits for stream channels 63 (bit 31) to 32 (bit 0) or the read/write request reception enable bits for broadcasts (bit 31) or nodes 62 (bit 30) to 32 (bit 0). 4.3.46 stream receive channel/nodeid selection 1 register 1 (0x118) the settings within the stream receive channel selection registers enable/disable isochronous channel reception when elis is set or enable/disable dma space read/write requests from other nodes when endmas is set. chsello channel select lo [31:0] default: 0 rw this ?ld contains the reception enable bits for stream channels 31 (bit 31) to 0 (bit 0) or the read/write request reception enable bits for nodes 31 (bit 31) to 0 (bit 0). 31 16 channel select hi 15 0 channel select hi 31 16 channel select lo 15 0 channel select lo
4-74 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.47 stream receive channel header register 1 (0x11c) this register contains the received information in the header quadlet of a stream packet (tcode equals 0xa isoch or async). isodatalen iso packet data length [31:16] default: 0 ro this ?ld indicates the number of data bytes in the cur- rent packet. transmission of zero data length packets is not supported. tag tag [15:14] default: 0 ro this ?ld contains the tag of the stream packet. channelno channel number [13:8] default: 0 ro this ?ld contains the channel number of the stream packet. res reserved 7 this bit is reserved for future use. it must be written as zero. speed speed [6:4] default: 0 ro this ?ld contains the speed at which the current packet was received. syn sync [3:0] default: 0 ro this ?ld is the sync ?ld of the stream packet. 31 16 isodatalen 15 14 13 8 7 6 4 3 0 tag channelno res speed syn speed[25:27] encoding 000 s100 speed 010 s200 speed 100 s400 speed
1394 registers 4-75 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.48 stream transmit channel header register 1 (0x120) this register contains the information in the header quadlet of a stream packet (tcode equals 0xa isoch or async). this information is used for stream transmits only if the embedded header bit is not enabled (otherwise the header information is obtained from the dbuf). this register is used for single stream transmit mode in which the dbuf contains isochronous transmit format 1 or 2 information to be transmitted. the speed ?ld generates speed bits when sending an lreq on the phy/link interface. isodatalen iso packet data length [31:16] default: 0 rw this ?ld indicates the number of data bytes in the current packet. tag tag [15:14] default: 0 rw this ?ld contains the tag of the stream packet. channelno channel number [13:8] default: 0 rw this ?ld contains the channel number of the stream packet. res reserved 7 this bit is reserved for future use. it must be written as zero. 31 16 isodatalen 15 14 13 8 7 6 4 3 0 tag channelno res speed syn
4-76 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. speed speed [6:4] default: 0 rw this ?ld contains the speed at which the current isochronous packet has to be transmitted. syn sync [3:0] default: 0 rw this ?ld is the sync ?ld of the stream packet. 4.3.49 data transfer control register 1 (0x124) this register contains information used in the transfer of packets. this information is used for outbound 1394 dbuf transfers only. res reserved [31:29] these bits are reserved for future use. they must be written as zeros. dfill dbuf threshold fill trigger [28:16] default: 0 rw the number of bytes in the dbuf transmit fifo must be greater than this value before a stream request is made. when in isochronous talk mode, if the dbuf transmit fifo level is not greater than this value, an empty cip packet is sent if gencip is set. no isochronous packet is sent in isochronous talk mode if gencip is not set and the dbuf transmit fifo level is not greater than this value. this ?ld is useful when the stream packet size or sum of simultaneous isochronous streams is greater than the fifo size and it is known that the sustained dma data rate is suf?ient to prevent under?w once speed[25:27] encoding 000 s100 speed 010 s200 speed 100 s400 speed 31 29 28 16 res dfill 15 0 pbcnt
1394 registers 4-77 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. transmission starts. when the ecq bit is set, dfill must be programmed no higher than the total number of bytes to be read from the fifo per isochronous phase less ?e bytes. pbcnt packet/byte count [15:0] default: 0 rw this ?ld can be written with the desired packet/byte transmit count before enabling pht transfers. this ?ld is decremented after each packet transmission (when epcnt or ebcnt is set). when the ?ld reaches zero, the pbcntr interrupt is set and transfers stop. 4.3.50 cip header transmit 0 register 1 (0x128) this register contains information used in the isochronous transfer of an iec-61883 format packet. this information is used for transfers from the dbuf only. this register must not be written while etalk is one. this register is not affected by phtrst. res reserved [31:29], [9:8] these bits are reserved and read as zeros. nsp number of source packets [28:24] default: 1 rw this ?ld speci?s the number of source packets transmitted when a nonempty cip packet is sent (used to control dbc ?ld incrementing). this value must be consistent with the isodatalen ?ld of the stream transmit control header register (for example, if ve 188-byte mpeg + four-byte time stamp (core generated source packet header) packets are to be transmitted in one 1394 packet, then nsp should be ?e and isodatalen should be 5 x (4 + 188) + 8 = 968. nsp must be one or more. 31 29 28 24 23 16 res nsp dbs 15 14 13 11 10 9 8 7 0 fn qpc sph res dbc
4-78 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dbs data block size [23:16] default: 0 rw this ?ld contains the data block size in quadlets. fn fraction number [15:14] default: 0 rw this ?ld contains the number of data blocks into which a source packet is divided. qpc quadlet padding count [13:11] default: 0 rw this ?ld contains the number of dummy quadlets padded to a source packet by the application to equalize the size of divided data blocks. sph source packet header 10 default: 0 rw a value of one on this bit indicates that the source packet has its own header. dbc data block counter [7:0] default: 0 ro this ?ld contains the continuity counter of data blocks to detect a loss of data blocks. the counter value for the ?st data block in a 1394 packet is shown in this ?ld. 4.3.51 cip header transmit 1 register 1 (0x12c) this register contains information used in the transfer of a iec-61883 format packet. this information is used for transfers to the dbuf only. this register must not be written while etalk is one. this register is not affected by phtrst. fn description 0b00 not divided (for example, dvcr). the dbc lsb increments after every nonempty cip packet transmission. 0b11 1/8 source packet (for example, mpeg). the three lsbs of dbc are always 0b000 because an integer multiple of source packets is transmitted or an empty cip per cycle occurred.
1394 registers 4-79 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. res reserved [31:30] these bits are reserved and read as zeros. fmt format id [29:24] default: 0 rw the appropriate value for this ?ld is application dependent. fdf format dependent field [23:16] default: 0 rw this ?ld is de?ed for each format. syt synchronization time field [15:0] default: 0 rw for dvcr format, the transmitted version of this ?ld is sometimes replaced with a pht-module-generated time stamp of the frame synchronization pulse. for mpeg2 format, this ?ld is 0x0000. 4.3.52 stream transmit time stamp offset register 1 (0x134) this register contains the time stamp offset used for transmitting a packet with an isochronous header tag ?ld of 0b01, if the gts bit is set. this register is not affected by phtrst. 31 30 29 24 23 16 res fmt fdf 15 0 syt fmt description 0x00 (dvcr) if the most-signi?ant bit (bit 2) is a 0, it indicates that the pht module can generate a time stamp in the transmitted syt ?ld (such as dvcr format). 0x20 (mpeg) if the most-signi?ant bit (bit 2) is a 1, the bits in the syt ?ld are always transmitted unmodi?d (used for mpeg format).
4-80 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. sytc syt carry 31 when this bit is set, there is a carry between the cycle offset and cycle count ?ld when generating syt time stamps (see the de?ition of the tsoff ?ld below). res reserved [30:29] these bits are reserved for future use. they must be written as zeros. sps source packet size [28:16] this ?ld contains the size in bytes of a source packet less any source packet header. for example, in the case of mpeg2 transport stream packets, the appropriate value is 188 bytes. this ?ld is only used when transmitting iec-61883 format streams. tsoff time stamp offset [15:0] default: 0 rw this ?ld contains the time stamp offset added to the cycle time register to produce the time stamp. for syt time stamps (when the sytc bit of the pht control and status register is zero), bits [11:0] are added to the cycle_offset ?ld 1 and bits [15:12] are added to the four lsbs of the cycle_count ?ld to produce the time stamp. for syt time stamps (when the sytc bit of the pht control and status register is one), bits [11:0] are added to the cycle_offset ?ld 2 and bits [15:12] are added to the 31 30 29 28 16 sytc res sps 15 0 tsoff 1. there is no carry to the next signi?ant nibble of the time stamp, and the result is limited to 0xbff (any addition that would result in a value greater than 0xbff does not wrap to zero - the result is 0xbff). 2. carry to the next signi?ant nibble of the time stamp (any addition that would result in a value greater than 0xbff does wrap around).
1394 registers 4-81 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. four lsbs of the cycle_count ?ld to produce the time stamp. for sph time stamps, bits [11:0] are added to the cycle_offset ?ld of the cycle timer. if the result is greater than 3071, the resulting sph cycle offset value transmitted is (cycle offset sum ? 3072). a carry of one is made to the addition of bits [15:12] and the cycle count ?ld of the cycle timer. if the sum of bits [15:12], the cycle count ?ld of the cycle timer, and the carry (if any) is greater than 7999, then the resulting sph cycle count value is (cycle count sum ? 8000). the cycle offset portion (bits [11:0]) of tsoff must not be programmed with a value greater than 3071. 4.3.53 dma control and status register 1 (0x138) the settings within the dma control register enable/disable various functions of the 1394 slave dma module. all bits in this register can be read and written from the application interface. res reserved [31:21], [15:1] these bits are reserved for future use. they must be written as zeros. lfirst least signi?ant first 20 default: 0 rw data is processed on a quadlet basis within the device. if this bit is not set, then on an eight-bit wide dma interface, the ?st byte output/input from/to the device is the most-signi?ant byte. if the least-signi?ant byte is output/input ?st, this bit must be set. similarly on a 16-bit interface, the ?st two bytes output/input from/to the device are the two most-signi?ant bytes, if this bit is not set. 31 21 20 19 18 17 16 res lfirst den dwidth ractl 15 10 res dact
4-82 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. den dma enable 19 default: 0 rw when this bit is set, the dma interface is enabled. dwidth dma width [18:17] default: 0b10 rw the following table lists the encoding for this ?ld. ractl request acknowledge control 16 default: 1 rw when this bit is cleared, all dma transfers use the dint1_dreqp and dmac1_dackp signals. when this bit is set, all packets read from the dbuf use dint1_dreqp and dmac1_dackp while packets written to the dbuf use dint1_dreqwp and dmac1_dackwp. dact dma active 0 default: 0 ro when this bit is set, the dma interface is active (due to data to be read by external controller or data needed to be written from external controller). 4.3.54 dma transfer threshold register 1 (0x13c) this register contains information used in the transfer of packets. this information is used to control dma transfers. dwidth description 00 8-bit interface 01 16-bit interface 10 32-bit interface 11 reserved value 31 29 28 16 res rdlvl 15 13 12 0 res wrlvl
1394 registers 4-83 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. res reserved [31:29], [15:13] these bits are reserved for future use. they must be written as zeros. rdlvl read level [28:16] default: 0 rw the number of bytes in the dbuf receive fifo must be greater than this value before the appropriate dint_dreqp signal is asserted to notify the external dma controller to read the fifo. wrlvl write level [12:0] default: 0 rw the number of bytes empty in the dbuf transmit fifo must be greater than this value before the appropriate dint_dreqp signal is asserted to notify the external dma controller to write the fifo. 4.3.55 dbuf fifos level register 1 (0x140) this register contains the number of bytes in the dbuf fifos. drrst dbuf receive fifo reset 31 default: 0 rw when set, this bit clears the dbuf receive fifo pointers. this bit automatically clears itself. res reserved [30:29], [14:13] these bits are reserved for future use. they must be written as zeros. rcvlvl receive level [28:16] default: 0 ro this ?ld contains the number of bytes in the dbuf receive fifo. 31 30 29 28 16 drrst res rcvlvl 15 14 13 12 0 dxrst res xmtlvl
4-84 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dxrst dbuf transmit fifo reset 15 default: 0 rw when set, this bit clears the dbuf transmit fifo pointers. this bit automatically clears itself. xmitlvl transmit level [12:0] default: 0 ro this ?ld indicates the number of bytes in the dbuf transmit fifo. 4.3.56 dbuf tx data register 1 (0x144) when the dma interface is disabled, the software writes to this register in order to perform writes to the tx dbuf fifo. the software uses this register to directly place data in the tx dbuf, which the pht can then transmit. dmatfdata dma transmit fifo data [31:0] default: none wo this ?ld contains the data value to be written to the tx dbuf fifo. 4.3.57 dbuf rx data register 1 (0x148) when the dma interface is disabled, the software reads from this register in order to perform reads from the rx dbuf fifo. the software uses this register to directly read data that the pht has received. 31 16 dmatfdata 15 0 dmatfdata 31 16 dmarfdata 15 0 dmarfdata
1394 registers 4-85 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. dmarfdata dma receive fifo data [31:0] default: none ro this ?ld contains the data value that is read from the rx dbuf fifo. 4.3.58 dbuf fifos watermark level register 1 (0x14c) this register contains the highest number of bytes in the dbuf fifos. rcvmen dbuf receive fifo watermark enable 31 default: 0 rw when this bit is cleared, the rcvmrk ?ld is reset. when this bit is set, the rcvmrk ?ld records the highest level of the receive fifo. res reserved [30:29], [14:13] these bits are reserved for future use. they must be written as zeros. rcvmrk receive watermark level [28:16] default: 0 ro this ?ld contains the highest number of bytes in the dbuf receive fifo since rcvmen was set. xmtmen dbuf transmit fifo watermark enable 15 default: 0 rw when this bit is cleared, the xmitmrk ?ld is reset. when this bit is set, the xmitmrk ?ld records the highest level of the transmit fifo. xmitmrk transmit watermark level [12:0] default: 0 ro this ?ld indicates the highest number of bytes in the dbuf transmit fifo since xmtmen was set. 31 30 29 28 16 rcvmen res rcvmrk 15 14 13 12 0 xmtmen res xmtmrk
4-86 registers rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4.3.59 dbuf fifos size register 1 (0x150) this register contains the size in number of quadlets of the dbuf fifos. res reserved [31:27], [15:12] these bits are reserved for future use. they must be written as zeros. rcvsize receive dbuf size [26:16] default: based on the size inputs to the core at reset rw this ?ld contains the size in number of quadlets of the dbuf receive fifo. xmitsize transmit dbuf level [11:0] default: based on the size inputs to the core at reset rw this ?ld indicates the size in number of quadlets of the dbuf transmit fifo. 31 27 26 16 res rcvsize 15 12 11 0 res xmtsize
1394 node controller core technical manual 5-1 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. chapter 5 operation overview this chapter discusses the operation of the blocks within the 1394 node controller core through written descriptions and waveforms. this chapter contains the following sections: ? section 5.1, ?ink layer controller ? section 5.2, ?pplication interface module ? section 5.3, ?acket header transformation modules (phts) ? section 5.4, ?nterrupt mechanism 5.1 link layer controller the link layer controller contains the transmitter and receiver blocks, the retry mechanism, and the phy interface. this section describes the operation of these functions within the link layer controller module. 5.1.1 transmitter the transmitter block starts arbitrating for the bus as soon as the packet is con?med into the transmit fifo. once the phy grants the device controller, it will reformat the transmit packet as a 1394 data packet format and will start transmitting at the indicated speed. the transmitter also adds the header and data crcs to the packet. once the packet is transmitted, the transmitter will wait for the acknowledge packet. if the acknowledge packet is missing, it waits until it receives the subaction gap indication from the phy. once the acknowledge packet is received, the ack code and the packets transaction label are stored into the acknowledge status register. the device controller generates the ackrcvd interrupt.
5-2 operation overview rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. the core implements the single phase retry protocol. the retry code in the transmit packet is retry_x. the transmit fifo can hold the full transmit packet. depending on the acknowledge code received (for example, ack_busy), if the receiver is busy, then the transmitter retransmits the packet until the retry limit has been reached. if the receiver is still issuing the busy acknowledge after the retry limit has been reached, the transmitter discards the packet and sets the retex interrupt. no te: the application software architecture must ensure that the software request and response queues are managed to guarantee no deadlocks can occur (that is, the request and response queues must be processed independently of each other). 5.1.2 receiver the receiver block decodes the incoming packet for a valid tcode. the receiver block accepts all incoming packets if the destination id matches with local node id or if the incoming packet is a broadcast packet and automatically sends the corresponding acknowledgment. the receiver block accepts all incoming packets if the tcode of the packet matches with one of the following tcodes (see table 5.1 ). table 5.1 tcodes type of asynchronous packet tcode write request for quadlet data 0x0000 write request for block data 0x0001 read request for quadlet data 0x0100 read request for block data 0x0101 write response 0x0010 read response for quadlet data 0x0110 read response for block data 0x0111
link layer controller 5-3 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. the receiver block receives all the packets, if the destination id decode is successful in one of the following conditions: ? destination id ?ld of the incoming packet matches the local node id ? destination bus id ?ld of the incoming packet is 0x3ff and the physical id matches the local physical id ? destination id ?ld of the incoming packet is 0xffff ? destination physical id ?ld of the incoming packet is 0x3f and the destination bus id matches the local bus id the receiver sets the tcerr interrupt on the application interface if it decodes the destination id of the incoming packet and there is a tcode error detected (the incoming packet tcode does not match the ones listed above). in this case, the receiver just ignores the incoming packet. the receiver also checks for mismatches in the incoming packet crc and the calculated crc from the crc block. if the header crc mismatch occurs for the incoming packet, the receiver sets the hdrerr interrupt on the application interface. in this case, the receiver just ignores the incoming packet. the receiver block will not send any ack for these packets. in the packets for which a data crc mismatch occurs, the receiver discards the packet. it also sends the ack_data_error type acknowledgment in response to the discarded packet. once the tcode is valid and the destination id decoding is successful, the receiver formats the incoming packets into the application data packet formats and writes into the asynchronous receive fifos. the receiver will not con?m the packet into the fifo if the packet header is not received and decoded properly. once the packet is decoded properly with a header crc match, then the packet is con?med after the data payload crc is veri?d (note that the cycle start 0x1010 lock request 0x1001 lock response 0x1011 table 5.1 tcodes (cont.) type of asynchronous packet tcode
5-4 operation overview rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. application will not see the packet received until the receiver con?ms anything into the fifo). at the end of each packet reception, the receiver block will append a status quadlet to the packets indicating the speed at which the packet is received. the application needs this information to generate the response packets for incoming requests. once the incoming packet is con?med into the fifo, the corresponding interrupt is set (urx). the application can recognize this interrupt and can read the packet from the corresponding fifo. the length of the packet is determined by reading the ubuf receive write level. 5.1.3 phy interface the 1394 node controller core communicates with the phy through the phy interface. this interface handles the phy arbitration and phy data services. the phy interface communicates the arbitration request to gain control of the bus to the phy. the request contains the type of arbitration to perform. the phy communicates back the arbitration result, which tells whether the arbitration was won or lost for the request. the phy interface also handles the data communication between the phy and the transmitter and receiver. the phy interface controls when data is presented to the receiver, and it also controls when the transmitter may present data to the phy. four basic operations may occur on the phy interface when communicating with the phy: request, status, transmit, or receive. the phy initiates all requests. the phy interface module uses the request operation to read or write the phy register space or to ask the phy to initiate a transmit action by arbitrating for the bus. the phy initiates a receive action whenever a packet is received from the serial bus . the phy interface module has two major functional blocks: ? request controller this block interfaces with the transmitter, receiver, and the csu. ? arbitration controller the arbitration controller has the phy interface on one side. this interface complies with the ieee p1394a draft 2.0 speci?ation. figure 5.1 shows the communication between these blocks.
link layer controller 5-5 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. figure 5.1 block diagram of the phy interface block 5.1.3.1 request to request the bus or to access a phy register, the phy interface module sends a short stream to the phy on the llc_lreq pin. the information sent includes the type of request, the speed at which the packet is to be sent, or a read or write command. the transfer size is variable, depending on whether it is a bus request, a read access, or a write access, respectively. a stop bit of ? is required after each type of request transfer before another transfer may begin. figure 5.2 shows the bus request for an asynchronous packet (uses fair request), which is transmitted at 200 mbits/s. the request formats and handling for different requests are given in the ieee p1394a draft 2.0 speci?ation. figure 5.2 bus request using llc_lreq 5.1.3.2 status the phy initiates this transfer whenever it has some status information and when it ?ds the interface idle. to initiate the transfer, the phy places the status code (0b01) on the phy_ctlin pins and the ?st two bits of status information on phy_din[0:1]. the phy_ctlin pins maintain request controller block arbitration controller block interface to tx/ rx/ csu interface to phy phy_sclk llc_lreq start bit (1) request type (011) request speed (010) stop bit (0)
5-6 operation overview rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. this value throughout the status transfer. the status transfer is interrupted in the middle if the phy receives a packet from another node. the phy normally sends the ?st four status bits to the phy interface. these bits are status ?gs that are needed by the 1394 state machines. the phy sends an entire status packet of 16 bits to the phy interface after a request transfer that contains the read request, or whenever the phy has pertinent information to send. the only de?ed condition where the phy automatically sends a register to the link is after self-identi?ation, where it sends the physical_id register that contains the new node address. figure 5.3 shows the status timing waveforms. the status bit descriptions are described following the ?ure. figure 5.3 status timing data [15:8] these bits contain the phy register data. address [7:4] these bits contain the phy register address. state time-out 3 a one on this bit indicates a loop was detected in the cable topology. bus reset 2 this bit indicates whether or not the phy has entered the reset state. subaction gap 1 this bit is set when the phy detects the subaction gap time. arbitration reset gap 0 this bit is set when the phy detects the arbitration reset gap time. phy_sclk phy_ctlln phy_dln 00 01 s0, 1 s2, 3 s14, 15 00 00 00 00 00 01 01
link layer controller 5-7 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 5.1.3.3 transmit after the phy wins the arbitration for the request, it grants the bus to the phy interface of the llc by placing the transmit code (0b10) on phy_ctlin for one phy_sclk cycle. the phy places the idle code on phy_ctlin on the following clock. after sampling the transmit state, the phy interface takes over the interface by placing either the hold code (0b01) or transmit code (0b10) on phyif_ctlout. the phy interface starts transmitting the packet on the phyif_dout pins when the control pins are set to transmit. when the control pins are set for the hold state, the phy retains ownership of the bus by placing the data-on state on the bus. figure 5.4 shows the timing for packet transmission. figure 5.4 transmit timing 5.1.3.4 receive when the phy detects the data-on state on the serial bus, it initiates a receive operation by placing the receive state on the phy_ctlin pins and holds the phy_din signals high. the phy indicates the start of a packet by placing the speed code on the phy_din pins, followed by the contents of the packet. the phy holds the receive state on phy_ctlin until the last symbol of the data has been transferred. the idle state on the phy_ctlin signals indicates the end of the packet is detected. figure 5.5 shows the receive timing. phy_sclk phy_ctlln 00 phy_dln phyif_ctlout phyif_dout phyif_ctlen zz 10 d1 d0 d2 dn transmit idle hold transmit idle 00 00 00 00 00 00 00 00 00 00 00 00 11 zz zz zz zz zz zz zz zz zz 10 10 zz zz zz zz zz 01 zz zz zz zz zz zz zz zz 01 10 zz zz zz 00 00 zz zz 01 00
5-8 operation overview rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. figure 5.5 receive timing table 5.2 shows the encoding of the speed code (sp), which is the ?st received data, as shown in figure 5.5 above. 5.1.4 single-phase retry mechanism this section describes the single-phase retry mechanism within the 1394 node controller core. all packets should be sent with a retry_x code. if the received response is ack_busy then the retry block resends the packet. this process continues until the busy retry limit is reached, in which case the retry block ?shes the packet from the fifo and sets the retex interrupt bit. if the retry mechanism is turned off (retlim ?ld of the pdc control register is zero), the packet is transmitted once. if the transmitter receives the busy response, the fifo is ?shed and the retex interrupt bit is set. the application can read the acknowledge status register to ?d out what occurred. phy_sclk phy_ctlln 00 phy_dln 10 ff sp 10 d0 d1 10 10 10 10 00 00 00 ff dn 00 00 table 5.2 speed codes phy_din[0:7] data rate 00xxxxxx 100 mbits/s 0100xxxx 200 mbits/s 01010000 400 mbits/s 11xxxxxx data-on indication
application interface module 5-9 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 5.2 application interface module this section describes the operation of the application interface module (appif). the appif module implements the following functions: ? asynchronous packet transmit/receive interface to application ? register access from application ? interrupt generation the 1394 node controller core acts as a slave for the application on this interface; that is, only the application initiates all accesses. the 1394 node controller core can interrupt the application and give it status information, so that the application can take appropriate action. an application can access the 1394 register space or the fifos. the application clock and the 1394 local clock (49.152 mhz) are asynchronous to each other. 1394 node controller core register accesses are to the buffers or the registers. depending on the address from the application, the appif diverts the transactions to the buffers or the registers. however, every buffer or register access to the application is considered a 1394 register access. 5.2.1 read accesses to start a read cycle, the application asserts app_selp and drives app_readp high. it places the address of the register to read on app_addrp[31:0]. the appif module latches the address and provides the address for reading. the appif synchronizes the data and presents it to the application with aint_waitp deasserted. figure 5.6 shows a typical read operation to a 1394 register.
5-10 operation overview rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. figure 5.6 read from the application 5.2.2 write accesses to initiate a write cycle, the application asserts app_selp and holds app_writep high. it places the address of the register on app_addrp[31:0] and the data to be written on app_wrdatap[31:0]. the appif deasserts aint_waitp to indicate that the write cycle is complete. figure 5.7 shows a typical write cycle to the 1394 register. sysclkp aint_rddatap[31:0] aint_waitp app_addrp[31:0] app_wrdatap[31:0] app_writep app_selp app_readp
packet header transformation modules (phts) 5-11 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. figure 5.7 write from application 5.3 packet header transformation modules (phts) functionally, each of the two pht modules is divided into the following blocks: 1. isochronous transmission 2. isochronous reception (tight and loose) 3. asynchronous request transmission 4. asynchronous request reception 5.3.1 isochronous transmission internally, an isochronous transmission cycle starts whenever a cycle start packet is transmitted or received. the llc arbitrates for the bus if needed to transmit isochronous packets from the pht. the pht asserts the isochronous request (pht_isoreqn) signal to the llc for data transmission. when a channel is being serviced, if any more channels are to be serviced, the pht informs the transmitter about the next pending channel and its speed (pht-nxtchpendn and pht-nxtchspd). the transmitter sysclkp aint_rddatap[31:0] aint_waitp app_addrp[31:0] app_wrdatap[31:0] app_writep app_selp app_readp
5-12 operation overview rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. uses this information to send an l-request to the cable phy, when the cable is transmitting the current isochronous channel data (required to meet the gap timings). the transmitter concatenates two consecutive isochronous packets, if their respective speeds of transmission allow it to do so. the pht gets the header from the stream transmit header register or from the dma transmit fifo, depending upon the ehdr bit of the pht control and status register. if ehdr is set, then the application must provide the header in the required format (as speci?d in chapter 2 , data formats ? before presenting the data. if the ehdr is not set, the application should program the isochronous transmit channel header register, in which case the pht prepends the header from the stream transmit header register to the data in the dma transmit fifo. 5.3.2 isochronous reception the loosetightiso bit in the pdc control register determines whether reception is loose or tight. 5.3.3 tight isochronous cycles the isochronous receive is triggered on a cycle sync (whenever a cycle start is received or transmitted) and ends on a subaction gap. if the ihdr bit is not set, the header is only written to the stream receive channel header register by the pht. if the ihdr bit is set, the header is also clocked into the fifo before the data. the isochronous receive is triggered on a cycle sync event (when a cycle start is received or transmitted). the pht receives the data from the receiver block, and decodes the channel number in the header against the channel number in the stream receive channel selection registers and then stores the data if the channel is enabled. 5.3.4 loose isochronous packets the loose isochronous packets are implemented just like the tight isochronous packets. however, a loose isochronous packet can be received any time as long as the channel is enabled.
packet header transformation modules (phts) 5-13 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 5.3.5 asynchronous request transmission the pht can generate read or write request packets. these transfers should always use a transaction label of 0x3f for pht 0 and 0x3e for pht 1, which is used to distinguish the received responses from those that should go to the ubuf. requests that are transmitted using the universal transmit fifo must never use a transaction label of 0x3f or 0x3e. pht asynchronous request packet transfers use the dma interface to transfer the data to/from the core. in addition, the pht can automatically initiate sequential request transmit transfers after being initially programmed. this operation increases the data transfer rate compared to request transmit transfers, which use the ubuf. the request transmit transfer must interrupt the cpu after each 1394 packet transfer to initiate the next sequential transfer. the pht asynchronous request transmission mode can be used for accelerating sbp-2 target-initiated data buffer transfers (especially when the data buffer associated with an orb was larger than the allowable 1394 packet transfer size that can take advantage of automatic request generation). 5.3.6 asynchronous request reception read and write request packets whose address is in a range speci?d by the dma space register are routed to a pht for processing. this rerouting can be useful in sbp-2 applications where the application is an sbp-2 initiator and the dma space register is programmed to the address region associated with the sbp-2 data buffers and/or orbs. using the dma interface associated with a pht unburdens the cpu from having to process these transfers (which is the case if the ubuf receive fifo was used to process these requests). 5.3.7 scheduling of packets for transmission the transmitter can transmit one of the following packets depending on the state of the core and the cable: ? cycle start, if the core is a cycle master ? isochronous packet
5-14 operation overview rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. ? asynchronous packet if the node is a cycle master and the cycle monitor has asserted a request to send a cycle start when the cycle offset counts 125 s, the transmitter transmits the cycle start packet. then the transmitter samples the isochronous request signal from the arbiter to see if there are any isochronous packets to be transmitted. if the core is not the cycle master, it looks for the isochronous request as soon as it receives a cycle start packet. when the core is transmitting the current isochronous packet, the transmitter samples the arb-iso packet pendn signal to look for additional pending isochronous cycles. if this signal is asserted, the transmitter sends a request to the phy when it is transmitting the current packet or is receiving another packet. this requesting has to be done to meet the gap timings. once all the isochronous packets are transmitted and there are no more pending isochronous packets, the transmitter samples the requests from the asynchronous buffers. 5.4 interrupt mechanism the 1394 node controller core provides a single interrupt signal per interrupt register and one global interrupt signal to connect to an application on the app bus. status indications and state changes from different areas of the core activate interrupts. the interrupt and interrupt mask registers work in tandem to generate the interrupt on the app bus when the state of the 1394 node controller core changes. each bit of the interrupt registers represents a unique interrupt. a particular interrupt can be masked off when the corresponding bit in the interrupt mask registers is zero. 5.4.1 setting up the interrupt mask registers to set up the interrupt mask registers, the application writes ones into the bits within the interrupt mask registers for all the interrupts the application needs.
interrupt mechanism 5-15 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 5.4.2 determining and clearing the interrupt once the application detects assertion of an interrupt signal, it must read the relevant interrupt register to determine what status has changed. once the application determines which status change caused the interrupt, it can clear the interrupt at any time after that. to clear the particular interrupt, write a one into that bit location in the relevant interrupt register.
5-16 operation overview rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved.
1394 node controller core technical manual 6-1 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. chapter 6 application operation this chapter describes how the application handles incoming and outgoing asynchronous packets. this chapter contains the following sections: ? section 6.1, ?synchronous packet reception ? section 6.2, ?synchronous packet transmission ? section 6.3, ?synchronous stream packet transmission ? section 6.4, ?xample register con?urations 6.1 asynchronous packet reception to enable the reception of asynchronous packets, the application sets the rxen bit and clears the rxrst bit in the control 0 register. a typical request packet is shown in figure 6.1 . to decode this packet, the application decodes the tcode ?ld of the packet. the spd ?ld indicates the speed at which the packet is received. the source_id ?ld indicates the node id of the device that sent this packet. once the application processes the received packet, it can form the response packet shown in figure 6.2 . figure 6.1 write quadlet request receive format destinationid tl rt tcode pri sourceid destinationoffsethigh destinationoffsetlow quadlet_data reserved spd reserved
6-2 application operation rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. here, the destination id is the same as the source id from the request packet. the rcvdbusid is the same as the destination bus id from the request packet and will be used as the source bus id in the response packet. the spd and tl ?lds are the same as the request packet ?lds. the application can similarly decode other packets. 6.2 asynchronous packet transmission to enable the transmission of asynchronous packets, the application sets the txen bit in the control 0 register and clears the txrst bit. the application can start sending the packets immediately after reset. when writing an asynchronous packet into the ubuf transmit fifo, the application should comply with the data formats that are de?ed in chapter 2 , data formats . the application must use three addresses to transmit request and response packets. for example, the application must use the ubuf transmit clear, ubuf transmit next, and ubuf transmit last addresses. the 1394 node controller core only starts the arbitration for the request once the packet is con?med into the fifo. the application can follow the steps given below for writing a packet into the fifo: ? write to ubuf transmit clear (0x48) (ensures the fifo is in an appropriate state). ? write to ubuf transmit next (0x40). data is not con?med (typically the ?st 'n ? 1' quadlets of the packet are written to this address in a packet with header and payload length of 'n'). ? write to ubuf transmit last (0x44). data is con?med (typically the last quadlet of the packet is written here). figure 6.2 write quadlet response packet transmit format rcvdbusid reserved spd tl rt tcode pri destinationid rcode reserved reserved
asynchronous stream packet transmission 6-3 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 6.3 asynchronous stream packet transmission asynchronous stream packets are isochronous packets transmitted during a nonisochronous period. the core arbitrates using a fair or priority request (subject to the prilim ?ld of the control 0 register) whenever there is an asynchronous packet to be transmitted, including packets with a tcode of 0xa. con?uring the appropriate registers and then setting the east bit in the pht control and status register is the primary method for transmitting asynchronous stream packets. also the ubuf can be used to send asynchronous stream packets by using the unformatted data transmit format (the application must generate a proper 1394 isochronous packet including crcs as the unformatted packet data). 6.4 example register con?urations this section describes eight example register con?urations. 6.4.1 automatic asynchronous write request packet generation to transmit a 16 kbyte buffer to local node 0x89 at address offset 0x1234.5678.9abc using 512-byte 1394 data ?lds at s100 speed, follow these steps: 1. write 0x0xxx.8xxx to 0xc0 (dbuf fifos level register). this step initializes the dmatf by setting the dxrst bit (which automatically clears itself). 2. write 0x0xxx.0020 to 0xa4 (data transfer control register). this step programs pcnt to 32. a total of 32 write requests are made then the pcntr interrupt is set. 3. write 0x1fff.003f to 0xbc (dma transfer threshold register). in this example, the external dma controller performs a minimum of 16 quadlet transfers or multiple of 16 for each assertion of the dint0_dreqp output signal. therefore dint0_dreqp must not be asserted if there are less than 64 bytes available to be written in the dmatf (the rdlvl ?ld is programmed such that the dint0_dreqp associated with the dmarf is never asserted).
6-4 application operation rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 4. write a one to the den bit in the dma control and status register (0xb8). this step enables the dma interface to assert the dint0_dreqp signal. 5. program the split time-out register, which is used for automatically generated requests. for example, write 0x0000.0800 (initial value speci?d by 1394-1995) to 0x84 (pht split time-out register). 6. program the pht request header registers with the destination address, transmission speed, and 1394 data ?ld length. write 0xffe9.1234 to 0x88 (pht request header 0), 0x5678.9abc to 0x8c (pht request header 1), 0x01f8.0200 to 0x90 (pht request header 2). 7. write a one to the ewreq and epctr bits in the pht control and status register (0x80). assuming that the txen and rxen bits in the control 0 register (0x08) are set, 1394 write requests are made when there is enough data (data ?ld length amount) in the dmatf. 6.4.2 automatic asynchronous read request packet generation this example retrieves a 16 kbyte buffer from local node 0x89 at address offset 0x1234.5678.9abc using 512-byte 1394 data ?lds at s100 speed. the steps are as follows: 1. write 0x8xxx.0xxx to 0xc0 (dbuf fifos level register). this step initializes the dmarf by setting the drrst bit (which automatically clears itself). 2. write 0x0xxx.0020 to 0xa4 (data transfer control register). this step programs pcnt to 32). once 32 read requests are made, the pcntr interrupt is set. 3. write 0x003f.1fff to 0xbc (dma transfer threshold register). in this example, the external dma controller performs a minimum of 16 quadlet transfers or multiple of 16 for each assertion of the dint0_dreqp output signal. therefore dint0_dreqp must not be asserted if there are less than 64 bytes available to be read in the dmarf (the wrlvl is programmed such that the dint0_dreqp associated with the dmatf is never asserted). 4. write a 1 to the den bit in the dma control and status register (0xb8). this step enables the dma interface to assert the dint0_dreqp signal.
example register con?urations 6-5 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 5. program the split time-out register used for automatically generated requests. for example, write 0x0000.0800 (initial value speci?d by 1394-1995) to 0x84 (pht split time-out register). 6. program the pht request header registers with the destination address, transmission speed, and 1394 data ?ld length. write 0xffe9.1234 to 0x88 (pht request header 0), 0x5678.9abc to 0x8c (pht request header 1), 0x01f8.0200 to 0x90 (pht request header 2). 7. write a 1 to the erreq and epctr bits in the pht control and status register (0x80). assuming that the txen and rxen bits in the control 0 register (0x08) are set, 1394 read requests are made. 6.4.3 cip format isochronous packet reception this example listens to isochronous channel 5, which is a dv format stream. do not put empty cip packets in dmarf or put 1394 headers in dmarf. the steps for this example are: 1. write 0x8xxx.0xxx to 0xc0 (dbuf fifos level register). this step initializes the dmarf by setting the drrst bit (which automatically clears itself). 2. write 0x0000.0000 to 0x94 and 0x0000.0020 to 0x98 (select channel 5 for listening). 3. write 0x01e7.1fff to 0xbc (dma transfer threshold register). in this example, the external dma controller performs a 488-byte transfer for each assertion of the dint0_dreqp output signal. therefore dint0_dreqp should not be asserted if there are less than 488 bytes (one dv data block and cip header) available to be read in the dmarf the wrlvl is programmed such that the dint0_dreqp associated with the dmatf is never asserted. 4. write a 1 to the den bit in the dma control and status register (0xb8). this step enables the dma interface to assert the dint0_dreqp signal. 5. writea1tothe elis and cch bits and 0b10 (strip only empty cips) in the pht control and status register (0x80). assuming that the rxen bit in the control 0 register (0x08) is already set.
6-6 application operation rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 6.4.4 simultaneous cip format isochronous packet reception and transmission this example listens to isochronous channel 5, which is a dv format stream. do not put empty cip packets or 1394 headers in dmarf. transmit mpeg2 streams on channel 63 at s400 speed. this example assumes a dbuf transmit fifo size of 1024 bytes. the steps are as follows: 1. write 0x8xxx.8xxx to 0xc0 (dbuf fifos level register). this step initializes the dmarf and dmatf by setting the drrst and dxrst bits (which automatically clear themselves). 2. write 0x0000.0000 to 0x94 and 0x0000.0020 to 0x98 (select channel 5 for listening). 3. write 0x0188.7f40 to 0xa0 (stream transmit channel header register). the isodatalen ?ld is 392 because two source packets are transmitted when a nonempty cip packet is transmitted. a non- empty cip packet consists of the following: 8-byte cip header + 4-byte sph time stamp + 188-byte mpeg packet + 4-byte sph time stamp + 188-byte mpeg packet the tag ?ld is 0b01 for iec-61883 formatted data. the channelno ?ld is 63, and the speed ?ld is s400. 4. write 0x01e7.0280 to 0xbc (dma transfer threshold register). in this example, the external dma controller performs a 488-byte read for each assertion of the dint0_dreqp output signal. therefore dint0_dreqp must not be asserted if there are less than 488 bytes (one dv data block and cip header) available to be read in the dmarf. the external dma controller must not perform more than a 188-byte (one mpeg source packet) write for each assertion of the dint0_dreqwp output signal. if you want to guarantee that the time stamps in consecutive nonempty cip 1394 packets differ by at least one in the cycle count portion of the source packet header time stamp, then no more than the number of mpeg packets in a 1394 packet can be allowed in the dmatf at any one time. this condition can be met when dint0_dreqwp is programmed to not be asserted if there are less than ?ight plus the dmatf size minus the 1394 payload size (392
example register con?urations 6-7 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. in this example) empty bytes available to be written in the dmatf (0x0280 in this example). 5. write 0x0206.c400 to 0xa8 (cip header transmit 0 register). the nsp ?ld is 2 (source packets). the dbs ?ld is 6. the fn ?ld is 0b11. the qpc ?ld is 0. the sph bit is 1. the beginning dbc is 0. 6. write 0x2000.0000 to 0xac (cip header transmit 1 register). fmt is mpeg2. in fdf, the time shift ?g is 0. 7. write 0x00bc.xxxx to 0xb4 (stream transmit time stamp offset register). the source packet size (sps) is 188 bytes. the ?xxx should correspond to the desired offset to be added to each time stamp, which compensates for jitter. 8. write 0x0187.xxxx to 0xa4 (data transfer control register). this step results in a nonempty cip packet being sent for any isochronous cycle in which two mpeg packets are in the dmatf. 9. writea1tothe elis and cch bits and 0b10 (strip only empty cips) and gts, gencip and etalk bits in the pht control and status register (0x80). assume that the rxen and txen bits in the control 0 register (0x08) are already set. 10. write a 1 to the den and ractl bits in the dma control and status register (0xb8). this step enables the dma interface to assert the dint0_dreqp signals (dint0_dreqp and dmac0_dackp are used for reads from dmarf; dint0_dreqwp and dmac0_dackwp are used for writes to the dmatf). 6.4.5 automatic asynchronous request packet processing this example has the pht process incoming read or write requests from node 0x25, which have an address offset below 0x0000.0010.xxxx. this procedure is primarily of use when higher layer software (for example, sbp-2) is being used in which a target node is made aware of a data buffer that has been created at this node. this node wants the target node to read or write the data buffer (for example, a data buffer associated with an sbp-2 orb). because this node creates the data buffer, it can program the external dma controller (that interfaces to the core) to access the data buffer when the core asserts the appropriate dint0_dreqp output because of an incoming request packet in the speci?d range.
6-8 application operation rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 1. write 0x8xxx.8xxx to 0xc0 (dbuf fifos level register). this step initializes the dmarf and dmatf by setting the drrst and dxrst bits (which automatically clear themselves). 2. write 0x000f.000f to 0xbc (dma transfer threshold register). in this example, the external dma controller performs at most a 16-byte read for each assertion of the dint0_dreqp output signal. therefore dint0_dreqp should not be asserted if there are less than 16 bytes. in this example, the external dma controller performs a 16-byte write for each assertion of the dint0_dreqwp output signal. therefore dint0_dreqwp should not be asserted if there are less than 16 empty bytes available to be written in the dmatf. 3. write a one to the den and ractl bits in the dma control and status register (0xb8). this step enables the dma interface to assert the dint0_dreqp signals (dint0_dreqp and dmac0_dackp used for reads from dmarf, dint0_dreqp, and dmac0_dackwp used for writes to the dmatf). 4. write 0x0000.0000 to 0x94 and 0x0200.0000 to 0x98 (select node 25 from which to accept requests). 5. write 0x0000.0010 to 0x38 (dma space register). this step enables automatic processing of requests from the target node in the desired address range. 6. write a 1 to the endmas, ihdr, and possibly ehdr bits in the pht control and status register 0 (0x80). 7. write a 1 to the txen and rxen bits in the control 0 register (0x08). automatic 1394 write/read responses are made to incoming requests in the speci?d range (assuming the application dma controller is capable of parsing 1394 read and write request packets). 6.4.6 asynchronous write request packet generation writing dma transmit fifo through the application interface this example transmits a 512-byte payload (using the application interface to supply the payload) to local node 0x89 at address offset 0x1234.5678.9abc using a 512-byte 1394 data ?ld at s100 speed. the steps are as follows: 1. write 0x0xxx.8xxx to 0xc0 (dbuf fifos level register 0). this step initializes the dmatf by setting the dxrst bit (which automatically clears itself).
example register con?urations 6-9 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 2. write 0x0xxx.0001 to 0xa4 (data transfer control register 0). one write request is made then the pcntr interrupt is set. 3. program the split time-out register used for automatically generated requests. for example, write 0x0000.0800 (initial value speci?d by 1394-1995) to 0x84 (pht split time-out register 0). 4. program the pht request header registers with the destination address, transmission speed, and 1394 data ?ld length. write 0xffe9.1234 to 0x88 (pht request header 0), 0x5678.9abc to 0x8c (pht request header 1), 0x01f8.0200 to 0x90 (pht request header 2). 5. write a 1 to the ewreq and epctr bits in the pht control and status register 0 (0x80). assume that the txen and rxen bits in the control 0 register (0x08) are set. a 1394 write request is made when there is enough data in the dmatf 0. 6. write the data to 0xc4 (dbuf tx fifo data register 0). 6.4.7 asynchronous read request packet generation reading dma receive fifo through the application interface this example retrieves a 512-byte buffer from local node 0x89 at address offset 0x1234.5678.9abc using a 512-byte 1394 data ?ld at s100 speed. the steps are as follows: 1. write 0x8xxx.0xxx to 0xc0 (dbuf fifos level register 0). this step initializes the dmarf by setting the drrst bit (which automatically clears itself). 2. write 0x0xxx.0001 to 0xa4 (data transfer control register 0). this step programs pcnt to 1). one read request is made then the pcntr interrupt is set up for receipt of the response. 3. program the split time-out register used for automatically generated requests. for example, write 0x0000.0800 (initial value speci?d by 1394-1995) to 0x84 (pht split time-out register 0). 4. program the pht request header registers with the destination address, transmission speed, and 1394 data ?ld length. write 0xffe9.1234 to 0x88 (pht request header 0), 0x5678.9abc to 0x8c (pht request header 1), 0x01f8.0200 to 0x90 (pht request header 2).
6-10 application operation rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 5. write a 1 to the erreq and epctr bits in the pht control and status register 0 (0x80). assuming that the txen and rxen bits in the control 0 register (0x08) are set, a 1394 read request is made. 6. read the data from 0xc8 (dbuf rx fifo data register 0) after the pcntr interrupt is detected. 6.4.8 cip format isochronous packet transmission with syt time stamps using programmable frame synchronization this example transmits a dv stream on channel 63 at s400 speed. it assumes a dbuf transmit fifo size of 1024 bytes 1. write 0x0xxx.8xxx to 0xc0 (dbuf fifo level register). this step initializes the dmatf by setting the dxrst bit (which automatically clears itself). 2. write 0xxxxx.01e7 to 0xbc (dma transfer threshold register). in this example, the core is programmed to request only one 1394 payload from the external dma controller per isochronous cycle. it is assumed that the external dma controller performs a 480-byte (one dv data block) write for each assertion of the dint0_dreqwp output signal. therefore dint0_dreqwp must not be asserted when there are less than 488 empty bytes (dv data block plus cip header) available to be written in the dmatf. 3. write 0x01e8.7f40 to 0xa0 (stream transmit channel header register). the isodatalen ?ld is 488 because one source packet will be transmitted when a nonempty cip packet is transmitted. the nonempty cip packet consists of a 480-byte dv data block + an 8-byte cip header. the tag ?ld is 0b01 for iec-61883 formatted data. the channelno ?ld is 63, and the speed ?ld is s400. 4. write 0x0178.0000 to 0xa8 (cip header transmit 0 register). the nsp ?ld is 1 (number of source packets). the dbs ?ld is 120 quadlets. the fn ?ld is 0b00. the qpc ?ld is 0. the sph bit is 0. the beginning dbc is 0. 5. write 0x0000.ffff to 0xac (cip header transmit 1 register). the fmt ?ld is dvcr. in the fdf ?ld, the time shift ?g is 0. the syt ?ld is programmed to the ?o information value as per iec-61883 (this will be replaced with the hardware time stamp in the transmitted packet, when appropriate).
example register con?urations 6-11 rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved. 6. write 0x01e0.0000 to 0xb4 (stream transmit time stamp offset register). the source packet size (sps) is 480 bytes. 7. write 0x01e4.xxxx to 0xa4 (data transfer control register). this step results in the sending of a nonempty cip packet for any isochronous cycle in which a source packet and cip header (0x01e8) are in the dmatf. 8. write 0x5f2x.xxxx to 0x84 (split time-out/empty cip interval register). assuming a 525-60 system, the ppf ?ld is 249 (0x0f9). 9. write 0x2088.0000 to 0x80 (phy control and status register), which enables gts, gencip, and etalk. this step assumes that the rxen and txen bits in the control 0 register (0x08) are already set. 10. write a 1 to the den and ractl bits in the dma control and status register (0xb8). this step enables the dma interface to assert the dint0_dreqp signals (dint0_dreqp and dmac0_dackp for reads from dmarf, dint0_dreqwp and dmac0_dackwp for writes to the dmatf).
6-12 application operation rev. c copyright 2000, 2001 by lsi logic corporation. all rights reserved.
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