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IRCC infrared communications controller features ? multi-protocol serial communications controller ? full irda v1.1 implementation: 2.4kbps, 115.2kbps, .576mbps, 1.152mbps and 4mbps ? consumer infrared (tv remote control) interface ? sharp amplitude shift keyed infrared (ask ir) interface ? direct rx/tx infrared diode control (raw) and general purpose data pins ? programmable high-speed synchronous communications engine (sce) with a 128- byte fifo and programmable threshold ? high-speed ns16c550a-compatible universal asynchronous receiver/ transmitter interface (ace uart2) with 16- byte send and receive fifos ? isa single-byte and burst-mode dma and interrupt-driven programmed i/o with zero wait state and string move timing ? 16-bit crc-ccitt and 32-bit ieee 802 crc32 hardware crc generators general description this document describes the infrared communications controller (IRCC) function which is common to a number of smsc products including the fdc37c669fr, fdc37c93xfr, and fdc37c957fr devices. the IRCC consists of two main architectural blocks: the ace 16550a uart and a synchronous communications engine (sce) (figure 2). each block is supported by its own unique register set. the IRCC uart-driven irda sir and sharp ask modes are backward-compatible with early smsc super i/o and ultra i/o infrared implementations. the IRCC sce supports irda v1.1 .576mbps, 1.152mbps, 4mbps, and consumer ir modes. all of the sce modes use dma. the IRCC offers flexible signal routing and programmable output c ontrol through the raw mode interface, general purpose data pins and output multiplexer. chip-level address decoding is required to access the IRCC register sets.
2 table of contents features....................................................................................................................... ...................... 1 general d escript ion ............................................................................................................ ......... 1 interface d escript ion .......................................................................................................... ........ 4 ports ......................................................................................................................... ................... 4 chip-level configura tion cont rols ................................................................................ 6 raw ir......................................................................................................................... .......................... 8 consumer ir (tv remo te) ........................................................................................................ ...... 9 intro duction .................................................................................................................. ........... 9 descri ption ................................................................................................................... ........... 10 irda sir and sharp ask ir inte rface ........................................................................................ 14 infrared data associat ion ................................................................................................ 19 registers ...................................................................................................................... ................... 24 ace uart contro ls............................................................................................................. ... 24 sce co ntro ls .................................................................................................................. ........ 25 master block co ntrol regis ter..................................................................................... 26 register bl ock ze ro ........................................................................................................... . 27 register bl ock one ............................................................................................................ .. 32 register bl ock two............................................................................................................ .. 36 register bl ock t hree .......................................................................................................... 37 register bl ock fo ur ........................................................................................................... . 38 ace ua rt....................................................................................................................... ..................... 40 register d escript ion.......................................................................................................... . 40 sce ............................................................................................................................ .......................... 55 descri ption ................................................................................................................... ........... 55 framing ....................................................................................................................... ............... 55 active frame indicator ....................................................................................................... 5 5 irda e ncoder.................................................................................................................. ........... 56 consumer ir encode r .......................................................................................................... 6 1 loopbac k mode ................................................................................................................. ...... 63 bus interf ace i/o .............................................................................................................. ............. 65 fifo mult iplexer.............................................................................................................. ....... 65 128-byte sc e fifo............................................................................................................. ........ 65 dma........................................................................................................................... .................... 67 progra mmed i/o ................................................................................................................ ...... 71 iochrdy ti me-out.............................................................................................................. ...... 73 zero wait st ate suppo rt.................................................................................................... 75 output mult iplexer ............................................................................................................. ........ 76 chip-level IRCC addr essing su pport ...................................................................................... 77 ac timing ...................................................................................................................... ..................... 78
3 raw ir ir transducer module registers ace uart bus interface i/o clock generator comm port irda ir ask ir consumer ir smc infrared communications controller output mux com aux sce encoders system figure 1 - smsc IRCC functional components ace uart sce irda sir sharp as k com i rda fi r consumer sce registers ace registers output mux fifo, dma, i/o, interrupts databus mux bus interface nace isa controls data (0-7) address (0-2) ir com aux g.p. nsce gp/raw/fast figure 2 - IRCC archite ctural block diagram
4 interface description the interface description lists the signals that are required to place the IRCC in a larger chip- level context. there are four groups of signals in this section: port signals, host bus controls, system controls, and chip-level configuration controls. ports the four ports (ir, com, aux, and general purpose) provide external access for serial data and controls. the active IRCC encoder is routed through the output multiple xer to either the ir, com, or aux port. the general purpose port provides external access for controls that are independent of the IRCC block control bits or the output multiplexer. table 1 - ir port signals name size (bits) type description irrx 1 input infrared receive data irtx 1 output infrared transmit data table 2 - com port signals name size (bits) type description crx 1 input com receive data ctx 1 output com transmit data nrts 1 output request to send ndtr 1 output data terminal ready ncts 1 input clear to send ndsr 1 input data set ready ndcd 1 input data carrier detect nri 1 input ring indicator table 3 - aux port signals (e.g., can be used for high-current drivers for consumer ir) name size (bits) type description arx 1 input aux. receive data atx 1 output aux. transmit data
5 table 4 - g. p. port signals name size (bits) type description fast 1 output general purpose data gp data 1 output general purpose data fast the fast pin always reflects the state of fast, bit 6 of sce line control regi ster a. the state of fast is independent of the IRCC block controls or the output multiplexer. the fast pin can be used at the chip level for ir transceiver configuration. gp data the g.p. data pin always reflects the state of general purpose data, bit 5 of sce line control register a. the state of g.p. data is independent of the IRCC blo ck controls or the output multiplexer. table 5 - host signals name size (bits) type description d0-d7 8 bidirectional host data bus a0-a2 3 input IRCC register address bus nior 1 input isa i/o read niow 1 input isa i/o write aen 1 input isa address enable drq 1 output dma request ndack 1 input isa dma acknowledge tc 1 input isa dma terminal count irq 1 output interrupt request iochrdy 1 output isa i/o channel ready nsrdy 1 output isa synchronous ready (zero wait state)
6 table 6 - system signals name size (bits) type description clk 1 input system clock reset 1 input IRCC system reset power down 1 input low power control dmaen 1 output drq tristate control irqen 1 output irq tristate control nace 1 input ace 550 register bank select nsce 1 input sce register bank select vcc power system supply gnd power system ground dmaen dmaen is used by the chip-level interface to tristate the IRCC drq output when the dma enable bit is inactive. the dma enable bit is located in sce configurat ion register b, bit 0. irqen irqen is used by the chip-level interface to tristate the IRCC irq output when the out2 bit is inactive. the out2 bit is located in 16550a modem control register. power down the power down pin is used by the chip-level interface to put the sce into low power mode. note: power down does not force the ace550 into low power mode. chip-level configuration controls the following signals come from chip-level configuration registers. there are two types of chip-level configuration controls: IRCC-specific controls, and legacy controls. both types have equivalent controls in either the IRCC ace or sce registers. the IRCC-specific c ontrols have been newly added primarily to support the IRCC block. provisions have been made in new chip-level configuraton contexts to accommodate these signals. the legacy controls already exist in other contexts. provisions have been made in legacy devices to accommodate these controls from either the chip-level c onfiguration registers or the IRCC registers; i.e ., the last updated value from either source dete rmines the current control state and is visible in both registers.
7 table 7 - IRCC-specific chip-level controls name size (bits) type description dma channel 4 input isa dma channel number irq level 4 input isa interrupt level dma channel 4-bit bus from a chip-level configuration register, used to identify the cu rrent IRCC dma channel number. the value appears in the upper nibble of IRCC register block three, address four. irq level 4-bit bus from a chip-level configuration register, used to identify the current IRCC irq level. the value appears in the lower nibble of IRCC register block three, address four. table 8 - legacy chip-level controls name size (bits) type description tx polarity 1 input output mux. transmit polarity rx polarity 1 input output mux. receive polarity half duplex 1 input 16550a ua rt half duplex control ir mode 3 input ir mode register bits ir location 2 input ir opti on register location bits tx polarity typically part of a 16550a serial port option register. the value also appears in IRCC register block one, address zero. rx polarity typically part of a 16550a serial port option register. the value also appears in IRCC register block one, address zero. half duplex typically part of a 16550a serial port option register. the value also appears in IRCC register block one, address zero. ir mode typically part of a 16550a serial port option register. these values are also part of the IRCC block control bits 3-5, register block one, address zero. ir location typically part of a 16550a serial port ir option register. these values are the IRCC output mux bits, register block one, address one. note : these legacy controls are uniformly updated in the IRCC and the top-level device configuration registers only when either set of registers are explicitly written using iow or following a device-level por. IRCC software resets will not affect the legacy bits.
8 operation modes raw ir in raw mode the state of the ir emitter and detector can be directly accessed through the host interface (figure 3). the ir emitter tracks the raw tx control bit. for example, depending on the state of the tx polarity control a logic '1' may turn the led on and a logic '0' may turn the led off. care must be taken in software to ensure that the led is not on continuously. the raw rx control bit represents the state of the pin diode. for example, depending on the state of the rx polarity control a logic '1' may mean no ir is detected, a logic '0' may mean ir is being detected. if an ir carrier is being received, the raw rx control bit will oscillate at the carrier frequency. if enabled, a raw mode interrupt will be generated when the raw rx control bit transitions to the acti ve state, depending on the state of the rx polarity control. raw tx registers transition detect enable interrupt encoder/decoder raw rx figure 3 - raw ir block diagram
9 consumer ir (tv remote) introduction the IRCC consumer ir (tv remote) block is a general-purpose programmable amplitude shift keyed serial communications interface that includes a carrier frequency divider, a programmable receive ca rrier range sensitivity register, and receive and transmit modulators (figure 4). the consumer ir block transfers data between the sce and output mult iplexer without framing as a fixed bit-cell serial nrz data stream. the components of this block can also modulate and demodulate serial data at programmable bit rates and carrier frequencies. variable length encoding and all packet framing is handled by system software. consequently, many encoding methods, modulation frequencies and bit rates can be supported, including 38khz ppm, pwm and rc-5 tv remote formats. register controls for this block can be found in register block two. they are the consumer ir control register, the consumer ir carrier rate register, and the consumer ir bit rate register. sce transmit bit-rate divider carrier frequency divider clock programmable receive carrier sense receive bit-rate divider tv tx tx enable range sync rx enable encoder/decoder carrier off tv rx figure 4 - IRCC consumer ir (tv remote) block
10 description carrier frequency divider the carrier frequency divider register is used to program the ask carrier frequency for the transmit modulator and receive detector (figure 5). the divider is eight bits wide. the input clock to the carrier frequency divider is 1.6mhz (48mhz 30). the relationship between the divider value (cfd) and the carrier frequency (fc) is as follows: cfd = (1.6mhz/fc) - 1 for example, program the carrier frequency divider register with 41 ('29'hex) for a 38khz tv remote: fc = 38.095khz. this is ~.25% accuracy. table 9 contains representative cfd vs. carrier frequency relationships. the carrier frequency range is 1.6mhz to 6.25khz. the carrier frequency encoder/decoder can be defeated using the carrier off bit. when carrier off is one, the transmitter outputs a non- modulated sce serial nrz data stream at the programmed bit rate; the receiver does not attempt to demodulate a carrier from the incoming serial data stream. table 9 - representative carrier frequencies cfd fc (khz) cfd fc (khz) cfd fc (khz) cfd fc (khz) 001 800.000 065 24.242 129 12.308 193 8.247 005 266.667 069 22.857 133 11.940 197 8.081 009 160.000 073 21.622 137 11.594 201 7.921 013 114.286 077 20.513 141 11.268 205 7.767 017 88.889 081 19.512 145 10.959 209 7.619 021 72.727 085 18.605 149 10.667 213 7.477 025 61.538 089 17.778 153 10.390 217 7.339 029 53.333 093 17.021 157 10.127 221 7.207 033 47.059 097 16.327 161 9.877 225 7.080 037 42.105 101 15.686 165 9.639 229 6.957 041 38.095 105 15.094 169 9.412 233 6.838 045 34.783 109 14.545 173 9.195 237 6.723 049 32.000 113 14.035 177 8.989 241 6.612 053 29.630 117 13.559 181 8.791 245 6.504 057 27.586 121 13.115 185 8.602 249 6.400 061 25.806 125 12.698 189 8.421 253 6.299
11 bit rate divider the transmit and receive bit rate divider register is used to extract a serial nrz data stream for the IRCC sce. t he divider is eight bits wide. the input clock to the bit rate divider is 100khz (carrier frequency divider input clock 16). the relationship between the bit rate divider (brd) and the bit rate (fb) is as follows: brd = (.1mhz/fb) - 1 for example, program the bit rate divider with 55 ('37'hex) for a .562ms tv remote bit cell: fb = 1.786khz. this is ~.5% accuracy. table 10 contains representativ e brd vs. bit rate relationships. the bit rate range is 100khz to 390.625hz. table 10 - representative bit rates brd fb (khz) brd fb (khz) brd fb (khz) brd fb (khz) 003 25.000 067 1.471 131 0.758 195 0.510 007 12.500 071 1.389 135 0.735 199 0.500 011 8.333 075 1.316 139 0.714 203 0.490 015 6.250 079 1.250 143 0.694 207 0.481 019 5.000 083 1.190 147 0.676 211 0.472 023 4.167 087 1.136 151 0.658 215 0.463 027 3.571 091 1.087 155 0.641 219 0.455 031 3.125 095 1.042 159 0.625 223 0.446 035 2.778 099 1.000 163 0.610 227 0.439 039 2.500 103 0.962 167 0.595 231 0.431 043 2.273 107 0.926 171 0.581 235 0.424 047 2.083 111 0.893 175 0.568 239 0.417 051 1.923 115 0.862 179 0.556 243 0.410 055 1.786 119 0.833 183 0.543 247 0.403 059 1.667 123 0.806 187 0.532 251 0.397 063 1.563 127 0.781 191 0.521 255 0.391
12 receive carrier sense the programmable receive carrier sense register is used to pr ogram the consumer ir decoder to detect the presenc e of ir energy in a wide-to-narrow range of carrier frequencies. the register is two bits wide. the range values are shown in table 11. carriers that fall outside of the receive carrier range sensitivity ?abort? the message; i.e., the abort bit is set, an eom interrupt is generated, and the receiver is disabled. if the ?carrier off? bit is active, the receiv e carrier range sensitivity is disabled. table 11 - receive carrier sense range d1 d0 range 0 0 10% 0 1 20% 1 0 40% 1 1 reserved 10 1 sce tx data tv tx output transmitter tv rx input sce rx data receiver 1/carrier 1/bit rate no light light light no light tx polarity bit = 1 rx polarity bit = 0 figure 5 - tv remote ask encode/decode
13 receiver bit cell synchronization the consumer ir receiver demodulates incoming ask waveforms into nrz data for the sce. the IRCC uses the edges of the demodulated incoming infrared data to indicate changes in bit state. for continuous periods of high or low data without transitions, the IRCC samples the signal level in the center of each incoming bit period. using the receiver bit cell synchronization mechanism, any transition resets the timer that is used in the sampling process to eliminate errors due to timing differences between the receive decoder and the incoming bit period (figure 6). receiver synchronization can be disabled to allow direct sampling of the demodulated incoming infrared data str eam at some preset receive bit rate. this is useful in situations where the speed of the receive data is not strictly known. in such cases, the receive bit rate is set as high as possible, the receiver bit cell synchronization is disabled, and the system software is used to measure the bit-cell period from the oversampled data. the learned parameters can then be us ed to switch to the synchronized, fixed bit-cell mode to reduce processing overhead in the host cpu for all future transactions. 11 000 0 111 sync sync 11000 1 111 ir rx data ir rx data nrz rx data (sync) nrz rx data (no sync) 1 2345678 910 clock 1 234567891011 clock 0 figure 6 - tv remote receiver: sync vs. no sync
14 irda sir and sharp ask ir interface this infrared interface provides a two-way wireless communications port using infrared as a transmission medium. two infrared implementations have been provided in this block of the IRCC, irda sir and sharp ask ir. irda sir allows serial communication at baud rates up to 115k baud. each word is sent serially beginning with a zero value start bit. a zero is signaled by sending a single infrared pulse at the beginning of the serial bit time. a one is signaled by sending no infrared pulse during the bit time. please refer to figure 7- figure 10 for the paramet ers of these pulses and the irda waveform. the ask infrared allows serial communication at baud rates up to 19.2k baud. each word is sent serially beginning with a zero value start bit. a zero is signaled by sending a 500khz waveform for the duration of the serial bit time. a one is signaled by sending no transmission during the bit time. please refer to the ac timing for the parameters of the askir waveform. if the half duplex option is chosen, there is a time-out when the directi on of the transmission is changed. this time-out st arts at the last bit transferred during a transmission and blocks the receiver input until the ti me-out expires. if the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after t he last receive bit has been received. if the start bit of another character is received during this time-out, the timer is restarted after the new character is received. the time-out is programmable up to a maximum of 10ms through the ir half-duplex time-out configuration register.
15 parameter min typ max units t1 pulse width at 115kbaud 1.4 1.6 2.71 s t1 pulse width at 57.6kbaud 1.4 3.22 3.69 s t1 pulse width at 38.4kbaud 1.4 4.8 5.53 s t1 pulse width at 19.2kbaud 1.4 9.7 11.07 s t1 pulse width at 9.6kbaud 1.4 19.5 22.13 s t1 pulse width at 4.8kbaud 1.4 39 44.27 s t1 pulse width at 2.4kbaud 1.4 78 88.5 s t2 bit time at 115kbaud 8.68 s t2 bit time at 57.6kbaud 17.4 s t2 bit time at 38.4kbaud 26 s t2 bit time at 19.2kbaud 52 s t2 bit time at 9.6kbaud 104 s t2 bit time at 4.8kbaud 208 s t2 bit time at 2.4kbaud 416 s notes: 1. irda @ 115k is hpsir compatible. irda @ 2400 will allow compatibility with hp95lx and 48sx. 2. irrx: crc bit 1: 1 = xmit active low nirrx: crc bit 1: 0 = xmit active high (default) t1 t2 t2 t1 0 1 0 1 00 11 0 11 data irrx nirrx figure 7 - irda receive timing
16 parameter min typ max units t1 pulse width at 115kbaud 1.41 1.6 2.71 s t1 pulse width at 57.6kbaud 1.41 3.22 3.69 s t1 pulse width at 38.4kbaud 1.41 4.8 5.53 s t1 pulse width at 19.2kbaud 1.41 9.7 11.07 s t1 pulse width at 9.6kbaud 1.41 19.5 22.13 s t1 pulse width at 4.8kbaud 1.41 39 44.27 s t1 pulse width at 2.4kbaud 1.41 78 88.55 s t2 bit time at 115kbaud 8.68 s t2 bit time at 57.6kbaud 17.4 s t2 bit time at 38.4kbaud 26 s t2 bit time at 19.2kbaud 52 s t2 bit time at 9.6kbaud 104 s t2 bit time at 4.8kbaud 208 s t2 bit time at 2.4kbaud 416 s notes: 1. receive pulse detection criteria: a received pul se is conidered detected if the received pulse is a minimum of 1.41 s 2. irtx: crc bit 0: 1 = rcv active low nirtx: crc bit 0: 0 = rcv active high (default) t1 t2 t2 t1 0 1 0 1 00 11 0 11 data irtx nirtx figure 8 - irda transmit timing
17 parameter min typ max units t1 modulated output bit time s t2 off bit time s t3 modulated output ?on? 0.8 1 1.2 s t4 modulated output ?off? 0.8 1 1.2 s t5 modulated output ?on? 0.8 1 1.2 s t6 modulated output ?off? 0.8 1 1.2 s notes: 1. irtx: crc bit 1: 1 = xmit active low nirtx: crc bit 1: 0 = xmit active high (default) mirtx, nmirtx are the modulated outputs. t1 t2 t3 t4 t5 t6 01010011011 data irtx nirtx mirtx nmirtx figure 9 - amplitude shift keyed ir transmit timing
18 parameter min typ max units t1 modulated output bit time s t2 off bit time s t3 modulated output ?on? 0.8 1 1.2 s t4 modulated output ?off? 0.8 1 1.2 s t5 modulated output ?on? 0.8 1 1.2 s t6 modulated output ?off? 0.8 1 1.2 s notes: 1. irrx: crc bit 1: 1 = rcv active low nirrx: crc bit 1: 0 = rcv active high (default) mirrx, nmirrx are t he modulated outputs. t1 t2 t3 t4 t5 t6 01010011011 data irtx nirtx mirtx nmirtx figure 10 - amplitude shift keyed ir receive timing
19 infrared data association description the infrared data association (irda) was created to develop an interoperable, low-cost, low-power, half-duplex serial data interconnection standard that supports a walk-up, point-to-point user model that is adaptabl e to a wide range of appliances and devices. the irda serial infrared data link standard , version 1.1 is the standar d to which the smsc IRCC conforms. relevant irda documents in this specification include t he sir-physical layer specification , version 1.1, oc tober 17, 1995, the sir-link access protocol (irlap), version 1.0, june 23, 1994, and t he link management protocol (irlmp), version 1.1, january 23, 1996. the high-speed extensions (fir) to the irda physical layer as described in the sir-physical layer specification appear as alternate modulation and demodulation paths for data from irlap bound for the ir medium and are transparent to irlap as it is defined for sir. ir hardware and software must comply as a system with the entire family of irda specifications, including the sir/fir-physical layer specifications , irlap , and irlmp . a block diagram of one end of an irda link that includes the sir and fir physical implementations is shown in figure 11. sir interaction pulse the sir interaction pulse (sip) is intended to guarantee non-disruptive c oexistence with sir- only systems which might otherwise interfere with fast ir links. a sip is defined as a 1.6 microsecond transmitter on pulse followed by 7.1 microseconds of off time (figure 12). once a fast connection has been es tablished the station must generate one sip every 500ms. 1.152mb/s 4mb/s sir encode r sce ir transceiver module ir out ir in fir encoders uart sip figure 11 - IRCC i rda block diagram
20 the sir interaction pulse is controlled by the IRCC configuration register sip enable bit and a timer. the IRCC transmits an sir interaction pulse every 500ms when the sip enable is active, an irda fir mode has been selected, and the transmitter or receiver is not otherwise engaged. the timer that controls the sip pulse is reset whenever 1) the sip enable is inactive, 2) an active fir frame is being transmitted or received or, 3) during an active sip pulse. the timer is decrementing whenever the sip enable bit is active and the sip pulse generator, the transmitter, and the receiver are inactive. when the timer reaches zero, the sip pulse generator is activated (figure 13). 1.6us 8.7us si p acti ve si p tim e figure 12 - sir interaction pulse active frame sip enable reset sip timer sip timer countdow n active si p time sip timer zero figure 13 - sip control timing
21 hdlc bof counting the IRCC can account for system-dependent limitations such as l ong interrupt latencies and transceiver stabilization times by increasing the number of sta flags at the beginning of every hdlc frame (figure 14). the bof count register contains the number additional start flags that are to be appended to the standard bof characters. note: the bof count extensions only apply to messages that start from an idle line state; i.e., bof counting does not apply to brick walled messages. hdlc back-to-back frame transmission hdlc back-to-back, or brick walled frames are allowed with two or more flags, '7e'hex, in between. if two consec utive frames are not back-to-back, the gap between the last sto flag of the first frame and the first sta field of the second frame are separated by at least seven bit times (abort sequence). the irda fir 1.152mbps and .576mbps physical layer specification allows back-to-back message packets with three flag characters which act as the closing flag of the first frame and the opening flags of the brick walled packet. additional flags can be added by programming the brick wall count register (figure 15). note: the bof count extensions do not apply to brick walled messages. addr 8-bit address field sta '01111110' binary data 8-bit control field plus up to 2k - 3 bytes information field sta '01111110' binary bof count register appends 0 - 4095 flags to beginning of frame figure 14 - extended beginning-of-frame
22 4ppm bof counting the IRCC can account for system-dependent limitations such as l ong interrupt latencies and transceiver stabilization times by increasing the number of pa flags at the beginning of every 4ppm frame (figure 16). the bof count register contains the number of additional pa bytes that are to be appended to the standard 4ppm bof characters. note: the bof count extensions only apply to messages that start from an idle line state; i.e., bof counting does not apply to brick walled messages. addr 8-bit address field sto '01111110' binary fcs ccitt 16-bit crc data 8-bit control field plus up to 2k - 3 bytes information field brick walled frame previous frame sta '01111110' binary bw count register inserts 0 - 4095 flags between brick walled frames sta '01111110' binary figure 15 - brick walled hdlc frames addr 8-bit address field data 8-bit control field plus up to 2k - 3 bytes information field bof count register appends 0 - 4095 pa bytes to beginning of frame ... pa (#16) pa (#1) sta 8-bit start field figure 16 - 4ppm extended bof
23 4ppm back-to-back frame transmission back-to-back, or brick walled frames are allowed with 32 or more pa flag bytes between the sto field of the first frame and the sta field of the second frame. additional flags can be added by programming the brick wall count register. note: the bof count ext ensions do not apply to brick walled messages. addr 8-bit address field 16-byte pa sequence data 8-bit control field plus up to 2k - 3 bytes information field brick walled frame previous frame sta bw count register inserts 0 - 4095 pa bytes between brick walled frames sto 16-byte pa sequence figure 17 - brick walled 4mbps frames
24 registers the IRCC is partially enabled through binary controls found in two 8-by te register banks. the banks, the ace550 uart controls and the sce controls, are selected with the nace and nsce register-bank selector inputs found in the interface description. if nace is zero, the three least significant bits of the host address bus decode the 16550a uart control registers. if nsce is zero, the sce control bank is address ed. all of the IRCC registers are 8 bits wide. ace uart controls the table below (table 12) lists the ace uart control registers (see the ace uart section) . table 12 - 16550a uart addressing dlab a2 a1 a0 direction register name 0 0 0 0 read receive buffer 0 0 0 0 write transmit buffer 0 0 0 1 read/write interrupt enable x 0 1 0 read interr upt identification x 0 1 0 write fifo control x 0 1 1 read/write line control x 1 0 0 read/write modem control x 1 0 1 read/write line status x 1 1 0 read/writ e modem status x 1 1 1 read/write scratchpad 1 0 0 0 read/write divisor (lsb) 1 0 0 1 read/write divisor (msb)
25 sce controls the IRCC sce registers are arranged in 7-byte blocks. of the eight possible register blocks, five are used in this implementation. the master block control register controls access to the register blocks. table 13 lists all of the sce registers in all blocks. table 13 - sce register addressing block address direction register name x 7 r/w master control 0 0 r/w data register 0 1 ro interrupt identification 0 2 r/w interrupt enable 0 3 ro line status (read) 0 3 wo line status address (write) 0 4 r/w line control a 0 5 r/w line control b 0 6 r/w bus status 1 0 r/w sce configuration a 1 1 r/w sce configuration b 1 2 r/w fifo threshold 2 0 r/w consumer ir control 2 1 r/w consumer ir carrier rate 2 2 r/w consumer ir bit rate 3 0 ro smsc id (high) 3 1 ro smsc id (low) 3 2 ro chip id 3 3 ro version number 3 4 ro irq level dma channel 4 0 r/w irda control bof count (high) 4 1 r/w bof count (low) 4 2 r/w brick wall count (low) 4 3 r/w bw count (high) tx data size (high) 4 4 r/w tx data size (low) 4 5 r/w rx data size (high) 4 6 r/w rx data size (low)
26 master block control register the master block control register contains the IRCC power down bit, two reset bits, the master interrupt enable bit, and the register block select lines (table 14). address seven is solely reserved for the master block control register. if the nsce input is zero, the mbc is always visible, regardless of the state of the register block select lines. table 14 - sce master block control register address direction description default a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 r/w master block c ontrol register '00'hex power down master reset master int en. error reset register block select register block select, bits 0-2 the register block select bits enable access to each of the eight possible register blocks. to access a register block ot her than the default (0), write a 3-bit register block number to the least significant bits of t he master block control register. all subsequent reads and writes to addresses 0 through 6 will access the registers in the new block. to return to register block 0, rewrite zeros to the register block select bits. error reset, bit 4 writing a one to the error reset bit will return all of the sce line status r egister bits (register block zero) to their inactive states and reset the message count bits to zero. master interrupt enable, bit 5 setting the master interrupt enable to a one enables all of the sce in terrupts only if their individual controls are enabled. setting this bit to a zero disables all sce interrupts regardless of the state of their individual enables. master reset, bit 6 setting the master reset bit to a one forces data in the sce registers and sce logical blocks into the power-on-reset state. the master reset bit is reset to zero following the reset operation. note: the legacy bits (register block one, address zero, bits d0-d6) are unaffected by master reset. power down, bit 7 setting this bit to a one causes only the sce to enter the low-power st ate. power down mode does not preclude access to the master block control register so that this mode can be maintained entirely under software control.
27 register block zero register block zero contains the sce data register, the interrupt c ontrol/status registers, the line control/status registers, and the bus status register (table 15). typically, the controls in register block zero are used during irda fir and consumer ir message transactions. table 15 - register block zero address directio description default a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 r/w data register 0 0 1 ro interrupt identification register '00'hex active frame eom raw mode fifo 0 1 0 r/w interrupt enable register '00'hex active frame eom raw mode fifo 0 1 1 ro line status register (read) '00'hex under- run over - run frame error size error crc error frame abort 0 1 1 wo line status address register (write) status register address 1 0 0 r/w line control register a '00'hex fifo reset fast g. p. data raw tx raw rx abort data done 1 0 1 r/w line control register b '00'hex sce modes bits sip enable brick wall message count 1 1 0 ro bus status register '00'hex not empty fifo full time- out data register (address 0) the data register is the fifo access port. typically, the user will only write to the fifo when transmitting and read from the fifo when receiving. the host always has read access to the fifo regardless of the state of the sce modes bits or the loopback bit. host read access to the fifo is blocked when the fifo is empty. the host has write access to the fifo only when the loopback bit is inactive and the sce modes bits are zero or transmit mode is enabled. host write access to the fifo is blocked when the fifo is full. interrupt identification register (address 1) active frame, bit 7 when this bit is one, an active frame has occurred (see the active frame indicator section). the active frame typically indicates that the sce receiver has detected a valid incoming irda fir or tv remote start-of-frame sequence. reading the in terrupt identification register resets the active frame bit.
28 eom, bit 6 when this bit is one, an end of message has occurred. the eom indicates the end of an irda fir eof or abort. during consumer ir messages eom also indicates fifo underruns/ overruns and dma terminal counts. reading the interrupt identificati on register resets the eom bit. raw mode interrupt, bit 5 when this bit is one, a raw mode interrupt has occurred. the raw mode interrupt indicates that the raw rx control bit has gone active. reading the interrupt ident ification register resets the raw mode interrupt bit. fifo interrupt, bit 4 when this bit is one, a fifo interrupt has occurred. the fifo interrupt indicates that the fifo interrupt enable is active and either a txservreq or an rxservreq has occurred. the fifo interrupt bit is cleared when the interrupt is disabled; i.e., reading the interrupt identification register does not reset the fifo interrupt bit. interrupt enable register (address 2) setting any of the bits in this register to one enables the associated interrupt (see the interrupt identificati on register) onto the interrupt request (irq) line defined in the interface description. interrupts will only occur if both the interrupt enabl e bit and the master interrupt enable bit (see the master block control register) are active. the interrupt enables do not affect the bits in the interrupt id (iid) register, except for the fifo interrupt. for example, a raw mode interrupt that occurs while the raw mode interrupt enable is inactive will alter the raw mode interrupt indicator in the iid register but will not activate the irq line. toggling the fifo interrupt enable will affect the fifo interrupt indicator in the iid register. line status register(s) (address 3) error indicators (read-only) there are eight line stat us registers at address 3. each register is read-only and is accessed using the three status register address bits, also located at this address. the fifo underrun, fifo overrun, frame error, size error, frame abort, and crc error flags indicate the status of any one of eight irda fir message frames. the error indicators, in all registers, are reset following a master reset, power-on-reset, and error reset (see the master block control register). the error indicators for the current status register only (s ee the message count bits) are reset following a valid irda bof sequence. fifo underrun, bit 7 the fifo underrun bit gets set to one when the irda fir transmitter runs out of fifo data and the data done bit is not active. fifo overrun, bit 6 the fifo overrun bit gets set to one when the irda fir receiver tries to write data to the fifo when the fifo full flag is active. frame error, bit 5 the frame error bit gets set to one when irda framing errors are detec ted; for example, hdlc pulse-widths greater than one bit-cell, and invalid framing fields (see the section framing errors). size error, bit 4 the size error bit is set to one whenever the irda fir receiver decrements the rx data size count to zero before the end-of-frame, or whenever the the brick wall bit is inactive and the irda fir transmitter decrements the tx data size count to zero before fifo empty goes active.
29 crc error, bit 3 the crc error bit is set to one following frame- check-sequence errors in irda fir receive message frames. frame abort, bit 2 the frame abort bit is set to one following; 1) a forced abort, i.e. after setting the abort bit to one in line control register a; 2) an irda fir fifo underrun with the data done bit inactive during transmit; 3) an irda fir fifo overrun during receive; 4) framing errors in irda fir payload data during receive. note: the frame abort bit will not go active during transmit if the tx data size register decrements to zero when the last byte is read from the fifo with the data done bit not set. status register address, bits 0 - 2 (write- only) three status register address bits control software access to, and reside at the same address as, the line stat us registers. the status register addre ss bits are write-only and occupy bits d0 to d2. to access any one of the eight line status regist ers, first write the address of the appropriate register (0 - 7), then read the register 's contents. line control register a (address 4) fifo reset, bit 7 when set to one, the fifo reset bit clears the fifo full and not empty flags in the 128-byte sce fifo. the fifo reset bit is automatically set to zero following the re-initialization. fast, bit 6 the fast bit controls t he state of an uncommitted IRCC output, fast. the bit is read/write. general purpose data, bit 5 the general purpose data bit controls the state of an uncommitted IRCC output, gp data. the bit is read/write. raw tx, bit 4 the raw tx bit controls the state of the infrared emitter in raw ir mode. the bit is read/write. raw rx, bit 3 the raw rx bit repres ents the state of the infrared detector in raw ir mode. the bit is read-only. abort, bit 2 the abort bit is used to terminate transmit messages in progress; i.e., once the transmitter has been enabled and the line is active. when the abort bit is one, the current transmit message is terminated, the eom flag is activated and the sce fifo is cleared. the abort bit is reset to zero by the end-of-frame. abort is used for irda fir transmit mode, only. data done, bit 1 when set to one, the data done bit is used during transmit to distinguish an end-of-valid- message-data condition from a fifo underrun that indicates incomplete message data. terminal count automatically activates the data done bit during dma operations. note : the data done bit is not activated by tc during receive operations. data done is automatically reset to zero following the end of a message only if the fifo is empty. line control register b (address 5) sce modes, bits 6 - 7 the sce modes bits enable the sce transmitter and receiver (table 16). these bits are r/w and must be manually reset by the host following irda message transactions. the sce modes bits are automatically reset by the hardware following consumer ir messages. note: the sce modes bits must be zero for loopback tests.
30 table 16 - sce modes d7 d6 mode description 0 0 receive/transmit disabled (default) 0 1 transmit mode 1 0 receive mode 1 1 undefined transmit mode transmit mode enables the sce irda fir and consumer ir transmitters whenever tc goes active, or the fifo threshold has been exceeded. in transmit mode, the sce fifo input is connected to the host system data bus and the fifo output is connected to the sce transmitter input. transmit mode is strictly software controlled when the irda fir encoders are active. the consumer ir encoder will reset transmit mode in hardware following the rising edge of nactive frame following a fifo underrun. receive mode receive mode enables the sce irda fir and consumer ir receivers. in receive mode, the sce fifo output is connected to the host system data bus, the fi fo input is connected to the sce receiver output. receive mode is strictly software controlled when the irda fir encoders are active. the consumer ir encoder will reset receive mode in hardware following the rising edge of nactive frame following a fifo underrun or tc. sip enable, bit 5 if the sip enable is one, an sir interaction pulse occurs every 500ms if an irda fir mode has been selected and the transmitter or receiver is not otherwise engaged. brick wall, bit 4 when the brick wall bit is active the IRCC sends back-to-back irda fir frames separated by the number of additional flags specified in the brick wall count register. note : bof counts do not apply during brick walled messages. the data size register can also be used when the brick wall bit is active to send back-to-back irda fir frames when the dma data block is larger than the irda message length. in this case, if the maximum number of data bytes according to the data size register hav e been transferred and the dma terminal count or the fifo empty flags have not been activated the next message is brick walled to the previous message (table 17). the brick wall bit is software controlled only.
31 table 17 - message flow control brick wall enable data done bit fifo empty state after eof description 1 1 0 bof brick wall next message 1 1 1 idle multi-frame window complete, reset data done bit 1 0 0 bof brick wall next message 1 0 1 bof brick wall next message (possible underrun) 0 1 0 idle re-enable transmitter for next message 0 1 1 idle single message complete, reset data done bit 0 0 0 idle single message complete, datasize counter = 0 0 0 1 idle single message complete, datasize counter = 0 message count, bits 0 - 3 the four message count bits control hardware access to the line status registers and are unaffected by the status r egister address bits. the message count bits also indicate the system message-state. for ex ample, if the message count bits are zero, i. e. the power-up default, line status register zero is active, although undefined because no mess ages have been sent or received. the message count bits are incremented after every acti ve frame. at point a in figure 18, for exam ple, the rising edge of nactive frame increm ents message count by one indicating that the first message has been received; i.e., line status register #1 (status register address 0) is valid, and line status register #2 is currently active, although undefined. hardware prevents the message count register fr om exceeding eight ('1000'binary). note : irda messages beyond eight frames are ignored. nactive frame message count (0000) 0001 a 0010 0011 figure 18 - message count example
32 bus status register (address 6) fifo indicators (read-only) the fifo indicators reflec t the current status of the sce fifo. fifo not empty, bit 7 the fifo not empty bit when set to one indicates that there is data in the sce fifo. fifo full, bit 6 the fifo full bit when set to one indicates that there is no room for data in the sce fifo. time-out, bit 5 the time-out bit is the iochrdy time-out error bit. the time-out bit when set to one indicates that an iochrdy time-out error has occurred. time-out is reset by the IRCC system reset (see interface description) following a read of the bus status register, and following a master reset (see master block control register). register block one register block one cont ains the sce control registers (table 18). typically, the controls in register block one ar e needed to configure the sce before message transactions can occur. table 18 - register block one address direction description default a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 r/w sce configuration register a '02'hex aux ir block control bits half duplx tx po- larity rx po- larity 0 0 1 r/w sce configuration register b '00'hex output mux bits loop- back lpbck tx crc no wait string move dma burst dma enable 0 1 0 r/w fifo threshold register '00'hex 0 1 1 1 0 0 1 0 1 1 1 0 sce configuration register a (address 0) auxiliary ir, bit 7 when the auxiliary ir bit is one and the active device is routed through the output multiplexer to the ir port or the com port, the transmit signal also appears at the auxiliary port. block control, bits 3 - 6 the block control bits select one of the eight IRCC operational modes (table 19). the three low-order block control bits are equivalent to the ir mode bits in the chip-l evel configuration space of earlier devices; e.g., the fdc37c93x ir option register, serial port 2, logical device 5, register 0xf1. provisions have been made in legacy devices to accommodate ir mode selection through either the chip-level configuration registers or the IRCC block control bits; i.e., the last write from either source determines the current mode selection and is visible in both registers.
33 table 19 - IRCC logical block controls d6 d5 d4 d3 mode description 0 0 0 0 com 16550 uart com port (default) 0 0 0 1 irda sir - a up to 115.2kbps, variable 3/16 pulse 0 0 1 0 ask ir amplitude shift keyed ir interface 0 0 1 1 irda sir - b up to 115.2kbps, fixed 1.6us pulse 0 1 0 0 irda hdlc includes.576mbps & 1.152mbps 0 1 0 1 irda4ppm includes 4mbps 0 1 1 0 consumer tv remote 0 1 1 1 raw ir direct ir diode control 1 x x x other reserved half duplex, bit 2 when half duplex is zero (default), the 16550a is in full duplex mode. the half duplex bit only supports the 16550a uart; i.e., this bit has no effect on the IRCC sce. the half duplex bit is analogous to the chip-level configuration register half duplex bit and has the same affect on the uart. provisions must be made in legacy devices to accommodate half duplex selection through either the chip -level configuration registers or the IRCC half duplex bit; i.e., the last write from either source determines the current mode selection and is visi ble in both registers. tx/rx polarity bits, 0 - 1 the tx and rx polarity bits define the active states for signals enteri ng and exiting the output multiplexer ports. IRCC active states are typically decoded as zero. the tx polarity bit default is one; the rx polarity bit default is zero. for backward compatibility, the tx and rx polarity bits do not apply to com mode; i.e., when the block control bits are zero. the relationship between the ou tput multiplexer port signals and the polarity bits is an exclusive-or (table 20). for example, if the irrx pin in the output multiplexer is one and the rx polarity bit is zero, the signal is inactive and therefore decoded as a one. the IRCC tx polarity bit (bit 1) is equivalent to the transmit polarity bit in the chip-level configuration space of earlier devices; e.g., the fdc37c93x ir option register, serial port 2, logical device 5, register 0xf1. the rx polarity bit (bit 0) is equivalent to the receive polarity bit in the same register. provisions have been made in legacy devices to accommodate polarity bit selection through either the chip-level configuration registers or the sce registers; i.e., the last write from eit her source determines the current polarity bit value and is visible in both registers. table 20 - tx/rx polarity bit effects signal polarity bit decoded signal 0 0 0 0 1 1 1 0 1 1 1 0
34 sce configuration register b (address 1) output mux, bits 7 - 6 the output mux bits select the output multiplexer port for the active encoder/decoder (table 21). inactive outputs depend on the state of the tx polarity bit when the output mux bits are both high, otherwise inactive outputs are always low. the output mux bits are equivalent to the 93x ir option register bits 6-7. the ir location mux, bit 6, in the 93x ir option register is equivalent to output mux bit, d6; bit 7 (reserved) in the 93x ir option register is equivalent to output mux bit, d7. provisions have been made in legacy devices to accommodate output mult iplexer port selection through either the chip -level configuration registers or the output mux bits; i.e., the last write from either source determines the current port selection and is visi ble in both registers. table 21 - IRCC output multiplexer d7 d6 mux. mode 0 0 active device to com port (default) 0 1 active device to ir port 1 0 active device to aux port 1 1 outputs inactive loopback, bit 5 the loopback bit configures the fifo and enables the transmitter/receiver for loopback testing. the sce modes bits must be set to zero before activating the loopback bit. when the loopback bit is one, the sce enters a full- duplex mode with internal loopback capability for testing. the crc generat or can be selectively reconfigured for either transmit or receive. the 128-byte fifo input is connected to the sce receiver output, the fifo output is connected to the sce transmit input. for irda fir loopback tests the loopback bit must be set to zero to exit loopback mode. consumer ir loopback tests reset the loopback bit automatically when the rx data size register reaches zero. provisions must be made following loopback tests in all modes to verify the rx message data in the fifo. loopback transmit crc, bit 4 when the loopback transmit crc bit is set to one, the crc generator is used by the transmitter during loopback testing regardless of the state of the crc sele ct bit. otherwise, the crc generator is connect ed to the receiver (table 22). table 22 - hardware crc programming loopback bit crc select loopback tx crc bit hardware description 0 0 x no crc generation, no crc checking 0 1 x crc generation., crc checking 1 0 0 no crc generation, no crc checking 1 0 1 crc generation, no crc checking 1 1 0 crc checking, no crc generation 1 1 1 crc generation, no crc checking
35 no wait, bit 3 when the no wait bit is one, the isa bus nsrdy signal goes active following the trailing edge of the isa i/o command and inactive following the rising edge (see zero wait state support). string move, bit 2 when the string move bit is one, the programmed i/o host interface is qualified by iochrdy (table 23). see iochrdy time-out. dma burst mode, bit 1 when the dma burst mode bit is one, dma burst (demand) mode is enabled. when the dma burst mode bit is zero, single byte dma mode is enabled (table 23). dma enable, bit 0 dma enable is connected to a signal in the interface description called dmaen that is used by the chip-level interface to tristate the IRCC dma controls when the dma interface is inactive. when the dma enable bit is one, the dma host interface is active (table 23). when the dma enable bit is zero (default), the ndack and tc inputs are dis abled and drq output is gated off. table 23 - i/o interface modes string move dma burst dma enable function 0 x 0 programmed i/o, no iochrdy 1 x 0 programmed i/o, uses iochrdy x 0 1 single byte dma mode x 1 1 demand mode dma fifo threshold register (address 2) the fifo threshold register contains the programmable fifo threshold count. the fifo threshold is programmable from 0 to 127. bit 7 in the fifo threshold register is read-only and will always return zero. fifo threshold values typically reflect the overall i/o performance characteristics of the hos t; the lower the value, the longer the interval between service requests and the faster the host must be to successfully service them. the same threshold value can be used for both i/o read and i/o write cases.
36 register block two register block two cont ains the consumer ir (tv remote) encoder/decoder configuration registers (table 24). table 24 - register block two address direction description default a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 r/w consumer ir (tv remote) control register '00'hex sync bit carrier off carrier range bits 0 0 1 r/w consumer ir carrier rate register '29'hex 0 1 0 r/w consumer ir bit rate register '37'hex 0 1 1 1 0 0 1 0 1 1 1 0 consumer ir control register (address 0) sync bit, bit 7 the sync bit enables the receiver bit-rate clock synchronization mechanisim. when the sync bit is one, receiver edge synchronization is enabled. carrier off, bit 2 the carrier off bit bypasses the consumer ir carrier generator/receiver. when the carrier off bit is one, the transmitter outputs a non- modulated sce nrz serial data stream at the programmed bit rate. also, when the carrier off bit is one, the receiver does not attempt to demodulate a carrier from the incoming data stream and samples the st ate of the pin diode at the programmed bit rate. carrier range, bits 0 - 1 the consumer ir carrier range bits set the carrier detect sensitivity of the receiver. the effects of this register are shown in table 11 - receive carrier sense range. consumer ir carrier rate register (address 1) the consumer ir carrier rate register programs the ask carrier frequency divider. the effects of this register are shown in table 9- representative carrier frequencies . consumer ir bit rate register (address2) the consumer ir bit rate register programs the transmit and receive bit-rate divider. the effects of this register are shown in table 10 - representative bit rates .
37 register block three register block three contains the IRCC block identifier registers. these read-only registers classify the hardware manufacturer, the device id, the version number, and host interface parameters. table 25 - register block three address direction description default a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 ro smsc id (high-byte) '10'hex 0 0 1 ro smsc id (low-byte) 'b8'hex 0 1 0 ro chip id 'f1'hex 0 1 1 ro version number '01'hex 1 0 0 ro irq level dma channel 1 0 1 1 1 0 smsc id (addresses 0 - 1) the smsc id registers contain a 16-bit manufacturer identificati on code. address zero contains the high byte of this code, address one contains the low byte. chip id (address 2) the chip id register spec ifically identifies this smsc product. version number (address 3) the version number r egister identifies the revision-level of the product referenced by the chip id register. irq level/ dma channel (address 4) irq level, bits 4 - 7 the irq level bits identify the current active irq number for this device. the value comes from the 4-bit irq level bus found in the interface description. dma channel, bits 0 - 3 the dma channel bits ident ify the current active dma channel number for this device. the value comes from the 4-bit dma channel bus found in the interface description.
38 register block four register block four cont ains the irda control registers. these regi sters control the irda message framing parameters, hdlc clock speed, and hardware crc selection. the registers are read/write. table 26 - sce register block four address direction description default a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 r/w irda control register 'c0'hex 1.152 selec t crc selec t bof count (high nibble) 0 0 1 r/w bof count (low byte) '00'hex 0 1 0 r/w brick wall count (low byte) '00'hex 0 1 1 r/w brick wall count (high nibble) tx data size (high nibble) '00'hex 1 0 0 r/w tx data size (low byte) '00'hex 1 0 1 r/w rx data size (high nibble) '00'hex 1 1 0 r/w rx data size (low byte) '00'hex irda control register/bof count high (address 0) 1.152 select, bit 7 when the 1.152 select bi t is one, the irda 1.152mbps hdlc-type fir data rate is selected. otherwise the .576mbps rate is chosen. this bit only applies to the sce clock when the block control bits select mode 2, irda hdlc. crc select, bit 6 when the crc select bit is one, a hardware- generated crc is appended to the frame payload data during irda fir message transactions (table 22). bof count high, bits 0 - 3 the bof count specif ies the number of additional flags that are used in a bof sequence. for example, at 1.152mbps, insert the bof count number of additional flag characters ('7e'hex) at t he start of every frame, excluding brick walled frames. at 4mbps insert the bof count number of additional pa bytes at the start of every fram e, excluding brick walled frames. the bof count is a 12-bit value. this register, bof count hi gh, is the bof count upper nibble. bof count low (address 1) the bof count low register is the lower byte of the bof count. brick wall count low (address 2) the brick wall count r egister specifies the number of additional interframe padding flags used for brick walled messages. the brick wall count is a 12-bit value. the brick wall count low register is the brick wall count lower byte. bw count high/tx data size high (address 3) brick wall count high, bits 4 - 7 the bw count high regist er is the upper nibble of the brick wall count. tx data size high, bits 0 - 3 the tx data size register specifies the irlap- negotiated maximum num ber of payload data bytes per irda transmit message frame if software crc is selected, or the irlap- negotiated maximum num ber of payload data bytes minus the number of crc bytes if hardware crc is selected. this register is used
39 to 1) constrain the transmitter to a valid irda frame size, 2) simplify multi-frame windowing for transmit data blocks that are larger than the maximum packet size and, 3) constrain the sce transmitter during loopback testing. note : only the tx data size register is used for irda fir loopback testing; only the rx data size register is required for consumer ir loopback tests. if the tx data size register is zero, the irda transmit message size is unlimited; i.e., the transmitter will operate until the fifo is empty. the tx data size high register is the tx data size high nibble. tx data size low (address 4) the tx data size low register is the tx data size low byte. rx data size high (address 5) rx data size high, bits 0 - 3 the rx data size register specifies the irlap- negotiated maximum num ber of payload data bytes per irda receive message frame. this register is used to check each irda fir receive frame for valid data size and to constrain the sce receiver during consumer ir loopback testing. note : only the rx data size register is required for consumer ir loopback tests; only the tx data size register is required for irda fir loopback tests. for consumer ir loopback tests, program the rx da ta size register with test_byte_count_1. if the rx data size register is zero the irda receive message size is unlimited; i.e., a size error cannot occur because frame size checking is disabled. the rx data size high register is the rx data size high nibble. rx data size low (address 6) the rx data size low register is the rxdata size low byte.
40 ace uart the smsc IRCC incorporates one full function uart compatible with the ns16450, the 16450 ace registers and the ns16550a. the uart performs serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. the data rates are independently programmable from 115.2k baud down to 50 baud. the character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. the uart contains a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. the uart is also capable of supporting the midi data rate. refer to the configuration register section of the smsc fdc37c669fr, fdc37c93xfr, or fdc37c957fr data sheet for information on disabling, power down and changing the base address of the uart. the interrupt from the uart is enabled by programming out2 of the uart to a logic "1". out2 being a logic "0" disables the uart's interrupt. register description addressing of the accessible registers of the serial port is shown below. the base addresses of the serial ports are defined by the configuration registers. the serial port registers are located at sequentially increasing addresses above these base addresses. the smsc IRCC uart register set is described below. table 27 - addressing the serial port dlab* a2 a1 a0 register name 0 0 0 0 receive buffer (read) 0 0 0 0 transmit buffer (write) 0 0 0 1 interrupt enable (read/write) x 0 1 0 interrupt identification (read) x 0 1 0 fifo control (write) x 0 1 1 line control (read/write) x 1 0 0 modem control (read/write) x 1 0 1 line stat us (read/write) x 1 1 0 modem stat us (read/write) x 1 1 1 scratchpad (read/write) 1 0 0 0 divisor lsb (read/write) 1 0 0 1 divisor msb (read/write *note: dlab is bit 7 of the line control register
41 the following section descr ibes the operation of the registers. receive buffer register (rb) address offset = 0h, dlab = 0, read only this register holds t he received incoming data byte. bit 0 is the least significant bit, which is transmitted and received first. received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the receive buffer register. the shift register is not accessible. transmit buffer register (tb) address offset = 0h, dlab = 0, write only this register contains the data byte to be transmitted. the transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. this shift register is loaded from the transmit buffer when the transmission of the previous byte is complete. interrupt enable register (ier) address offset = 1h, dlab = 0, read/write the lower four bits of th is register control the enables of the five interrupt sources of the serial port interrupt. it is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. similarly, setting the appropriate bits of this register to a hi gh, selected interrupts can be enabled. disabling the interrupt system inhibits the interrupt identificati on register and disables any serial port interrupt out of the smsc IRCC. all other system functions operate in their normal manner, including the line status and modem status registers. the contents of the interrupt enable register are described below. bit 0 this bit enables the received data available interrupt (and timeout inte rrupts in the fifo mode) when set to logic "1". bit 1 this bit enables the transmitter holding register empty interrupt when set to logic "1". bit 2 this bit enables the received line status interrupt when set to logic "1". the error sources causing the interrupt are overrun, parity, framing and break. the line status r egister must be read to determine the source. bit 3 this bit enables the modem status interrupt when set to logic "1". this is caused when one of the modem status regist er bits changes state. bits 4 through 7 these bits are always logic "0". fifo control register (fcr) address offset = 2h, dlab = x, write this is a write only regist er at the same location as the iir. this register is used to enable and clear the fifos, set the rcvr fifo trigger level. note: dma is not supported. bit 0 setting this bit to a logic "1" enables both the xmit and rcvr fifos. clearing this bit to a logic "0" disables both the xmit and rcvr fifos and clears all bytes from both fifos. when changing from fifo mode to non- fifo (16450) mode, data is automatically cleared fr om the fifos. this bit must be a 1 when other bits in this register are written to or they will not be properly programmed. bit 1 setting this bit to a logic "1" clears all bytes in the rcvr fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self- clearing.
42 bit 2 setting this bit to a logic "1" clears all bytes in the xmit fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self- clearing. bit 3 writting to this bit has no effect on the operation of the uart. the rxrdy and txrdy pins are not available on this chip. bit 4,5 reserved bit 7 bit 6 rcvr fifo trigger level 0 0 1 0 1 4 1 0 8 1 1 14 bit 6,7 these bits are used to set the trigger level for the rcvr fifo interrupt. interrupt identification register (iir) address offset = 2h, dlab = x, read by accessing this register, the host cpu can determine the highest priority interrupt and its source. four levels of priority interrupt exist. they are in descending order of priority: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the interrupt identific ation register (refer to interrupt control table). when the cpu accesses the iir, the serial port freezes all interrupts and indicates the highest priority pending interrupt to the cpu. during this cpu access, even if the serial port records new interrupts, the current indication does not change until access is completed. the contents of the iir are described below. bit 0 this bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. when bit 0 is a logic "0", an interrupt is pending and the contents of the iir may be used as a pointer to the appropriate internal service routine. when bit 0 is a logic "1", no interrupt is pending. bits 1 and 2 these two bits of the iir are used to identify the highest priority interrupt pending as indicated by the interrupt control table. bit 3 in non-fifo mode, this bit is a logic "0". in fifo mode this bit is set along with bit 2 when a timeout interrupt is pending. bits 4 and 5 these bits of the iir are always logic "0". bits 6 and 7 these two bits are set when the fifo control register bit 0 equals 1.
43 table 28 - interrupt control table fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error, parity error, framing error or break interrupt reading the line status register 0 1 0 0 second received data available receiver data available read receiver buffer or the fifo drops below the trigger level. 1 1 0 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time reading the receiver buffer register 0 0 1 0 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register
44 line control register (lcr) address offset = 3h, dlab = 0, read/write this register contains the format information of the serial line. the bit definitions are: bits 0 and 1 these two bits specify the number of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: bit 1 bit 0 word length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits the start, stop and parity bits are not included in the word length. bit 2 this bit specifies the num ber of stop bits in each transmitted or received serial character. the following table summarizes the information. bit 2 word length number of stop bits 0 -- 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2 note: the receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. bit 3 parity enable bit. when bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (the parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). bit 4 even parity select bit. when bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or check ed in the data word bits and the parity bit. when bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. bit 5 stick parity bit. when bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then detected by the receiver in the opposite state indicated by bit 4. bit 6 set break control bit. when bit 6 is a logic "1", the transmit data output (txd) is forced to the spacing or logic "0" stat e and remains there (until reset by a low level bit 6) regardless of other transmitter activity. this feature enables the serial port to alert a terminal in a communications system. bit 7 divisor latch access bit (dlab). it must be set high (logic "1") to access the divisor latches of the baud rate generator during read or write operations. it must be set low (logic "0") to access the receiver buffer register, the transmitter holding register, or the interrupt enable register. modem control register (mcr) address offset = 4h, dlab = x, read/write this 8 bit register contro ls the interface with the modem or data set (or device emulating a modem). the contents of the modem control register are described below.
45 bit 0 this bit controls the data terminal ready (ndtr) output. when bit 0 is set to a logic "1", the ndtr output is forced to a logic "0". when bit 0 is a logic "0", the ndtr output is forced to a logic "1". bit 1 this bit controls the request to send (nrts) output. bit 1 affects the nrts output in a manner identical to that described above for bit 0. bit 2 this bit controls the output 1 (out1) bit. this bit does not have an output pin and can only be read or written by the cpu. bit 3 output 2 (out2). this bit is used to enable an uart interrupt. when out2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. when out2 is a logic "1", the serial po rt interrupt outputs are enabled. bit 4 this bit provides the loopback feature for diagnostic testing of the serial port. when bit 4 is set to logic "1", the following occur: 1. the txd is set to the marking state(logic "1"). 2. the receiver serial input (rxd) is disconnected. 3. the output of the trans mitter shift register is "looped back" into the receiver shift register input. 4. all modem control inputs (ncts, ndsr, nri and ndcd) are disconnected. 5. the four modem co ntrol outputs (ndtr, nrts, and out2) are internally connected to the four modem control inputs. 6. the modem control output pins are forced inactive high. 7. data that is trans mitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the serial port. in the diagnostic mode, the receiver and the transmitter interrupts are fully operational. the modem control interrupts are also operational but the interrupts' sources are now the lower four bits of the modem contro l register instead of the modem control inputs. the interrupts are still controlled by the interrupt enable register. bits 5 through 7 these bits are permanently set to logic zero. line status register (lsr) address offset = 5h, dlab = x, read/ write bit 0 data ready (dr). it is set to a logic "1" whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic "0" by reading all of the data in the receive buffer register or the fifo. bit 1 overrun error (oe). bit 1 indicates that data in the receiver buffer register was not read before the next character was transferred into the register, thereby destroying the previous character. in fifo mode, an overrunn error will occur only when the fifo is full and the next character has been completely received in the shift register, the character in the shift regist er is overwritten but not transferred to the fifo. the oe indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the line status register is read. bit 2 parity error (pe). bit 2 i ndicates that the received data character does not hav e the correct even or odd parity, as selected by the even parity select bit. the pe is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the line status register
46 is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. bit 3 framing error (fe). bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). the fe is reset to a logic "0" whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. the serial port will try to resynchronize after a framing error. to do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. bit 4 break interrupt (bi). bit 4 is set to a logic "1" whenever the received data input is held in the spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). the bi is reset after the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. restarting after a break is received, requires the serial data (rxd) to be logic "1" for at least 1/2 bit time. note: bits 1 through 4 are the error conditions that produce a receiver li ne status interrupt whenever any of the corresponding conditions are detected and the inte rrupt is enabled. bit 5 transmitter holding register empty (thre). bit 5 indicates that the serial po rt is ready to accept a new character for transmission . in addition, this bit causes the serial port to issue an interrupt when the transmitter holding register interrupt enable is set high. the thre bit is set to a logic "1" when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic "0" whenever the cpu loads the transmitter holding register. in the fifo mode this bit is set when the xmit fifo is empty, it is cleared when at least 1 byte is written to the xmit fifo. bit 5 is a read only bit. bit 6 transmitter empty (temt). bit 6 is set to a logic "1" whenever the transmitter holding register (thr) and transmitter shift register (tsr) are both empty. it is reset to logic "0" whenever either the thr or tsr contains a data character. bit 6 is a read only bit. in the fifo mode this bit is set whenever the thr and tsr are both empty, bit 7 this bit is permanently set to logic "0" in the 450 mode. in the fifo mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the fifo. this bit is cleared when the lsr is read if there are no subsequent errors in the fifo. modem status register (msr) address offset = 6h, dlab = x, read/ write this 8 bit register provides the current state of the control lines from the modem (or peripheral device). in addition to this current state information, four bits of the modem status register (msr) provide change information.
47 these bits are set to logic "1" whenever a control input from the modem changes state. they are reset to logic "0" whenever the modem status register is read. bit 0 delta clear to send (dcts). bit 0 indicates that the ncts input to the chip has changed state since the last time the msr was read. bit 1 delta data set ready (ddsr). bit 1 indicates that the ndsr input has changed state since the last time the msr was read. bit 2 trailing edge of ring indicator (teri). bit 2 indicates that the nri input has changed from logic "0" to logic "1". bit 3 delta data carrier detect (ddcd). bit 3 indicates that the ndcd input to the chip has changed state. note: whenever bit 0, 1, 2, or 3 is set to a logic "1", a modem status in terrupt is generated. bit 4 this bit is the complement of the clear to send (ncts) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to nrts in the mcr. bit 5 this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to dtr in the mcr. bit 6 this bit is the complement of the ring indicator (nri) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to out1 in the mcr. bit 7 this bit is the complement of the data carrier detect (ndcd) input. if bit 4 of the mcr is set to logic "1", this bit is equival ent to out2 in the mcr. scratchpad register (scr) address offset =7h, dlab =x, read/write this 8 bit read/write regist er has no effect on the operation of the serial port. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. programmable baud rate generator (and divisor latches dlh, dll) the serial port contains a programmable baud rate generator that is capable of taking any clock input (dc to 3 mhz) and dividing it by any divisor from 1 to 65535. this output frequency of the baud rate generator is 16x the baud rate. two 8 bit latches store the divisor in 16 bit binary format. these divisor latches must be loaded during initialization in order to insure desired operation of the baud rate generator. upon loading either of the divisor latches, a 16 bit baud counter is immediately loaded. this prevents long counts on initial load. if a 0 is loaded into the brg registers the output divides the clo ck by the number 3. if a 1 is loaded the output is the inverse of the input oscillator. if a two is loaded the output is a divide by 2 signal with a 50% duty cycle. if a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. the input clock to the brg is the 24 mhz crystal divided by 13, giving a 1.8462 mhz clock. table 29 shows the baud rates possible with a 1.8462 mhz crystal.
48 effect of the reset on register file the reset function table (table 30) details the effect of the reset input on each of the registers of the serial port. fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr bit 0 = "1", ier bit 0 = "1"), rcvr interrupts occur as follows: a. the receive data available interrupt will be issued when the fifo has reached its programmed trigger level; it is cleared as soon as the fifo drops below its programmed trigger level. b. the iir receive data available indication also occurs when the fifo trigger level is reached. it is cleared when the fifo drops below the trigger level. c. the receiver line stat us interrupt (iir=06h), has higher priority than the received data available (iir=04h) interrupt. d. the data ready bit (lsr bit 0)is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo timeout interrupts occur as follows: a. a fifo timeout interrupt occurs if all the following conditions exist: ? at least one character is in the fifo ? the most recent serial character received was longer than 4 continuous character times ago. (if 2 stop bits are programmed, the second one is included in this time delay.) ? the most recent cpu read of the fifo was longer than 4 continuous character times ago. ? this will cause a maximum character received to interrupt issued delay of 160 msec at 300 baud with a 12 bit character. b. character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baudrate). c. when a timeout interr upt has occurred it is cleared and the timer reset when the cpu reads one character from the rcvr fifo. d. when a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (fcr bit 0 = "1", ier bit 1 = "1"), xmit interrupts occur as follows: a. the transmitter holding register interrupt (02h) occurs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. b. the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre=1 and there have not been at least two bytes at the same time in the transmitte fifo since the last thre=1. the transmitter interrupt after changing fcr0 will be immediate, if it is enabled. character timeout and rcvr fifo trigger level interrupts have the sme pr iority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt. fifo polled mode operation with fcr bit 0 = "1" resetting ier bits 0, 1, 2 or 3 or all to zero puts the uart in the fifo polled mode of operation. si nce the rcvr and are controlled separately, eit her one or both can be in the polled mode of operation.
49 in this mode, the user's program will check rcvr and xmitter status via th e lsr. lsr definitions for the fifo polled mode are as follows: - bit 0=1 as long as there is one byte in the rcvr fifo. - bits 1 to 4 specify which error(s) have occurred. character error status is handled the same way as when in the interruptmode, the iir is not affected since eir bit 2=0. - bit 5 indicates when the xmit fifo is empty. - bit 6 indicates that both the xmit fifo and shift register are empty. - bit 7 indicates whether there are any errors in the rcvr fifo. there is no trigger level reached or timeout condition indicated in the fifo polled mode, however, the rcvr and xmit fifos are still fully capable of holding characters. table 29 - baud rates using 1.8462 mhz clock (24 mhz/13) desired baud rate divisor used to generate 16x clock percent error difference between desired and actual* crc: bit 7 or 6 50 2304 0.001 x 75 1536 - x 110 1047 - x 134.5 857 0.004 x 150 768 - x 300 384 - x 600 192 - x 1200 96 - x 1800 64 - x 2000 58 0.005 x 2400 48 - x 3600 32 - x 4800 24 - x 7200 16 - x 9600 12 - x 19200 6 - x 38400 3 0.030 x 57600 2 0.16 x 115200 1 0.16 x 230400 32770 0.16 1 460800 32769 0.16 1 * note: the percentage error for all baud rates, exc ept where indicated otherwise, is 0.2%.
50 table 30 - reset function table register/signal reset control reset state interrupt enable register reset all bits low interrupt identification reg. reset bit 0 is high; bits 1 thru 7 low fifo control reset all bits low line control reg. reset all bits low modem control reg. reset all bits low line status reg. reset all bits low except 5, 6 high modem status reg. reset bits 0 - 3 low; bits 4 - 7 input txd1, txd2 reset high intrpt (rcvr errs) reset/read lsr low intrpt (rcvr data ready) reset/read rbr low intrpt (thre) reset/readiir/write thr low out2b reset high rtsb reset high dtrb reset high out1b reset high rcvr fifo reset/fcr1*fcr0/_fcr0 all bits low xmit fifo reset/fcr1*fcr0/_fcr0 all bits low
51 table 31 - register summary for an individual uart channel register address* register name register symbol bit 0 bit 1 addr = 0 dlab = 0 receive buffer register (read only) rbr data bit 0 (note 1) data bit 1 addr = 0 dlab = 0 transmitter holding register (write only) thr data bit 0 data bit 1 addr = 1 dlab = 0 interrupt enable register ier enable received data available interrupt (erdai) enable transmitter holding register empty interrupt (ethrei) addr = 2 interrupt ident. register (read only) iir "0" if interrupt pending interrupt id bit addr = 2 fifo control register (wri te only) fcr fifo enable rcvr fifo reset addr = 3 line control register lcr word length select bit 0 (wls0) word length select bit 1 (wls1) addr = 4 modem control register mcr data terminal ready (dtr) request to send (rts) addr = 5 line status register lsr data ready (dr) overrun error (oe) addr = 6 modem status register msr delta clear to send (dcts) delta data set ready (ddsr) addr = 7 scratch register (note 4) scr bit 0 bit 1 addr = 0 dlab = 1 divisor latch (ls) ddl bit 0 bit 1 addr = 1 dlab = 1 divisor latch (ms) dlm bit 8 bit 9 *dlab is bit 7 of the line control register (addr = 3). note 1: bit 0 is the least signi ficant bit. it is the first bit serially transmitted or received. note 2: when operating in the xt mode, this bit will be se t any time that the transmitter shift register is empty.
52 table 31 - register summary for an individual uart channel (continued) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 enable receiver line status interrupt (elsi) enable modem status interrupt (emsi) 0 0 0 0 interrupt id bit interrupt id bit (note 5) 0 0 fifos enabled (note 5) fifos enabled (note 5) xmit fifo reset dma mode select (note 6) reserved reserved rcvr trigger lsb rcvr trigger msb number of stop bits (stb) parity enable (pen) even parity select (eps) stick parity set break divisor latch access bit (dlab) out1 (note 3) out2 (note 3) loop 0 0 0 parity error (pe) framing error (fe) break interrupt (bi) transmitter holding register (thre) transmitter empty (temt) (note 2) error in rcvr fifo (note 5) trailing edge ring indicator (teri) delta data carrier detect (ddcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 note 3: this bit no longer has a pin associated with it. note 4: when operating in the xt mode, this register is not available. note 5: these bits are always zero in the non-fifo mode. note 6: writing a one to this bit has no effe ct. dma modes are not supported in this chip.
53 notes on serial port operation fifo mode operation: general the rcvr fifo will hold up to 16 bytes regardless of which trigger level is selected. tx and rx fifo operation the tx portion of the uart transmits data through txd as soon as the cpu loads a byte into the tx fifo. the uart will prevent loads to the tx fifo if it currently holds 16 characters. loading to the tx fifo will again be enabled as soon as the next character is transferred to the tx shift register. these capabilities account for the largely autonomous oper ation of the tx. the uart starts the above operations typically with a tx interrupt. the chip issues a tx interrupt whenever the tx fifo is empty and the tx interrupt is enabled, except in the following instance. assume that t he tx fifo is empty and the cpu starts to load it. when the first byte enters the fifo the tx fi fo empty interrupt will transition from active to inactive. depending on the execution speed of the service routine software, the uart may be able to transfer this byte from the fifo to the shift register before the cpu loads another byte. if this happens, the tx fifo will be empty again and typically the uart's interrupt line would transiti on to the active state. this could cause a system with an interrupt control unit to record a tx fifo empty condition, even though the cpu is current ly servicing that interrupt. therefore, after the first byte has been loaded into the fi fo the uart will wait one serial character transmission time before issuing a new tx fifo empty interrupt. this one character tx interrupt delay will remain active until at least two bytes have been loaded into the fi fo, concurrently. when the tx fifo empties after this condition, the tx interrupt will be activated without a one character delay. rx support functions and operation are quite different from those described for the transmitter. the rx fifo receives data until the number of bytes in the fifo equals the selected interrupt trigger level. at that time if rx interrupts are enabled, the uart will issue an interrupt to the cpu. the rx fifo will continue to store bytes until it holds 16 of them. it will not accept any more data when it is full. any more data entering the rx shift register will se t the overrun error flag. normally, the fifo depth and the programmable trigger levels will give the cpu ample time to empty the rx fifo before an overrun occurs. one side-effect of having a rx fifo is that the selected interrupt trigger level may be above the data level in the fifo. this could occur when data at the end of the block contains fewer bytes than the trigger level. no interrupt would be issued to the cpu and the data would remain in the uart. to prevent the software from having to check for this situation the chip incorporates a timeout interrupt. the timeout interrupt is activated when there is a least one byte in the rx fifo, and neither the cpu nor the rx shift regi ster has accessed the rx fifo within 4 character times of the last byte. the timeout interrupt is cleared or reset when the cpu reads the rx fifo or another character enters it. these fifo related featur es allow optimization of cpu/uart transactions and are especially useful given the higer baud rate capability (256 kbaud).
54 t1 t5 t2 t4 t6 t3 niow nrtsx, ndtrx irqx nctsx, ndsrx, ndcdx irqx niow irqx nior nrix figure 19 - serial port timing
55 sce description the sce is a half-duplex synchronous serial communications controller t hat controls data flow between the bus interface i/o block and the irda fir and consumer ir (tv remote) encoders (figure 20). the sce also includes partial full-duplex loopback functionality for diagnostic testing. bit rates from .4kbps to 4mbps are supported. a ll of the sce register controls are located in the nsce-addressable 8- bit register blocks. framing the sce operates with and without framing. with framing implies that the sce works with the irda fir encoder/decoder so the required symbols for the non-payl oad data portions of the .576mbps, 1.152mbps and 4mbps packets can be generated. without fr aming implies that the sce acts simply as serial-to-parallel converter for the consumer ir (tv remote) encoder/ decoder. active frame indicator the sce signal nactiveframe is a pla state variable that is synchronized to both irda fir and consumer ir message frames. nactiveframe cycles high and low for each message frame, regardless of the state of the brick wall bit. nactiveframe is primarily used to trigger active frame interrupts and to advance the message count bits t hat control hardware access to the line status registers. irda modes transmit nactiveframe goes active as soon as the irda transmitter initiates a bof sequence. nactiveframe becomes i nactive as soon as the irda transmitter completes an eof sequence. in the case of a transmit abort, nactiveframe becomes inactive as soon as the irda transmitter completes the abort sequence. receive nactiveframe goes active as soon as the irda receiver detects valid payload data; i.e., after a valid bof sequence. na ctiveframe becomes inactive as soon as the irda receiver detects an eof sequence. in the case of a fifo overrun or abort, nactiveframe becomes inactive as soon as the irda receiv er updates the status register and signals the end of message. serial-to-parallel converter parallel-to-serial converter 16/32-bit crc generator 16/32-bit crc checker 8 1 8 1 timing & control transmit receive controls fir/tv encoder fir/tv decoder figure 20 - sce block diagram
56 consumer ir mode transmit nactiveframe goes active as soon as the consumer ir transmitter starts modulating the sce data stream. nactiveframe becomes inactive as soon as the transmit register is empty. receive nactiveframe goes active as soon as the consumer ir receiver detects the first active bit- time of infrared energy. nactiveframe becomes inactive whenever the consumer ir receiver is manually disabled, a dma terminal count has occurred, or following a fifo overrun. irda encoder description the irda fir encoder supports the synchronous bit-oriented hdlc prot ocol at .576mbps and 1.152mbps, and 4ppm encoding at 4mbps including all message framing, bit stuffing, and crc generation (figure 21). the irda fir encoder exchanges only payload data with the host and supports multi-frame windows for brick walled messages as well as bof and bw framing extensions. the irda fir encoder also includes an sir interaction pulse generator in hardware. sce 4ppm encoder hdlc encoder tx rx framing 4ppm decoder hdlc decoder control & status sip generator figure 21 - irda fir encoder
57 transmit timing the sce irda-mode transmitter is enabled by setting the appropriate sce modes bits in sce line control register b. if the fifo threshold is zero, message transmission begins as soon as transmit mode has been enabled and there is data in the fifo (figure 22). if the fifo threshold is greater than zero, message transmission begins only after transmit mode has been enabled and the fifo threshold has been exceeded or tc is active (figure 23). note : the irda-mode sce transmitter will only be enabled when the sir interaction pulse generator is inactive. once an irda transmission has begun, the end of message (eom) and other state indicators are cleared and the nactive fr ame signal is enabled. following the frame check sequence, eom is reactivated and an eom in terrupt is generated. following the end of the fr ame, nactive frame is disabled (figure 24). fifo empty tx enable transmit active sip time figure 22 - irda fir transmit enable timing: fifo threshold = 0 fifo threshold tx enable transm it tc active sip time figure 23 - irda fir transmit timing: fifo threshold > 0
58 when active, the data done flag in register block zero, line control register a alerts the transmitter that the next fifo underrun condition signifies the end of the valid payload data and that an eof should begin (figure 24). during dma operations tc automat ically sets the data done flag. a message byte counter that is initialized with the value in the data size register when the message begins can also signal the end of the valid payload data. if the me ssage byte counter goes to zero before the fifo is empty and the brick wall bit is one, a fifo underrun with an active data done flag is simulated, a hardware crc is appended (if required), and the next message is brick walled (not shown). if the fifo is empty, the data done flag is always cleared following the eom, regardless of how the bit was set. if the data done flag is inactive when an underrun occurs, the transmitter aborts the message and set the abort and underrun errors appropriately (figure 25). eof fcs i c a bof eom eom interrupt tx enable active frame data done fifo empty figure 24 - irda fir tx message timing (software crc) i c a bof eom eom interrupt tx enable active frame data done/tc fifo empty underrun error abort error abort figure 25 - tx abort on underrun timing
59 receive timing once enabled using the sce modes bits in line control register b, the irda-mode receiver begins searching for valid fir frames. the affects of non-valid irda infrared activity such as out of spec pulse widths and invalid bof sequences are always refl ected in the status indicators in the IRCC registers. when a valid bof is detected, the eo m from the previous message is disabled, errors are reset, and an nactive frame interrupt is sent (figure 26). eom and the eom interrupt are enabled following an active fcs. framing errors or a fifo overrun that occurs before the frame check sequence is complete is indicated in the appropria te status register bits and the message is aborted (figure 27). eof fcs i c a bof fifo empty eom interrupt rx enable active frame active frame int. eom figure 26 - irda rx message timing i c a bof fifo full eom interrupt rx enable active frame eom active frame int. overrun error abort error figure 27 - irda fir rx abort on overrun timing
60 crc select timing during transmit if the crc select control is low the fcs is assumed to be part of the message payload data sent from the host and the hardware crc generator is not engaged (figure 28). during receive if t he crc select control is low the hardware crc gener ator is not engaged, no comparison with the received fcs is made, and the state of the conf iguration register crc error flag is undefined. during transmit if the crc select control is high the fcs is assumed not to be part of the message data sent from the host, the hardware crc generator is engaged, and the fcs result is appended to the host payload data (figure 29). during receive, if the crc select control is high, the output from the har dware crc generator is compared to the crc from the received message and the result recorded in the configuration register crc error flag. note: for all irda fir received messages, the fcs is sent to the host through the fifo regardless of the state of the crc se lect control. eof fcs i c a bof fifo empty eom crc select data done tc figure 28 - irda fir frame with software crc crc (hw ) eof fcs i c a bof fifo empty eom crc select data done tc figure 29 - irda fir frame with hardware crc
61 framing errors the irda fir pulse and signaling violations listed in this section are considered framing errors. when the frame error bit in the IRCC line status register is one, a framing error has occurred. the irda receiver response to framing errors depends upon when the errors occur. framing errors that occur before a valid bof has been detected will always set the frame error bit but will not alter the system state in any other way; i.e., the abort bit is not activated. if framing errors occur following a valid bof, i.e. while nactive frame is zero, the message is aborted. for both the hdlc and 4ppm encoding schemes, messages with data fields larger than the value contained in t he data size register violate irda framing rule s but are not aborted. note : the size error and the frame error bits are set. pulses less than 60ns should be ignored, in all modes. the events listed in the following two sections are framing errors. 1.152mbps pulse widths greater t han one bit-cell. invalid bof: includes data fields before bof, pulse- width violations dur ing bof, and subsequent invalid bofs (including aborts) following a valid bof before the address fiel d. invalid data fields: includes frames with invalid data field characters (including aborts), and pulse-width violations during a data field (including during crc). invalid eof fields: includes invalid eof flags (including aborts), pulse-width violations, and subsequent invalid eofs following a valid eof. 4mbps pulse widths greater than two chip times. invalid pa field: includes invalid pa symbols, pulse- width violations, and subsequent invalid pa symbols following at least one valid pa symbol (including aborts) before the sta field. invalid sta field: includes invalid sta symbols, pulse- width violations, and subsequent invalid sta symbols following at least one valid symbol (including aborts) befor e the payload data. invalid data field: includes frames with invalid data symbols (including aborts), and pulse-width violations during a data field (including during crc). invalid eof field: includes invalid eof flag (including aborts), pulse-width violations, and subsequent invalid eofs following a valid eof. consumer ir encoder timing the consumer ir-mode sce does not require the framing signals that ar e specified in the irda- mode timing, although bot h modes utilize the nactive frame and eom interrupt. there is also no need to differentiate the irda-mode eom signal from an inactive nactive frame. the consumer ir-mode sce operates at the bit rates set in the consumer ir bit rate register. the consumer ir-mode sce can operate in programmed i/o or dma mode. the crc generator is not used. transmit timing the sce tv remote transmitter uses the same enabling mechanisms as the irda-mode transmitter (see page 57). note: the irda-mode active sip pulse tx enable timing restriction does not apply. once enabled, the tv remote transmitter operates until the fifo underruns (figure 30). the nactive frame and eom interrupt signals behave as shown. the sce modes bits are reset to zero, disabling the transmitter, following nactive frame.
62 receive timing the sce tv remote receiver can be enabled with the configuration r egister sce modes bits, polled using programmed i/o, and manually disabled when sufficient data has been collected (figure 31). once enabled, the sce receiver will only begin to interpret line data following the first valid zero detection. figure 32 illustrates how the tv remote receiver operates using dma. tc disables the receiver, sends an eom interrupt, and resets the sce modes bits to zero. fifo empty eom interrupt tx enable active frame tx reg. empty figure 30 - tv remote transmit timing rx enable active frame active frame int. zero detect figure 31 - tv remote manual rx timing tc eom interrupt rx enable active frame active frame int. zero detect clear fifo figure 32 - tv remote dma rx timing
63 the sce tv remote receiver will abort on a fifo overrun condition. when the overrun occurs the receiver is disabled, an eom interrupt is sent, and the fifo is flushed. irda multi-frame window support the tx data size register can be used with dma blocks that are larger t han the size of an irda message frame to support multi-frame windows, i.e. multiple unacknowledged message frames. mfws with a single dma block can occur in both brick walled and non-brick walled modes. non-brickwalled mfws to support non-brick walled multi-frame windows set the sce modes bits to zero and setup the dma controller with a block-size larger than a single frame but smaller-than or equal-to the tx data size 8. choose the appropriate encoder, start the transmitter, and wait for an eom interrupt. repeat this procedure by reseting and then re-enabling the transmitter dma block-size tx data size times, until the dma block has been transferred. reset the fifo threshold for the last frame, if necessary. brickwalled mfws to support brick walled multi-frame windows set the sce modes bits to zero and setup the dma controller with a block-size larger than a single frame but smalle r-than or equal-to the tx data size 8. choose the appropriate encoder, initialize the brick wall count, and set the brick wall bit. start the transmitter and wait for dma block-size tx data size eof interrupts or poll the message count bits; i. e., until the dma block has been transferred. loopback mode loopback mode allows diagnostic testing of the irda fir and consumer ir encoders. loopback tests require that the sce fifo be used for both transmit and receive modes, simultaneously. the data size registers are used to constrain the loopback test. brick walled messages are not supported in loopback mode. fifo full eom interrupt rx enable active frame active frame int. zero detect overrun figure 33 - tv remote rx abort on overrun
64 initialization the fifo must be loaded with the appropriate transmit data while the block control bits in sce configuration register a are set to the required transfer mode with the sce modes bits set to transmit/receive disabled. enough room must remain in the fifo for receive data. the loopback transmit crc bit (d6) in sce configuration register b must be initialized for the appropriate crc response during loopback testing. the data size registers must be properly initialized to constrain the loopback function so that rece ived data is not re- transmitted. the rx data size register is required for consumer ir loopback tests and the tx data size register is required for irda fir loopback tests. the rx data size register must be programmed with one less than the total number of bytes in the cir loopback test; i.e., test_byte_count_1. proper programming of the tx data size register depends upon the state of the crc select and loopback tx crc bits. the fifo threshold is not used for loopback tests. the tx polarity and rx polarity bits must be the same state for loopback tests. set the loopback bit in sce configuration register b to begin the loopback test. retrieving results the loopback test data can be read from the fifo immediately follo wing the end-of-message; i.e., the loopback bit does not need to be reset, nor does the fifo need to be explicitly re- configured for isa bus access.
65 bus interface i/o the bus interface i/o block contains a 128-byte fifo, dma/interrupt logic, and multiplexers to control access to the fifo and the isa bus (figure 34). the databus multiplexer provides exclusive isa bus access to either the 16550a uart or the IRCC sce depending on the state of block mode controls in the configur ation registers. disabled blocks are tristated from the isa bus. fifo multiplexer sce fifo access the fifo multiplexer cont rols the configuration of the sce fifo in the bus interface i/o block. this configuration can be inferred from the state of the sce modes bits in line control register b: when the transmit/receive modes are disabled, or the trans mit mode is enabled, the fifo is configured for transmit; otherwise, the fifo is configured for receive. the signal transmit in figure 34, above, can be satisfied by the inverse of the sce modes msb; e.g., nd7. host fifo access the host always has read access to the fifo, regardless of the state of the sce modes bits, or the loopback bit. the host has write access to the fifo when the loopback bit is inactive and the transmit/receive modes are disabled or the transmit mode is enabled. 128-byte sce fifo fifo timing & controls the fifo uses interleaved access timing to allow simultaneous fifo data reads and data fifo multiplexer 128-byte fifo transmi t loopbac k sce databus multiplexer 16550a uart isa bus loopback transmit function 0 0 fifo in to sce rx fifo out to host bus 0 1 fifo in to host bus fifo out to sce tx 1 x fifo in to sce rx fifo out to sce tx i/o & interrupt control figure 34 - bus interface i/o block
66 writes. this is requir ed both for normal operation with asynchronous host/ sce access timing, and during loopback tests with synchronous sce- only access timing where the fifo is simultaneouly used for transmit and receive. fifo controls include, s eparate read/ write lines, fifo full and fifo not empty flags, reset, fifo threshold, and interrupt. fifo threshold description the sce fifo threshold generates programmed i/o service requests to accommodate systems with widely varying i/o response times. fifo threshold values typically reflect the overall i/o response characteristics of a system. the same threshold value can be used for both i/o read and i/o write cases. during dma operatons, the fifo threshold is only used to trigger the sce transmitter. the fifo threshold value is programmable from 0 to 127. the fifo threshold register, located in register block one, address two, contains the fifo threshold value. low threshold values result in longer periods of time between service requests because more of the fifo is utilized before the request is i ssued. systems that program low threshold values must typically provide fast response times to these requests; i.e., high performance systems that move i/o data quickly. high threshold values are used in "sluggish" systems with long service request latencies. low performance systems typically take longer to move i/o data and require more frequent i/o service. for systems that program high fifo threshold values, much less of the fifo is utilized before service requests are issued. receive threshold once the fifo interrupt is enabled, receive service requests (rxservreq), i.e. data transfers from the fifo to the host, are generated whenever ther e are 128 minus the fifo threshold value or more data bytes in the fifo, given by: rxservreq 128 - fifo threshold for example, if the fifo threshold value is 12, rxservreq will be active whenever there 116 to 128 data bytes in the fifo. if the fifo threshold is 0, rxservreq will be active whenever the fifo is full. if the fifo threshold is 127, rxservreq will be active whenever the fifo is not empty. transmit threshold once the fifo interrupt is enabled, transmit service requests (txservreq), i.e. data transfers from the host to the fifo, are generated whenever there are fifo threshold value or fewer data bytes in the fifo, given by: txservreq fifo threshold for example, if the fifo threshold value is 12, txservreq will be active whenever there are 12 or less data bytes in the fifo. if the fifo threshold is 0, txservreq will be active whenever the fifo is empty. if the fifo threshold value is 127, txservreq will be active whenever the fifo is not full. fifo interrupt the fifo interrupt becomes active whenever the fifo interrupt enable is active and either txservreq or rxservreq is active. when fifo interrupt enable becomes inactive, the fifo interrupt goes inactive. for example, the fifo interrupt will become active during a transmit operation if the fifo threshold is fifty, the fifo interrupt enable is active, and there are from one to fifty data bytes in the fifo (figure 35). in figure 35, notice that fi ve bytes are written to the fifo every time a service request is answered. the third request occurs as soon as the fifo interrupt enable is activated because
67 the five bytes written to the fifo following the second service request was not enough data to exceed the fifo threshold given the long interrupt latency. dma the dma channel works in single-byte and burst (demand) mode. aen is high during dma transfers. the dma controls are located in sce configuration register b. when the dma enable bit (d0) is one, dma is enabled. the dma burst mode bit (d1) controls the dma mode. drq is further gated by the sce modes bits; e.g., drq can only be enabled if either transmit or receive mode has been enabled. during transmit drq remains active as long as the fifo is not full until tc. during receive drq remains active as long as the fifo is not empty until tc. single-byte mode single-byte mode is enabled by resetting the dma burst bit in sce configuration register b. single-byte dma transfers one data byte for each drq (figure 36). terminal count occurs only once, during the last byte of data block. fifo int. enable fifo interrupt service req. satisfied data bytes in fif o 51 50 49 54 ... 51 50 49 48 47 46 45 44 49 48 ... serv. req. satisfied (long int. latency) 1st service request 2nd service request 3rd service request txservreq figure 35 - fifo interrupt example dma enable drq i/ox ndack dma burst aen tc figure 36 - dma single-byte mode timing
68 burst (demand) mode dma burst mode is enabled by setting the dma burst bit in sce configuration register b. demand mode dma transfers up to 32 data bytes for each drq (figure 37). the IRCC guarantees that drq reli nquishes the isa bus after thirty-two dma i/o read or write cycles to allow for memory refresh. 32 i/ox clock dma refresh counter the 32 i/ox clock dma refresh counter is used to prevent drq from staying active for more than 32 i/o read/write cycles at a time. the counter is st opped and preloaded whenever drq is not active. once drq becomes active, the counter decrements until zero-count or drq is deactived. in demand mode, the count-zero condition always clears drq and triggers a refresh interval. the refresh inte rval remains active for 350ns following an inactive ndack (figure 38). if there is more data to transfer, drq goes active again and the cycle repeats. single byte mode dma does not use the 32 i/ox clock refresh counter. dm a enable drq i/o x ndack dm a burst aen tc figure 37 - dma burst mode timing
69 burst mode transmit uses fifo threshold for triggered transmit. the irda 4ppm transmit encoder can deplete the sce fifo faster than an isa host can fill it. the fifo threshold can be used to allow the dma controller to load enough data into the fifo before transmission begins to accommodate system latencies for subsequent dma transfer cycles. the fifo threshold is otherwise not used for dma transfers. drq control in dma burst mode, drq remains active until the entire dma data blo ck has been transferred, as indicated by dma terminal count (tc). the internal fifo full signal can temporarily deactivate drq if the dma block has not been completely transferred but there is no room left in the fifo for more data. as soon as the fifo full becomes inactive, drq is reasserted. the internal refresh interval signal can also temporarily deactivate drq (see the 32 i/ox clock dma refresh counter). example: transmit a 256-byte irda message 1. setup and enable the dm a controller for the 256-byte message. 2. set the appropriate fifo threshold, typically this number can be high, e.g. 127, and set the sce modes bits in register block zero, address 6 to enable the transmitter. 3. the dma controller proceeds to load the fifo until txservreq activates the transmitter. dma transfer cycles continue until tc. drq is only de-asserted when fifo full or refresh interval are active (figure 39). dma enable drq i/ox ndack refresh interval 32 clocks max. 350ns min. disable 32-clk countdown & reset 32-clk counter enable 32-clk countdown dma burst figure 38 - 32 i/ox clock dm a refresh count timing
70 burst mode receive drq control in dma burst mode, drq remains active until the entire dma data blo ck has been transferred, as indicated by dma terminal count (tc). since the fifo threshold is not used for dma transfer cycles, drq is asserted as soon as fifo not empty is true. fifo not empty can temporarily deactivate drq if the dma block has not been completely transferred but there is no data left in the fifo to transfer. as soon as fifo not empty becomes true, drq is reasserted. the internal refresh interval signal can also temporarily deactivate drq (see the 32 i/ox clock dma refresh counter). example: receive a 256-byte irda message 1. setup and enable the dm a controller for the 256-byte message. 2. enable the irda receiver. 3. drq is asserted as soon as fifo not empty is true. 4. the dma controller proceeds to empty the fifo until tc. drq is otherwise only de- asserted when fifo not empty is false or refresh interval is active (figure 40). dm a enable drq tc fifo full dm a burst refresh interval t x e nable txservreq figure 39 - dma burst mode transmit timing dm a enable drq tc fifo not em pty dm a burst refresh interval rx enable figure 40 - dma burst mode receive timing
71 programmed i/o programmed i/o mode is selected when the dma enable bit in sce configuration register b is zero. the IRCC also supports string move timing which is a block-mode progra mmed i/o operation that utilizes iochrdy to contro l the transfer (figure 41). string move mode is selected when the string move bit in sce configuration register b is one. polling interface programmed i/o without iochrdy requires polling the fifo status flags before reading or writing fifo data. the receiver interface depends upon the fifo not empty flag. if fifo not empty is true, there is read data available in the fifo (figure 42). the transmitter interface depends upon the fifo full flag. if fifo full is false, there is room for write data in the fifo ( figure 43). fifo not empty iochrdy ior string move aen figure 41 - string move timing dm a enable ior string move fifo data read status read fifo not empty figure 42 - programmed i/o read timing
72 fifo interrupt interface transmit description transmitting messages with programmed i/o using fifo interrupt requires writing a fixed number of data bytes, us ually related to the threshold, whenever the fifo interrupt becomes active. an appropriate fifo threshold value allows the host to efficiently satsify the fifo service requests until the message transmission is complete. for slow systems, the fifo can be manually filled with tr ansmit data before the transmitter is enabled. note: the fifo will automatically request service before the transmitter is activated if the fifo threshold is greater than zero. example: transmit a 256-byte irda message 1. set an appropriate fifo threshold for the system type. for the greatest performance advantage, pre-load the fifo with transmit data. 2. set the fifo interrupt enable active and activate the transmitter. 3. service the fifo interrupts as required. set the data done flag when all of the transmit message data has been loaded (figure 44). dma enable iow string move fifo data write status read fifo full figure 43 - programmed i/o write timing dma enable iow string move tx enable txservreq fifo int. enable fifo interrupt data done eom interrupt figure 44 - interrupt driven programmed i/o transmit timing
73 receive description receiving messages with programmed i/o using fifo interrupt requires reading a fixed number of data bytes, usually rela ted to the threshold, whenever the fifo interrupt becomes active. an appropriate fifo threshold value allows the host to efficiently satisfy the fifo service requests until the me ssage reception is complete. example: receive a 256-byte irda message 1. set an appropriate fifo threshold for the system type. 2. set the fifo interrupt enable active and enable the receiver. 3. service the fifo interrupts as required (figure 45). note: the amount of data remaining in the fifo following the last service request (rxservreq) in figure 45 is probably less than the typical read block size. this will occur when an irda eof has been detected, the fifo receive threshold has not been reached and the fifo not empty flag is true. iochrdy time-out description in programmed i/o mode when aen = low and string move = active, iochrdy can be used to slightly extend the access cycle if the fifo is temporarily unable to fulfill the transfer request (figure 46). if iochrdy remains inactive for more than 10us, a time-out error occurs and subsequent iochrdy cycles are prevented until the string move bit is spec ifically reactivated. because of the 10us iochrdy time-out, it is recommended that string move timing only be used for 1.152mbps transfers and above. dma enable ior string move rx enable rxservreq fifo int. enable fifo interrupt eom interrupt figure 45 - interrupt driven programmed i/o receive timing
74 iochrdy timer the 10us iochrdy timer is initialized when iochrdy is active. the timer count sequence is activated when iochrdy goes inactive. if iochrdy becomes active before the 10us time- out has elapsed, the timer is stopped and the count is re-initialized. if iochrdy is still inactive when the 10us time-out occurs, the timer stops, the time-out error bit is set, iochrdy is re- asserted, and the string move bit is reset (figure 47). string move iochrdy ior fifo not empty aen 24ns (max) 10us (max) figure 46 - valid i/o read ready cycle string move iochrdy ior fifo not empty aen 10us iochrdy time-ou t start timer iochrdy error figure 47 - iochrdy 10us time-out
75 zero wait state support nsrdy nsrdy can be driven by the IRCC to indicate that an access cycle shorter than the standard i/o cycle can be executed. note : the names nsrdy & nnows can be used interchangeably. nsrdy is enabled by the no wait bit in sce configuration register b. when no wait is one, nsrdy goes active following the trailing edge of the isa i/o command and inactive following the rising edge (figure 48). nsrdy is suppressed during dma & refresh cycles, i.e. when aen is active, or when iochrdy is inactive. zero wait state support is only available when the sce is enabled. the interaction of nsrdy and iochrdy nsrdy and iochrdy determine the three types of isa access cycles: no-wait-state cycle, standard cycle, ready cycle (table 32). note: an inactive iochrdy suppresses nsrdy. table 32 - nsrdy and iochrdy interaction nsrdy iochrdy description active active no-wait-state cycle (shortest length) inactive active standard cycle (mean length) x inactive ready cycle (longest length) aen i/ox nsrdy no wait figure 48 - nsrdy timing
76 output multiplexer the output multiplexe r routes the active encoder/decoder to one of three IRCC serial communications ports. there are no restrictions on any of these connecti ons other than rx/tx source pairs go to the same destination (figure 49). descriptions of the block control, output mux. and aux ir signals can be found in the sce configuration registers in register block one. there are rx and tx polarity controls that determine the active states for the ir port signals, see sce configurat ion register a. the state of inactive ir outputs depends upon the tx polarity bit; e.g., if tx po larity is zero (default), inactive outputs will be one. routing for the com port flow-control signal s is fixed. when the com port is inactive, the flow-control signals behave according to the current smsc 16550a serial port specification. the tx/rx polarity bits do not apply when com mode is selected. there is a provision for added transmit current capacity by selectively duplicating the transmit output of the ir port or the com port at the aux port. this can be used, for example, to accommodate the high-pow er optics found in consumer ir tv remote controls. there are gp data pins that always reflects the state of general purpose data & fast bits (5-6) of line control register a, in register block zero, address four. the state of the g.p. data pins is independent of the IRCC block controls or the output multiplexer. irrx irtx a rx a tx crx ctx ndsr nrts ndtr ncts ndcd nri 1 to 3 demux. 3 to 1 mux. 1 to 6 demux. 6 to 1 mux. 2 to 1 mux. raw r x raw t x tv rx tv tx ask rx ask tx irda sir rx irda sir tx com rx com tx output mux. 2 4 block control aux. ir 1 ir port aux port com port 1 tx polarity 1 rx polarity g.p. data gp data g.p. port irda fir rx irda fir tx fast fast figure 49 - output multiplexer block
77 chip-level IRCC addressing support IRCC register addressing is controlled at the chip level. both the ace bank select, nace, and the sce bank select, nsce, are decoded at the chip level from the host address bus to access data in the IRCC register banks (figure 50). table 33 illustrates a chip-level IRCC address decoder using a base address of 2f8 for the ace uart and 2f8+400 or 6f8 for the sce registers. table 33 - IRCC address decode at '400'hex hex address nace nsce description 2f8 - 2ff 0 1 ace uart registers enabled 6f8 - 6ff 1 0 sce registers enabled all other registers 1 1 ir cc registers not accessible chip-level address decoder ace select sce select address bus aen i/o select nace nsce IRCC figure 50 - chip-level IRCC address decode
ac timing ir rx pulse rejection encoder pulse rejection 4ppm 72.8ns hdlc 1.152mbps 72.8ns hdlc .576mbps 145.6ns irda sir 60.0ns consumer ir 166ns irda 4ppm bit rate tolerance tbd of bit rate rx pulse width min. nom. max. single pulse 85ns 125ns tbd double pulse 210ns 250ns 290ns irda hdlc bit rate tolerance tbd of bit rate max rx pulse width min. nom. max. .576mbps tbd 434ns tbd 1.152mbps tbd 217ns tbd
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