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spread spectrum ftg for via k7 chipset W230 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07224 rev. *a revised december 21, 2002 features ? maximized emi suppression using cypress?s spread spectrum technology single-chip system frequency synthesizer for via k7 chipset two copies of cpu output six copies of pci output one 48-mhz output for usb one 24-mhz or 48-mhz output for sio two buffered reference outputs thirteen sdram outputs provide support for 3 dimms supports frequencies up to 200 mhz i 2 c? interface for programming power management control inputs available in 48-pin ssop key specifications cpu to cpu output skew: ......................................... 175 ps pci to pci output skew: ............................................ 500 ps v ddq3 : ..................................................................... 3.3v5% i 2 c is a trademark of phillips corporation. table 1. mode input table mode pin 2 0cpu_stop# 1ref0 table 2. pin selectable frequency input address cput_cs cput0 (mhz) pci 0:5 (mhz) spread spectrum fs3 fs2 fs1 fs0 1111 100.0 33.3 ? 0.5% 1 1 1 0 100.0 33.3 0.25% 1 1 0 1 100.0 33.3 0.5% 1100 95.0 31.7 off 1011 133.3 33.3 ? 0.5% 1 0 1 0 133.3 33.3 0.25% 1 0 0 1 133.3 33.3 0.5% 1000 102.0 34.0 off 0111 104.0 34.6 off 0110 106.0 35.3 off 0101 107.0 35.6 off 0100 108.0 36.0 off 0011 109.0 36.3 off 0 0 1 0 110.0 36.6 off 0 0 0 1 111.0 37.0 off 0 0 0 0 112.0 37.3 off block diagram pin configuration note: 1. internal pull-up resistors should not be relied upon for setting i/o pins high. pin function with parentheses determined by mode pin resistor strapping. unlike other i/o pins, input fs3 has an internal pull-down resistor. [1] vddq3 ref0/(cpu_stop#) pci0/mode xtal pll ref freq pll 1 x2 x1 ref1/fs0 vddq3 stop clock control pci2 pci3 pci4 48mhz/fs2 24_48mhz/fs3 pll2 2,3,4 osc pwrdwn# vddq3 pci5 i 2 c sdata logic sclk i/o pin control sdram0:12 sdramin 13 vddq3 pci1/fs1 cput0 2 cput_cs cpuc0 vddq3 ref0/(cpu_stop#) gnd x1 x2 vddq3 pci0/mode pci1/fs1* gnd pci2 pci3 pci4 pci5 vddq3 sdramin gnd sdram11 sdram10 vddq3 sdram9 sdram8 gnd sdata sclk W230 ref1/fs0* gnd cput_cs gnd cpuc0 cput0 vddq3 pwrdwn#* sdram12 gnd sdram0 sdram1 vddq3 sdram2 sdram3 gnd sdram4 sdram5 vddq3 sdram6 sdram7 vddq3 48mhz/fs2* 24_48mhz/fs3^ 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 i 2 c {
W230 document #: 38-07224 rev. *a page 2 of 15 pin definitions pin name pin no. pin type pin description cput0, cpuc0, cput_cs 43, 44, 46 o (open- drain) cpu clock output 0: cput0 and cpuc0 are the differential cpu clock outputs for the k7 processor. cput_cs is the open-drain clock output for the chipset. it has the same phase relationship as cput0. pci2:5 10, 11, 12, 13 o pci clock outputs 2 through 5: these four pci clock outputs are controlled by the pwrdwn# control pin. frequency is set by fs0:3 inputs or through serial input interface, see tables 2 and 6 for details. output voltage swing is controlled by voltage applied to vddq3. pci1/fs1 8 i/o fixed pci clock output/frequency select 1: as an output, frequency is set by fs0:3 inputs or through serial input interface. this output is controlled by the pwrdwn# input. this pin also serves as a power-on strap option to determine device operating frequency as described in table 2 . pci0/mode 7 i/o fixed pci clock output/mode: as an output, frequency is set by the fs0:3 inputs or through serial input interface, see tables 2 and 6 . this output is controlled by the pwrdwn# input. this pin also serves as a power-on strap option to determine the function of pin 2, see table 1 for details. pwrdwn# 41 i pwrdwn# input: lvttl-compatible input that places the device in power-down mode when held low. in power-down mode,cpuc0 will be three-stated and all the other output clocks will be driven low. 48mhz/fs2 26 i/o 48-mhz output/frequency select 2: 48 mhz is provided in normal operation. in standard pc systems, this output can be used as the reference for the universal serial bus host controller. this pin also serves as a power on strap option to determine device operating frequency as described in table 2 . 24_48mhz/ fs3 25 i/o 24/48-mhz output/frequency select 3: in standard pc systems, this output can be used as the clock input for a super i/o chip. the output frequency is controlled by configuration byte 3 bit[6]. the default output frequency is 48 mhz. this pin also serves as a power-on strap option to determine device operating frequency as described in table 2 . ref1/fs0 48 i/o reference clock output 1/frequency select 2: 3.3v 14.318-mhz output clock. this pin also serves as a power-on strap option to determine device operating frequency as described in table 2 . upon power-up, fs0 input will be latched which will set clock frequencies as described in table 2 . ref0/ cpu_stop# 2 i/o reference clock output 0 or cpu_stop# input pin: function is determined by the mode pin. when cpu_stop# input is asserted low, it will drive cput0 and cput_cs to logic 0, and it will three-state cpuc0. when this pin is configured as an output, this pin becomes a 3.3v 14.318-mhz output clock. sdramin 15 i buffered input pin: the signal provided to this input pin is buffered to 13 outputs (sdram0:12). sdram0:12 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40 o buffered outputs: these thirteen dedicated outputs provide copies of the signal provided at the sdramin input. the swing is set by vddq3, and they are deac- tivated when pwrdwn# input is set low. sclk 24 i clock pin for i 2 c circuitry. sdata 23 i/o data pin for i 2 c circuitry. x1 4 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 5 i crystal connection: an input connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. vddq3 1, 6, 14, 19, 27, 30, 36, 42 p power connection: power supply for core logic, pll circuitry, sdram outputs, pci outputs, reference outputs, 48-mhz output, and 24/48-mhz output. connect to 3.3v supply gnd 3, 9, 16, 22, 33, 39, 45, 47 g ground connections: connect all ground pins to the common system ground plane.
W230 document #: 38-07224 rev. *a page 3 of 15 overview the W230 was developed as a single-chip device to meet the clocking needs of via k7 core logic chip sets. in addition to the typical outputs provided by a standard ftg, the W230 adds a thirteenth output buffer, supporting sdram dimm modules in conjunction with the chipset. cypress ? s proprietary spread spectrum frequency synthesis technique is a feature of the cpu and pci outputs. when en- abled, this feature reduces the peak emi measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them. functional description i/o pin operation pins 7, 8, 25, 26, and 48 are dual-purpose l/o pins. upon power-up these pins act as logic inputs, allowing the determi- nation of assigned device functions. a short time after power- up, the logic state of each pin is latched and the pins become clock outputs. this feature reduces device pin count by com- bining clock outputs with input select pins. an external 10-k ? ? strapping ? resistor is connected between the l/o pin and ground or v dd . connection to ground sets a latch to ? 0, ? connection to v dd sets a latch to ? 1. ? figure 1 and figure 2 show two suggested methods for strapping resistor connections. upon W230 power-up, the first 2 ms of operation is used for input logic selection. during this period, the five i/o pins (7, 8, 25, 26, 48) are three-stated, allowing the output strapping re- sistor on the l/o pins to pull the pins and their associated ca- pacitive clock load to either a logic high or low state. at the end of the 2-ms period, the established logic ? 0 ? or ? 1 ? condi- tion of the l/o pin is latched. next the output buffer is enabled converting the l/o pins into operating clock outputs. the 2-ms timer starts when v dd reaches 2.0v. the input bits can only be reset by turning v dd off and then back on again. it should be noted that the strapping resistors have no signifi- cant effect on clock output signal integrity. the drive imped- ance of clock outputs is <40 ? (nominal), which is minimally affected by the 10-k ? strap to ground or v dd . as with the se- ries termination resistor, the output strapping resistor should be placed as close to the l/o pin as possible in order to keep the interconnecting trace short. the trace from the resistor to ground or v dd should be kept less than two inches in length to prevent system noise coupling during input logic sampling. when the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assuming that v dd has stabilized. if v dd has not yet reached full value, output frequency initially may be below target but will increase to target once v dd voltage has stabilized. in either case, a short output clock cycle may be produced from the cpu clock outputs when the outputs are enabled. power-on reset timer output three-state data latch hold qd W230 v dd clock load r 10 k ? output buffer (load option 1) 10 k ? (load option 0) output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option control logic v dd clock load r 10 k ? output strapping resistor series termination resistor jumper options figure 2. input logic selection through jumper option resistor value r power-on reset timer output three-state data latch hold qd W230 output buffer output low control logic
W230 document #: 38-07224 rev. *a page 4 of 15 spread spectrum frequency timing generator the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 3 . as shown in figure 3 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 4 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is specified in table 6 . figure 4 details the cypress spreading pattern. cypress does offer op- tions with more spread and greater emi reduction. contact your local sales representative for details on these devices. spread spectrum clocking is activated or deactivated by se- lecting the appropriate values for bits 1 ? 0 in data byte 0 of the i 2 c data stream. refer to table 6 for more details. figure 3. clock harmonic with and without sscg modulation frequency domain representation ssftg typical clock amplitude (db) spread spectrum enabled emi reduction non- spread speactrum amplitude (db) frequency span (mhz) center spread frequency span (mhz) down spread figure 4. typical modulation profile max (0%) min ( ? 0.5%) 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency
W230 document #: 38-07224 rev. *a page 5 of 15 serial data interface the W230 features a two-pin, serial data interface that can be used to configure internal register settings that control partic- ular device functions. upon power-up, the W230 initializes with default register settings, therefore the use of this serial data interface is optional. the serial interface is write-only (to the clock chip) and is the dedicated function of device pins sdata and sclock. in motherboard applications, sdata and sclock are typically driven by two logic outputs of the chipset. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power manage- ment functions. table 3 summarizes the control functions of the serial data interface. operation data is written to the W230 in eleven bytes of eight bits each. bytes are written in the order shown in table 4 . table 3. serial data interface control functions summary control function description common application clock output disable any individual clock output(s) can be disabled. dis- abled outputs are actively held low. unused outputs are disabled to reduce emi and system power. examples are clock out- puts to unused pci slots. cpu clock frequency selection provides cpu/pci frequency selections through software. frequency is changed in a smooth and controlled fashion. for alternate microprocessors and power management options. smooth frequency transition allows cpu frequency change un- der normal system operation. spread spectrum enabling enables or disables spread spectrum clocking. for emi reduction. output three-state puts clock output into a high impedance state. production pcb testing. (reserved) reserved function for future device revision or pro- duction device testing. no user application. register bit must be writ- ten as 0. table 4. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the W230 to accept the bits in data bytes 0 ? 6 for internal register configuration. since other devices may exist on the same com- mon serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the W230 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don ? t care unused by the W230, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the command code byte is part of the standard serial com- munication protocol and may be used when writing to another ad- dressed slave receiver on the serial data bus. 3 byte count don ? t care unused by the W230, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the byte count byte is part of the standard serial communi- cation protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 data byte 0 refer to table 5 the data bits in data bytes 0 ? 7 set internal W230 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for description of bit control functions, refer to table 5 , data byte serial configuration map. 5 data byte 1 6 data byte 2 7 data byte 3 8 data byte 4 9 data byte 5 10 data byte 6 11 data byte 7
W230 document #: 38-07224 rev. *a page 6 of 15 writing data bytes each bit in the data bytes controls a particular device function except for the ? reserved ? bits, which must be written as a logic 0. bits are written msb (most significant bit) first, which is bit 7. table 5 gives the bit formats for registers located in data bytes 0 ? 7. table 6 details additional frequency selections that are avail- able through the serial data interface. table 5. data bytes 0 ? 7 serial configuration map bit(s) affected pin control function bit control default pin no. pin name 0 1 data byte 0 7 -- -- (reserved) -- -- 0 6 -- -- sel_2 see table 6 0 5 -- -- sel_1 see table 6 0 4 -- -- sel_0 see table 6 0 3 -- -- hardware/software frequency select hardware software 0 2 -- -- sel_4 see table 6 1 1 -- -- sel_3 see table 6 0 0 -- -- normal three-stated 0 data byte 1 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) write to ? 1 ? -- -- 1 2 -- -- (reserved) write to ? 1 ? -- -- 1 1 -- -- (reserved) write to ? 1 ? -- -- 1 0 -- -- (reserved) write to ? 1 ? -- -- 1 data byte 2 7 -- -- (reserved) -- -- 0 6 7 pci0 clock output disable low active 1 5 -- -- (reserved) -- -- 0 4 13 pci5 clock output disable low active 1 3 12 pci4 clock output disable low active 1 2 11 pci3 clock output disable low active 1 1 10 pci2 clock output disable low active 1 0 8 pci1 clock output disable low active 1 data byte 3 7 -- -- (reserved) -- -- 0 6 -- sel_48mhz sel_48mhz as the output fre- quency for 24_48mhz 24-mhz 48-mhz 0 5 26 48mhz clock output disable low active 1 4 25 24_48mhz clock output disable low active 1 3 -- -- (reserved) -- -- 0 2 21, 20, 18, 17 sdram8:11 clock output disable low active 1
W230 document #: 38-07224 rev. *a page 7 of 15 1 32, 31, 29, 28 sdram4:7 clock output disable low active 1 0 38, 37, 35, 34 sdram0:3 clock output disable low active 1 data byte 4 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 data byte 5 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 1 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 48 ref1 clock output disable low active 1 0 2 ref0 clock output disable low active 1 data byte 6 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 data byte 7 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 table 5. data bytes 0 ? 7 serial configuration map (continued) bit(s) affected pin control function bit control default pin no. pin name 0 1
W230 document #: 38-07224 rev. *a page 8 of 15 table 6. additional frequency selections through serial data interface data bytes input conditions output frequency data byte 0, bit 3 = 1 cpu pci spread spectrum bit 2 sel_4 bit 1 sel_3 bit 6 sel_2 bit 5 sel_1 bit 4 sel_0 11111 100.0 33.3 ? 0.5% 11110 100.0 33.3 0.25% 11101 100.0 33.3 0.5% 11100 95.0 31.7 off 11011 133.3 33.3 ? 0.5% 11010 133.3 33.3 0.25% 11001 133.3 33.3 0.5% 11000 102.0 34.0 off 10111 104.0 34.6 off 10110 106.0 35.3 off 10101 107.0 35.6 off 10100 108.0 36.0 off 10011 109.0 36.3 off 10010 110.0 36.6 off 10001 111.0 37.0 off 10000 112.0 37.3 off 01111 113.0 37.6 off 01110 114.0 38.0 off 01101 115.0 38.3 off 01100 116.0 38.6 off 01011 118.0 39.3 off 01010 120.0 40.0 off 01001 124.0 31.0 off 01000 127.0 31.7 off 00111 130.0 32.5 off 00110 136.0 34.0 off 00101 140.0 35.0 off 00100 145.0 36.2 off 00011 150.0 37.5 off 00010 155.0 38.7 off 00001 160.0 40 off 00000 166.0 41.6 off
W230 document #: 38-07224 rev. *a page 9 of 15 absolute maximum ratings [2] stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t b ambient temperature under bias ? 55 to +125 c t a operating temperature 0 to +70 c esd prot input esd protection 2 (min.) kv dc electrical characteristics: t a = 0 c to +70 c, v ddq3 = 3.3v5% parameter description test condition min. typ. max. unit supply current i dd 3.3v supply current cput0, cpuc0, cpu_cs =100 mhz outputs loaded [3] 260 ma i dd 2.5v supply current cput0, cpuc0, cpu_cs =100 mhz outputs loaded [3] 25 ma logic inputs v il input low voltage gnd ? 0.3 0.8 v v ih input high voltage 2.0 v dd + 0.3 v i il input low current [4] ? 25 a i ih input high current [4] 10 a clock outputs v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ? 1 ma 3.1 v v ol output low voltage cput_cs, cput0, cpuc0 termination to v pull-up (external) 00.3v v oh output high voltage cput_cs, cput0, cpuc0 termination to v pull-up (external) 1.0 1.2 v i ol output low current pci0:5 v ol = 1.5v 70 110 135 ma ref0:1 v ol = 1.5v 50 70 100 ma 48 mhz v ol = 1.5v 50 70 100 ma 24 mhz v ol = 1.5v 50 70 100 ma sdram0:12 v ol = 1.5v 70 110 135 ma i oh output high current pci0:5 v oh = 1.5v 70 110 135 ma ref0:1 v oh = 1.5v 50 70 100 ma 48 mhz v oh = 1.5v 50 70 100 ma 24 mhz v oh = 1.5v 50 70 100 ma sdram0:12 v oh = 1.5v 70 110 135 ma notes: 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. 3. all clock outputs loaded with 6" 60 ? transmission lines with 20-pf capacitors. 4. W230 logic inputs (except fs3) have internal pull-up devices (pull-ups not full cmos level). logic input fs3 has an internal pull-down device.
W230 document #: 38-07224 rev. *a page 10 of 15 ac electrical characteristics t a = 0 c to +70 c, v ddq3 = 3.3v5%, f xtl = 14.31818 mhz ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; spread spectrum is disabled. notes: 5. x1 input threshold voltage (typical) is v dd /2. 6. the W230 contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. total l oad placed on crystal is 14 pf; this includes typical stray capacitance of short pcb traces to crystal. 7. x1 input capacitance is applicable when driving x1 with an external clock source (x2 is left unconnected). 8. refer to figure 5 for k7 operation clock driver test circuit. crystal oscillator v th x1 input threshold voltage [5] v ddq3 = 3.3v 1.65 v c load load capacitance, imposed on external crystal [6] 14 pf c in,x1 x1 input capacitance [7] pin x2 unconnected 28 pf pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6 pf l in input pin inductance 7nh dc electrical characteristics: t a = 0 c to +70 c, v ddq3 = 3.3v5% (continued) parameter description test condition min. typ. max. unit cpu clock outputs (cput0, cpuc0, cput_cs) [8] parameter description test condition/comments cpu = 100 mhz cpu = 133 mhz unit min. typ. max. min. typ. max. t r output rise edge rate 1.0 1.0 v/ns t f output fall edge rate 1.0 1.0 v/ns t d duty cycle measured at 50% point 50 50 % t jc jitter, cycle to cycle 250 250 ps f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance v o = v x 50 50 ?
W230 document #: 38-07224 rev. *a page 11 of 15 pci clock outputs, pci0:5 (lump capacitance test load = 30 pf parameter description test condition/comments min. typ. max. unit t p period measured on rising edge at 1.5v 30 ns t h high time duration of clock cycle above 2.4v 12 ns t l low time duration of clock cycle below 0.4v 12 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 500 ps f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 30 ? ref0:1 clock outputs (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 40 ? 48-mhz clock output (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual determined by pll divider ratio (see m/n below) 48.008 mhz f d deviation from 48 mhz (48.008 ? 48)/48 +167 ppm m/n pll ratio (14.31818 mhz x 57/17 = 48.008 mhz) 57/17 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to fre- quency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 40 ?
W230 document #: 38-07224 rev. *a page 12 of 15 24-mhz clock output (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual determined by pll divider ratio (see m/n below) 24.004 mhz f d deviation from 24 mhz (24.004 ? 24)/24 +167 ppm m/n pll ratio (14.31818 mhz x 57/34 = 24.004 mhz) 57/34 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to fre- quency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 40 ? clock chip cpu driver 1.5v r1 68 z0 = 52 ? length = 3 ? t2 z0 = 52 ? length = 5 ? t1 r8 47 cpuclk_t vdd 3.3 + ? v1 z0 = 52 ? length = 3 ? t5 z0 = 52 ? length = 5 ? t4 r9 47 20p 20p cpuclk_c 1.5v r3 68 figure 5. k7 open drain clock driver test circuit ordering information ordering code package name package type W230 h 48-pin ssop (300 mils)
W230 document #: 38-07224 rev. *a page 13 of 15 layout diagram g = via to gnd plane layer v =via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors g c1 c2 fb +3.3v supply c4 c1, c3 & c5 = 10 ? 22 f c2 & c4 = 0.005 f 10 f fb = dale ilb1206 - 300 (300 ? @ 100 mhz) 0.005 f g g v ddq3 c3 c6 = 0.1 f g g v ddq3 c5 c6 48 47 46 45 44 43 42 41 40 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 g v W230 g v g v g v g v 5 ? g v g v core v ddq3 g g g g g g g g g g g g g g g g g g g g
W230 document #: 38-07224 rev. *a page 14 of 15 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 48-pin small shrink outline package (ssop, 300 mils) summary of nominal dimensions in inches: body width: 0.296 lead pitch: 0.025 body length: 0.625 body height: 0.102
W230 document #: 38-07224 rev. *a page 15 of 15 document title:W230 spread spectrum ftg for via k7 chipset document number: 38-07224 rev. ecn no. issue date orig. of change description of change ** 110489 10/21/01 szv change from spec number: 38-00890 to 38-07224 *a 122841 12/21/02 rbi add power up requirements to absolute maximum ratings information

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