connection diagrams to-99 (h) package AD707 7 6 2 8 1 3 4 5 null null ?n +in ? s +v s output nc nc = no connect note: pin 4 connected to case plastic (n) and cerdip (q) packages soic (r) package rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultralow drift op amp AD707 ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features very high dc precision 15 m v max offset voltage 0.1 m v/ 8 c max offset voltage drift 0.35 m v p-p max voltage noise (0.1 hz to 10 hz} 8 v/ m v min open-loop gain 130 db min cmrr 120 db min psrr 1 na max input bias current ac performance 0.3 v/ m s slew rate 0.9 mhz closed-loop bandwidth dual version: ad708 available in tape and reel in accordance with eia-481a standard application highlights 1. the AD707s 13 v/ m v typical open-loop gain and 140 db typical common-mode rejection ratio make it ideal for precision instrumentation applications. 2. the precision of the AD707 makes tighter error budgets possible at a lower cost. 3. the low offset voltage drift and low noise of the AD707 allow the designer to amplify very small signals without sacrificing overall system performance. 4. the AD707 can be used where chopper amplifiers are required, but without the inherent noise and application problems. 5. the AD707 is an improved pin-for-pin replacement for the lt1001. product description the AD707 is a low cost, high precision op amp with state-of- the-art performance that makes it ideal for a wide range of precision applications. the offset voltage spec of less than 15 m v is the best available in a bipolar op amp, and maximum input offset current is 1.0 na. the top grade is the first bipolar monolithic op amp to offer a maximum offset voltage drift of 0.1 m v/ c, and offset current drift and input bias current drift are both specified at 25 pa/ c maximum. the AD707s open-loop gain is 8 v/ m v minimum over the full 10 v output range when driving a 1 k w load. maximum input voltage noise is 350 nv p-p (0.1 hz to 10 hz). cmrr and psrr are 130 db and 120 db minimum, respectively. the AD707 is available in versions specified over commercial, industrial and military temperature ranges. it is offered in 8-pin plastic mini-dip, small outline (soic), hermetic cerdip and hermetic to-99 metal can packages. chips, mil-std-883b, rev. c, and tape & reel parts are also available. 1 2 3 4 8 7 6 5 AD707 nc = no connect null nc output +v s null ?n +in ? s AD707 1 4 8 5 nc = no connect null nc output +v s null ?n +in ? s
AD707Cspecifications rev. b C2C (@ +25 8 c and 6 15 v, unless otherwise noted) AD707j/a AD707k/b conditions min typ max min typ max units input offset voltage initial 30 90 10 25 m v vs. temperature 0.3 1.0 0.1 0.3 m v/ c t min to t max 50 100 15 45 m v long-term stability 0.3 0.3 m v/month adjustment range r2 = 20 k w (figure 19) 4 4mv input bias current 1.0 2.5 0.5 2.0 na t min to t max 2.0 4.0 1.5 4.0 na average drift 15 40 15 40/40/40 pa/ c offset current v cm = 0 v 0.5 2.0 0.3 1.5 na t min to t max 2.0 4.0 1.0 2.0 na average drift 2 40 1 25/25/35 pa/ c input voltage noise 0.1 hz to 10 hz 0.23 0.6 0.23 0.6 m v p-p f = 10 hz 10.3 28 10.3 18 nv/ ? hz f = 100 hz 10.0 13.0 10.0 12 nv/ ? hz f = 1 khz 9.6 11.0 9.6 11.0 nv/ ? hz input current noise 0.1 hz to 10 hz 14 35 14 30 pa p-p f = 10 hz 0.32 0.9 0.32 0.8 pa/ ? hz f = 100 hz 0.14 0.27 0.14 0.23 pa/ ? hz f = 1 khz 0.12 0.18 0.12 0.17 pa/ ? hz common-mode rejection ratio v cm = 13 v 120 140 130 140 db t min to t max 120 140 120 140 db open-loop gain v o = 10 v r load 3 2 k w 3 13 5 13 v/ m v t min to t max 3 13 3 13 v/ m v power supply rejection ratio v s = 3 v to 18 v 110 130 115 130 db t min to t max 110 130 110 130 db frequency response closed-loop bandwidth 0.4 0.9 0.4 0.9 mhz slew rate 0.12 0.3 0.12 0.3 v/ m s input resistance differential 24 100 45 200 m w common mode 200 300 g w output characteristics voltage r load 3 10 k w 13.5 14 13.5 14 v r load 3 2 k w 12.5 13.0 12.5 13.0 v r load 3 1 k w 12.0 12.5 12.0 12.5 v r load 3 2 k w t min to t max 12.0 13.0 12.0 13.0 v open-loop output resistance 60 60 w power supply current, quiescent 2.5 3 2.5 3 ma power consumption, no load v s = 15 v 75 90 75 90 mw v s = 3 v 7.5 9.0 7.5 9.0 mw notes all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. specifications subject to change without notice.
AD707 rev. b C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 500 mw input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . +v s and Cv s storage temperature range (q, h) . . . . . . C65 c to +150 c storage temperature range (n, r) . . . . . . . C65 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 8-pin plastic package: q ja = 165 c/watt; 8-pin cerdip package: q ja = 110 c/watt; 8-pin small outline package: q ja = 155 c/watt; 8-pin header package: q ja = 200 c/watt. ordering guide temperature package package model range description option AD707ah C40 c to +85 c 8-pin metal can h-08a AD707aq C40 c to +85 c 8-pin ceramic dip q-8 AD707ar C40 c to +85 c 8-pin plastic soic so-8 AD707ar-reel C40 c to +85 c 8-pin plastic soic so-8 AD707ar-reel7 C40 c to +85 c 8-pin plastic soic so-8 AD707bq C40 c to +85 c 8-pin ceramic dip q-8 AD707jn 0 c to +70 c 8-pin plastic dip n-8 AD707jr 0 c to +70 c 8-pin plastic soic so-8 AD707jr-reel 0 c to +70 c 8-pin plastic soic so-8 AD707jr-reel7 0 c to +70 c 8-pin plastic soic so-8 AD707kn 0 c to +70 c 8-pin plastic dip n-8 AD707kr 0 c to +70 c 8-pin plastic soic so-8 AD707kr-reel 0 c to +70 c 8-pin plastic soic so-8 AD707kr-reel7 0 c to +70 c 8-pin plastic soic so-8 metalization photograph dimensions shown in inches and (mm). contact factory for latest dimensions. 0.059 (1.51) null 8 +v s 7 6 v out 4 ? s 3 +in 2 ?n 1 null 0.110 (2.79) warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD707 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD707Ctypical characteristics rev. b C4C supply voltage ? v +v s ?.5 ? s 025 5101520 ?.5 ?.0 +1.5 +0.5 +1.0 + v out ?v out output voltage swing ? v (referred to supply voltages) r l = 2k w @ +25 c figure 2. output voltage swing vs. supply voltage offset voltage drift ??/ c number of units 100 70 20 ?.4 ?.3 0.4 ?.2 ?.1 0 0.1 0.2 0.3 90 80 50 30 60 40 10 0 256 units tested ?55 c to +125 c figure 5. typical distribution of offset voltage drift frequency ?hz 45 40 0 0.01 0.1 100 110 35 30 25 20 15 10 5 input voltage noise ?nv/ ? hz i/f corner 0.7hz figure 8. input noise spectral density load resistance ? w output voltage ?v p -p 35 15 0 10 100 10k 1k 10 25 20 30 5 15v supplies figure 3. output voltage swing vs. load resistance frequency ?hz output impedance ? w 100 0.0001 0.1 100k 1 10 100 1k 10k 10 1 0.1 0.001 0.01 i o = 1ma a v = +1000 a v = +1 figure 6. output impedance vs. frequency 10 0% 100 90 time ?1sec/div voltage noise ?100nv/div figure 9. 0.1 hz to 10 hz voltage noise supply voltage ? v +v s ?.5 ?.5 ?.0 ? s +1.5 +0.5 +1.0 025 5101520 +v ? commom-mode voltage limit ?v (referred to supply voltages) figure 1. input common-mode range vs. supply voltage time after power on ?minutes change in offset ?? 4 0 04 123 3 2 1 dual-in-line package plastic (n) or cerdip (q) metal can (h) package figure 4. offset voltage warm-up drift differential voltage ? v 40 30 0 0 1 100 10 20 10 inverting or noninverting input current ?ma figure 7. input current vs. differential input voltage
AD707 rev. b C5C temperature ? c 16 10 0 ?0 ?0 140 ?0 0 20 40 60 80 100 120 14 12 6 2 8 4 open-loop gain ? v/? r l = 1k w v out = 10v figure 10. open-loop gain vs. temperature frequency ?hz common-mode rejection ?db 160 0 0.1 1 10 100 1k 10k 100k 1m 140 100 80 60 20 120 40 figure 13. common-mode rejection vs. frequency supply voltage ? v supply current ?ma 4 0 03 24 6 9 12 15 18 21 2 1 3 +125 c +25 c ?5 c figure 16. supply current vs. supply voltage supply voltage ?v open-loop gain ? v/? 16 10 0 025 5 101520 14 12 6 2 8 4 r load = 1k w figure 11. open-loop gain vs. supply voltage frequency ?hz output voltage ?v p-p 35 15 0 1k 10k 1m 100k 10 25 20 30 5 f max = 3khz r l = 2k w +25 c v s = 15v figure 14. large signal frequency response 20mv/div ch1 time ?2?/div figure 17. small signal transient response; a v = +1, r l = 2 k w , c l = 50 pf frequency ?hz open-loop gain ? v/? 140 80 0 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 120 100 40 10 60 20 phase ?degrees 30 180 0 90 150 60 120 r l = 2k w c l = 1000pf phase margin =58 gain figure 12. open-loop gain and phase vs. frequency frequency ?hz power supply rejection ?db 160 0 0.001 0.01 100k 0.1 1 10 100 1k 10k 140 80 60 40 20 120 100 figure 15. power supply rejection vs. frequency 20mv/div ch1 time ?2?/div figure 18. small signal transient response; a v = +1, r l = 2 k w , c l = 1000 pf
AD707 rev. b C6C operation with a gain of 100 demonstrating the outstanding dc precision of the AD707 in practical applications, table i shows an error budget calculation for the gain of C100 configuration shown in figure 21. table i. error budget maximum error contribution av = 100 (c grade) error source (full scale: v out = 10 v, v in = 100 mv) v os 15 m v/100 mv = 150 ppm i os (100 w )(1 na)/100 mv = 1 ppm gain (2 k w load) (100 v/8 10 6 )100 mv = 13 ppm noise 0.35 m v/100 mv = 4 ppm v os drift (0.1 v/ c)/100 mv = 1 ppm/ c = 168 ppm +1 ppm/ c total unadjusted error @ +25 c = 168 ppm > 12 bits @ C55 c to +125 c = 268 ppm > 11 bits with offset calibrated out @ +25 c = 17 ppm > 15 bits @ C55 c to +125 c = 117 ppm > 13 bits 6 2 3 +v s AD707 0.1? ? s 4 99 w v out 0.1? 7 v in 10k w 100 w figure 21. gain of C100 configuration although the initial offset voltage of the AD707 is very low, it is nonetheless the major contributor to system error. in cases requiring additional accuracy, the circuit shown in figure 19 can be used to null out the initial offset voltage. this method will also cancel the effects of input offset current error. with the offsets nulled, the AD707c will add less than 17 ppm of error. this error budget assumes no error in the resistor ratio and no errors from power supply variation (the 120 db minimum psrr of the AD707c makes this a good assumption). the external resistors can cause gain error from mismatch and drift over temperature. offset nulling the input offset voltage of the AD707 is the lowest available in a bipolar op amp, but if additional nulling is required, the circuit shown in figure 19 offers a null range of 200 m v. for wider null capability, omit r1 and substitute a 20 k w potenti- ometer for r2. 6 2 3 8 r2 2k w 1 r1 10k w 0.1? +v s 7 AD707 0.1? ? s 4 offset adjust figure 19. external offset nulling and power supply bypassing gain linearity into a 1 k w load the gain and gain linearity of the AD707 are the highest available among monolithic bipolar amplifiers. unlike other dc precision amplifiers, the AD707 shows no degradation in gain or gain linearity when driving loads in excess of 1 k w over a 10 v output swing. this means high gain accuracy is assured over the output range. figure 20 shows the gain of the AD707, op07, and the op77 amplifiers when driving a 1 k w load. the AD707 will drive 10 ma of output current with no signifi- cant effect on its gain or linearity. output voltage ?v change in offset voltage ?10?/div ?5 15 ?0 ? 0 5 10 AD707 op07 op77 @ +25 c r load = 1k w figure 20. gain linearity of the AD707 vs. other dc precision op amps
AD707 rev. b C7C 18-bit settling time figure 22 shows the AD707 settling to within 80 m v of its final value for a 20 v output step in less than 100 m s (in the test con- figuration shown in figure 23). to achieve settling to 18 bits, any amplifier specified to have a gain of 4 v/ m v would appear to be good enough, however, this is not the case. in order to truly achieve 18-bit accuracy, the gain linearity must be better than 4 ppm. the gain nonlinearity of the AD707 does not contribute to the error, and the gain itself only contributes 0.1 ppm. the gain error, along with the v os and v os drift errors do not comprise 1 lsb of error in an 18-bit system over the military temperature range. if calibration is used to null offset errors, the AD707 resolves up to 20 bits at +25 c. time ?50?/div reference signal 10v/div d.u.t. output error 50?/div output: 10v/div figure 22. 18-bit settling ? s 6 2 3 op27 200k w 2x hp1n6263 v error x 100 7 10? 0.1? +v s 10? 0.1? ? s 6 2 3 d.u.t. AD707 100 w 7 10? 0.1? +v s 10? 0.1? 1.9k w 2k w 4 2k w v in flat-top pulse generator data dynamics 5109 or equivalent 2k w 4 figure 23. op amp settling time test circuit 140 db cmrr instrumentation amplifier the extremely tight dc specifications of the AD707 enable the designer to build very high performance, high gain instrumenta- tion amplifiers without having to select matched op amps for the crucial first stage. for the second stage, the lowest grade AD707 is ideally suited. the cmrr is typically the same as the high grade parts, but does not exact a premium for drift performance (which is less critical in the second stage). figure 24 shows an example of the classic instrumentation amp. figure 25 shows that the circuit has at least 140 db of common-mode rejection for a 10 v common-mode input at a gain of 1001 (r g = 20 w ). 6 2 3 a1 AD707 10k w 200 w 9.9k w r2 10k w ?n r4 10k w r g 10k w r1 10k w 6 2 3 a3 AD707 6 2 3 a2 AD707 +in r2 r cm circuit gain = + 1 r g 20,000 figure 24. a 3 op amp instrumentation amplifier high cmrr is obtained by first adjusting r cm until the output does not change as the input is swept through the full common- mode range. the value of r g , should then be selected to achieve the desired gain. matched resistors should be used for the output stage so that r cm is as small as possible. the smaller the value of r cm , the lower the noise introduced by potentiometer wiper vibrations. to maintain the cmrr at 140 db over a 20 c range, the resistor ratios in the output stage, r1/r2 and r3/r4, must track each other better than 10 ppm/ c. time ?2 sec/div ch1 ch2 input common-mode signal: 10v/div common-mode error referred to input: 5?/div figure 25. instrumentation amplifier common-mode rejection
AD707 rev. b C8C c1164aC2C12/95 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 8-pin metal can (h-08a) 45 bsc 0.100 (2.54) bsc 0.034 (0.86) 0.027 (0.69) 0.045 (1.14) 0.027 (0.69) 0.160 (4.06) 0.110 (2.79) 0.100 (2.54) bsc 0.200 (5.08) bsc 6 8 5 7 1 4 2 3 reference plane base & seating plane 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 0.750 (19.05) 0.500 (12.70) 0.045 (1.14) 0.010 (0.25) 0.050 (1.27) max 0.040 (1.02) max 0.019 (0.48) 0.016 (0.41) 0.021 (0.53) 0.016 (0.41) 0.185 (4.70) 0.165 (4.19) 0.250 (6.35) min 8-pin cerdip (q-8) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 0.005 (0.13) min 0.055 (1.4) max 1 pin 1 4 5 8 0.310 (7.87) 0.220 (5.59) 0.405 (10.29) max 0.200 (5.08) max seating plane 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 8-pin plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 precision current transmitter the AD707s excellent dc performance, especially the low offset voltage, low offset voltage drift and high cmrr, makes it possible to make a high precision voltage-controlled current transmitter using a variation of the howland current source circuit (figure 26). this circuit provides a bidirectional load current which is derived from a differential input voltage. 6 2 3 +v s AD707 0.1? ? s 4 0.1? 7 r4 100k w r3 100k w r2 100k w r1 100k w r l i l r scale v in v in r scale t l = ? ( ) r2 r1 figure 26. precision current source/sink the performance and accuracy of this circuit will depend almost entirely on the tolerance and selection of the resistors. the scale resistor (r scale ) and the four feedback resistors directly affect the accuracy of the load current and should be chosen carefully or trimmed. as an example of the accuracy achievable, assume i l must be 10 ma, and the available v in is only 10 mv. r scale = 10 mv/10 ma = 1 w i error due to the AD707c: maximum i error = 2(v os )/r scale + 2(v os drift)/r scale + i os (100 k/r scale ) = 2 (15 m v)/l w +2 (0.1 m v/ c)/l w + 1 na (100 k)/l w (1.5 na @ 125 c) = 30 m a + 0.2 m a/ c + 100 m a (150 m a @ 125 c) = 130 m a/10 ma = 1.3% @ 25 c = 180 m a/10 ma = 1.8% @ 125 c low drift, high accuracy resistors are required to achieve high precision.
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