spice device model si1900dl vishay siliconix dual n-channel 30-v (d-s) mosfet characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and sw itching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the ty pical electrical characteristics of the n-channel ve rtical dmos. the subcircuit model schematic is extrac ted and optimized over the ? 55 to 125 c temperature ranges under the pulsed 0 to ? 5v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance netw o rk is used to model the gate charge characteristics w h ile avoiding convergence difficulties of the sw itched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact phy sical interpretation of the device. subcircuit model schematic this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. document number : 71496 www. vi s h a y . c o m 25-apr-04 1
spice device model si1900dl vishay siliconix specificat ions (t j = 2 5 c unless ot herwise not e d) pa ra me te r s y m b o l te s t conditions ty pic a l u n i t static gate threshold voltage v gs(t h ) v ds = v gs , i d = 250 a 2 v on-state drain current a i d ( on) v ds 5 v, v gs = 10 v 1 1 a v gs = 10 v, i d = 0.59 a 0.41 drain-source on-state resistance a r ds(o n ) v gs = 4.5v, i d = 0.2 a 0.57 ? forw ard transconductance a g fs v ds = 10 v, i d = 0.59 a 1 s diode forw ard voltage a v sd i s = 0.23 a, v gs = 0 v 0.67 v dy namic b total gate charge q g 1 gate-source charge q gs 1 3 gate-drain charge q gd v ds = 15 v, v gs = 10 v, i d = 0.59 a 0.08 nc turn-on delay time t d(on) 6 ris e time t r 8 turn-off delay time t d(off) 1 1 fall time t f v dd = 15 v, r l = 30 ? i d ? 0.5 a, v gen = 10 v, r g = 6 ? 12 source-drain rev e rse recov e ry time t rr i f = 0.23 a, di/dt = 100 a/ s 15 ns not e s a. pulse test; pulse w i dth 300 s, duty cy cle 2%. b. guaranteed by design, not s ubject to production testing. www . v is ha y . c o m document number: 71496 2 25-apr-04
spice device model si1900dl vishay siliconix comparison of model wit h measured dat a (t j =2 5 c unless ot herwise not e d) document number : 71496 www. vi s h a y . c o m 25-apr-04 3
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