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1 features ? compatible with an embedded arm7tdmi ? processor programmable baud rate generator parity, framing and overrun error detection line break generation and detection automatic echo, local loopback and remote loopback channel modes multi-drop mode: address detection and generation interrupt generation 5-, 6-, 7-, 8- and 9-bit character length protocoliso7816t=0andt=1 modem, handshaking (hardware and software) and rs485 signals infrared data association (irda) 115.2 kbps full scan testable (up to 98%) two dedicated peripheral data controller channels can be easily implemented can be directly connected to the atmel implementation of the amba ? peripheral bus (apb) description the two-channel, full-duplex USART3 features parity, framing and overrun error detec- tion. a baud rate generator provides the bit period clock, named the baud rate clock, to both the receiver and the transmitter. the USART3 can be programmed to operate in six different modes: normal, modem, handshaking (hardware and software), rs485, irda, and iso7816 (t = 0 and t = 1). in normal mode, three different test con- figurations are available: automatic echo, local loopback, and remote loopback. two dedicated peripheral data controller channels can be easily implemented. one is dedicated to the receiver. the other is dedicated to the transmitter. they can be con- nected to either the pdc or pdc2 block. the generation of interrupts is controlled in the status register by asserting the corre- sponding interrupt line. the USART3 can be used with any 32-bit microcontroller core if the timing diagram shown in figure 5 on page 8 is respected. when using an arm7tdmi as the core, the atmel bridge must be used to provide the correct bus interface to the peripheral. 32-bit embedded asic core peripheral USART3 rev. 1739c?casic?03/02
2 USART3 1739c?casic?03/02 figure 1. USART3 symbol p_stb p_write p_stb_rising p_a[13:0] p_sel_usart scan_test_mode usart_int test_so[2:1] usart2 functional functional test_se test_si[2:1] test scan test scan nreset p_d_out[31:0] rxd usart2 clk_ext txd usart2 rxrdy_to_dma txrdy_to_dma clk_txd en_clk_n 2 2 p_d_in[31:0] cts dcd ri dsr comm_rx comm_tx rts dtr arm core clock fdiv1 slow_clock slclk_eq_sysclk power management /clock controller rx_buf_full tx_buf_empty pdc/pdc2 en_tx_n pdc_size 2 rx_dma_end tx_dma_end iso_txd_in r
3 USART3 1739c ? casic ? 03/02 table 1 . USART3 pin description name function type active level comments functional nreset reset system input low resets all the counters and signals. p_a[13:0] address bus input ? theaddresstakesintoaccountthetwolsbs [1:0], but the macrocell does not take these bits into account (left unconnected). p_d_in[31:0] input data bus input ? from host (bridge.) p_d_out[31:0] output data bus output ? to host (bridge.) p_write write enable input high from host (bridge). p_stb peripheral strobe input high to host (bridge). p_stb_rising user interface control signal input ? from host (bridge), clock for all dffs controlling the configuration registers. p_sel_usart selection of the block input high from host (bridge). usart_int interrupt signal to aic output high power management/clock controller clock system clock input ? system clock for the USART3 output wave forms. fdiv1 USART3 clock enable input ? system clock (clock) divided. slow_clock arm ? core operation input ? slclk_eq_sysclk arm core operation input ? arm core comm_rx arm core operation input high must be connected to arm core. comm_tx arm core operation input high must be connected to arm core. USART3 clk_ext baud rate signal input ? from sck pad. iso_txd_in feedback from txd pad for iso7816 line input ? must be connected to txd pad feedback when using iso functions rxd receive serial data pin input ? txd transmit serial data pin output ? rxrdy_to_dma output signal to dma channel output high byte available in the receiver holding register (rhr). this signal connects to the pdc / pdc2 (1) txrdy_to_dma output signal to the dma channel output high there are no more characters in the transmitter holding register (thr). this signal connects to the pdc / pdc2 (1) clk_txd output of the baud rate generator output ? to s c k p a d . en_clk_n direction signal for sck pad output ? active in synchronous mode.
4 USART3 1739c ? casic ? 03/02 note: 1. the peripheral data controllers (pdc and pdc2) are separate blocks. please refer to the corresponding datasheets. scan test configuration the fault coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. in order to achieve this, the atpg vectors must be generated on the entire circuit (top-level), which includes the USART3, or all USART3 i/os (must have a top-level access) and atpg vectors must be applied to these pins. en_tx_n direction signal for scic pad output ? rts request to send output low used in handshaking, modem and rs485 modes. dtr data terminal ready output low only used in modem mode. cts clear to send input low used in handshaking and modem modes. dcd data carrier detect input low only used in modem mode. ri ring indicator input low only used in modem mode. dsr data set ready input low only used in modem mode. pdc_size[1:0] size of transfer output ? connectedtopdc. pdc/pdc2 (1) rx_buf_full input signal from dma channel input high generated by pdc2. tx_buf_empty input signal from dma channel input high generated by pdc2. rx_dma_end end of receive dma transfer input high generated by pdc/pdc2 (1) . tx_dma_end end of transmit dma transfer input high generated by pdc/pdc2 (1) . test scan scan_test_mode must be set when running the scan vectors input high test_se scan test enable input high/low scan shift/scan capture. test_si[2:1] scan test input input high entry of scan chain. test_so[2:1] scan test output output ? output of scan chain. table 1 . USART3 pin description (continued) name function type active level comments
5 USART3 1739c ? casic ? 03/02 figure 2. USART3 block diagram peripheral data controller (pdc/pdc2) when the dedicated atmel pdc/pdc2 is used, four additional registers are available in the USART3 (see page 26). these registers are physically located in the pdc/pdc2 and accessed when selecting the USART3. for more details concerning these registers, please refer to the pdc and pdc2 datasheets. the following pins are exclusively reserved for use with the pdc/pdc2: rxrdy_to_dma, txrdy_to_dma, rx_dma_end, tx_dma_end, rx_buf_full and tx_buf_empty. if the pdc/pdc2 is not used, rx_dma_end, tx_dma_end, rx_buf_full and tx_buf_empty must be tied to zero. peripheral data controller receiver channel transmitter channel control logic interrupt control baud rate generator receiver transmitter atmel bridge asb apb usart_int clock fdiv1 rxd txd sck USART3 channel baud rate clock pio or pad clk_ext ri dsr dcd iso_txd_in cts pdc/pdc2 slow_clock slclk_eq_sysclk
6 USART3 1739c ? casic ? 03/02 figure 3. connecting the USART3 to an arm-based microcontroller note: 1. see figure 12 on page 17 for iso mode connection. 32-bit core (arm) atmel bridge asb clock nreset usart2 en_clk_n clk_txd clk_ext txd rx_dma_end tx_dma_end pad or pio pdc/pdc2 to advanced interrupt controller (aic) usart_int sck p_write p_d_in[31:0] p_a[13:0] p_stb p_sel_usart p_d_out[31:0] p_stb_rising p_write p_d_in[31:0 ] p_d_out[31:0] p_stb p_a[13:0] p_sel_usart atmel bus interface p_stb_rising rxd rxd txd (1) rxrdy_to_dma txrdy_to_dma rx_buf_full tx_buf_empty fdiv1 slow_clock slclk_eq_sysclk
7 USART3 1739c ? casic ? 03/02 pin description each USART3 channel has the following external signals: timing diagrams figure 4. USART3 timing diagram: write/read cycle ta ble 2. external signals for USART3 channels name description sck USART3 serial clock can be configured as an input or output: sck is configured as an input if an external clock is selected (usclks = 11). sck is driven as an output if the external clock is disabled (usclks[1] = 0) and clock output is enabled (clko = 1). txd transmit serial data is an output. rxd receive serial data is an input. ri ring indicator is an input used only in modem mode. dsr data set ready is an input used only in modem mode. dcd data carrier detect is an input used only in modem mode. cts clear to send is an input used in handshaking and modem modes. valid p_stb p_a[13:0] p_d_in[31:0] p_write p_d_out[31:0] t pd1 t su_write t hold_write t hold_din t su_din p_stb_rising t su_a t hold_a t pd2 t hold_sel t hold_sel p_sel_usart
8 USART3 1739c ? casic ? 03/02 figure 5. USART3 timing diagram: propagation delays, control signals clock t pd_int , t pd_rxrdy_to_dma, usart_int rxrdy_to_dma txrdy_to_dma clk_ext t pd_txrdy_to_dma txd t pd_txd clk_txd t pd_clk_txd en_clk_n t pd_en_clk_n t hold t su tx_dma_end rx_dma_end fdiv1 comm_rx comm_tx slclk_eq_sysclock
9 USART3 1739c ? casic ? 03/02 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator can select between external and internal clock sources. the external clock source is sck (clk_ext) or slow_clock. the internal clock sources can be either the master clock (clock) or the master clock divided (fdiv1). note: in all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (clock) period. the external clock frequency must be at least 4.5 times lower than the system clock. when the USART3 is programmed to operate in asynchronous mode (sync = 0 in the mode register us_mr), the selected clock is divided by 16, or, 8 times the value (cd) written in us_brgr (baud rate generator register), depending on the value of the over bit in us_mr. furthermore, if us_brgr is set to 0, the baud rate clock is disabled. or when the USART3 is programmed to operate in synchronous mode (sync = 1) and the selected clock is internal (usclks[1] = 0 in the mode register us_mr), the baud rate clock is the internal selected clock divided by the value written in us_brgr. if us_brgr is set to 0, the baud rate clock is disabled. in synchronous mode with external clock selected (usclks = 11), the clock is provided directly by the signal on the sck pin (clk_ext). no division is active. the value written in us_brgr has no effect. when the USART3 is programmed to operate in is07816 mode (USART3_mode field in the mode register us_mr), the selected clock is divided by the value fi_di_ratio written in us_fidi. if us_fidi is set to 0, the baud rate clock is disabled. baud rate selected clock 16 cd --------------------------------------- - = baud rate selected clock 8cd --------------------------------------- - = baud rate selected clock cd --------------------------------------- - =
10 USART3 1739c ? casic ? 03/02 figure 6. baud rate generator note: 1. divide by 16 or 8 or fi_di_ratio depends on mode. 00 01 clock fdiv1 selected clock 16-bit counter 0 0 1 baud rate clock sync usclks = 11 cd cd out 0 1 divide by 16 or 8 or fi_di_ratio (1) sync 0 1 >1 usclks slow_clock 10 11 clk_ext ext_clock
11 USART3 1739c ? casic ? 03/02 receiver asynchronous receiver the USART3 is configured for asynchronous operation when sync = 0 (us_mr). in asynchronous mode, the USART3 detects the start of a received character by sampling the rxd signal until it detects a valid start bit. a low level (space) on rxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the rxd at the theoretical mid-point of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1- bit period) so the sampling point is eight cycles (0.5 bit period) after the start of the bit. therefore, the first sampling point is 24 cycles (1.5 bit periods) after the falling edge of the start bit has been detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 7. asynchronous mode: start bit detection figure 8. asynchronous mode: character reception 16 x baud rate clock rxd true start detection d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period
12 USART3 1739c ? casic ? 03/02 synchronous receiver when configured for synchronous operation (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a low level is detected, it is consid- ered a start. the data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit. see the example in figure 9. figure 9. synchronous mode: character reception receiver ready when a complete character is received, it is transferred to the us_rhr and the rxrdy status bit in us_csr is set. if us_rhr has not been read since the last transfer, the ovre status bit in us_csr is set. parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in us_mr. it then compares the result with the received parity bit. if different, the parity error bit pare in us_csr is set. framing error if a character is received with a stop bit at low level and with at least one data bit at high level, a framing error is generated. this sets frame in us_csr. time-out this function allows an idle condition on the rxd line to be detected. the maximum delay for which the USART3 should wait for a new character to arrive while the rxd line is inac- tive (high level) is programmed in us_rtor (receiver time-out). when this register is set to 0, no time-out is detected. otherwise, the receiver waits for a first character and then initializes a counter, which is decremented at each bit period and reloaded at each byte reception. when the counter reaches 0, the timeout bit in us_csr is set. the user can restart the wait for a first character with the sttto (start time-out) bit in us_cr. calculation of time-out duration: generating clk_txd in synchronous mode, clk_txd is the clock as defined in figure 9. in asynchronous mode, or depending on bit over in us_mr register, or in iso7816 mode. d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled 1 stop clk_ext sampling true start detection duration us_rtor value bit period = clk_txd 16 baud rate clock = clk_txd 8 baud rate clock = clk_txd fi_di_ratio baud rate clock =
13 USART3 1739c ? casic ? 03/02 transmitter the transmitter has the same behavior in both synchronous and asynchronous operat- ing modes. the start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of the serial clock. see the example in figure 10. the number of data bits is selected in the chrl field in us_mr. the parity bit is set according to the par field in us_mr. the number of stop bits is selected in the nbstop field in us_mr. when a character is written to us_thr (transmit holding), it is transferred to the shift register as soon as it is empty. when the transfer occurs, the txrdy bit in us_csr is set until a new character is written to us_thr. if transmit shift register and us_thr are both empty, the txempty bit in us_csr is set. time-guard the time-guard function allows the transmitter to insert an idle state on the txd line between two characters. the duration of the idle state is programmed in us_ttgr (transmitter time-guard). when this register is set to zero, no time-guard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in us_ttgr: multi-drop mode when the field par in us_mr equals 11x (binary value), the USART3 is configured to run in multi-drop mode. in this case, the parity error bit pare in us_csr is set when data is detected with a parity bit set to identify an address byte. pare is cleared with the reset status bits command (rststa) in us_cr. if the parity bit is detected low, identi- fying a data byte, pare is not set. the transmitter sends an address byte (parity bit set) when a send address command (senda) is written to us_cr. in this case, the next byte written to us_thr will be transmitted as an address. after this, any byte transmitted will have the parity bit cleared. figure 10. synchronous and asynchronous modes: character transmission idle state duration between two characters time-guard value bit period = d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock
14 USART3 1739c ? casic ? 03/02 break a break condition is a low signal level that has a duration of at least one character (including start/stop bits and parity). transmit break the transmitter generates a break condition on the txd line when sttbrk is set in us_cr (control register). in this case, the character present in the transmit shift reg- ister is completed before the line is held low. to cancel a break condition on the txd line, the stpbrk command in us_cr must be set. the USART3 completes a minimum break duration of one character length. the txd line then returns to high level (idle state) for at least 12-bit periods, or the value of the time-guard register if it is greater than 12, to ensure that the end of break is correctly detected. then the transmitter resumes normal operation. the break is managed like a character: the sttbrk and the stpbrk commands are performed only if the transmitter is ready (bit txrdy = 1 in us_csr). the sttbrk command blocks the transmitter holding register (bit txrdy is cleared in us_csr) until the break has started. a break is started when the shift register is empty (any previous character is fully transmitted). us_csr.txempty is cleared. the break blocks the transmitter shift register until it is completed (high level for at least 12-bit periods after the stpbrk command is requested). in order to avoid unpredictable states: sttbrk and stpbrk commands must not be requested at the same time. once an sttbrk command is requested, further sttbrk commands are ignored until the break is ended (high level for at least 12-bit periods). all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending but not started (bit txrdy = 0 in us_csr) is ignored. it is not permitted to write new data in the transmit holding register while a break is in progress (stpbrk has not been requested), even though txrdy = 1 in us_csr. a new sttbrk command must not be issued until an existing break has ended (txempty=1 in us_csr). the standard break transmission sequence is: 1. wait for the transmitter ready. (us_csr.txrdy = 1) 2. send the sttbrk command. (write 0x0200 to us_cr) 3. wait for the transmitter ready. (bittxrdy=1inus_csr) 4. send the stpbrk command. (write 0x0400 to us_cr) the next byte can then be sent: 5. wait for the transmitter ready. (bittxrdy=1inus_csr) 6. send the next byte. (write byte to us_thr)
15 USART3 1739c ? casic ? 03/02 each of these steps can be scheduled by using the interrupt if the bit txrdy in us_imr is set. for character transmission, the USART3 channel must be enabled before sending a break. receive break the receiver detects a break condition when all data, parity and stop bits are low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. an end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or at least one sample in synchronous operating mode. rxbrk is also asserted when an end-of-break is detected. both the beginning and the end of a break can be detected by interrupt if the bit us_imr.rxbrk is set. peripheral data controller channels (pdc/pdc2) each USART3 channel is closely connected to a corresponding peripheral data con- troller channel (either the pdc or the pdc2). one is dedicated to the receiver. the other is dedicated to the transmitter. the pdc/pdc2 channel is programmed using us_tpr (transmit pointer) and us_tcr (transmit counter) for the transmitter and us_rpr (receive pointer) and us_rcr (receive counter) for the receiver. the status of the pdc/pdc2 is given in us_csr by the endtx bit for the transmitter and by the endrx bit for the receiver. note: pdc2 = pdc + one additional buffer. when the first buffer is full, the pdc2 buffers may filled, thereby permitting the continued transfer of data. the pointer registers (us_tpr and us_rpr) are used to store the address of the transmit or receive buffers. the counter registers (us_tcr and us_rcr) are used to store the size of these buffers. the receiver data transfer is triggered by the rxrdy bit and the transmitter data trans- fer is triggered by txrdy. when a transfer is performed, the counter is decremented and the pointer is incremented. when the counter reaches 0, the status bit is set (endrx for the receiver, endtx for the transmitter in us_csr) and can be pro- grammed to generate an interrupt. while the counter is at 0, the status bit is asserted and transfers are disabled. interrupt generation most bits in us_csr have a corresponding bit in us_ier (interrupt enable) and us_idr (interrupt disable), which controls the generation of interrupts by asserting the USART3 interrupt line connected to the advanced interrupt controller. us_imr (inter- rupt mask register) indicates the status of the corresponding bits. whenabitissetinus_csrandthesamebitissetinus_imr,theinterruptlineis asserted.
16 USART3 1739c ? casic ? 03/02 channel test configurations the USART3 can be programmed to operate in three different test modes, using the field chmode in us_mr. automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd line, it is sent to the txd line. programming the transmitter has no effect. local loopback mode allows the transmitted characters to be received. the txd and rxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the rxd pin level has no effect and the txd pin is held high, as in idle state. remote loopback mode directly connects the rxd pin to the txd pin. the transmitter and the receiver are disabled and have no effect. this mode allows bit-by-bit retransmission. figure 11. channel test configurations note: in iso mode, the channel test configurations are not functional. receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
17 USART3 1739c ? casic ? 03/02 is07816 mode the USART3 handles all specific requirements defined in iso7816 t = 0 and t = 1 pro- tocol types. to select iso7816 mode, the protocol and master or slave field USART3_mode in the mode register (us_mr) has to be set correctly depending on the desired configuration, as described in table 8 on page 26. note: the channel test configuration is not available in iso mode. the is07816 USART3 is configured and controlled via several registers: USART3 mode register (us_mr) USART3 control register (us_cr) USART3 interrupt enable register (us_ier) USART3 interrupt disable register (us_idr) USART3 interrupt mask register (us_imr) USART3 channel status register (us_csr) USART3 fi_di_ratio register (us_fidi) USART3 nb errors register (us_ner) USART3 receiver time out register (us_rtor) figure 12. iso mode connection USART3 iso_txd_in txd en_tx_n iso line i/o pad buffer
18 USART3 1739c ? casic ? 03/02 programmable bit rate the bit rate is determined by the following formula: where: b=bitrate d = bit-rate adjustment factor f = clock frequency division factor f = iso clock frequency (hz) as defined with iso clock d is a 4-bit encoded binary value (di) with the corresponding decimal index (di) as rep- resented in table 3. f is a 4-bit encoded binary value (fi) with the corresponding decimal index (fi) as repre- sented in table 4. b d f --- - f = table 3 . binary and decimal values for d di (bits) 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal) 1 2 4 8 16 32 12 20 table 4 . binary and decimal values for f fi (bits) 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048
19 USART3 1739c ? casic ? 03/02 the baud rate clock used in mode iso7816 is configured via the field fi_di_ratio in us_fidi. this is a 11-bit divider, hence the divider must be programmed between 0 and 2047. the fi_di_ratio value loaded in us_fidi will define the bit rate. the fi/di value shown in table 5 is loaded in the us_fidi register. for example, if an fi/di of 372 is desired, 174 h is programmed into the us_fidi register. reset value for fi_di_ratio is 174. bit time etu the bit duration is determined by the relation between the iso clock and the baud rate clock divisor factor fi_di_ratio. as a result, in iso7816 mode, there are fi_di_ratio clock cycles in one elementary time unit (etu). figure 13. bit duration table 5 . presentation of the possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4 etu isoclk iso i/oline
20 USART3 1739c ? casic ? 03/02 protocols figure 14. t = 0 protocol without and with parity error table 6 . description of receiver and transmitter sides for protocols t = 1 and t = 0 protocol t = 1 receiver side upon detection of a start bit, the following data byte and the parity bit are shifted in the receiver holding register (us_rhr) when the shift is completed and the parity is checked. if a parity error is detected, the pare bit is set in us_csr. in this protocol there is only one stop bit. transmitter side the data is loaded in the transmit holding register and parity is calculated. the data and the parity bit are shifted out following the start bit. protocol t = 0 receiver side upon detection of a start bit, the following data byte and the parity bit are shifted in the receiver holding register (us_rhr) when the shift is completed and the parity is checked. if a parity error is detected, a low error signal is sent for one elementary time unit (etu), 10.5 etus after the start bit. this error signal is sent from the receiver to the transmitter. the shift register value is not loaded in the receiver holding register. transmitter side the data is loaded in the transmit holding register and parity is calculated. the data and the parity bit are shifted out following the start bit. the txd line returns to high impedance 10 etus after the start bit. in this protocol there are two stop bits. without parity error sampling clock sb next sb b0 b1 b2 b3 b4 b5 b7 pb gt1 gt2 iso line 0 0.5 10 10.5 9 12 etu 1 bit period a state (1) c (1) b (1) b6 a (1) without parity error sampling clock sb next sb b0 b1 b2 b3 b4 b5 b7 pb gt1 gt2 iso line 0 0.5 10 10.5 9 13 etu 1 bit period state (1) c (1) b (1) b6 a (1) ed (3) 11.5 e (2) a (1) (1) state a - receiver mode b - transit mode c - check parity e - error signal asserted by the receiver in receiver mode - (2) (3) ed error delay (extra guard time added by the transmitter)
21 USART3 1739c ? casic ? 03/02 table 7 . description of supplemental protocol t = 0 characteristics additional features in protocol t = 0 error number if errors occurred during a transfer, it is possible to know the total amount of errors by reading the field nb_errors in us_ner. this is a read only register reset by a read action. up to 255 errors can be recorded. non acknowledge inhibited in some cases it can be important to inhibit an error. this can be achieved by setting the inack bit in us_mr. this means that even if an error is detected by the receiver, it will not send an error signal (nack). if inack is reset, on each error, the nack bit in us_sr will be set. it can be reset by using the rstnack command in us_cr. moreover, when inack is reset and the USART3 receives a byte with a parity error, this value is available in the us_rhr register but the us_rxrdy bit will not be set. character repetition a character repetition can be executed if the max_iteration field in us_mr is different from 0. max_iteration is a 3-bit field configurable with a value between 0 and 7. this implies that a character can be repeated up to seven times. (initial send + seven repeats.) if max_iteration is equal to zero, the protocol t = 0 transfer format explained previously is still valid. if max_iteration is different from zero and no parity error has been detected, the protocol t = 0 transfer format explained previously is still valid. if max_iteration is different from zero and a parity error has been detected, the transmitter will again send the value. if a parity error is still detected, the value is sent as many times as the value loaded in the max_iteration field. if the number of repetitions of the value reaches the value loaded in the max_iteration field, the iteration (us_csr) flag is set. if at some stage during the repetition schematic, no error parity is detected by the far-end receiver, the repetition is stopped. to reset the iteration (us_csr) flag, the rsit bit must be set in the usart control register (us_cr). disable successive nack in some cases, it may be useful to limit the number of successive nacks sent on the line. this can be achieved by setting the dsnack bit in us_mr. if this bit is set, successive parity errors are counted up to the value specified in the max_iteration field. as soon as this value is reached, no additional nack is sent on the iso line and the flag iteration is asserted. if it is not set, nack is sent on the iso line as soon as a parity error occurs in the received character (unless inack is set). bit order if set, msb is sent first, otherwise lsb.
22 USART3 1739c ? casic ? 03/02 irda mode the USART3 handles all requirements for irda. it is compliant with irda version 1.1 and supports data transfer speeds ranging from 2,4 kbps to 115,2 kbps. to select irda mode, the USART3_mode field in us_mr has to be set correctly depending on the desired configuration. see ? USART3 mode register ? on page 29. the USART3 irda is configured and controlled via two registers: USART3 mode register (us_mr) bit [3:0] USART3_mode USART3 irda_filter register (us_if) bit [7:0] irda_filter transmission in emission, after having configured the USART3 in irda mode, irda pulses will be automatically generated by the USART3. this implies that the USART3 will operate as in normal mode. for example, to transmit 34 hex, the correct operating mode is to write 34 hex in the tx_holding register after having selected the irda mode and enabling the transmitter. figure 15. transmission in irda mode reception in reception, the behavior is slightly different. pulses can be filtered on the rxd line via the irda_filter register. this is an 8-bit register with read/write access. according to the baud rate and the value written in the irda_filter register, pulses of different widths will be filtered. figure 16. receptioninirdamode bit period bit period 3 16 start bit data bits start bit 0 0 0 0 0 1 1 1 1 1 normal mode irda mode data bits start stop 00 0 00 11 1 1 1 irda mode normal mode
23 USART3 1739c ? casic ? 03/02 handshaking soft handshaking mode the USART3 handles all requirements for soft handshaking mode. to select this mode, the USART3_mode field in us_mr on page 29 has to be set correctly depending on the desired configuration. the USART3 soft handshaking is configured and controlled via two registers: USART3 mode register (us_mr) bit [3:0] USART3_mode USART3 xon_xoff register (us_xxr) bit [7:0] off bit [8:15] on when there is no activity on the rx_buf_full input (low level), upon enabling the receiver, the xon character previously loaded in the us_xxr will be transmitted on the txd line (refertofigure17onpage24). when there is no activity on the rx_buf_full input (low level), as soon as the receiver is disabled, the previously loaded xoff character in the us_xxr will be transmit on the txd line (see figure 17 on page 24). if the rx_buf_full input becomes active (goes from low to high), the xoff character will be transmitted on the txd line. depending on the transmitter sequence, there are two different behavior modes. 1. if there was no character transmission at this time, the xoff character is trans- mitted alone as a classical one-character transmission. 2. if character transmission occurred, the xoff character is inserted between two characters to be transmitted. if the rx_buf_full input becomes inactive (goes high to low), the xon character will be transmitted on the txd line. here again, depending on the transmitter sequence, there are two different behaviors: 1. if there was no character transmission at this time, the xon character is trans- mitted alone as a classical one-character transmission. 2. if character transmission occurred, the xon character is inserted between two characters to be transmitted hardware handshaking mode in this mode, an additional output rts (request to send) is generated. if an active rx_buf_full is received, the receiver will force the rts pin to a high level on the next start bit reception. an additional input cts (clear to send) is activated in this mode. if a high level signal is received on this pin, the transmitter will be disabled after finishing the current character transmission. to select hardware handshaking mode, the USART3_mode field in the mode register (us_mr) has to be set correctly as shown in the bit description of ? USART3_mode ? on page 29.
24 USART3 1739c ? casic ? 03/02 figure 17. rts/cts behavior in soft handshaking mode figure 18. connections in hardware handshaking mode figure 19. rts/cts behavior in hardware handshaking mode enable receiver txd/rxd rx_buf_full disable receiver xon xon xoff xoff USART3 txd cts USART3 rxd rts enable receiver rts/cts txd/rxd rxbuff disable receiver
25 USART3 1739c ? casic ? 03/02 rs485 mode in this mode, an additional request to send output (rts) is generated. the behavior of rts will follow the behavior of txempty. to select rs485 mode, the usart_mode field in the mode register (us_mr) has to be set correctly as shown in table 8 on page 26. figure 20. rts behavior in rs485 mode modem mode in this mode, two additional outputs are generated: 1. request to send (rts) 2. data terminal ready (dtr) if the rts transmitter is enabled, the rts pin will be forced to its active level (low). the behavior of the dtr pin is controlled via 2 bits (dtrdis and dtren) located in the controlregister(us_cr).ifdtrenisset,thedtrpinwillbeforcedtoitsactivelevel (low). if dtrdis is set, the dtr pin will be forced to its inactive level (high). the modem mode also activates four additional inputs: 1. ring indicator (ri) 2. data set ready (dsr) 3. data carrier detect (dcd) 4. clear to send (cts) if an input change is detected on the ri pin, the riic flag in the channel status register (us_csr) is raised. to reset this flag, the us_csr register must be read. furthermore, if an input change is received on the dsr pin, the flag dsric in the chan- nel status register (us_csr) is raised. to reset this flag, the us_csr register must be read. in addition, if an input change is received on the dcd pin, the dcdic flag in the chan- nel status register (us_csr) is raised. to reset this flag, the us_csr register must be read. moreover, if an active signal is detected on the cts pin, the transmitter will be disabled after finishing the current character transmission. if an input change is received on this pin, the ctsic flag in the channel status register (us_csr) is raised. to reset this flag, the us_csr register must be read. USART3 p s time-guard rts rts txd configurable period via time-guard register external rs485 transceiver
26 USART3 1739c ? casic ? 03/02 USART3 user interface notes: 1. the address takes into account the 2 lsbs [1:0], but the macrocell does not take these bits into account (left unconnected). therefore loading 0x0001, 0x0002 or 0x0003 on p_a[13:0] addresses the control register. 2. in the following register descriptions, all undefined bits ( ??? )read ? 0 ? . 3. if the user selects an address that is not defined in the above table, the value of p_d_out[31:0] is 0x00000000. 4. the corresponding decimal value is 372. table 8 . USART3 memory map (1) (2) (3) offset register name access reset state 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read/write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read/write 0 0x0024 receiver time-out register us_rtor read/write 0 0x0028 transmitter time-guard register us_ttgr read/write 0 0x002c reserved ??? 0x0030 reserved for pdc/pdc2 connection ??? 0x0034 reserved for pdc/pdc2 connection ??? 0x0038 reserved for pdc/pdc2 connection ??? 0x003c reserved for pdc/pdc2 connection ??? 0x0040 fi_di_ratio register us_fidi read/write 0x174 (4) 0x0044 nb errors register us_ner read-only ? 0x0048 xon_xoff register us_xxr read/write 0 0x004c irda_filter register us_if read/write 0
27 USART3 1739c ? casic ? 03/02 USART3 control register name: us_cr access type: write-only rstrx: reset receiver 0=noeffect. 1 = the receiver logic is reset, disabling the receive function (rxdis is set internally). rsttx: reset transmitter 0=noeffect. 1 = the transmitter logic is reset, disabling the transmit function (txdis and stpbrk are set internally). rxen: receiver enable 0=noeffect. 1 = the receiver is enabled if rxdis is 0. rxdis: receiver disable 0=noeffect. 1 = the receiver is disabled. txen: transmitter enable 0=noeffect. 1 = the transmitter is enabled if txdis is 0. txdis: transmitter disable 0=noeffect. 1 = the transmitter is disabled. rststa: reset status bits 0=noeffect. 1 = resets the status bits pare, frame, ovre and rxbrk in the us_csr. sttbrk: start break 0=noeffect. 1 = if break is not being transmitted, start transmission of a break after the characters present in us_thr and the transmit shift register have been transmitted. stpbrk: stop break 0=noeffect. 1 = if a break is being transmitted, stop transmission of the break after a minimum of one character length and transmit a high level during 12-bit periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? rtsdis rtsen dtrdis dtren 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ??
28 USART3 1739c ? casic ? 03/02 sttto: start time-out 0=noeffect 1 = start waiting for a character before clocking the time-out counter. senda: send address 0=noeffect. 1 = in multi-drop mode only, the next character written to the us_thr is sent with the address bit set. rstit: reset iterations note: this bit only has an effect in iso7816 mode. 0=noeffect. 1 = resets the status bit iteration. rstnack: reset non acknowledge 0=noeffect 1 = resets the status bit nack retto: rearm time-out 0=noeffect 1 = restart time-out dtren: data terminal ready enable 0=noeffect. 1=thedtrpinisforcedto0. dtrdis: data terminal ready disable 0=noeffect. 1=thedtrpinisforcedto1. rtsen: request to send enable 0=noeffect. 1=thertspinisforcedto0. rtsdis: request to send disable 0=noeffect. 1=thertspinisforcedto1.
29 USART3 1739c ? casic ? 03/02 USART3 mode register name: us_mr access type: read/write USART3_mode note: the baud rate clock used in mode is07816 can be configured via the register fi_di_ratio. the modes are described in detail in the register descriptions and tables which follow. usclks: clock selection (baud rate generator input clock) chrl: character length 31 30 29 28 27 26 25 24 ??? filter ? max_iteration 23 22 21 20 19 18 17 16 ?? dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks USART3_mode USART3_mode modes of the USART3 0000normal 0001rs485 0010hardwareh andshaking 0011m odem 0100is 07816 protocol: t = 0 0110is 07816 protocol: t = 1 1000irda 1100softwarehandshaking usclks selected clock 00clock 01fdiv1 10slow_clock(arm) 1 1 external (sck)
30 USART3 1739c ? casic ? 03/02 start, stop and parity bits are added to the character length. sync: synchronous mode select 0 = usart operates in asynchronous mode. 1 = usart operates in synchronous mode par: parity type when the par field is set to even parity, the parity bit is set ( ? 1 ? ) if the data parity is odd in order to ensure an even parity on the data and parity field. nbstop: number of stop bits the interpretation of the number of stop bits depends on sync. note: 1.5or2stopbitsarereservedforthetxfunction.therxfunctionusesonlythe1stopbit(thereisnocheckonthe2stopbit time slot if nbstop = 10). chmode: channel mode chrl character length 005bits 016bits 107bits 118bits par parity type 0 0 0 even parity 0 0 1 odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 10xnoparity 1 1 x multi-drop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1stopbit 1stopbit 0 1 1.5 stop bits reserved 1 0 2stopbits 2stopbits 1 1 reserved reserved chmode mode description 0 0 normal mode the USART3 channel operates as an rx/tx USART3.
31 USART3 1739c ? casic ? 03/02 msbf:bitorder 0=lsbfirst 1=msbfirst mode9: 9-bit character length 0 = chrl defines character length. 1 = 9-bit character length. mode9 has priority on character length. cklo: clock output select 0 = the usart does not drive the sck pin. 1 = the usart drives the sck pin if usclks[1] is 0. over: oversampling mode 0 = 16x oversampling 1 = 8x oversampling inack: inhibit non acknowledge 0 = the nack is generated 1 = the nack is not generated note: this bit will be used only in iso7816 mode, protocol t = 0 receiver. dsnack: disable successive nack 0 = nack is sent on the iso line as soon as a parity error occurs in the received character (unless inack is set). 1 = successive parity errors are counted up to the value specified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is reached, no additional nack is sent on the iso line. the flag iteration is asserted. max_iteration filter: receive line filter 0 = the USART3 does not filter the receive line. 1 = the USART3 filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). 01automaticecho receiver data input is connected to the txd pin. 1 0 local loopback transmitter output signal is connected to receiver input signal. 1 1 remote loopback rxd pin is internally connected to txd pin. max_iteration number of repetitions 0 -7 this will operate in mode iso7816, protocol t = 0 only
32 USART3 1739c ? casic ? 03/02 USART3 interrupt enable register name: us_ier access type: write-only rxrdy: enable rxrdy interrupt 0=noeffect. 1 = enables rxrdy interrupt. txrdy: enable txrdy interrupt 0=noeffect. 1 = enables txrdy interrupt. rxbrk: enable receiver break interrupt 0=noeffect. 1 = enables receiver break interrupt. endrx: enable end of receive transfer interrupt 0=noeffect. 1 = enables end of receive transfer interrupt. endtx: enable end of transmit interrupt 0=noeffect. 1 = enables end of transmit interrupt. ovre: enable overrun error interrupt 0=noeffect. 1 = enables overrun error interrupt. frame: enable framing error interrupt 0=noeffect. 1 = enables framing error interrupt. pare: enable parity error interrupt 0=noeffect. 1 = enables parity error interrupt. timeout: enable time-out interrupt 0=noeffect. 1 = enables reception time-out interrupt. 31 30 29 28 27 26 25 24 comm_rx comm_tx ?????? 23 22 21 20 19 18 17 16 ???? ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ?? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
33 USART3 1739c ? casic ? 03/02 txempty: enable txempty interrupt 0=noeffect. 1 = enables txempty interrupt. iteration: enable iteration interrupt note: this will operate only in is07816 mode, protocol t = 0. 0=noeffect. 1 = enables iteration interrupt. txbufe: enable buffer empty interrupt 0=noeffect. 1 = enables buffer empty interrupt. rxbuff: enable buffer full interrupt 0=noeffect. 1 = enable buffer full interrupt. nack: enable non acknowledge interrupt 0=noeffect. 1 = enable non acknowledge interrupt riic: enable ring indicator input change 0=noeffect. 1 = enables ring indicator input change interrupt. dsric: enable data set ready input change 0=noeffect. 1 = enables data set ready input change interrupt. dcdic: enable data carrier detect input change interrupt 0=noeffect. 1 = enables data carrier detect input change interrupt. ctsic: enable clear to send input change interrupt 0=noeffect. 1 = enables clear to send input change interrupt. comm_tx: enable comm_tx (from arm) interrupt 0=noeffect. 1 = enables comm_tx interrupt. comm_rx: enable comm_rx (from arm) interrupt 0=noeffect. 1 = enables comm_rx interrupt.
34 USART3 1739c ? casic ? 03/02 USART3 interrupt disable register name: us_idr access type: write-only rxrdy: disable rxrdy interrupt 0=noeffect. 1 = disables rxrdy interrupt. txrdy: disable txrdy interrupt 0=noeffect. 1 = disables txrdy interrupt. rxbrk: disable receiver break interrupt 0=noeffect. 1 = disables receiver break interrupt. endrx: disable end of receive transfer interrupt 0=noeffect. 1 = disables end of receive transfer interrupt. endtx: disable end of transmit interrupt 0=noeffect. 1 = disables end of transmit interrupt. ovre: disable overrun error interrupt 0=noeffect. 1 = disables overrun error interrupt. frame: disable framing error interrupt 0=noeffect. 1 = disables framing error interrupt. pare: disable parity error interrupt 0=noeffect. 1 = disables parity error interrupt. timeout: disable time-out interrupt 0=noeffect. 1 = disables receiver time-out interrupt. 31 30 29 28 27 26 25 24 comm_rx comm_tx ?????? 23 22 21 20 19 18 17 16 ???? ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ?? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
35 USART3 1739c ? casic ? 03/02 txempty: disable txempty interrupt 0=noeffect. 1 = disables txempty interrupt. iteration: disable iteration interrupt note: this will operate only in is07816 mode, protocol t = 0. 0=noeffect. 1 = disables iteration interrupt. txbufe: disable buffer empty interrupt 0=noeffect. 1 = disables buffer empty interrupt. rxbuff: disable buffer full interrupt 0=noeffect. 1 = disables buffer full interrupt. nack: disable non acknowledge interrupt 0=noeffect. 1 = disable non acknowledge interrupt riic: disable ring indicator input change 0=noeffect. 1 = disables ring indicator input change interrupt. dsric: disable data set ready input change 0=noeffect. 1 = disables data set ready input change interrupt. dcdic: disable data carrier detect input change interrupt 0=noeffect. 1 = disables data carrier detect input change interrupt. ctsic: disable clear to send input change interrupt 0=noeffect. 1 = disables clear to send input change interrupt. comm_tx: disable comm_tx (from arm) interrupt 0=noeffect. 1 = disables comm_tx interrupt. comm_rx: disable comm_rx (from arm) interrupt 0=noeffect. 1 = disables comm_rx interrupt.
36 USART3 1739c ? casic ? 03/02 USART3 interrupt mask register name: us_imr access type: read-only rxrdy: mask rxrdy interrupt 0 = rxrdy interrupt is disabled. 1 = rxrdy interrupt is enabled. txrdy: mask txrdy interrupt 0 = txrdy interrupt is disabled. 1 = txrdy interrupt is enabled. rxbrk: mask receiver break interrupt 0 = receiver break interrupt is disabled. 1 = receiver break interrupt is enabled. endrx: mask end of receive transfer interrupt 0 = end of receive transfer interrupt is disabled. 1 = end of receive transfer interrupt is enabled. endtx: mask end of transmit interrupt 0 = end of transmit interrupt is disabled. 1 = end of transmit interrupt is enabled. ovre: mask overrun error interrupt 0 = overrun error interrupt is disabled. 1 = overrun error interrupt is enabled. frame: mask framing error interrupt 0 = framing error interrupt is disabled. 1 = framing error interrupt is enabled. pare: mask parity error interrupt 0 = parity error interrupt is disabled. 1 = parity error interrupt is enabled. timeout: mask time-out interrupt 0 = receive time-out interrupt is disabled. 1 = receive time-out interrupt is enabled. 31 30 29 28 27 26 25 24 comm_rx comm_tx ?????? 23 22 21 20 19 18 17 16 ???? ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ?? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
37 USART3 1739c ? casic ? 03/02 txempty: mask txempty interrupt 0 = txempty interrupt is disabled. 1 = txempty interrupt is enabled. iteration: mask iteration interrupt note: this will operate only in is07816 mode, protocol t = 0. 0 = iteration interrupt is disabled. 1 = iteration interrupt is enabled. txbufe: mask buffer empty interrupt 0 = txbufe interrupt is disabled. 1 = txbufe interrupt is enabled. rxbuff: mask buffer full interrupt 0 = rxbuff interrupt is disabled. 1 = rxbuff interrupt is enabled. nack: mask non acknowledge interrupt 0 = nack interrupt is disabled. 1 = nack interrupt is enabled. riic: mask ring indicator input change 0 = riic interrupt is disabled. 1 = riic interrupt is enabled. dsric: mask data set ready input change 0 = dsric interrupt is disabled. 1 = dsric interrupt is enabled. dcdic: mask data carrier detect input change interrupt 0 = dcdic interrupt is disabled. 1 = dcdic interrupt is enabled. ctsic: mask clear to send input change interrupt 0 = ctsic interrupt is disabled. 1 = ctsic interrupt is enabled. comm_tx: mask comm_tx (from arm) interrupt 0 = comm_tx interrupt is disabled. 1 = comm_tx interrupt is enabled. comm_rx: mask comm_rx (from arm) interrupt 0 = comm_rx interrupt is disabled. 1 = comm_rx interrupt is enabled.
38 USART3 1739c ? casic ? 03/02 USART3 channel status register name: us_csr access type: read-only rxrdy: receiver ready 0 = no complete character has been received since the last read of the us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1 = at least one complete character has been received and the us_rhr has not yet been read. txrdy: transmitter ready 0 = a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1 = there is no character in the us_thr. equal to zero when the USART3 is disabled or at reset. the transmitter enable command (in us_cr) sets this bit to 1 if the transmitter was previously disabled. rxbrk: break received/end of break 0 = no break received or end of break detected since the last reset status bits command in the control register. 1 = break received or end of break detected since the last reset status bits command in the control register. endrx: end of receiver transfer 0 = the end of transfer signal from the peripheral data controller channel dedicated to the receiver is inactive. 1 = the end of transfer signal from the peripheral data controller channel dedicated to the receiver is active. endtx: end of transmitter transfer 0 = the end of transfer signal from the peripheral data controller channel dedicated to the transmitter is inactive. 1 = the end of transfer signal from the peripheral data controller channel dedicated to the transmitter is active. ovre: overrun error 0 = no byte has been transferred from the receive shift register to the us_rhr when rxrdy was asserted since the last reset status bits command. 1 = at least one byte has been transferred from the receive shift register to the us_rhr when rxrdy was asserted since the last reset status bits command. frame: framing error 0 = no stop bit has been detected low since the last reset status bits command. 1 = at least one stop bit has been detected low since the last reset status bits command. 31 30 29 28 27 26 25 24 comm_rx comm_tx ?????? 23 22 21 20 19 18 17 16 cts dcd dsr ri ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ?? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
39 USART3 1739c ? casic ? 03/02 pare:parityerror 1 = at least one parity bit has been detected as false (or a parity bit high in multi-drop mode) since the last reset status bits command. 0 = no parity bit has been detected as false (or a parity bit high in multi-drop mode) since the last reset status bits command. timeout: receiver time-out 0 = there has not been a time-out since the last start time-out command or the time-out register is 0. 1 = there has been a time-out since the last start time-out command. txempty: transmitter empty 0 = there are characters in either us_thr or the transmit shift register, or the transmitter is disabled. 1 = there are no characters in either us_thr or the transmit shift register. txempty is 1 after parity, stop bit and time- guard have been transmitted. txempty is 1 after stop bit has been sent, or after time-guard has been sent if us_ttgr is not 0. equal to zero when the USART3 is disabled or at reset. the transmitter enable command (in us_cr) sets this bit to one if the transmitter is disabled. iteration: max number of repetitions reached note: this bit will operate only in is07816 mode, protocol t = 0. 0 = max number of repetitions has not been reached. 1 = max number of repetitions has been reached. a repetition consists of transmitted characters or successive nack. txbufe: transmission buffer empty 0 = pdc2 transmission buffer is not empty. 1 = pdc2 transmission buffer is empty. rxbuff: reception buffer full 0 = pdc2 reception buffer is not full. 1 = pdc2 reception buffer is full. nack: non acknowledge 0 = a non acknowledge has not been detected. 1 = a non acknowledge has been detected. riic: ring indicator input change flag 0 = no input change has been detected on the ri pin since the last read of us_csr. 1 = an input change has been detected on the ri pin. dsric:datasetreadyinputchangeflag 0 = no input change has been detected on the dsr pin since the last read of us_csr. 1 = an input change has been detected on the dsr pin. dcdic: data carrier detect input change flag 0 = no input change has been detected on the dcd pin since the last read of us_csr. 1 = an input change has been detected on the dcd pin. ctsic: clear to send input change flag 0 = no input change has been detected on the cts pin since the last read of us_csr. 1 = an input change has been detected on the cts pin. ri: image of ri input 0 = ri is at 0. 1 = ri is at 1.
40 USART3 1739c ? casic ? 03/02 dsr: image of dsr input 0=dsr 1=dsrisat1. dcd: image of dcd input 0=dcdisat0. 1=dcdisat1. cts: image of cts input 0=ctsisat0. 1=ctsisat1. comm_tx: (from arm) 0=comm_txisat0. 1=comm_txisat1. comm_rx: (from arm) 0=comm_rxisat0. 1=comm_rxisat1.
41 USART3 1739c ? casic ? 03/02 USART3 receiver holding register name: us_rhr access type: read-only rxchr: received character last character received if rxrdy is set. when the number of data bits is less than 9 bits, the bits are right-aligned. all non- significant bits read zero. USART3 transmitter holding register name: us_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. when the number of data bits is less than 9 bits, the bits are right-aligned. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? rxchr 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? txchr 76543210 txchr
42 USART3 1739c ? casic ? 03/02 USART3 baud rate generator register name: us_brgr access type: read/write cd: clock divisor this register has no effect if synchronous mode is selected with an external clock. notes: 1. in synchronous mode, when either external clock (clk_ext or fdiv1) is selected, the value programmed must be even to ensure a 50:50 mark:space ratio. in synchronous mode, when the internal clock (clock) is selected, the cd can be even and the duty clock is 50:50. 2. clock divisor bypass (cd = 1) must not be used when the internal clock (clock) is selected (usclks = 0). 3. in asynchronous mode, the divisor of selected clock depends upon the value of the bit, over in us_mr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd description 0 disables clock 1 clock divisor bypass 2 to 65535 baud rate (asynchronous mode) = selected clock/(16 x cd) or (8 x cd) baud rate (synchronous mode) = selected clock/cd
43 USART3 1739c ? casic ? 03/02 USART3 receiver time-out register name: us_rtor access type: read/write to:time-outvalue USART3 transmitter time-guard register name: us_ttgr access type: read/write tg:time-guardvalue time-guard duration = tg x bit period 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to to description 0 disables the rx time-out function. 1 - 65535 the time-out counter is loaded with to (16 bits) when the start time-out command is given or when each new data character is received (after reception has started). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg tg description 0 disables the tx time-guard function. 1 - 255 txd is inactive high after the transmission of each character for the time-guard duration.
44 USART3 1739c ? casic ? 03/02 USART3 fi_di_ratio register (1) name: us_fidi access type: read/write reset value: 0x174 (2) notes: 1. this register has no effect if iso7816 mode is not selected. 2. the hexadecimal value is 0x174. the corresponding decimal value is 372. fi_di_ratio: fi over di ratio value parameter used in mode iso7816 to generate a specific bit rate. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio fi_di_ratio description 0 baud rate = 0 1 - 2047 baud rate = selected clock /fi_di_ratio/16
45 USART3 1739c ? casic ? 03/02 USART3 nb errors register name: us_ner access type: read-only nb_errors: error number during iso7816 transfers this 8-bit register presents the total amount of errors that occurred during an iso7816 transfer. it is a read-only register and it is reset by reading the register. USART3 xon_xoff register name: us_xxr access type: read/write xon, xoff characters 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 xon 76543210 xoff xon/xoff description bit 15 to bit 8 xon character bit 7 to bit 0 xoff character
46 USART3 1739c ? casic ? 03/02 USART3 irda_filter register name: us_if access type: read/write irda_filter 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter irda_filter description 0 ? 255 parameter to reject pulses on irda reception
47 USART3 1739c ? casic ? 03/02 document details title USART3 literature number 1739c revision history version a publication date: 17-july-2001 version b publication date: 11-nov-2001 version c publication date: 26-feb-2002 revisions since previous version page: 2 ? iso_txd_in ? input pin added to symbol. page: 3 ? iso_txd_in ? input pin added to pin description table. page: 4 function of ? rx_buf_full ? signal changed in pin description table. page: 4 function of ? tx_buf_empty ? signal changed in pin description table. page: 5 ? iso_txd_in input ? pin added to block diagram. page: 17 figure 12. iso mode connection, new drawing added. page: 21 table7, description of supplemental protocol t = 0 characteristics, text changed. page: 21 table7, non acknowledge inhibited, text changed. page 22 ? irda mode ? section, bit order changed. page: 23 ? soft handshaking mode ? section, bit order changed. page: 23 ? hardware handshaking mode ? section, text changed. page: 25 text changed in ? modem mode ? section. page: 26 table 8. usart2 memory map, fi_di ratio register, reset state noted. page: 29 USART3_mode, table note amended. page: 44 fi_di ratio register, reset state noted.
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