108 ps8341b 03/05/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 pi6c9910 zero-delay clock buffer block diagram features ? zero input to output delay ? eight clock copies from one clock input ? 15 - 80 mhz output operation ? fifty percent duty cycle ? low skew (< 250ps typ.) ?v cc = 5.0v +/- 10%, t a = 0 to 70 ? low jitter (< 250 ps cycle to cycle), < 60ps rms ? low noise unbalanced drive outputs (pi6c9910-5) ? low noise balanced drive outputs (pi6c9910a) ? packages available: ? 24-pin 300 mil wide soic (s) ? 24-pin 209 mil wide ssop (h) ? compatible with cypress cy7b9910-5 test mode in normal operation the test pin is tied to ground. for testing purposes it can have a removable jumper to ground or a 100 w pull-down resistor. when the test pin is driven high, the vco output is disconnected, and all eight outputs (q0-q7) are directly driven from the ref input. pinout description the pi6c9910 is a low-skew clock driver designed to simplify clock distribution in systems requiring near synchronous clocks. a typical application is in sdram modules. each of the eight outputs (q0-q7) can drive individual 50 w transmission lines with minimal distortion or skew, and full 5v swing. an on-chip phase-locked loop (pll) synchronizes the feedback (fb) to the reference (ref) input, achieving ?zero-delay? buffered outputs. inserting an external counter between any of the qx outputs and the fb pin allows for generation of eight synchronous clock copies whose frequency is a multiple of a lower frequency ref input. the voltage-controlled oscillator (vco) frequency is determined by the filtered ouput coming from the phase/frequency detector. the frequency select (fs) input sets the vco operating range. pi6c9910-5 has unbalanced output drivers (ttl), and is fully compati ble with the cypress cy7b9910-5. the pi6c9910a f eatures balanced-drive outputs (cmos) for improved rise/fall time symmetry. the fs and test inputs have internal pull-up resistors. ref v ccq fs nc v ccq v ccn q 0 q1 gnd q2 q3 v ccn gnd test nc gnd v ccn q7 q6 gnd q5 q4 v ccn fb 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 24-pin s, h voltage controlled oscillator filter phase freq. det fb test ref fs q0 q1 q2 q3 q4 q5 q6 q7
pi6c9910 zero-delay clock buffer 109 ps8341b 03/05/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 storage temperature................................................. ?65c to +150c ambient temperature with power applied .............. ?55c to +125c supply voltage to ground potential ............................ ?0.5v to +7.0v dc input voltage ......................................................... ?0.5v to +7.0v output current into outputs (low) ........................................... 64ma static discharge voltage (per mil-std-883, method 3015) >2001v latch-up current .................................................................... >200ma note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. pin description operating range e g n a re r u t a r e p m e t t n e i b m av cc l a i c r e m m o c0 0 7 + o t c c% 0 1 v 5 e m a n n i po / in o i t p i r c s e d l a n o i t c n u f f e ri y c n e u q e r f e h t s e i l p p u s t u p n i s i h t . t u p n i y c n e u q e r f e c n e r e f e r . d e r u s a e m s i n o i t a i r a v l a n o i t c n u f l l a h c i h w t s n i a g a g n i m i t d n a b fi t h g i e f o e n o o t d e t c e n n o c y l l a c i p y t ( t u p n i k c a b d e e f l l p . ) s t u p t u o s fi - l l u p l a n r e t n i . 1 e l b a t e e s . t c e l e s e g n a r y c n e u q e r f l e v e l - o w t . p u t s e ti p u - l l u p l a n r e t n i . n o i t c e s e d o m t s e t e e s . t c e l e s l e v e l - o w t ] 7 - 0 [ qo . s t u p t u o k c o l c v ccn r w p. s r e v i r d t u p t u o r o f y l p p u s r e w o p v ccq r w p. y r t i u c r i c l a n r e t n i r o f y l p p u s r e w o p d n gr w p. d n u o r g maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.)
pi6c9910 zero-delay clock buffer 110 ps8341b 03/05/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 electrical characteristics over operating range (1) notes: 1. these inputs are normally wired to v cc , gnd. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time betore all datasheet limits are achieved. 2. tested one output at a time, output shorted for less than one second, less than l0% duty cycle. room temperature only. capacitance (t a = 25 c, f = 1 mhz) l o b m y sr e t e m a r a ps n o i t i d n o c t s e t. n i m. x a ms t i n u v oh ) 5 - 0 1 9 9 c 6 i p ( e g a t l o v h g i h t u p t u ov cc i , . n i m = oh a m 6 1 - = 4 . 2 ? v v ol ) 5 - 0 1 9 9 c 6 i p ( e g a t l o v w o l t u p t u ov cc i , . n i m = ol a m 6 4 = ? 5 4 . 0 v oh ) a 0 1 9 9 c 6 i p ( e g a t l o v h g i h t u p t u ov cc i , . n i m = oh a m 4 2 - = 4 . 2 ? v ol ) a 0 1 9 9 c 6 i p ( e g a t l o v w o l t u p t u ov cc i , . n i m = ol a m 4 2 = ? 0 4 . 0 i ih t n e r r u c e g a k a e l h g l h t u p n i ) y l n o s t u p n i b f d n a , s f , t s e t , f e r ( v cc v , . x a m = in . x a m = ? 0 1 m a i il t n e r r u c e g a k a e l w o l t u p n i ) y l n o s t u p n i b f d n a f e r ( v cc v , . x a m = in v 4 . 0 = - 0 1 ? t n e r r u c e g a k a e l w o l t u p n i ) y l n o s t u p n i s f d n a t s e t ( 0 0 5 - ? i os t n e r r u c t i u c r i c t r o h s t u p t u o ) 2 ( v cc v , . x a m = out 5 2 ( d n g = ) y l n o c ?- 0 5 2 a m i ccq t n e r r u c g n i t a r e p o y r t i u c r i c l a n r e t n i y b d e s u v ccn v = ccq , . x a m = n e p o s t c e l e s s t u p n i l l a ? 5 8 i ccn t n e r r u c r e f f u b t u p t u o r i a p t u p t u o r e p v ccn v = ccq , . x a m = i out a m 0 = f , n e p o s t c e l e s s t u p n i max ? 4 1 d p n o i t a p i s s i d r e w o p r i a p t u p t u o r e p v ccn v = ccq , . x a m = i out a m 0 = f , n e p o s t c e l e s s t u p n i max ? 8 7w m r e t e m a r a p n o i t p i r c s e ds n o i t i d n o c t s e t . x a ms t i n u c in e c n a t i c a p a c t u p n i b f d n a f e r t a v , z h m 1 = f , c 5 2 = cc v 0 . 5 =0 1f p
pi6c9910 zero-delay clock buffer 111 ps8341b 03/05/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 unbalanced output drive ac test load and waveform ac timing diagram ttl ac test load ttl input test waveform 2.0v vth = 1.5v 0.8v 0.0v 2.0v vth = 1.5v 0.8v 1 ns 1 ns table 1. frequency range select 3.0v 5v r1 r2 c l r1 = 130 w r2 = 91 w c l = 30pf (includes fixture and probe capacitance) s f f nom ) z h m ( m u m i n i mm u m i x a m w o l5 15 3 h g i h5 20 8 t pd t rpwh t ref t rpwl t odcv t skew t skew t jr t odcv other q q fb ref
pi6c9910 zero-delay clock buffer 112 ps8341b 03/05/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com switching characteristics over operating range (1) notes: 1. test measurement levels for the pi6c9910-5 are ttl levels (1.5v to 1.5v). test conditions assume signal transition times of 2ns or less and output loading as shown in the ac test loads and waveforms unless otherwise specified. 2. skew is defined as the time between the earliest and the latest output transition among all outputs with ac test load. 3. t skew is defined as the skew between outputs. 4. t dev is the output-to-output skew between any two outputs on separate devices operating under the same conditions (v cc , ambient temperature, air flow, etc.). 5. tested initially and after any design or process changes that may affect these parameters. 6. t odcv is the deviation of the output from a 50% duty cycle. 7. specified with outputs loaded with ac test load (30pf). 8. t orise and t ofall measured between 0.8v and 2.0v. 9. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. l o b m y sn o i t p i r c s e d. n i m. p y t. x a ms t i n u f nom k c o l c n o i t a r e p o z h m n i y c n e u q e r f w o l = s f5 1? 5 3 z h m h g i h = s f5 2? 0 8 t rpwh h g i h h t d i w e s l u p f e r0 . 5?? s n t rpwl w o l h t d i w e s l u p f e r0 . 5?? t skew ) s t u p t u o l l a ( w e k s t u p t u o o r e z ) 3 , 2 ( ?5 2 . 05 . 0 t dev w e k s e c i v e d - o t - e c i v e d ) 5 , 4 ( ?? 0 . 1 t pd e s i r b f o t e s i r f e r , y a l e d n o i t a g a p o r p5 . 0 -0 . 05 . 0 + t odcv n o i t a i r a v e l c y c y t u d t u p t u o ) 6 ( 0 . 1 -0 . 00 . 1 + t orise e m i t e s i r t u p t u o ) 8 , 7 ( 5 1 . 00 . 15 . 1 t ofall e m i t l l a f t u p t u o ) 8 , 7 ( 5 1 . 00 . 15 . 1 t lock e m i t k c o l l l p ) 9 ( ?? 5 . 0s m t jr r e t t i j t u p t u o e l c y c - o t - e l c y c ) 5 ( ?? 0 5 2 s p s m r ) 5 ( ?? 0 6
pi6c9910 zero-delay clock buffer 113 ps8341b 03/05/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 seating plane .050 bsc 1 0-8? .2914 .2992 x.xx x.xx denotes dimensions in millimeters 7.40 7.60 .5985 .6141 15.20 15.60 1.27 .0926 .1043 2.35 2.65 .394 .419 10.00 10.65 .0040 .0118 0.10 0.30 .013 .020 0.33 0.51 .010 .029 0.254 0.737 .0091 .0125 0.23 0.32 0.41 1.27 .016 .050 x 45? 24 .021 .031 0.533 0.787 .311 .334 .078 .002 seating plane .0098 max. .0256 bsc .022 .037 .004 .009 .291 .322 1 24 .197 .220 0.25 x.xx x.xx denotes dimensions in millimeters 0.050 7.40 8.20 0.55 0.95 0.09 0.25 5.00 5.60 2.0 7.90 8.50 0.65 max min package mechanical information 300-mil 24-pin soic 209-mil 24-pin ssop ordering information r e b m u n t r a pe g a k c a p s a 0 1 9 9 c 6 i p4 2 s e g a k c a p c i o s n i p - 4 2 l i m - 0 0 3 h a 0 1 9 9 c 6 i p4 2 h e g a k c a p p o s s n i p - 4 2 l i m - 9 0 2 s 5 - 0 1 9 9 c 6 i p4 2 s e g a k c a p c i o s n i p - 4 2 l i m - 0 0 3 h 5 - 0 1 9 9 c 6 i p4 2 h e g a k c a p p o s s n i p - 4 2 l i m - 9 0 2
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