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1997 document no. s10766ej9v0um00 (9th edition) date published march 1997 n cp(n) printed in japan m pD72103A hdlc controller m pD72103A
notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 the export of this product from japan is prohibited without governmental license. to export or re-export this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. v25+ is a trademark of nec corporation.
preface target users this manual describes the functions of the m pD72103A to engineers who will use the m pD72103A when designing application systems. objective the objective of this manual is to describe the hardware functions of the m pD72103A, which includes the following components. composition this manual can be broadly divided into the following sections. general bus interface communication operations commands status system configuration example example of m pD72103A?s operation sequence connecting hdlc controller to a motorola system questions and answers about the m pD72103A command list status list use this manual assumes that the reader has a general knowledge of electricity, logic circuits, and microcontrollers. users who would like to check commands ? read chapter 4 command list . users who would like to learn about the m pD72103A?s functions ? read this manual in the order shown in the table of contents. users who have questions about the m pD72103A?s operations ? read appendix c q&a .
legend data representation weight : high-order digits are indicated at left and low-order digits at right. active low representation : xxx (pin or signal name is overlined) or xxxb (b is added after signal and pin names) memory map address : high order at low stage and low order at high stage (address 0h) note : explanation of note in the text caution : item deserving extra attention remark : supplementary explanation to the text number representation : decimal number is xxxx hexadecimal number is xxxxh appendix c uses the following abbreviations for reference documentation. data sheet ? ds user?s manual ? um application note ? an related documentation document name data sheet user?s manual application note m pD72103A s10189j note this manual ? the corresponding application note for this manual is the m pd72103 application note (iea-713 note ). in this application note, all references to the m pd72103 should be understood as referring to the m pD72103A. note this document number is that of the japanese version.
e i e table of contents chapter 1 general ............................................................................................................................ 1 1.1 features ............................................................................................................................... ...... 1 1.2 block diagram .......................................................................................................................... 2 1.3 internal block functions ......................................................................................................... 3 1.4 pin configuration (top view) ................................................................................................. 4 1.5 pin functions ........................................................................................................................... 6 1.6 initialization via reset ........................................................................................................... 11 chapter 2 bus interface ..............................................................................................................13 2.1 internal registers ...................................................................................................................13 2.1.1 control register .......................................................................................................... ................... 14 2.1.2 internal status register .................................................................................................. ................ 15 2.2 dmac (direct memory access controller) .........................................................................16 2.2.1 block transfers ........................................................................................................... ................... 16 2.2.2 extension of active (low-level) width of mrd and mwr signals ................................................... 17 2.2.3 basic timing of dma ....................................................................................................... ............... 18 2.2.4 address/data multiplexing ................................................................................................. ............ 20 2.3 interface between m pD72103A and host processor ......................................................... 22 2.3.1 command issuance .......................................................................................................... ............ 23 2.3.2 status report ............................................................................................................. .................... 25 2.3.3 command chain function .................................................................................................... .......... 26 2.4 initialization of external memory .........................................................................................27 2.5 methods for using external memory .................................................................................. 27 2.5.1 command table ............................................................................................................. ................ 27 2.5.2 status table .............................................................................................................. ..................... 32 2.5.3 receive buffer address table .............................................................................................. .......... 36 2.5.4 receive buffer ............................................................................................................ ................... 45 2.5.5 transmit buffer ........................................................................................................... ................... 45 2.5.6 external memory table configuration example .............................................................................. 4 5 chapter 3 communication operations ...................................................................................47 3.1 initial settings ........................................................................................................................47 3.2 start of communication control operation and flag synchronization setup ............. 48 3.2.1 transmit operation ........................................................................................................ ................ 48 3.2.2 receive operation ......................................................................................................... ................ 48 3.2.3 status reporting .......................................................................................................... ................... 48 3.3 data transmission .................................................................................................................49 3.3.1 transmission timing ....................................................................................................... ............... 49 3.3.2 linkage of transmit data .................................................................................................. .............. 49 3.3.3 transmit buffer chain ..................................................................................................... ............... 50 3.3.4 transmission underrun ..................................................................................................... ............ 50 3.4 data reception .......................................................................................................................51 3.4.1 reception timing .......................................................................................................... ................. 51 3.4.2 separation of receive data ................................................................................................ ............ 53
e ii e 3.4.3 receive buffer chain ...................................................................................................... ............... 53 3.4.4 address field recognition ................................................................................................. .............. 53 3.4.5 discarding of abnormal frames ............................................................................................. ........ 53 3.4.6 idle monitor timer ........................................................................................................ .................. 54 3.4.7 idle reception count ...................................................................................................... ................. 54 3.4.8 cautions regarding overrun errors ......................................................................................... ....... 55 3.5 completion of transmit/receive operation .......................................................................58 3.6 transmit and receive frame flags .....................................................................................58 3.6.1 transmit frame flags ...................................................................................................... ............... 58 3.6.2 receive frame flags ....................................................................................................... ............... 58 3.7 general-purpose input/output pins ....................................................................................58 3.7.1 detection of changes in general-purpose input pins ..................................................................... 58 3.7.2 control of general-purpose output pins .................................................................................... .... 58 3.7.3 general-purpose input/output pin status ................................................................................... .... 58 chapter 4 commands (lcw) ..........................................................................................................59 chapter 5 status (lsw) ..................................................................................................................87 chapter 6 system configuration examples ...................................................................... 113 6.1 connection with host system ........................................................................................... 113 6.1.1 local memory type ......................................................................................................... ..............113 6.1.2 main memory type .......................................................................................................... .............114 6.2 physical interface examples .............................................................................................. 115 6.2.1 interface example using rs-485 ............................................................................................ ..... 115 6.2.2 interface example using m pd98201 .............................................................................................115 appendix a m pD72103A operation sequence examples .................................................. 117 appendix b connection between hdlc controller and motorola system ...... 119 b.1 differences between nec/intel buses and motorola buses ......................................... 119 b.1.1 difference in allocation of physical even-numbered byte and odd-numbered byte in 16-bit bus .......................................................................................... 11 9 b.1.2 difference in representation order of logical 16-bit and 24-bit data ............................................. 119 b.2 method for connecting hdlc controller with motorola-based system ..................... 120 b.2.1 data bus connection in hardware ........................................................................................... .... 120 b.2.2 hdlc controller?s mdst command setting (operation mode setting lcw) ............................... 120 appendix c questions and answers about the m pD72103A ......................................... 121 appendix d command list ........................................................................................................... 161 appendix e status list ................................................................................................................ 163
e iii e list of figure figure no. title page 2-1 control register ............................................................................................................................... ........ 14 2-2 internal status register ........................................................................................................................... 15 2-3 basic clocks in one bus cycle during block transfer .......................................................................... 16 2-4 example: two programmable waits ...................................................................................................... 17 2-5 memory write timing ............................................................................................................................... 18 2-6 memory read timing ............................................................................................................................... 19 2-7 byte mode (b/w = 0) ............................................................................................................................... 20 2-8 word mode (b/w = 1) .............................................................................................................................. 2 1 2-9 command/status handling between m pD72103A and host processor ................................................ 22 2-10 flow chart for writing memory area setting lcw command to internal fifo ................................. 24 2-11 status report (when status area is lsw0 to lsw2) ............................................................................ 26 2-12 command table ............................................................................................................................... ........ 28 2-13 command fetch operation ..................................................................................................................... 30 2-14 status table ............................................................................................................................... ............... 32 2-15 status information operations ................................................................................................................ 34 2-16 receive buffer address table ................................................................................................................. 36 2-17 initial status (line closed) ...................................................................................................................... 38 2-18 after line open command is issued ...................................................................................................... 39 2-19 rbafifo full status ............................................................................................................................... 40 2-20 reception of first frame ......................................................................................................................... 41 2-21 completion of first frame reception (fcs error) ................................................................................. 42 2-22 start of second frame reception ........................................................................................................... 43 2-23 completion of second frame reception ................................................................................................ 44 2-24 external memory configuration example ............................................................................................... 45 3-1 initialization steps for m pD72103A and external memory ..................................................................... 47 3-2 transmission timing ............................................................................................................................... .49 3-3 reception timing (external clock mode) ............................................................................................... 51 3-4 reception timing (dpll mode) .............................................................................................................. 52 3-5 idle reception count ............................................................................................................................... 54 6-1 m pD72103A system configuration example (local memory type) .................................................... 113 6-2 m pD72103A system configuration example (main memory type) ..................................................... 114 6-3 two-wire interface example .................................................................................................................. 115 6-4 connection example with isdn lsi (connection with sifc [ m pd98201]) .......................................... 115
e iv e list of table table no. title page 1-1 pin status after reset .............................................................................................................................. 1 1 2-1 i/o port map ............................................................................................................................... .............. 13 2-2 control register ............................................................................................................................... ........ 14 2-3 internal status register ........................................................................................................................... 15 2-4 bus cycles in byte transfer mode and word transfer mode ............................................................... 16 2-5 command fields ............................................................................................................................... ....... 29 2-6 status fields ............................................................................................................................... ............. 33 2-7 receive buffer address fields ................................................................................................................ 37 2-8 external memory table configuration example ..................................................................................... 45 3-1 reception timing mode settings ............................................................................................................ 51 c-1 question categories .............................................................................................................................. 1 21 d-1 command list ............................................................................................................................... ..... 161 e-1 status list ............................................................................................................................... .......... 163
1 chapter 1 general the m pD72103A hdlcc (high-level data link control procedure controller) is a communication control lsi that supports the hdlc standard. because this hdlcc includes a dma (direct memory access) function, the host machine can use commands and data previously stored in memory to perform serial communication using hdlc frames. 1.1 features hdlc frame control address field recognition function: 1 byte/2 bytes full-duplex communication via one channel baud rate: 8 mbps max. (2 mbps max. when using dpll) note maximum transmit/receive data length: 16 kbytes can be divided in external memory as level-two header and 1 field or level-two, level-three header and user various statistical data dpll (digital phase-locked loop) function on-chip dma controller: 8/16-bit data, 24-bit address general-purpose input/output pins: input pin x 2 output pin x 2 on-chip transmission control function (lap-d mode) data format: nrz and nrzi decoding/encoding command chain function fcs (frame check sequence) generation/detection: 16/32 bits system clock: 1 to 16 mhz cmos 5-v single power supply note transfer speed is restricted by the system clock?s frequency and operation conditions. for details, see the caution points described in 3.4.8 cautions regarding overrun errors . ordering information part no. package m pD72103Agc-3b9 80-pin plastic qfp (14 x 14 mm) m pD72103Alp 68-pin plastic qfj (950 x 950 mil)
2 chapter 1 general 1.2 block diagram corresponding sections of this manual are indicated in the bubbles. d0-d7 a0-a15 a16d8- a23d15 cs iord iowr ube aen astb hldrq hldak mrd mwr ready crq int clrint b/w test v dd gnd reset clk dmac rx fifo tx fifo 2.2 3.3 3.4 2.3.1 2.3.1 txc txd gi1 gi2 go1 go2 go3 rxc rxd all chapters internal controller transmitter internal buses bus interface receiver chapter 2
3 chapter 1 general 1.3 internal block functions name function bus interface interface between the m pD72103A and external memory or external host processor internal controller hdlc framing including the dmac, transmitter, and receiver block control dmac controls transfer of data in external memory to the internal controller (direct memory or transmitter, or controls writing of data to external memory from access controller) the internal controller or receiver tx fifo a 32-byte buffer for transmitting transmit data from the dmac to the transmitter rx fifo a 128-byte buffer for transmitting receive data from the receiver to the dmac transmitter converts contents of tx fifo to hdlc frames that are sent as serial data receiver writes data received in hdlc frames to rx fifo internal buses these buses, which include a 24-bit address bus and 8/16-bit data buses, connect the internal controller, dmac, fifos, serial block, and bus interface block
4 chapter 1 general 1.4 pin configuration (top view) 80-pin plastic qfp (14 x 14 mm) m pD72103Agc-3b9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 nc hldrq hldak ready astb aen nc crq gi1 go1 nc go2 rxc rxd nc txc txd gi2 go3 nc nc clrint int ube mwr mrd gnd iowr iord cs v dd nc v dd d7 d6 d5 d4 d3 d2 nc nc reset ic b/w test clk gnd gnd nc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 nc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 d1 d0 a23d15 a22d14 a21d13 nc a20d12 a19d11 a18d10 nc nc a17d9 a16d8 a15 a14 a13 a12 a11 a10 nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5 chapter 1 general 68-pin plastic qfj (950 x 950 mil) m pD72103Alp 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 reset ic b/w test clk gnd gnd a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 go3 gi2 txd txc nc rxd rxc go2 nc go1 gi1 crq aen astb ready hldak hldrq a10 a11 a12 a13 a14 a15 a16d8 a17d9 nc a18d10 a19d11 a20d12 a21d13 a22d14 a23d15 d0 d1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 clrint int ube mwr mrd gnd iowr iord cs v dd v dd d7 d6 d5 d4 d3 d2 9876543216867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
6 chapter 1 general 1.5 pin functions pin no. pin name i/o active function 80-pin 68-pin level qfp qfj 12 2 go2 o e this is a general-purpose output pin. the output level of this pin is changed when general-purpose output pin write lcw is executed. 13 3 rxc i e when in on-chip dpll mode: (receive clock) this is the transmit/receive clock input for the m pD72103A?s on-chip dpll. (enables input up to 32 mhz) when in external dpll mode: this is a receive clock input pin. 14 4 rxd i e this is a serial receive data input pin. (receive data) 15 5 nc e e leave this pin unconnected. (no connection) 16 6 txc i/o e when in on-chip dpll mode: (transmit clock) the rxc pin?s input signal that was generated in the m pD72103A is divided by 16 and output via this pin as a clock signal. when in external dpll mode: a transmit clock is input via this pin from an external source. 17 7 txd o e this is the serial transmit data output pin. (transmit data) 18 8 gi2 i l when not in lap-d mode: this is a general-purpose input pin. general-purpose input pin status change detection 1 lsw is reported when a change in the input level is detected. when in lap-d mode: this pin is used for externally applied frame transmit enable signals. 19 9 go3 o l when not in lap-d mode: this pin has no function. leave this pin unconnected. when in lap-d mode: this pin is used for externally output frame transmit request signals. 20 e nc e e leave this pin unconnected. (no connection) 21 e nc e e leave this pin unconnected. (no connection) 22 10 reset i l this pin is used to initialize (reset) the m pD72103A?s internal (reset) circuits. this requires at least seven clock cycles of the clk signal. bus slave mode is entered after reset. e e nc e e leave this pin unconnected. (no connection) 23 11 ic e e do not connect anything to this pin. (internally connected)
7 chapter 1 general pin no. pin name i/o active function 80-pin 68-pin level qfp qfj 24 12 b/w i l/h during bus master mode, this indicates the data bus used to access (byte/word) external memory. when b/w = 0: byte unit (8 bits) when b/w = 1: word unit (16 bits) the status of the b/w pin should be fixed after power-on. when accessing in word units, the low-order bits in the data bus are the data contents of even-number addresses. 25 13 test i e when using this pin, it should be pulled up to high level. (text) 26 14 clk i e system clock input (clock) input a 1-mhz to 16-mhz clock to this pin. note 27 15 gnd e e ground pins make sure that there are several ground pins. 28 16 gnd e e ground pins make sure that there are several ground pins. 29 e nc e e leave this pin unconnected. (no connection) 30 and 31 17 and 18 a0 and a1 i/o e bi-directional during bus master mode: (output) * 3-state indicates the low-order two bits of the memory address line access address. during bus slave mode: (input) these pins are used to input addresses during i/o access to the m pD72103A by an external host. 32 to 39 19 to 26 a2 to a9 o e during bus master mode: * outputs memory addresses from 2 bits to 15 bits. during bus slave mode: changes to high impedance. 40 e nc e e leave this pin unconnected. (no connection) 41 e nc e e leave this pin unconnected. (no connection) 42 to 47 27 to 32 a10 to a15 o e see a2 to a9 above. * 48 and 49 33 and 34 a16d8 and a17d9 i/o e these pins are for the bi-directional 3-state/data bus. * they are multiplex pins for high-order 8 bits starting from bits 16 to 23 of an address and for high-order 8 bits starting from bits 8 to 15 of the data. 50 35 nc e e leave this pin unconnected. (no connection) 51 e nc e e leave this pin unconnected. (no connection) 52 to 54 36 to 38 a18d10 to a20d12 i/o e see a16d8 and a17d9 above. * note see the caution points described in 3.4.8 cautions regarding overrun errors . remark * indicates 3-state.
8 chapter 1 general pin no. pin name i/o active function 80-pin 68-pin level qfp qfj 55 e nc e e leave this pin unconnected. (no connection) 56 to 58 39 to 41 a21d13 to a23d15 i/o e see a16d8 and a17d9 above. * 59 and 60 42 and 43 d0 and d1 i/o e bi-directional during bus master mode: * 3-state this pin is an output pin during write to external address line memory and is an input pin during read from external memory. during bus slave mode: this pin is normally set to high impedance. it is used to output internal register data when an external host processor executes i/o read from the m pD72103A. 61 e nc e e leave this pin unconnected. (no connection) 62 to 67 44 to 49 d2 to d7 i/o e see d0 and d1 * 68 50 v dd e e +5-v power supply pin 69 e nc e e leave this pin unconnected. (no connection) 70 51 v dd e e +5-v power supply pin 71 52 cs i l during bus master mode: (chip select) disable this pin. during bus slave mode: read/write operation from host processor is enabled when this pin is low. 72 53 iord i l an external host processor uses this pin to read the contents of the (i/o read) m pD72103A?s internal registers. during bus master mode: disable this pin (by inputting a high-level signal). 73 54 iowr i l an external host processor uses this pin to write data to the m pD72103A?s (i/o write) internal registers. during bus master mode: disable this pin (by inputting a high-level signal). 74 55 gnd e e ground pins make sure that there are several ground pins. 75 56 mrd o l during bus master mode: (memory read) * data is read from external memory when this pin is low. during bus slave mode: this pin goes to high impedance. 76 57 mwr o l during bus master mode: (memory write) * data is written to external memory when this pin is low. during bus slave mode: this pin goes to high impedance. remark * indicates 3-state.
9 chapter 1 general pin no. pin name i/o active function 80-pin 68-pin level qfp qfj 77 58 ube i/o l/h during bus master mode: (upper byte enable) * the signal that is output from this pin varies depending on the input value of the b/w pin. byte transfer mode (b/w = 0) ube is always high impedance. word transfer mode (b/w = 1) indicates whether valid data is present at pins d0 to d7 and/or pins a16d8 to a23d15. ube a0 d0-d7 a16d8-a23d15 00 ?? 01 ? ? 10 ? ? 11 ? ? during bus slave mode: the ube pin is used for input and indicates whether valid data is present at pins d0 to d7 and/or pins a16d8 to a23d15. ube a0 d0-d7 a16d8-a23d15 00 ? ? 01 ? ? 10 ? ? 11 ? ? 78 59 int o h interrupt signal from the m pD72103A to an external host processor. (interrupt) 79 60 clrint i h this pin?s signal sets as inactive the int signal that is output by the (clear interrupt) m pD72103A. in the m pD72103A, the int signal goes low at this signal?s rising edge. 80 e nc e e leave this pin unconnected. (no connection) 1 e nc e e leave this pin unconnected. (no connection) 2 61 hldrq o h this pin is for the hold request signal, which is issued to an external (hold request) host processor. during a dma operation in the m pD72103A, this signal is active in order to switch from bus slave mode to bus master mode. 3 62 hldak i h this pin is for the hold acknowledge signal, which is received from (hold acknowledge) an external host processor. when the m pD72103A detects that this signal is active, it begins the dma operation after switching from bus slave mode to bus master mode. remark * indicates 3-state.
10 chapter 1 general pin no. pin name i/o active function 80-pin 68-pin level qfp qfj 4 63 ready i h this is an input pin for the signal that is used to extend the width of (ready) the mrd and mwr signals. when the ready signal is low, the mrd and mwr signals are held at active low level. change the ready signal to conform to the rated setup/hold time. 5 64 astb o h this pin is used to externally latch addresses output by the m pD72103A. (address strobe) 6 65 aen o h during bus master mode, this pin?s signal enables latched high-order (address enable) addresses, which are output via the system address bus. this signal is also used to inhibit other system bus drivers. 7 e nc e e leave this pin unconnected. (no connection) 8 66 crq i h this pin?s signal is used to request command execution from an (command request) external host processor to the m pD72103A. the m pD72103A fetches the command from external memory at the rising edge of this signal. 9 67 gi1 i l this is a general-purpose input pin. the general-purpose input pin change detection 1 lsw is reported when a change in the input level is detected. 10 68 go1 o l this is a general-purpose output pin. the output level of this pin is changed when the general-purpose output pin write lcw command is executed. 11 1 nc e e leave this pin unconnected. (no connection)
11 chapter 1 general 1.6 initialization via reset the m pD72103A is initialized when a negative potential pulse that is longer than the pulse input to the clk pin (which is seven clocks in length as set by system clock conversion) is input to the reset pin, or when a 1 is written to the crst bit in the control register. table 1-1 lists the status of output pins and input/output pins when the m pD72103A is reset. since the reset signal is latched by the clk signal, four clocks of the clk signal are required before the reset status becomes as shown in table 1-1. table 1-1. pin status after reset pin no. pin name i/o during reset 80-pin qfp 68-pin qfj (same status after reset) 12 2 go2 o h 16 6 txc i/o hi-z 17 7 txd o h 19 9 go3 o h 30, 31 17, 18 a0, a1 i/o hi-z 3-state 32-39, 19-26, a2-a15 o hi-z 42-47 27-32 3-state 48, 49, 33, 34, a16d8-a23d15 i/o hi-z 52-54, 36-41 3-state 56-58 59, 60, 42-49 d0-d7 i/o hi-z 62-67 3-state 75 56 mrd o hi-z 3-state 76 57 mwr o hi-z 3-state 77 58 ube i/o hi-z 3-state 78 59 int o l 2 61 hldrq o l 5 64 astb o l 6 65 aen o l 10 68 go1 o h
12 [memo]
13 chapter 2 bus interface 2.1 internal registers the m pD72103A includes four internal registers. these registers are controlled via six pins: iord, iowr, a0, a1, ube, and cs. the host processor can only have i/o access to the m pD72103A when the m pD72103A is in bus slave mode. table 2-1 shows an i/o port map (for details of the ube pin, see ube column in 1.5 pin functions ). table 2-1. i/o port map cs iord iowr a1 a0 internal register function 1xxxx e no function 01000 control register write 00100 internal status register read 01001 internal fifo active register when 5 is written to this register, the mset command is written to the internal fifo. note 01010 e setting inhibited (internal test mode) 01011 internal fifo register the mset command is written to the internal fifo. 00111 e setting inhibited note see chapter 4 commands (lcw) remark x: don?t care
14 chapter 2 bus interface 2.1.1 control register the control register is used when the host processor accesses the m pD72103A. figure 2-1. control register 0000 0 76543210 ccrq crst cclrint caution be sure to write ??to bits 2, 4, 5, 6, and 7. table 2-2. control register bit name meaning function ccrq control a command is executed when ??is written to this bit. the command execution method for this command operation is the same as for the crq pin. either method can be selected by host processor. request since this bit is automatically cleared to zero internally, there is no need to write a ??after the host processor has written a ??to this bit. crst control the m pD72103As internal circuits are automatically reset when a ??is written to this bit. this reset reset operation is the same as that controlled via the reset pin. since this bit is automatically cleared to zero internally, there is no need to write a ??after the host processor has written a ??to this bit. cclrint control the int pin is automatically reset when a ??is written to this bit. this function is the same as clear when the int pin is reset by the clrint pin. it does not matter which pin is selected by the int host processor. since this bit is automatically cleared to zero internally, there is no need to write a ??after the host processor has written a ??to this bit.
15 chapter 2 bus interface 2.1.2 internal status register the internal status register is used to indicate the internal status of the m pD72103A. its value immediately after reset is 0ch. figure 2-2. internal status register table 2-3. internal status register bit name meaning function frdy fifo this bit is accessed when the memory area setting lcw note command is written to the internal ready fifo. write is enabled when this bit?s value is 0. if this bit?s value is 1, wait until it becomes 0 before writing to the fifo. the value of this bit after reset is 0. ints int this is the same signal as for the int pin. the host processor can be informed of the status status report timing from the m pD72103A not only by interrupts via the int pin but also by polling this bit. the value of this bit after reset is 0. crqurdy command after the memory area setting lcw command is issued, this bit value becomes zero and a request 10-ms wait period (when system clock = 8 mhz) is required before the next command can be unready issued. the value of this bit after reset is 0. note lcw: link command word ** ** * 76543210 frdy ints crqurdy * : don? care
16 chapter 2 bus interface 2.2 dmac (direct memory access controller) during bus master mode, the m pD72103A uses the on-chip dmac to read certain commands or transmit data that is stored in external memory or to write internal status contents or receive data to external memory. addresses used for dma are 24 bits long, and the data length is selectable via the b/w pin to support either 8- bit or 16-bit memory. 2.2.1 block transfers the m pD72103A uses dma transfers to transfer long data segments. in the m pD72103A, dma sets the hldrq signal as active (high) after each block is transferred. dma transfers can be executed in either 4-byte or 8-byte blocks as set by dmab note , and one bus cycle (four clocks) transfers either one byte (8 bits: byte unit) or two bytes (16 bits: word unit) of data. accordingly, the number of bus cycles is determined by the transfer mode and the number of bytes to be transferred in data blocks, as listed in table 2-4. note dmab is a parameter of the operation mode setting lcw command. table 2-4. bus cycles in byte transfer mode and word transfer mode bytes per block byte transfer mode word transfer mode 4 bytes/block 4 bus cycles 2 bus cycles (when starting from even address) (dmab = 0) 3 bus cycles (when starting from odd address) 8 bytes/block 8 bus cycles 4 bus cycles (when starting from even address) (dmab = 1) 5 bus cycles (when starting from odd address) figure 2-3. basic clocks in one bus cycle during block transfer s1 s2 s3 s4 s1 s2 clk astb mrd, mwr
17 chapter 2 bus interface 2.2.2 extension of active (low-level) width of mrd and mwr signals the basic number of clocks per bus cycle in the m pD72103A?s dma is four clocks. during dma transfer, the active (low-level) width of the mrd and mwr signals is two clocks. either of the following methods can be used when there is not enough memory for a two-clock width. (1) programmable wait function this function causes the m pD72103A to internally and automatically insert wait cycles to extend the active (low- level) width of mrd and mwr. the programmable wait value can also be set via a parameter (dmaw) in the operation mode setting lcw command. figure 2-4 shows an example in which the programmable wait value is 2. (2) control via ready signal this method sets the externally applied ready signal to low level to extend the active (low-level) width of mrd and mwr. this method is valid when the value set to dmaw is exceeded. figure 2-4. example: two programmable waits s1 s2 s3 sw sw s4 clk mrd, mwr s4 s1
18 chapter 2 bus interface 2.2.3 basic timing of dma figure 2-5. memory write timing (a) b/w = 0 clk si si s0 s0 s1 s2 s3 s4 s1 s2 s3 sw s4 si hldrq hldak aen astb a0-a15 a16d8-a23d15 hi-z hi-z mwr ready (b) b/w = 1 clk si si s0 s0 s1 s2 s3 s4 s1 s2 s3 sw s4 si hldrq hldak aen astb a0-a15 hi-z hi-z mwr ready a16d8-a23d15 hi-z
19 chapter 2 bus interface figure 2-6. memory read timing (a) b/w = 0 clk s0 si s0 s1 s2 s3 s4 s1 s2 s3 sw s4 si hldrq hldak aen astb a0-a15 a16d8-a23d15 hi-z hi-z mrd ready (b) b/w = 1 clk s0 si s0 s1 s2 s3 s4 s1 s2 s3 sw s4 si hldrq hldak aen astb a0-a15 hi-z hi-z mrd ready a16d8-a23d15 hi-z
20 chapter 2 bus interface 2.2.4 address/data multiplexing addresses and data are multiplexed as shown below. pin address data a0 to a15 0 to 15 e a16d8 to a23d15 16 to 23 8 to 15 d0 to d7 e 0 to 7 this multiplexing method is used to reduce the external address latch. therefore, the operation of the pins (a16d8 to a23d15) used for address/data multiplexing varies depending on the value input to the b/w pin. when external memory is configured using byte mode (b/w = 0), an external address latch is not required, as is shown in figure 2-7. when external memory is configured using word mode (b/w = 1), an external address latch is not required as along as the memory contents do not exceed 64 kbytes (requiring no more than 16 address pins), as shown in figure 2-8. when the memory contents exceed 64 kbytes, an external address latch is required for pins a16d8 to a23d15. figure 2-7. byte mode (b/w = 0) (a) memory read (b) memory write s1 s2 s3 s4 s1 clk s4 a16d8-a23d15 addresses 16 to 23 address address s1 s2 s3 s4 s1 clk s4 a16d8-a23d15 addresses 16 to 23
21 chapter 2 bus interface figure 2-8. word mode (b/w = 1) (a) memory read (b) memory write s1 s2 s3 s4 s1 clk s4 a16d8-a23d15 addresses 16 to 23 addresses 16 to 23 hi-z s1 s2 s3 s4 s1 clk s4 a16d8-a23d15 data 8 to 15 addresses 16 to 23
22 chapter 2 bus interface 2.3 interface between m pD72103A and host processor figure 2-9. command/status handling between m pD72103A and host processor as shown in figure 2-9 above, command/status handling between the m pD72103A and the host processor is performed via dma transfers to and from external memory. the transmit data is written from the host processor to external memory. the m pD72103A then reads the transmit data from external memory and converts it to serial data. for the receive data, the m pD72103A converts them from serial data to parallel data, which is then written to external memory, where it is read by the host processor. there are two basic methods for synchronizing these operations: (1) a method that uses the crq pin, int pin, and clrint pin and (2) a method that uses the ccrq bit and cclrint bit in the control register and the int bit in the internal status register. it is also possible to combine these two methods. note see 2.1.1 control register . (1) method using the crq pin, int pin, and clrint pin <1> when the host processor issues a command to the m pD72103A, the command is written to a command table in external memory note and the crq pin becomes active (high level). when this operation is completed, the m pD72103A begins reading the command. <2> when it is necessary for the m pD72103A to report to the host processor, the host processor sets the int pin as inactive (low level) by setting the clrint pin as active (high level). <3> next, the m pD72103A writes a status report to external memory and sets int pin as active (high level). the host processor uses this signal as an interrupt to detect the timing of the status report from the m pD72103A. note see 2.3.1 b. method using write to external memory . pD72103A m host processor external memory < 1 > write command to external memory < 2 > read command from external memory < 4 > read status from external memory < 3 > write status to external memory data bus
23 chapter 2 bus interface (2) method using the ccrq bit and cclrint bit in the control register and the ints bit in the internal status register <1> when the host processor issues a command to the m pD72103A, the command is written to external memory as was done via method (1) above note 1 . after that, 1 is written to the ccrq bit. <2> when it is necessary for the m pD72103A to report to the host processor, the host processor writes a 1 to the cclrint bit in the m pD72103A?s control register, which sets a 0 to the ints bit. <3> after the m pD72103A writes the status information to external memory, it sets 1 to the ints bit. since the ints bit and the int pin correspond to the same signal, the host processor is able to detect the status report timing simply by polling the ints bit, and without using an interrupt for the int pin note 2 . notes 1. see 2.3.1 b. method using write to external memory . 2. see 2.1.2 internal status register . 2.3.1 command issuance commands can be issued via the following two methods. method using write to internal fifo this method is used to initiate the memory area setting lcw command. method using write to external memory this method can be used to initiate the memory area setting lcw command or to initiate commands other than the memory area setting lcw command. a. method using internal fifo write immediately after the fifo in the m pD72103A has been reset, this method writes only the memory area setting lcw command. this method can only be used once when setting a start address of the system area immediately after a reset. the flow to be followed when writing to the internal fifo is shown below.
24 chapter 2 bus interface figure 2-10. flow chart for writing memory area setting lcw command to internal fifo frdy = 0 no yes frdy = 0 no yes no yes crqurdy = 0 no yes start read frdy in status register write "5" to port 1 address write one byte of mset command data to port 3 address read frdy in status register has all of mset command been written? issue crq note read crqurdy bit in status register wait 10 ms end during this period, the "memory area setting lcw" command is written in byte units starting from lcw (0). (when system clock = 8 mhz) note this is done via a pulse input to the crq pin or by setting ??to the ccrq bit in the command register.
25 chapter 2 bus interface b. method using write to external memory actually, there are two methods that use a write to external memory. the first method writes the memory area setting lcw command in byte units immediately after a reset, starting from address 0. after the command is executed (and the crq pin and ccrq bit of the control register are active), this method is the same as when writing the memory area setting lcw command to the internal fifo. the other method writes a command to a command table. this method is used when issuing a command other than the memory area setting lcw command. use the following steps to write the command. (1) check that the cmds field in the lcw where a command is written is fch/fdh/feh. if the cmds field is something else, lcw cannot be used, so wait until it becomes fch/fdh/feh. (2) after writing the command number to lcw (0) and the command information to lcw (2) to (15), write 00h to lcw (1). make sure that writing to lcw (1) is the last operation in this sequence. (3) issue the command after the crq pin or ccrq bit of the control register becomes active. after the issued command has been executed, command execution can be confirmed by inserting fch/fdh/ feh into the command area?s cmds field or by writing a command end status to the status table. 2.3.2 status report after a command has been executed or data has been received, the m pD72103A writes information to the status table, then sets the int pin or the ints bit as active. meanwhile, the host processor detects the active state of the int pin or ints bit, after which the status table should be checked. use the following steps to check the status table. (1) set the clrint pin or cclrint bit as active and the int pin or ints bit as inactive. (2) check the status table and process all of the reported status settings. note that several status settings may be reported for a single interrupt. (3) after completing this processing, write ffh to lsw (0) in the status table and then release the status table. however, in some cases when the above processing steps are used, a status check by the host processor shows that there are no status reports. this occurs when all processing has been completed during the previous round of status processing, such as is shown in figure 2-11. therefore, such cases do not indicate a fault or abnormality.
26 chapter 2 bus interface figure 2-11. status report (when status area is lsw0 to lsw2) 2.3.3 command chain function the command chain function enables the m pD72103A to sequentially execute several commands allocated successively in memory by issuing only one command request (which is executed by setting the crq pin or ccrq bit as active). this function operates via the following sequence. (1) the host processor sets all of the commands to be executed to external memory in advance. ffh is then set to lcw(1) in the command table following the last command to be executed. (2) after the commands are set to external memory, the crq pin or ccrq bit is set as active. the m pD72103A then executes all of the commands in external memory up to where ffh has been set to lcw(1) in the command table. pD72103A m host processor system (cpu + memory) < 1 > write status to lsw(0) in lsw0 of status table < 2 > set int as active < 3 > write status to lsw1 of status table < 4 > interrupt (check) by host processor < 5 > issue clrint (active) < 6 > write status to lsw2 of status table < 7 > set int as active < 8 > process lsw0 to lsw2 write ffh to stsn (lsw(0)) < 9 > interrupt (check) by host processor no status to be processed
27 chapter 2 bus interface 2.4 initialization of external memory after the m pD72103A has been reset, the host processor writes ffh to initialize the external memory before issuing the memory area setting lcw command. this empties the command table and status table. 2.5 methods for using external memory from the perspective of the m pD72103A, external memory is memory that exists externally and is used for the host interface. set the following five areas in external memory using the methods described in sections 2.5.1 to 2.5.5 below. (1) command table (2) status table (3) receive buffer address table (4) receive buffer (5) transmit buffer 2.5.1 command table the command table is a table where commands used by the host processor to direct operations in the m pD72103A are written. the command table?s start address is set by the memory area setting lcw command. in the command table, each command area lcw (link command word) consists of several (quantity = n) 16-byte lcws. the number of command area lcws (1 < n < 128, where n is an exponent of two) is set via the memory area setting lcw command. the command area lcw (n - 1) that is the (nth - 1) command area lcw in the command table is linked by this method to the first command area lcw0, so if the host processor issues a command after lcw (n - 1), the next command is set to lcw0. the command table and command fields are shown below.
28 chapter 2 bus interface figure 2-12. command table cmdt cmdn cmds * * * * * * * * * * * * * * * : info lcw0 lcw1 lcw2 lcw (n?) lcw (n?) lcw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) lcw 16 bytes . . . . .
29 chapter 2 bus interface table 2-5. command fields lcw (n) field name description 0 cmdn this is the command number field. the host processor writes the command number when the cmds field is fch/fdh/feh. 1 cmds this is the command status field. after the transmit command fetch operation is completed, the m pD72103A writes 0ch to this field. after the command has been executed, the m pD72103A writes fch/fdh/feh to this field. this operation releases the command table. when this field contains fch/fdh/feh, the host processor writes a command number and command information and then writes 00h to this field. 2 to 15 info these are the command information fields. when the cmds field contains fch/fdh/feh, the host processor writes information to these fields. however, the number of usable command information fields differs according to the command. 00h is written to fields that are not used. remark the meanings of fch/fdh/feh in the cmds field are as follows. fch: set when a execution of a command other than a transmit command has been completed fdh: set when a transfer is stopped after a transmit command has been executed. feh: set when a transfer ends normally after a transmit command has been executed. figure 2-13 illustrates the m pD72103A?s command fetch operations.
30 chapter 2 bus interface figure 2-13. command fetch operation cmdn cmds cmdn cmds host processor parameters < 1 > cmds check < 2 > command write < 3 > crq active < 4 > hldrq active parameters < 6 > dma command transfer < 8 > < 6 > < 9 > < 9 > external memory command queue < 7 > < 7 > execution end of execution hdlc controller command table pointer dma controller < 5 > hldak active < 7 >
31 chapter 2 bus interface the operations enumerated as <1> to <9> in figure 2-13 are described below. <1> the m pD72103A has an internal command table pointer. make sure that the second byte (cmds) of the command area indicated by the command table pointer is fxh. in this case, the host system may need to have a command table pointer (whose initial value is set by the mset command) in memory. <2> write one or more commands to the command table. <3> the host processor sets the m pD72103A?s crq pin as active so that the command is captured by the m pD72103A. <4> the m pD72103A issues a bus mastership request to the host processor so that it can capture the command. (hldrq pin active) <5> the host processor sets the m pD72103A?s hldak pin as active to shift bus mastership to the m pD72103A. <6> the m pD72103A sends to the command queue (via dma transfer) a command that it has fetched from the table indicated by its internal command table pointer. <7> the command is executed. <8> when command execution is completed, fxh is written to cmds. <9> the m pD72103A increments the command table pointer by +10h. the m pD72103A then proceeds to the next operation according to the command indicated by the incremented command table pointer. cmds m pD72103A operation fxh stop reading command 00h fetch command and execute after this, operations <1> to <9> above are repeated. remark since the m pD72103A?s dma operation is performed in either 4-byte or 8-byte units during one period when the hldrq pin is at high level, operations <4> and <5> above are repeated to capture commands and transfer transmit and receive data.
32 chapter 2 bus interface 2.5.2 status table the m pD72103A uses the status table to provide status reports to the host processor. the status table?s start address is the address following the command table. in the status table, each status area lsw (link status word) consists of several (quantity = n) 16-byte lsws. the number of status area lsws (1 < n < 128, where n is an exponent of two) is set via the memory area setting lcw command. the status area lsw (n - 1) that is the (nth - 1) status area lsw in the status table is linked by this method to the first status area lsw0. therefore, if the m pD72103A writes a status to lsw (n - 1), the next status is written to lsw0. the status table and status fields are shown below. figure 2-14. status table stst stsn * * * * * * * * * * * * * * * * : info lsw0 lsw1 lsw2 lsw (n?) lsw (n?) lsw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) lsw 16 bytes . . . . .
33 chapter 2 bus interface table 2-6. status fields lsw (n) field name description 0 stsn this is the status number field. the host processor writes ffh to this field when status processing has been completed. by writing ffh to this field, the m pD72103A releases the status table. 1 to 15 info these are the status information fields. however, the number of usable status information fields differs according to the status. figure 2-15 illustrates the m pD72103A?s status information operations.
34 chapter 2 bus interface figure 2-15. status information operations < 9 > stsn stsn external memory host processor dma controller status table pointer status queue hdlc controller status report request < 4 > stsn read status check < 10 > stsn write < 2 > hldrq active < 3 > hldak active < 6 > int active < 8 > clrint active < 7 > < 5 > status transfer < 7 > < 1 > < 1 >
35 chapter 2 bus interface the operations enumerated as <1> to <9> in figure 2-15 are described below. <1> the m pD72103A internally generates status reports such as data reception reports and line open completion status reports. <2> the m pD72103A sends the host processor a hldrq signal to obtain bus mastership. <3> the host processor sets the m pD72103A?s hldak pin as active to shift bus mastership to the m pD72103A. <4> the m pD72103A has an internal status table pointer. a dma read operation is performed to read the data at the address indicated by this status table pointer to check whether or not the data value is ffh. if it is not ffh, the current status is held until it becomes ffh. a status table overflow is reported when a series of status report requests are issued even though there is no empty space in the status table, which causes status to be lost. <5> the status is written via a dma transfer (stsn is written last). <6> after writing the first status to the status table, the m pD72103A sets the int pin as active. <7> when a status report request is issued, the status is reported to the second status table via the same operation as in steps <4> and <5> above. <8> the operation of the host processor branches to a interrupt service routine when the m pD72103A?s int pin becomes active. the int pin is reset by setting the clrint pin as active at the start of this interrupt service routine. <9> the host processor checks the status table and responds in various ways according to the cause. <10> when a status is no longer needed, the status table?s start data (stsn) is set to ffh (empty status).
36 chapter 2 bus interface 2.5.3 receive buffer address table the receive buffer address table is a table of start addresses for several receive buffers. the m pD72103A writes the frames it receives to these receive buffers. the host processor sets up this table before receiving any frames. the receive buffer address table begins at the address following the status table. the receive buffer address table consists of a receive buffer address area lrbw (link receive buffer address word) that includes several (quantity = n) 4-byte lrbws. the number of lrbws (1 n 128, where n is an exponent of two) is set via the memory address setting lcw command. each receive buffer address area lrbw consists of four bytes. the receive address area lrbw (n - 1) that is the (nth - 1) receive buffer address area lrbw in the receive buffer address table is linked by this method to the first receive buffer address area lrbw0. therefore, if the host processor issues a receive buffer address following lrbw (n - 1), it is written to lrbw0. the receive buffer address table and receive buffer address fields are shown below. figure 2-16. receive buffer address table rbat brdy rba (l) / (h) rba (m) rba (h) / (l) lrbw0 lrbw1 lrbw2 lrbw (0) (1) (2) (3) lrbw 4 bytes . . . . . lrbw (n?) lrbw (n?)
37 chapter 2 bus interface table 2-7. receive buffer address fields lrbw (n) field name description 0 brdy this is the receive buffer status field. the m pD72103A reads the receive buffer address field, and then writes ffh to this field when this field is 00h. however, when in receive buffer chain mode, f0h is first written to this field after the read operation, then ffh is written after completion of frame reception. the host processor writes 00h to this field once processing of receive data is completed. the m pD72103A releases the receive buffer once 00h has been written. 1 to 3 rba this is the receive buffer address field. the host processor writes the start address of the receive buffer where m pD72103A?s receive data is written. note that this field should be written to before issuing the line open lcw command. when setting addresses, write addresses separately to the (h), (m), and (l) positions. cautions 1. for lrbw (1) and lrbw (3), the (h) and (l) positions vary according to the parameter values set by the operation mode setting lcw command. 2. first write to lrbw (1) to lrbw (3), then finish by writing 00h to lrbw (0). 3. when a discarded frame is received, the lrbw table corresponding to the discarded frame is used as the receive buffer pointer for the frame that is received next. figures 2-17 to 2-23 show examples of relationships between receive buffer address tables and received frames. (1) initial status (line closed) (see figure 2-17) before issuing the line open lcw command, the host processor sets receive addresses to the receive buffer address table. in the example shown in figure 2-17, addresses 100, 200, 300, and 400 in the receive buffer address table are set as start addresses for the receive buffer. (2) line open status (see figures 2-18 and 2-19) when the line open lcw command is issued, the m pD72103A reads the contents of the receive buffer address table in order starting from lrbw0 and sets the data to its internal receive buffer address fifo (rbafifo). once the table has been completely read, the m pD72103A changes brdy parameter contents to ffh (or f0h if using a receive buffer chain). in the example shown in figure 2-18, the rba in the lrbw0 field is set to the rbafifo and the brdy parameter?s value is changed to ffh. figure 2-19 illustrates how four rbas are fetched and set to the rbafifo. (3) start of frame reception (see figures 2-20 to 2-23) when the m pD72103A receives an hdlc frame, it accepts dma transfer of the data following the start flag to the receive buffer specified by rba0. figure 2-20 shows how the first frame is received and how the data values 30h and 31h are set via dma transfer. after the fcs and end flag are received, the fcs is checked for errors. if the frame is normal, the data reception lsw is reported to the status table (it is not reported if the received frame is abnormal), and the interrupt signal is set as active. figure 2-21 shows the internal status after data is received with an fcs error. figure 2-22 shows the status when starting to receive the second frame. figure 2-23 shows the status when reception of the second frame ends normally, after which the data reception lsw is reported and the interrupt signal is set as active. the m pD72103A also has an internal pointer for the receive buffer address table. the m pD72103A increments this pointer each time a receive buffer address is captured in the rbafifo. accordingly, if the table indicated by this pointer is not empty, the m pD72103A continues to wait until the table is empty.
38 chapter 2 bus interface figure 2-17. initial status (line closed) 00 00 01 00 00 00 02 00 00 00 03 00 00 00 04 00 brdy rba (l) rba (m) rba (h) rbafifo empty empty empty empty rba0 rba1 rba2 rba3 address 100 address 200 pD72103A rxd lrbw0 lrbw1 lrbw2 lrbw3 m
39 chapter 2 bus interface figure 2-18. after line open command is issued ff 00 01 00 00 00 02 00 00 00 03 00 00 00 04 00 write ffh to brdy note rbafifo empty empty empty 000100h rba0 rba1 rba2 rba3 address 100 address 200 pD72103A rxd dma transfer lrbw0 lrbw1 lrbw2 lrbw3 m note f0h is written when in receive buffer chain mode.
40 chapter 2 bus interface figure 2-19. rbafifo full status ff 00 01 00 ff 00 02 00 ff 00 03 00 ff 00 04 00 rbafifo 000100h 000200h 000300h 000400h rba0 rba1 rba2 rba3 address 100 address 200 pD72103A rxd dma transfer lrbw0 lrbw1 lrbw2 lrbw3 m
41 chapter 2 bus interface figure 2-20. reception of first frame ff 00 01 00 ff 00 02 00 ff 00 03 00 ff 00 04 00 30h 31h rbafifo 000100h 000200h 000300h 000400h rba0 rba1 rba2 rba3 address 100 address 200 pD72103A rxd flag 30h 31h reception of first frame lrbw0 lrbw1 lrbw2 lrbw3 dma transfer m
42 chapter 2 bus interface figure 2-21. completion of first frame reception (fcs error) ff 00 01 00 ff 00 02 00 ff 00 03 00 ff 00 04 00 30h 31h 7fh rbafifo 000100h 000200h 000300h 000400h rba0 rba1 rba2 rba3 address 100 address 200 pD72103A rxd 7fh fcs end flag lrbw0 lrbw1 lrbw2 lrbw3 dma transfer m
43 chapter 2 bus interface figure 2-22. start of second frame reception ff 00 01 00 ff 00 02 00 ff 00 03 00 ff 00 04 00 40h 41h 7fh rbafifo 000100h 000200h 000300h 000400h rba0 rba1 rba2 rba3 address 100 address 200 pD72103A rxd start flag 40h 41h second frame reception lrbw0 lrbw1 lrbw2 lrbw3 dma transfer m
44 chapter 2 bus interface figure 2-23. completion of second frame reception ff 00 01 00 ff 00 02 00 ff 00 03 00 ff 00 04 00 40h 41h 8fh rbafifo 000200h 000300h 000400h empty rba0 rba1 rba2 rba3 address 100 address 200 pD72103A rxd int ? 8fh fcs end flag lrbw0 lrbw1 lrbw2 lrbw3 dma transfer 100h is discarded and rbafifo is incremented. after dtrv status report, interrupt signal is set as active m
45 chapter 2 bus interface 2.5.4 receive buffer the receive buffer is the area where data received by the m pD72103A is written. the receive buffer?s start address is set by the host processor to the receive buffer address table. the receive buffer?s size is set via the operation mode setting lcw command. any size up to 16 kbytes can be set for the receive buffer. 2.5.5 transmit buffer the transmit buffer is the area where the m pD72103A writes data to be transmitted. the host processor uses the data transmission lcw command to set the transmit buffer?s start address and size. any size up to 16 kbytes can be set for the transmit buffer. 2.5.6 external memory table configuration example below is an external memory configuration example for the memory area setting lcw command. table 2-8. external memory table configuration example parameter function parameter setting example addr (l), (m), (h) indicates the start address of the command table 000000h nlcw specifies the number of blocks in the command table 20h nlsw specifies the number of blocks in the status table 20h nlrbw specifies the number of blocks in the receive buffer address table 40h figure 2-24. external memory configuration example 0000h 0200h 0400h 0500h command table status table receive buffer address table
46 [memo]
47 chapter 3 communication operations 3.1 initial settings the host processor initializes the m pD72103A and the external memory via the steps shown in figure 3-1 below. figure 3-1. initialization steps for m pD72103A and external memory start reset pD72103A end initialize external memory set receive buffer address table transmit/receive processing issue "memory area setting lcw" command issue "operation mode setting lcw" command line open command start transmit/receive operation line close command end transmit/receive operation m
48 chapter 3 communication operations 3.2 start of communication control operation and flag synchronization setup when starting a transmit/receive operation, issue line open lcw command and set the m pD72103A?s transmit/ receive mode. the operations following issuance of the line open lcw command are described below. 3.2.1 transmit operation this operation varies according to the tfil setting in the operation mode lcw command. tfil = 0 transmit flag after issuance of line open lcw command tfil = 1 transmit idle (1) after issuance of line open lcw command 3.2.2 receive operation after the line open lcw command has been issued, the m pD72103A enters flag search mode. 3.2.3 status reporting after the line open lcw command has been issued, the m pD72103A reports a line open completion lsw. the timing of line open completion lsw reporting varies according to the loak and tfil settings in the operation mode setting lcw command. when tfil = 0 loak = 0 report status when flag transfer has begun from local side. loak = 1 report status when flag has been received from remote side. when tfil = 1 the status is reported following execution of the line open lcw command.
49 chapter 3 communication operations 3.3 data transmission the m pD72103A transmits in bc byte units the data in the transmit buffer in external memory that is specified by the bufa parameter in the data transmission lcw command. when the m pD72103A completes transmission of the data, it reports the data transmission completion lsw command. 3.3.1 transmission timing data transmitted via the txd pin during the period from the falling edge of txc to the next falling edge of txc is output as one bit. figure 3-2. transmission timing txc txd remark the txc pin is an output pin when dpll is used and is an input pin when dpll is not used. 3.3.2 linkage of transmit data transmit data is set to the transmit buffer and the ?ata transmission lcw?command. up to eight bytes can be set to the ?ata transmission lcw?command. after data is written to the transmit buffer, the ?ata transmission lcw?command is set and the transmit operation begins. at this time, the transmit data from the ?ata transmission lcw?command is lined with the transmit data specified by the bufa parameter in the transmit buffer to form one frame. in this case, the frame is transmitted in the following order: first the start flag is transmitted, followed by the data in the ?ata transmission lcw?command and then the data in the transmit buffer.
50 chapter 3 communication operations 3.3.3 transmit buffer chain the m pD72103A transmits in bc byte units the data in the memory address that is specified by the bufa parameter via the data transmission lcw command execution. in this case, the maximum data length is 16 kbytes (data in the transmit buffer and data in the data transmission lcw). a transmit buffer chain can be used for data transfers when the data length in one frame exceeds 16 kbytes or when specified data in the transmit buffer is divided among several areas. a transmit buffer chain is a continuous series of data transmission lcw commands that set transmit data to transmit buffers and specify the transmit data addresses corresponding to each block of data. transmit chain bits are set corresponding to the commands for the data in the chain. the reset bit value is assigned to the transmit chain bit for the data transmission lcw command corresponding to the data that is the last data in the chain. after the data transmission lcw commands have been set and as soon as the crq pin (ccrq bit) becomes active, the data in the transmit buffer specified by the chain is transmitted as one frame. when using a transmit buffer chain, setting of transmit data within the data transmission lcw command is enabled only for the first command. caution when using transmit chains to transmit data, if the transmit data length corresponding to individual commands is too short, the transmit fifo may be left empty during the period when the m pD72103A reads, parses, and executes a command and reads new transmit data, which increases the chance of a transmission underrun error. for example, if the m pD72103A is being used only for transmitting and the communication speed is 1 mbps (system clock = 8 mhz) the minimum transmit data length is 22 or 23 bytes. if the m pD72103A is also being used for receiving, a data length of at least twice that length must be set. 3.3.4 transmission underrun when an underrun occurs, the m pD72103A aborts transmission of the corresponding frame. after aborting the transmission, the m pD72103A retransmits the frame for which the underrun occurred (auto retransmission). the statistical information read acknowledge lsw can be used to detect the number of underrun occurrences. when 1 is set to the txur bit in the operation mode setting lcw command, data transmission stop lsw is reported when the number of underrun errors set in retn occur.
51 chapter 3 communication operations 3.4 data reception when the m pD72103A receives a frame, it writes the received data to a receive buffer in external memory. the m pD72103A reports data reception lsw as the status information when data has been received. 3.4.1 reception timing the reception timing is set as shown below, according to the clk parameter in the operation mode setting lcw command. table 3-1. reception timing mode settings clk parameter setting mode sampling of receive data from rxd pin 0 reception timing determined by external receive clock sampling at rising edge of rxc pin 1 reception timing when using dpll sampling at rising edge of dpll signal (1) reception timing determined by external receive clock figure 3-3 shows the reception timing when in external clock mode. figure 3-3. reception timing (external clock mode) rxc rxd (2) reception timing when using dpll figure 3-4 shows the reception timing in dpll mode. the dpll circuit includes a 4-bit counter (brc), which counts the source clocks input from the rxc pin (at 16 times the transfer rate). this counter operates as described below. <1> when the brc counter value becomes ?? the dpll output is set to ?? <2> if the state of the rxd pin changes when the brc counters count value n is within the range of 0 < n 7, the next incrementation of the brc count is not executed, as shown in figure 3-4 (b). <3> when the brc counter value becomes ?? the dpll output is set to ?? <4> if the status of the rxd pin changes when the brc counters count value n is within the range of 8 n < 15, the next incrementation of the brc count is executed as +2, as shown in figure 3-4 (c). <5> when the brc counters count value is either 0 or 15, the increment operation does not change even if the status of the rxd pin changes.
52 chapter 3 communication operations caution if nrz has been selected as the data format and if there is no edge information for the received data, such as when the receive data contains a series of zeros and a mark idle is being received, the dpll?s count correction operation may not be performed and a reception error may occur. figure 3-4. reception timing (dpll mode) (a) ideal waveform remark *: the brc counter count is incremented by two. rxc rxd brc count value 0123456789 10 11 12 13 14 15 0123456789 10 dpll output (b) edge detected in range of 0 < brc counter value 7 rxc rxd brc count value 0123345678 9 101112131415 0122345678 dpll output 9 ** remark *: brc count is not incremented. (c) edge detected in range of 8 brc counter value < 15 rxc rxd brc count value 0123456789 10 11 12 13 15 0123456789 10 11 dpll output 12 *
53 chapter 3 communication operations 3.4.2 separation of receive data the m pD72103A is able to separate data in received frames into receive buffer and data reception lsw data areas. the receive data that is separated into data reception lsw is specified by the operation mode setting lcw command. when the m pD72103A receives data, it writes data beginning immediately after the start flag and in the amount indicated by operation mode setting lcw command to the data reception lsw data area. after the received data is set to the data reception lsw data area, it writes the other data to the receive buffer. 3.4.3 receive buffer chain the m pD72103A is able to use receive buffer chains. the receive buffer chain is set up in relation to the receive buffer size set by the operation mode setting lcw command. 3.4.4 address field recognition the m pD72103A includes a recognition function for data in the address section that immediately follows the start flag. the data size for which address recognition is enabled is either one byte or two bytes. the reception addresses are set within the receive address field setting lcw command. all of the address values used during the reception operation are set. 3.4.5 discarding of abnormal frames when receiving frames, the m pD72103A discards abnormal frames and does not report a data reception lsw. the statistical information read acknowledge lsw can be used to detect the number of abnormal frames that have occurred. the following are examples of abnormal frames. fcs errors overrun errors frames containing a series of seven or more bits with 1 values frames containing fewer bits that the number specified by the short parameter in the operation mode setting lcw command frames whose receive buffer size exceeds the size specified by the rxbs parameter in the operation mode setting lcw command frames that contain fractional bits when 1 has been set to the oct parameter in the operation mode setting lcw command frames that contain address fields for addresses other than those set by the receive address field setting lcw command frames received when there is no empty space in the status table or receive buffer address table
54 chapter 3 communication operations 3.4.6 idle monitor timer the idle monitor timer is activated when an idle = 1 value follows an idle = 0 value; in other words, when a mark status is detected. when this occurs, if the mark status continues, an idle monitor timer timeout status is reported when the idle monitor timer reaches the timeout limit. after the idle value becomes 1 and the idle monitor timer is activated, the idle monitor timer is stopped when the idle value becomes 0. accordingly, the idle monitor timer cannot be activated or stopped in the following cases. (i) if the idle value is changed from 0 to 1 during the idle detection timing period (8 ms or 100 ms), activation of the idle monitor timer is shifted to the next idle detection timing period. (ii) once the idle monitor timer has been activated, if the idle value is changed from 1 to 0 during the idle detection timing period, the idle monitor timer is not stopped until an idle = 0 condition is detection during the next idle detection timing period. (iii) once the idle monitor timer has been activated, if the idle value is changed from 1 to 0 and then back to 1 during the idle detection timing period, the idle monitor timer is not stopped. 3.4.7 idle reception count when mark idle status (15 continuos bits with 1 values) is detected, the m pD72103A sets the idle bit to 1. once idle has been set to 1, the idle bit is set to 0 as soon as a 0 bit value is received. as shown in figure 3-5, when the idle detection timer reaches its count-out limit during the idle detection timing period (8 ms or 100 ms), if the idle bit value is 1, it is counted as one idle reception occurrence. figure 3-5. idle reception count flag or data 0 mark 1 one time 8 ms 8 ms 8 ms flag or data 0 mark 0 rxd idle detection timing period idle bit idle reception count
55 chapter 3 communication operations 3.4.8 cautions regarding overrun errors during reception processing by the m pD72103A, any of the following four causes can slow reception dma processing to the point where an overrun occurs when receiving frames during the processing period, in which case frames are discarded internally. the principal causes of such overruns are described below. [causes] a. overruns caused by address search processing when the auto value is set as other than 00h and address recognition is performed, it increases the time between frame reception and activation of reception dma processing, which can result in overrun errors. address table values set via the afst parameter are compared consecutively with receive address field values, and when the two values match reception dma processing begins. accordingly, the closer the matching addresses are to the end of the address table, the more likely it is that an overrun error will occur. b. overruns caused by status report processing during the period when a status report is being processed, dma transfer activation processing for received data is prohibited (this dma transfer activation processing includes setting receive buffer addresses for the internal dmac and activating reception dma channels). consequently, if the period of status report processing overlaps with the timing period for starting frame reception, reception dma cannot be activated until the status report processing has been completed. as a result, data accumulates in the reception fifo and an overrun may occur if the received data exceeds 128 bytes. c. overruns caused by reception completion interrupt servicing during the period of interrupt servicing for frame reception completion, any reception interrupt generated by the next frame is masked and data received during this period is accumulated in reception fifo. this condition may eventually result in an overrun. d. overruns caused by reception buffer chain processing if the receive buffer is small, increasing the transfer rate relative to the time required for receive buffer dma activation may cause a large amount of data to be accumulated in the reception fifo. this condition may eventually result in an overrun. the following countermeasures are recommended as ways to avoid overrun errors. [countermeasures] set a slow transfer rate. use upper-layer software for retransmission processing. use a faster system clock (up to 16 mhz). increase the timer interval between receive operations. when using a receive buffer chain, make the receive buffer as large as possible. data related to causes a through c above is shown in (1) and (2) below. the period during which reception dma processing is prohibited for each cause varies according the parameter settings, etc.
56 chapter 3 communication operations (1) reception dma processing prohibit periods for settings corresponding to causes a, b, and c cause conditions setting and reception dma processing category prohibit period [ m s] a 1 auto = 00h, stbc = 0 about 16 2 auto = 00h, stbc = 4 about 27 3 auto = 00h, stbc = 8 about 38 4 auto = 01h, stbc = 4, afst bc = 3 about 27 5 auto = 01h, stbc = 4, afst bc = 12 about 40 6 auto = 01h, stbc = 8, afst bc = 3 about 39 7 auto = 01h, stbc = 8, afst bc = 12 about 52 b 1 if there is no status report about 17 2 if there is a siak status report about 70 3 if there is a siaf status report about 31 c 1 if stbc = 0 and there is no receive buffer chain about 65 2 if stbc = 4 and there is no receive buffer chain about 70 3 if stbc = 8 and there is no receive buffer chain about 81 4 if there is a receive buffer chain for any of the above three conditions (conditions c1 to c3) (number of used receive buffers = n) + about 13 m s x n remarks 1. the time for the mdak or gpae status is about the same as for condition b1. 2. the above data was calculated based on a 16-mhz system clock. 3. this does not affect transmission operations.
57 chapter 3 communication operations (2) upper limits for avoiding overrun errors when causes a, b, and c are combined cause upper limit (mbps) for transfer note a b c rate to avoid overrun 111 8.0 35 2 6.8 e 3 8.0 67 212 8.0 46 2 6.1 e 3 7.9 78 4 1 8.0 52 2 6.1 e 3 7.9 84 5 1 8.0 75 2 5.6 e 3 7.2 e 313 7.5 70 2 5.4 e 3 6.8 102 6 1 7.4 76 2 5.4 e 3 6.7 108 7 1 6.8 98 2 5.0 e 3 6.2 e note this column contains frame interval times [ m s] required for 2-mbps communications. as long as the frame interval time exceeds the above values, cause c will have no effect and 2-mbps communications will be enabled. a dash (e) in this column indicates that 2-mbps cannot be implemented. remark the above data was calculated based on a 16-mhz system clock and a 1- m s hldrq acknowledge time.
58 chapter 3 communication operations 3.5 completion of transmit/receive operation to stop a data transmit/receive operation, issue the line close lcw command. when this command is issued, the m pD72103A sets 1 for the transmission line and stops the receive operation. after the m pD72103A receives the line close lcw command and stops the data transmit/receive operation, it reports line close completion lsw as the current status. 3.6 transmit and receive frame flags 3.6.1 transmit frame flags when the tfil = 0 setting has been selected, the m pD72103A inserts at least three flags corresponding to the transmit frame. accordingly, even when a series of frames are output to the m pD72103A, three flags are inserted between each frame (it is not possible to insert fewer than three flags). since the m pD72103A is not able to control the number of transmit flags at the command level, the host processor?s control of the transmit data write operation can be used (to provide time for writing between frames) in cases where three or more flags must be inserted. when the tfil = 1 setting has been selected, a one-byte end flag is sent after the fcs is added to the transmit frame and marks are sent until a new frame is transmitted. after the line open lcw command has restored transmit mode, the m pD72103A continues to transmit flags or marks unless transmit data from the host processor is being written. 3.6.2 receive frame flags the m pD72103A receives frames as normal receive frames if there is at least one flag between the frames. it also receives frames as normal receive frames when the same flag is used as an end flag and start flag. 3.7 general-purpose input/output pins 3.7.1 detection of changes in general-purpose input pins the m pD72103A checks the status of the general-purpose input pins (gi1 and gi2) once every 8 ms and detects any changes in their status (high level/low level). to perform detection such status changes in general-purpose input pins, select 01 or 10 for operation mode setting lcw command?s gics parameter. when a pin?s level changes from 0 to 1 or 1 to 0 and is retained, the general-purpose input pin change detection 1 lsw or the general-purpose input pin change detection 2 lsw is reported. 3.7.2 control of general-purpose output pins the levels of the m pD72103A?s general-purpose output pins (go1 and go2) are controlled by the general-purpose output pin write lcw command. when the m pD72103A receives a general-purpose output pin write lcw command issued by the host processor, execution of the lcw causes a change in the status of the general-purpose output pins. 3.7.3 general-purpose input/output pin status the host processor issues the general-purpose input/output pin read lcw command after reading the status of the general-purpose input/output pins. when the m pD72103A receives the general-purpose input/output pin read lcw command, it reports the general- purpose input/output pin read acknowledge lsw.
59 chapter 4 commands (lcw) the m pD72103A supports following commands. command no. (h) symbol command name 31 dtsd data send 34 mset memory area setting 35 mdst operation mode setting 36 afst receive address field setting 37 lopn line open 38 lcls line close 3a mard memory area read 3b mdrd operation mode read 3c afrd receive address field read 3d sird statistical information read 41 gowr general-purpose output pin write 42 gprd general-purpose input/output pin read 44 sire statistical information read 2 45 gpre general-purpose input/output pin read 2 46 mdse operation mode setting 2 47 afse receive address field setting 2
60 chapter 4 commands (lcw) command name data transmission symbol dtsd field definitions function this command is used to transmit data that has been set to a command or has been stored in the transmit buffer. description of parameters 1. txbc : transmit data byte count (set within command) this parameter sets the number of transmit data bytes to be set within this command. the number of transmit data bytes can be set as 0 to 8 bytes. when there are more than eight bytes of transmit data, the data is set to the transmit buffer. 2. frbc : fractional bit count this sets the number of fractional bits. frbc can be set as 0 to 7 bits. in the transmit data, the valid bit length is the frbc value counted from the lsb of the last byte. 3. bc : transmit data byte count this indicates the number of bytes of transmit data that are stored in the transmit buffer. bc can be set as 0 to 16 kbytes (0h to 3fffh). 4. bufa : transmit buffer start address this indicates the transmit buffer?s start address. cmdn (31h) lcw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) 00000000 cb frbc txbc bc bufa txdt 76543210
61 chapter 4 commands (lcw) 5. cb : transmit chain specification this selects the transmit buffer chain function. 0 = no transmit buffer chain 1 = transmit buffer chain 6. txdt : transmit data this is the transmit data buffer that is set within the cmdn field. operations using m pD72103A 1. when bufe = 0 in operation mode setting lcw command (mode is not transmit buffer chain mode) (1) when txbc = 0 this setting transmits data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by bufa. however, when frbc 1 0, the transmit data corresponds to the frbc bit at (bc e 1) bytes plus bc bytes. (2) when txbc 1 0 and bc = 0 this setting sends the number of data bytes specified for txbc, which have been set to txdt. however, when frbc 1 0, the transmit data corresponds to the frbc bit at (txbc e 1) bytes plus txbc bytes. (3) when txbc 1 0 and bc 1 0 this setting sends data (having the number of data bytes specified for txbc) which has been set to txdt as well as data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by bufa. however, when frbc 1 0, the transmit data corresponds to the frbc bit at (bc e 1) bytes plus bc bytes. 2. when bufe = 1 in operation mode setting lcw command (mode is transmit buffer chain mode) (1) when first cb = 0 and txbc = 0 (transmit buffer chain is not specified) this setting transmits data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by the first bufa. however, when frbc 1 0, the transmit data corresponds to the frbc bit at (bc e 1) bytes plus bc bytes. (2) when first cb = 0, txbc 1 0, and bc = 0 (transmit buffer chain is not specified) this setting sends the number of data bytes specified for the txbc, which have been set to the first txdt. however, when frbc 1 0, the transmit data corresponds to the frbc bit at (bc e 1) bytes plus bc bytes. (3) when first cb = 0, txbc 1 0, and bc 1 0 (transmit buffer chain is not specified) this setting sends data (having the number of data bytes specified for txbc) which has been set to the first txdt as well as data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by bufa. however, when frbc 1 0, the transmit data corresponds to the frbc bit at (bc e 1) bytes plus bc bytes.
62 chapter 4 commands (lcw) (4) when the cb that is n e 1 from the first cb = 1, the nth cb = 0, txbc = 0, and bc 1 0 (transmit buffer chain is specified) this setting sends data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by the first bufa, data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by the second bufa, and data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by the (n e 1) + nth bufa. however, when frbc 1 0, the transmit data corresponds to the frbc bit at (bc e 1) bytes plus bc bytes. (5) when the cb that is n e 1 from the first cb = 1, the nth cb = 0, the first txbc 1 0, the second txbc = 0, and bc 1 0 (transmit buffer chain is specified) this setting sends the number of data bytes specified for the txbc, which have been set to the first txdt, data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by bufa, data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by the second bufa, and data (having a byte count set by bc) that is stored in the transmit buffer having the start address set by the (n e 1) + nth bufa. however, when frbc 1 0, the transmit data corresponds to the frbc bit at (bc e 1) bytes plus bc bytes. transmit data cannot be set corresponding to the second and subsequent txdts. 3. end of transmission (1) normal end when 1 is set to the txed bit in the operation mode setting lcw command, data transmission completion lsw is reported. (2) abnormal end when 1 is set to the txur bit in the operation mode setting lcw command, data transmission stop lsw is reported. cautions 1. frbc is valid regardless of the oct value set by operation mode setting lcw command. 2. cb is valid when bufe = 1 has been set by operation mode setting lcw command. 3. when there are n (2 n nlcw) data transmission lcw commands in the transmit buffer chain, txbc is valid for the first data transmission lcw command. in addition, frbc is valid for the nth data transmission lcw command. this setting cannot be made under any other conditions. 4. when using transmit buffer chains, data transmission lcw commands are set in the sequence n ? (n e 1) ? first data transmission lcw command. 5. when using a transmit buffer chain, set 1 to the cb that is (n e 1) from the first cb and set 0 to the nth cb. 6. when retn (a parameter in the operation mode setting lcw command) is 0, the m pD72103A continually executes the data send command (cmds is not set to feh) until the frame transmission is completed. 7. be sure to set the transmission baud rate to a value greater than 0 bps. if a transmission baud rate of zero is set, the m pD72103A continually executes the data send command until a hang-up occurs.
63 chapter 4 commands (lcw) command name memory area setting symbol mset field definitions function this command is used to set the command table, status table, and receive buffer address table. description of parameters 1. addr : start address of command table this specifies the command table?s start address. 2. nlcw : number of command table blocks this specifies the number of command table blocks. the specifiable range for nlcw is 1 to 128 (exponent of two) blocks. each block consists of 16 bytes. 3. nlsw : number of status table blocks this specifies the number of status table blocks. the specifiable range for nlsw is 1 to 128 (exponent of two) blocks. each block consists of 16 bytes. 4. nlrbw : number of receive buffer address table blocks this specifies the number of receive buffer address table blocks. each block consists of 4 bytes. the specifiable range for nlrbw is 1 to 128 (exponent of two) blocks. caution set the low-order four bits of addr to 0. cmdn (34h) lcw (0) (1) (2) (3) (4) (5) (6) (7) 00000000 (l) nlcw nlsw 76543210 nlrbw (m) addr (h)
64 chapter 4 commands (lcw) command name operation mode setting symbol mdst field definitions function this command sets the operation mode. issue this command when the system is in idle mode. description of parameters 1. cpu : host processor type this sets the address type according to the host processor type. the default value is 0. 0 this is the default value. it sets the address type for nec and intel cpus. 1 this sets the address type for motorola cpus. cautions 1. nec/intel type : this type assigns low-order data to low-order memory addresses motorola type : this type assigns low-order data to high-order memory addresses 2. appendix b includes caution points concerning use of a motorola cpu with the m pD72103A. 2. dmab : dma block transfer this specifies the number of transfer bytes per data block controlled by the on-chip dma controller. the default value is 0. 0 sets transfer of four bytes per block 1 sets transfer of eight bytes per block cmdn (35h) lcw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) 00000000 fcs dmaw time maxd 76543210 rxbs hold retn txur 0 0 0 0 stbc 0 lapd bufe bufc gics txed loak short loop step oct auto tfil code clk dmab cpu
65 chapter 4 commands (lcw) 3. dmaw : number of dma wait cycles this specifies the number of wait cycles used by the on-chip dma controller. the default value is 11. 00 no wait cycles are inserted 01 1 wait cycle is inserted 10 2 wait cycles are inserted 11 3 wait cycles are inserted 4. clk : transmit/receive clock this selects input pins for the transmit and receive clocks. the default value is 0. 0 the transmit clock is input via the txc pin and the receive clock is input via the rxc pin. (when not using dpll) 1 the transmit and receive clocks are the clock input via the rxc pin divided by 16. (when using dpll) 5. code : coding this selects the data format code for transmit and receive data. 0 selects nrz mode if the rxd pin?s input level is h, the data value is 1. if it is l, the data value is 0. 1 selects nrzi mode if the rxd pin?s input level is inverted, the data value is 0. if it does not change, the data value is 1. 6. tfil : transmission time file during transmission, this selects transmission of flags or marks. the default value is 0. 0 selects transmission of flags at least one flag is inserted between a frame?s end flag and the next frame?s start flag. 1 selects transmission of marks marks for at least one bit are inserted between a frame?s end flag and the next frame?s start flag. 7. fcs : number of bits in the fcs field this specifies the number of bits in the fcs generating polynomial. the default value is 0. 0 selects a 16-bit generating polynomial (fcs = 2 bytes). the generating expression is itu-t (formerly ccitt) x 16 + x 12 + x 5 + 1. 1 selects a 32-bit generating polynomial (fcs = 4 bytes). the generating expression is itu-t (formerly ccitt) x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x 1 + 1.
66 chapter 4 commands (lcw) 8. auto : address field detection this detects the address field during receive operations. either one-byte or two-byte detection can be selected. when auto is specified, the receive operations use the receive data at the address specified by the receive address field setting command or the receive data at a global address. the default value is 00. 00 no address recognition for the receive data 01 recognizes one byte of data immediately after the receive data?s leading flag and recognizes a one-byte address at the address specified by the receive field setting command 10 recognizes the address corresponding to the second byte of the two bytes of data immediately after the receive data?s leading flag 11 recognizes two bytes of data immediately after the receive data?s leading flag and recognizes the address specified by the receive field setting command 9. short : short frame detection this specifies the number of bits for short frame detection. a short frame is defined as when the number of bits between two flags or between a flag and an abort pattern is equal to or less than the number of bits set by this parameter. the fcs field is not included among the bits detected under the short parameter setting. the default value is 00. 00 frame having less than 2 bytes 01 frame having less than 3 bytes 10 frame having less than 4 bytes 11 illegal command is reported (previous setting remains valid) 10. oct : fractional bit frame this specifies fractional bit frame receive operations. in this case, a fractional bit frame is any frame other than one in which one byte of data consists of exactly eight bits. the default value is 0. 0 receive 1 do not receive 11. step : timer step value this specifies the timer step time for the idle monitor timer. this parameter is used with the time bit. the idle monitor timer recognizes an idle status as when at least 15 consecutive 1 bits are received. the time bit is incremented when an idle status exists during the step time period specified by the step parameter. the default value is 0 (when system clock = 8 mhz). 0 time step = 100 ms 1 time step = 8 ms
67 chapter 4 commands (lcw) the step value when the system clock is x mhz is as follows. step = 0 100 ms 8 x step = 1 8 ms 8 x 12. loop : loopback mode this specifies one of the following connection modes for the m pD72103A?s internal connection between the transmission and reception blocks. this is used for auto loopback testing, external loopback, etc. the default value is 00. 00 transmit and receive lines have independent modes 01 loopback mode 1 10 loopback mode 2 11 loopback mode 3 reception block transmission block x ? rxd txd loopback mode 1 rxd txd loopback mode 3 reception block transmission block x rxd txd loopback mode 2 reception block transmission block
68 chapter 4 commands (lcw) 13. stbc : number of receive data bytes (for receive status) this specifies the number of bytes of receive data that is captured in the status. the specifiable range of values for the stbc parameter varies depending on the auto and short parameter settings. these specifiable ranges are listed below. setting range for stbc auto short 00 00 stbc = 0 or 2 stbc 8 00 01 stbc = 0 or 3 stbc 8 00 10 stbc = 0 or 4 stbc 8 01/10/11 00 2 stbc 8 01/10/11 01 3 stbc 8 01/10/11 10 4 stbc 8 14. loak : line open report timing this specifies the timing of the line open completion lsw report. the default value is 0. 0 when flag has been transmitted from local terminal 1 when flag has been received from remote terminal 15. txed : enable/disable transmission completion report this specifies whether or not to output a data transmission completion lsw. the default value is 0. 0 do not output report 1 output report 16. gics : general-purpose input pin change report this specifies output of the general-purpose input pin change detection 1 lsw and the general- purpose input pin change detection 2 lsw. the default value is 00. 00 no report 01 reports general-purpose input pin change detection 1 lsw 10 reports general-purpose input pin change detection 1 lsw and general-purpose input pin change detection 2 lsw caution 11 is a don?t care setting. 17. time : timer value this specifies the number of times that idle status is detected. the idle status is detected based on the step time set via the step parameter. when an idle status is detected, this timer is incremented. the specifiable range of time settings is 0 to 255. the idle status is not detected when time = 0.
69 chapter 4 commands (lcw) 18. rxbs : receive buffer size this specifies the size of the receive buffer. the specifiable range for rxbs is 0 to 16383 (0h to 3fffh). 19. bufc : select receive buffer chain this specifies the receive buffer chain function. the default value is 0. 0 do not use chain function 1 use chain function caution when using the receive buffer chain function, some time is required for processing a change of receive buffer addresses. consequently, an overrun error may occur when the receive buffer size is small and the transfer rate is fast. for details, see 3.4.8 cautions regarding overrun errors. 20. bufe : select transmit chain this specifies the transmit buffer chain function. the default value is 0. 0 do not use chain function 1 use chain function 21. lapd : lapd mode this specifies communication control (in lapd mode) via the gi2 and go3 pins. the default value is 0. 0 no transmission control via gi2 and go3 pins 1 transmission control via gi2 and go3 pins (lapd mode) when lapd mode has been selected, the go3 pin is used for the frame transmission request signal and the gi2 pin is used for the frame transmission enable signal. the operations of these pins during lapd mode are described below. (1) go3 pin when a transmit command is fetched and the transmit data is written to the transmit fifo, this pin goes to l level and a transmit request is sent to an external circuit. when the external circuit causes the gi2 pin to go to l level, frame transmission begins. after the end flag is transmitted, it returns to h level. (2) gi2 pin when the go3 pin goes to l level, the m pD72103A samples this pin and, if it is at l level, frame transmission begins. during frame transmission, if this pin returns to h level frame transmission is stopped and the txd pin is set to the mode specified by tfil. the operation timing of the gi2 and go3 pins is described below.
70 chapter 4 commands (lcw) (a) frame transmission txc go3 gi2 txd mode set by tfil start flag (b) frame transmission stop txc gi2 go3 txd mode set by tfil (c) frame transmission end txc go3 txd mode set by tfil end flag
71 chapter 4 commands (lcw) 22. maxd : maximum bytes of receive data this specifies the maximum number of receive data bytes. maxd values can be specified in the range of 0 to 16383. the maxd setting is valid when bufc = 1. be sure that maxd rxbs x (nlrbw note e 4). note nlrbw is a parameter of the memory area setting lcw command. be sure to set a value of 8 or greater to make maxd valid. 23. hold : transmission wait time this sets the time between the setting of data to the transmit fifo and the start of data transmission from txd. the default value is 00. hold values can be specified in the range of 0 to 255. a value of 1 is approximately equal to 4 m s. this parameter is not related to the tfil parameter. no matter how long a wait time is set by this parameter, the number of start flags remains just one (tfil = 1). 24. retn : number of retries this specifies the number of retries when attempting to execute the data transmission lcw command after an underrun occurs. the retn value e 1 becomes the maximum number of data transmission lcw command execution retries. retn values can be specified in the range of 0 to 127. when set to 0, the data transmission lcw command is issued until a normal end occurs. 25. txur : transmit underrun report this specifies whether or not to report the data transmission stop lsw. the default value is 0. 0 do not report 1 report
72 chapter 4 commands (lcw) command name receive address field setting symbol afst field definitions function this command is used to set address fields for receive frames. it is valid when auto has been set for the operation mode setting command. description of parameters 1. bc : number of receive address fields this specifies the number of address fields to be received. the number of address fields is determined according to the operation mode setting lcw command settings. when auto = 01 or 10 : 1 bc 12 when auto = 11 : bc = 2, 4, 6, 8, 10, 12 2. af : address field this sets the address field. when auto = 01 or 10 has been specified, the first or second byte?s address is set to lcw (3) to (14). when auto = 11 has been specified, the first byte?s address is set to lcw (3) and the second byte?s address is set to lcw (4) as a two-byte combination. cmdn (36h) lcw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) 00000000 0bc af 76543210 000
73 chapter 4 commands (lcw) operations using m pD72103A 1. when auto = 01 or 10 for the address set by af, the address values for the number of fields specified by bc are compared to one byte in the receive data?s address field. if the address set by af matches the receive data, the receive operation begins. example: when bc = 4, the receive operation begins if the received address matches the address set to lcw (3), lcw (4), lcw (5), or lcw (6). 2. when auto = 11 for the two-byte address unit set by af, the address values for the number of fields specified by bc are compared to two bytes in the receive data?s address field. if the address set by af matches the receive data, the receive operation begins. example: when bc = 6, the receive operation begins if the first and second bytes of the received address matches either the address set to lcw (3) and lcw (4) or lcw (5) and lcw (6). caution ffh is set in the af field when reception using a global address (ffh) is required.
74 chapter 4 commands (lcw) command name line open symbol lopn field definitions function this command is used to start data transmission or reception. operations using m pD72103A the operation varies according to the tfil setting for the operation mode setting lcw command. 1. when tfil = 0 (flag) the txd pin is set to flag transmit mode. the line open completion lsw is reported when a flag is sent from a local terminal or when a flag is received from a remote terminal based on the loak setting. 2. when tfil = 1 (mark) the txd pin is set to mark transmit mode (data value = 1). cmdn (37h) lcw (0) lcw (1) 00000000 76543210
75 chapter 4 commands (lcw) command name line close symbol lcls field definitions function this command is used to stop data transmission or reception. operations using m pD72103A after this command is issued, the txd pin goes to high level. this command also stops any receive operation for input data received via the rxd pin. the line close completion lsw is reported when this command is issued. cmdn (38h) lcw (0) lcw (1) 00000000 76543210
76 chapter 4 commands (lcw) command name memory area read symbol mard field definitions function this command is issued when reading various parameters set for the memory area setting lcw command. operations using m pD72103A the memory area read acknowledge lsw is reported when this command is issued. cmdn (3ah) lcw (0) (1) 00000000 76543210
77 chapter 4 commands (lcw) command name operation mode read symbol mdrd field definitions function this command is issued when reading various parameters set for the operation mode setting lcw command. operations using m pD72103A the operation mode read acknowledge lsw is reported when this command is issued. cmdn (3bh) lcw (0) (1) 00000000 76543210
78 chapter 4 commands (lcw) command name receive address field read symbol afrd field definitions function this command is used when reading parameters set for the receive address field setting lcw command. operations using m pD72103A the receive address field read acknowledge lsw is reported when this command is issued. cmdn (3ch) lcw (0) (1) 00000000 76543210
79 chapter 4 commands (lcw) command name statistical information read symbol sird field definitions function this command is issued when reading various types of statistical information note . note all statistical information read by this command is error information. operations using m pD72103A the statistical information read acknowledge lsw is reported when this command is issued. cmdn (3dh) lcw (0) (1) 00000000 76543210
80 chapter 4 commands (lcw) command name general-purpose output pin write symbol gowr field definitions function this command is issued to change the level of general-purpose output pins go1 and go2. description of parameters 1. go1f : status of go1 pin this changes the output level of the go1 pin. go1f bit go1 pin 0l 1h 2. go2f : status of go2 pin this changes the output level of the go2 pin. go2f bit go2 pin 0l 1h caution the level of each general-purpose output pin is set to h after reset. cmdn (41h) lcw (0) (1) (2) 00000000 0 76543210 00000 go2f go1f
81 chapter 4 commands (lcw) command name general-purpose input/output pin read symbol gprd field definitions function this command is issued to read the levels of general-purpose input pins gi1 and gi2 as well as general-purpose output pins go1 and go2. operations using m pD72103A the general-purpose input/output pin read acknowledge lsw is reported when this command is issued. caution the general-purpose input/output values that are read are detected at an 8-ms interval. cmdn (42h) lcw (0) (1) 00000000 76543210
82 chapter 4 commands (lcw) command name statistical information read 2 symbol sire field definitions function this command is issued when reading various types of statistical information note . note all statistical information read by this command is error information. description of parameters 1. sin0, sin1 : statistical information number this set the statistical information number to be read. set ffh for sin1 to read all statistical information as one type. 00h overrun count 01h underrun count 02h idle receive count 03h short frame receive count 04h address field error frame receive count 05h long frame receive count 06h abort frame receive count 07h fcs error frame receive count 08h fractional bit frame receive count 09h status table overflow count 0ah receive buffer address table overflow count operations using m pD72103A the statistical information read acknowledge 2 lsw is reported when this command is issued. cmdn (44h) lcw (0) (1) (2) (3) 00000000 sin0 76543210 sin1
83 chapter 4 commands (lcw) command name general-purpose input/output pin read 2 symbol gpre field definitions function this command is issued to read the levels of general-purpose input pins gi1 and gi2 as well as that of general- purpose output pins go1 and go2. operations using m pD72103A the general-purpose input/output pin read acknowledge 2 lsw is reported when this command is issued. caution the input/output pin modes which are read are those used in the status report. cmdn (45h) lcw (0) (1) 00000000 76543210
84 chapter 4 commands (lcw) command name operation mode setting 2 symbol mdse field definitions function this command sets the operation mode. it is issued to change the operation mode when line open mode has been set. issuing this command does not affect the internal status. however, data received when this command is issued is not guaranteed. description of parameters 1. auto : address field detection this detects the address field during receive operations. 00 no address recognition for the receive data 01 recognizes address for first byte 10 recognizes address for second byte 11 recognizes addresses for first and second bytes caution if auto has been set to any value other than 00, be sure to use the afse command to set addresses. 2. short : number of bits for short frame detection this specifies the number of bits for short frame detection during a receive operation. the fcs field is not included among the bits detected under the short parameter setting. 00 less than 2 bytes 01 less than 3 bytes 10 less than 4 bytes 3. gics : general-purpose input pin change detection this specifies output of the general-purpose input pin change detection 1 lsw and the general- purpose input pin change detection 2 lsw. 00 no report 01 reports general-purpose input pin change detection 1 lsw 10 reports general-purpose input pin change detection 1 lsw and general-purpose input pin change detection 2 lsw cmdn (46h) lcw (0) (1) (2) 00000000 0 76543210 0 gics short auto
85 chapter 4 commands (lcw) command name receive address field setting 2 symbol afse field definitions function this command is used to set address fields for receive frames. this command is issued when auto = 01, 10, or 11 has been set for operation mode setting 2 lcw command and the receive address field is changed in line open status. issuing this command does not affect the internal status. however, data that is received (or being received) when this command is issued is not guaranteed. description of parameters 1. bc : number of receive address fields this specifies the number of address fields to be received. the number of address fields is determined according to the operation mode setting lcw command settings. when auto = 01 or 10 : 1 bc 12 when auto = 11 : bc = 2, 4, 6, 8, 10, 12 2. af : address field this sets the address field. when auto = 01 or 10 has been specified, the first or second byte?s address is set to lcw (3) to (14). when auto = 11 has been specified, the first byte?s address is set to lcw (3) and the second byte?s address is set to lcw (4) as a two-byte combination. cmdn (47h) lcw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) 00000000 0bc af 76543210 000
86 chapter 4 commands (lcw) operations using m pD72103A 1. when auto = 01 or 10 for the address set by af, the address values for the number of fields specified by bc are compared to one byte in the receive data?s address field. if the address set by af matches the receive data, the receive operation begins. example: when bc = 4, the receive operation begins if the received address matches the address set to lcw (3), lcw (4), lcw (5), or lcw (6). 2. when auto = 11 for the two-byte address unit set by af, the address values for the number of fields specified by bc are compared to two bytes in the receive data?s address field. if the address set by af matches the receive data, the receive operation begins. example: when bc = 6, the receive operation begins if the first and second bytes of the received address matches either the address set to lcw (3) and lcw (4) or lcw (5) and lcw (6). caution ffh is set in the af field when reception using a global address (ffh) is required.
87 chapter 5 status (lsw) the m pD72103A uses the status listed below. status no. (h) symbol status name 31 dtrv data receive 32 txur data transmission stop 33 tout idle monitor timer timeout 37 loak line open completion 38 lcak line close completion 39 txed data transmission completion 3a maak memory area read acknowledge 3b mdak operation mode read acknowledge 3c afak receive address field read acknowledge 3d siak statistical information read acknowledge 3f cilg command illegal 40 gi1c general-purpose input pin change detection 1 41 gi2c general-purpose input pin change detection 2 42 gpak general-purpose input/output pin read acknowledge 43 olsw status table overflow 44 siaf statistical information read acknowledge 2 45 gpae general-purpose input/output pin read acknowledge 2
88 chapter 5 status (lsw) status name data receive symbol dtrv field definitions report cause(s) this status is reported when data is received. description of parameters 1. rxbc : receive data byte count (set within status) this parameter sets the number of receive data bytes to be set within this status. the number of receive data bytes can be set as 0 to 8 bytes. when there are more than eight bytes of receive data, the data must be set to the receive buffer. 2. frbc : fractional bit count this sets the number of fractional bits. the value reported as frbc can be set as 0 to 7. in the receive data at the bc value, the valid bit length is the frbc value counted from the lsb of the last byte. 3. bc : receive data byte count this indicates the number of bytes of receive data that are stored in the receive buffer. bc can be set as 0 to 16 kbytes (0h to 3fffh). 4. cb : receive chain specification this selects the receive buffer chain function. 0 = no receive buffer chain 1 = receive buffer chain stsn (31h) lsw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) don? care cb frbc rxbc bc bufa rxdt 76543210
89 chapter 5 status (lsw) 5. bufa : receive buffer start address this indicates the receive buffer?s start address. 6. rxdt : receive data this is the receive data buffer that is set within the dtrv field. operations using m pD72103A the data reception lsw is set to one of the following modes according to the stbc parameter setting in operation mode setting lcw command. a. when stbc = 0 (i) when receive data size rxbs this setting writes data (having a byte count set by bc) that is stored in the receive buffer having a start address specified by bufa. however, when frbc 1 0, the receive data corresponds to the frbc bit at (bc e 1) plus bc bytes. (ii) rxbs < receive data size maxd when bufc = 1 has been set, data (having a byte count set by bc) is write via a receive buffer chain from the receive buffer having the start address specified by bufa. however, when frbc 1 0, the receive data corresponds to the frbc bit at (bc e 1) plus bc bytes. when bufc = 0, the corresponding frames are discarded internally. b. when stbc 1 0 (i) when receive data size stbc data having a byte count set by rxbc is written to the status. when frbc 1 0, the receive data corresponds to the frbc bit at (bc e 1) plus bc bytes. (ii) when receive data size rxbs + stbc data having a byte count set by stbc is written to the status, and data having a byte count set by bc is written to the receive buffer having the start address specified by bufa. however, when frbc 1 0, the receive data corresponds to the frbc bit at (bc e 1) plus bc bytes. (iii) when rxbs + stbc < receive data size maxd + stbc when bufc has been set to 1, the receive buffer having the start address specified by bufa is chained and data (having a byte count set by bc) is written. however, when frbc 1 0, the receive data corresponds to the frbc bit at (bc e 1) plus bc bytes. when bufc = 0, the corresponding frames are discarded internally. caution when cb = 1, bufa is the start address of the first chained receive buffer.
90 chapter 5 status (lsw) status name data transmission stop symbol txur field definitions report cause(s) this status is reported when the operation mode setting lcw command?s txur parameter has been set to 1. it indicates that the data transmission lcw command ended due to an underrun status. description of parameters 1. txur : number of transmission underruns this indicates the number of data transmission lcw commands that have been stopped. stsn (32h) lsw (0) (1) txur 76543210
91 chapter 5 status (lsw) status name idle monitor timer timeout symbol tout field definitions report cause(s) this status is reported when the operation mode setting lcw command?s time parameter 1 0 and a idle monitor timer timeout has occurred. caution this status is reported when data transmission is enabled. stsn (33h) lsw (0) 76543210
92 chapter 5 status (lsw) status name line open completion symbol loak field definitions report cause(s) this status is reported when the line open lcw command has been executed. this status is reported when the operation mode setting lcw command?s tfil parameter is set for flag transmission and while idle mode or flag reception standby mode has been set. stsn (37h) lsw (0) 76543210
93 chapter 5 status (lsw) status name line close completion symbol lcak field definitions report cause(s) this status is reported when the line close lcw command has been executed. caution this status is reported when flag reception standby mode or data transmission enable mode has been set. stsn (38h) lsw (0) 76543210
94 chapter 5 status (lsw) status name data transmission completion symbol txed field definitions report cause(s) this status is reported when the operation mode setting lcw command?s txed parameter has been set to 1 and data transmission via the data transmission lcw command has been completed. description of parameters 1. txen = number of frames whose transmission has been completed this indicates the number of frames that were transmitted during the period between the previous report and this report. caution this status is reported when data transmission enable mode has been set. stsn (39h) lsw (0) txen 76543210
95 chapter 5 status (lsw) status name memory area read acknowledge symbol maak field definitions report cause(s) this status is reported when the memory area setting lcw command has been executed. description of parameters for details of the parameters, see the description of the memory area setting lcw command. the rom version indicates the revision history of the m pD72103A?s internal firmware. the correspondence between rom versions and standards is shown below. standard rom version k . . . 50 e . . . 60 p . . . 60 stsn (3ah) lsw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) don? care addr nlsw 76543210 nlcw nlrbw don? care rom version
96 chapter 5 status (lsw) status name operation mode read acknowledge symbol mdak field definitions report cause(s) this indicates the operation mode that is reported when the operation mode read lcw command has been executed. description of parameters for details of the parameters, see the description of the operation mode setting lcw command. stsn (3bh) lsw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) fcs dmaw time maxd 76543210 rbs hold retn txur stbc bufe bufc gics txed loak short loop step oct auto tfil code clk dmab cpu don? care
97 chapter 5 status (lsw) status name receive address field read acknowledge symbol afak field definitions report cause(s) this status is reported when the receive address field read lcw command has been executed. this status indicates the receive address field that is set via the receive address field setting lcw command. description of parameters for details of the parameters, see the description of the receive address field setting lcw command. stsn (3ch) lsw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) don? care ?c af 76543210
98 chapter 5 status (lsw) status name statistical information read acknowledge symbol siak field definitions report cause(s) this status is reported when the statistical information read lcw command has been executed. the status information includes various kinds of error information. the statistical information is cleared after this status is reported. accordingly, once the statistical information read lcw command is executed, the errors that have occurred before then are reported and a new count begins of any error information that occurs subsequently in the m pD72103A. description of parameters 1. count : count total the count value is 00h when the status information in lsw (2) to (12) consists entirely of 00h values. if error information appears in at least one field from lsw (2) to (12), the count value is 01h. 2. ovrn : overrun count this indicates the number of times an overrun has occurred due to full rxfifo status during data receive operations. 3. unrn : underrun count this indicates the number of times an underrun has occurred due to empty txfifo status during data transmit operations. 4. idle : mark idle detection count this indicates the number of times idle status (at least 15 consecutive 1 values) has been received. stsn (3dh) lsw (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) count 76543210 ovrn unrn idle short addr long abort fcs frac flsw flrbw
99 chapter 5 status (lsw) 5. abort : abort detection count this indicates the number of times an abort pattern (at least 7 consecutive 1 values) has been received. 6. fcs : fcs error detection count this indicates the number of frames in which an fcs error has been detected by crc checking of received frames. 7. addr : unmatched address frame count this parameter is valid when the operation mode setting lcw command?s auto parameter is set to 01 or 10. this indicates the number of times that a frame having an address field other than those specified by the receive address field setting lcw command has been received. 8. frac : fractional bit frame count this parameter is valid when the operation mode setting lcw command?s oct parameter has been set to 1. this indicates the number of times that a frame containing fractional bits has been received. 9. long : long frame count this indicates the number of times that a frame which exceeds the receive buffer size set by the operation mode setting lcw command?s rxbs parameter has been received. when using receive buffer chain mode, it indicates the number of times that a frame which exceeds the receive buffer size set by maxd (a parameter in operation mode read acknowledge lsw) has been received. 10. flsw : status overflow count this indicates the number of times that a status table overflow has occurred for a received frame due to lack of empty space in the receive status table. 11. flrbw : receive buffer overflow count this indicates the number of received frame that have been discarded due to lack of empty space in the receive buffer address table. when there are several instances of error information concerning received frames, the count uses the following prioritization of causes and counts only the cause having the highest priority.
100 chapter 5 status (lsw) 1 2 3 4 5 6 7 overrun short frame address error frame long frame abort frame fcs error frame fractional bit frame highest priority (h) lowest priority (l) caution the count value is ffh in cases where the various statistical information is ffh or greater. remark frames in which the number of bits between a flag and an abort pattern are fewer than the number of bits set by the short parameter are counted as short frames rather than abort frames.
101 chapter 5 status (lsw) status name command illegal symbol cilg field definitions report cause(s) this status is reported when a command having an undefined command number or containing incorrect parameters has been executed. description of parameters 1. ilst : illegal state this indicates that an illegal state exists. 00h indicates that an undefined command number has been issued 01h indicates that an error exists in at least one parameter of the issued command 02h unmatched state 2. lstn : state when illegal this indicates the state (mode) that was in effect when the illegal command was issued. 00h indicates that idle mode was in effect 01h indicates that flag reception standby mode was in effect 02h indicates that data transmission mode was in effect 3. lcwn : illegal command block this indicates the block number in the command table where the illegal command was issued. 4. cmdn : illegal command number this indicates the illegal command?s command number. stsn (3fh) lsw (0) (1) (2) (3) (4) ilst 76543210 lstn lcwn cmdn
102 chapter 5 status (lsw) status name general-purpose input pin change detection 1 symbol gi1c field definitions report cause(s) this status is valid when the gics parameters in the operation mode setting lcw and operation mode setting 2 lcw commands have been set to 01 or 10. it reports that a status change has been detected in general- purpose input pin gi1. description of parameters 1. go1f : go1 pin status this indicates the output level of the go1 pin. 0 indicates that go1 pin is at low level 1 indicates that go1 pin is at high level 2. go2f : go2 pin status this indicates the output level of the go2 pin. 0 indicates that go2 pin is at low level 1 indicates that go2 pin is at high level 3. gi1f : gi1 pin status this indicates the input level of the gi1 pin. 0 indicates that gi1 pin is at low level 1 indicates that gi1 pin is at high level 4. gi2f : gi2 pin status this indicates the input level of the gi2 pin. 0 indicates that gi2 pin is at low level 1 indicates that gi2 pin is at high level 5. idle : idle mode this indicates the state of the rxd pin. 0 not idle 1 idle stsn (40h) lsw (0) (1) sync idle gi2f gi1f go2f go1f 76543210
103 chapter 5 status (lsw) 6. sync : synchronization status this indicates the status of the rxd pin. 0 not receiving flags 1 receiving flags cautions 1. idle and sync are valid during data transmission enable mode. 2. this status indicates states that are detected at an interval of 8 ms.
104 chapter 5 status (lsw) status name general-purpose input pin change detection 2 symbol gi2c field definitions report cause(s) this status is valid when the gics parameter in the operation mode setting lcw command has been set to 10. it reports that a status change has been detected in general-purpose input pin gi2. description of parameters 1. go1f : go1 pin status this indicates the output level of the go1 pin. 0 indicates that go1 pin is at low level 1 indicates that go1 pin is at high level 2. go2f : go2 pin status this indicates the output level of the go2 pin. 0 indicates that go2 pin is at low level 1 indicates that go2 pin is at high level 3. gi1f : gi1 pin status this indicates the input level of the gi1 pin. 0 indicates that gi1 pin is at low level 1 indicates that gi1 pin is at high level 4. gi2f : gi2 pin status this indicates the input level of the gi2 pin. 0 indicates that gi2 pin is at low level 1 indicates that gi2 pin is at high level 5. idle : idle mode this indicates the status of the rxd pin. 0 not idle 1 idle stsn (41h) lsw (0) (1) sync idle gi2f gi1f go2f go1f 76543210
105 chapter 5 status (lsw) 6. sync : synchronization status this indicates the status of the rxd pin. 0 not receiving flags 1 receiving flags cautions 1. idle and sync are valid during data transmission enable mode. 2. this status indicates states that are detected at an interval of 8 ms.
106 chapter 5 status (lsw) status name general-purpose input/output pin read acknowledge symbol gpak field definitions report cause(s) this status indicates the status of general-purpose input/output pins as reported when the general-purpose input/output pin read acknowledge lcw command is executed. description of parameters 1. go1f : go1 pin status this indicates the output level of the go1 pin. 0 indicates that go1 pin is at low level 1 indicates that go1 pin is at high level 2. go2f : go2 pin status this indicates the output level of the go2 pin. 0 indicates that go2 pin is at low level 1 indicates that go2 pin is at high level 3. gi1f : gi1 pin status this indicates the input level of the gi1 pin. 0 indicates that gi1 pin is at low level 1 indicates that gi1 pin is at high level 4. gi2f : gi2 pin status this indicates the input level of the gi2 pin. 0 indicates that gi2 pin is at low level 1 indicates that gi2 pin is at high level 5. idle : idle mode this indicates the status of the rxd pin. 0 not idle 1 idle stsn (42h) lsw (0) (1) sync idle gi2f gi1f go2f go1f 76543210
107 chapter 5 status (lsw) 6. sync : synchronization status this indicates the status of the rxd pin. 0 not receiving flags 1 receiving flags cautions 1. idle and sync are valid during data transmission enable mode. 2. this status indicates states that are detected at an interval of 8 ms.
108 chapter 5 status (lsw) status name status table overflow symbol olsw field definitions report cause(s) this indicates that a status table overflow has occurred. the m pD72103A includes a two-part status buffer. if a status report request is issued when the buffer has not empty space, this status is reported once an empty space is available in the status table. once this status is reported, the status that is stored in the internal status buffer is not reported. caution if a status report request is issued when there is no empty space in the status buffer, the status in the status buffer are discarded and a status overflow flag is set. if the status report request is for data reception lsw, the internal discard occurs regardless of the buffer?s empty/full status, so there is no status overflow in this case. description of parameters 1. go1f : go1 pin status this indicates the output level of the go1 pin. 0 indicates that go1 pin is at low level 1 indicates that go1 pin is at high level 2. go2f : go2 pin status this indicates the output level of the go2 pin. 0 indicates that go2 pin is at low level 1 indicates that go2 pin is at high level 3. gi1f : gi1 pin status this indicates the input level of the gi1 pin. 0 indicates that gi1 pin is at low level 1 indicates that gi1 pin is at high level 4. gi2f : gi2 pin status this indicates the input level of the gi2 pin. 0 indicates that gi2 pin is at low level 1 indicates that gi2 pin is at high level stsn (43h) lcw (0) lcw (1) gi2f gi1f go2f go1f 76543210 lstn
109 chapter 5 status (lsw) 5. lstn : link status this indicates the state (mode) when a status table overflow has occurred. 00h idle mode 01h flag reception standby mode 02h data reception enable mode cautions 1. idle and sync are valid during data transmission enable mode. 2. this status indicates states that are detected at an interval of 8 ms. 3. this status is reported when the status table has been released.
110 chapter 5 status (lsw) status name statistical information read acknowledge 2 symbol siaf field definitions report cause(s) this status is reported when the statistical information read 2 lcw command has been executed. this status reports status information specified by the statistical information read 2 lcw command?s sin0 and sin1 parameters. after this report is issued, the statistical information specified by sin0 and sin1 is cleared. other statistical information that was not specified by the statistical information read 2 lcw command is retained. description of parameters for details of the parameters, see the description of the statistical information read acknowledge lsw. stsn (44h) lsw (0) (1) (2) sin0 76543210 sin1
111 chapter 5 status (lsw) status name general-purpose input/output pin read acknowledge 2 symbol gpae field definitions report cause(s) this status indicates the status of general-purpose input/output pins as reported when the general-purpose input/output pin read acknowledge 2 lcw command is executed. this status indicates each status as it existed at the time of the report. description of parameters 1. go1f : go1 pin status this indicates the output level of the go1 pin. 0 indicates that go1 pin is at low level 1 indicates that go1 pin is at high level 2. go2f : go2 pin status this indicates the output level of the go2 pin. 0 indicates that go2 pin is at low level 1 indicates that go2 pin is at high level 3. gi1f : gi1 pin status this indicates the input level of the gi1 pin. 0 indicates that gi1 pin is at low level 1 indicates that gi1 pin is at high level 4. gi2f : gi2 pin status this indicates the input level of the gi2 pin. 0 indicates that gi2 pin is at low level 1 indicates that gi2 pin is at high level 5. idle : idle mode this indicates the status of the rxd pin. 0 not idle 1 idle stsn (45h) lsw (0) (1) sync idle gi2f gi1f go2f go1f 76543210
112 chapter 5 status (lsw) 6. sync : synchronization status this indicates the status of the rxd pin. 0 not receiving flags 1 receiving flags
113 chapter 6 system configuration examples 6.1 connection with host system two host system/ m pD72103A system configuration examples are described below. (1) local memory type (2) main memory type 6.1.1 local memory type in the local memory type of system configuration, the m pD72103A accesses only the special purpose local memory. it is possible for the host system and the m pD72103A to have simultaneous access, but this requires the external addition of a priority logic circuit for contention resolution. one of the features of this configuration type is that the host system is able to be operated even when the m pD72103A is in bus master mode (i.e., during dma transfers). one of its drawbacks is that it requires dma transfers between the host system?s main memory and local memory. figure 6-1 shows a configuration diagram of the local memory type. figure 6-1. m pD72103A system configuration example (local memory type) ab d71086 oe decoder ab0-ab7 ab8-ab15 ab d71086 oe db0-db15 ab d71086 oe ab16-ab19 bre memr memw ior iow mrd mwr iord iowr host cs a0-a15 d0-d7 ube aen int hldrq hldak int local bus req wait a16d8-a23d15 rd wr cs ube a0-a15 d0-d15 local memory (64 kbytes) priority logic (access contention resolution circuit) pD72103A a0-a15 d0-d15 ab d71086 oe m
114 chapter 6 system configuration examples 6.1.2 main memory type the main memory type enables the m pD72103A to directly access the host system?s main memory. one of its features is that it minimizes memory transfer operations for transmit and receive data. one of its disadvantages is that the host processor must be set to a hold state when the m pD72103A is in bus master mode (i.e., during dma transfers), which reduces the host processor?s operational efficiency. figure 6-2 shows a configuration diagram of the main memory type. figure 6-2. m pD72103A system configuration example (main memory type) host (d70116) pD72103A decoder int intak a16-a19 ad8-ad15 ad0-ad7 rd wr hldrq hldak astb ube buf r/w bufen d71059 ir cs a0 d0-7 wr rd intak int stb oe oe t d71082 3 d71086 2 oe stb rd wr ube cs d0-d7 d8-d15 memory a16-a19 a0-a15 d8-d15 d0-d7 d71082 int cs mrd mwr hldrq hldak aen iord iowr astb d0-d7 a16d8-a23d15 a0-a15 ube m
115 chapter 6 system configuration examples 6.2 physical interface examples 6.2.1 interface example using rs-485 the m pD72103A?s possible applications include lan applications. figure 6-3 shows a two-wire interface example using the rs485 driver. figure 6-3. two-wire interface example 1 2 6 ds3695 7 3 4 transmit/receive data (rs-485 cable) osc (32 mhz) rxd go1 txd rxc pD72103A m 6.2.2 interface example using m pd98201 when the m pD72103A is set to lapd mode, it can be connected with the m pd98201 to be used as a controller for d-channel communications. figure 6-4 illustrates the connection with the m pd98201. figure 6-4. connection example with isdn lsi (connection with sifc [ m pd98201]) hdlc sifc go1 go3 gi2 txd txc rxc rxd cksel/prio abit/dreq drdy din dout nt/te dclk pD72103A pd98201 mm
116 [memo]
117 appendix a m pD72103A operation sequence examples mset local remote pD72103A host processor mdst cmds fch afst note 1 cmds fch cmds fch lopn lopn note 2 cmds feh dtsd txed note 3 if tfil = 0, then mark is transmitted if tfil = 1, then flag transmission is started frame transmission dtrv frame reception in progress frame transmission end cmds fdh dtsd txur note 4 frame transmission frame transmission stop m crqurdy 0 notes 1. valid when auto 00 2. the report timing varies depending on the tfil and loak parameter settings. 3. reported when txed = 1 in the mode setting. 4. reported when txur = 1 in the mode setting.
118 [memo]
119 appendix b connection between hdlc controller and motorola system b.1 differences between nec/intel buses and motorola buses the following are two points of difference between nec/intel buses and motorola buses. b.1.1 difference in allocation of physical even-numbered byte and odd-numbered byte in 16-bit bus in nec and intel buses, when the bits in a 16-bit bus are designated as d0 to d15, d0 to d7 comprise the even address byte and d8 to d15 comprise the odd address byte. in a motorola 16-bit bus, d0 to d7 comprise the odd address byte and d8 to d15 comprise the even address byte. nec/intel type motorola type d0-d7 d8-d15 d0-d7 d8-d15 address 0 address 1 address 1 address 0 address 2 address 3 address 3 address 2 address 4 address 5 address 5 address 4 address 6 address 7 address 7 address 6 :::: :::: b.1.2 difference in representation order of logical 16-bit and 24-bit data in nec/intel type buses, logical 16-bit or 24-bit (multiple byte) data is recognized starting from its low-order address in memory, (for 16-bit data, the order is low-order eight bits, then high-order eight bits; for 24-bit data, the order is low-order eight bits, middle eight bits, then high-order eight bits). in motorola type buses, logical 16-bit or 24-bit (multiple byte) data is recognized starting from its high-order address in memory, (for 16-bit data, the order is high- order eight bits, then low-order eight bits; for 24-bit data, the order is high-order eight bits, middle eight bits, then low- order eight bits). for example, the following shows the representation order of the data value 123456h (hexadecimal) in these two types of buses. nec/intel type motorola type address n 56h 12h address n + 1 34h 34h address n + 2 12h 56h
120 appendix b connection between hdlc controller and motorola system b.2 method for connecting hdlc controller with motorola-based system the hdlc controller is designed to be used with nec/intel buses. accordingly, the following connection method is recommended when connecting to a motorola-based system. b.2.1 data bus connection in hardware hdlc controller motorola bus d0 e e e e e e e e d8 d1 e e e e e e e e d9 d2 e e e e e e e e d10 d3 e e e e e e e e d11 d4 e e e e e e e e d12 d5 e e e e e e e e d13 d6 e e e e e e e e d14 d7 e e e e e e e e d15 a16d8 e e e e e e e e d0 a17d9 e e e e e e e e d1 a18d10 e e e e e e e e d2 a19d11 e e e e e e e e d3 a20d12 e e e e e e e e d4 a21d13 e e e e e e e e d5 a22d14 e e e e e e e e d6 a23d15 e e e e e e e e d7 this connection method resolves the difference described in b.1.1 above. b.2.2 hdlc controller?s mdst command setting (operation mode setting lcw) select cpu = 1 (motorola type). this setting resolves the difference described in b.1.2 above.
121 appendix c questions and answers about the m pD72103A table c-1. question categories (1 of 2) bus interface q.1 during the dma cycle, how much time is required before the hldrq signal becomes active? 2 operation of m pD72103A when crq is issued 3 what is the time period between when crq is issued and when frame transmission begins? 4 operations when commands are issued from m pD72103A 5 processing when int pin is not used 6 dma request 7 dma transfer time and application program processing time 8 what is the priority ranking among dma controller operations? 9 cascade connection example 10 aen pin immediately after reset 11 interrupt occurrence immediately after the int pin goes inactive 12 confirmation of unused pins 13 test pin usage/operation status 14 regarding use of the cmos buffer for the txd pin 15 number of dma blocks transferred during transmit/receive 16 crq pin input 17 minimum pulse width of clrint pin 18 connection with v25+ tm ( m pd70325) host interface q.19 sequence for issuing mset command 20 external memory access 21 command read sequence 22 data transmit lcw 23 issuance of operation mode setting 2 lcw command 24 interrupt following execution of operation mode setting lcw command 25 what is the time period between the line open lcw command is issued and when the line open completion lsw is reported? 26 m pD72103A?s operation when status table cannot be used 27 status table 28 receive buffer table overflow 29 causes of and responses to reception overrun errors 30 what is the m pD72103A?s operation when lrbws are use-disabled? 31 receive buffer address table 32 what does (h), (m), and (l) refer to in the user?s manual? 33 operation of hldrq signal for mset command 34 reception of unmatched address frame during address search 35 maxd setting when not using receive buffer chain 36 reception during receive status reporting 37 full duplex operation 38 fcs error frame processing 39 amount of data retained in fifo
122 appendix c questions and answers about the m pD72103A table c-1. question categories (2 of 2) 40 rba size 41 transmit completion lsw report timing 42 stopping command fetch operation 43 write to command register 44 changing auto parameter 45 status completion detection method 46 undefined status number 47 random write for commands 48 processing of transmit completion status during reception 49 transmission method for fractional frames 50 stbc setting when auto 1 0 communication operations q. 51 is it possible to expand the address recognition function? 52 what is the relationship between the clk signal and the communication speed? 53 operation when transmit clock input is lost 54 use of txc and rxc pins when in internal dpll mode 55 method for stopping transmit operation 56 transmit/receive operations 57 abort transmission 58 allowable jitter for dpll 59 minimum number of transmitted flags 60 dpll lock and flag reception 61 crc polynomial equation and initial value 62 flow control and sequence control 63 transmission steps for transmit crc 64 transmit crc example 65 flag search during mark reception 66 handling of tfil parameter for reception 67 crc calculation range 68 idle pattern when hold 3 1 69 stopping/starting flag transmission 70 stopping reception only 71 confirmation of receive completion at remote side 72 transmit/receive frame intervals other q. 73 functional comparison with similar products 74 ic replacement 75 address/data bus status after reset 76 transmit complete timer function
123 appendix c questions and answers about the m pD72103A bus interface during the dma cycle, how much time is required before the hldrq signal becomes active? q.1 according to this manual, when transmitting and receiving in full duplex mode, the m pD72103A continuously performs dma transfers (in 4-byte units). what is the shortest possible period between the time when hldrq (the hold request signal) becomes inactive (l) during the previous dma cycle and the time when it becomes active (h) during the next dma cycle? a.1 the minimum time period is the system clock time (t cyk ) 12. related reference see 2.2.1 block transfers in this manual. operation of m pD72103A when crq is issued q.2 according to the m pD72103A user?s manual, when the host processor makes a command request, the crq pin or ccrq bit becomes active. at that time, does the m pD72103A send a hold request to the host processor? also, does the host processor set the bus to a hold state? a.2 the m pD72103A does send a hold request. think of the host processor?s control method vis-a-vis the m pD72103A as exactly the same as that used by an ordinary dma controller (such as the m pd71037). when the host processor sends a command request (crq: h/ccrq = 1) to the m pD72103A, the m pD72103A sets hldrq (the hold request signal) for the host processor as active in order to acquire bus access mastership. next, the host processor responds to the hldrq sent from the m pD72103A by returning hldak (hold acknowledge signal) to enable bus access. at this point, the m pD72103A performs a dma transfer of data from memory. related reference see 2.3 interface between m pD72103A and host processor in this manual.
124 appendix c questions and answers about the m pD72103A what is the time period between when crq is issued and when frame transmission begins? q.3 after crq is issued, what is the time period before the m pD72103A actually starts transmitting frames? a.3 there is no rating for the time period between when crq is issued and when frame transmission begins. the time between issuing the transmit command and receiving the transmit command depends on the bus status. similarly, the bus status (timing of bus release by host processor, etc.) also determines the amount of time between receiving the transmit command and starting dma transfer of the transmit data, and thus there is no rating for this time period either. in other words, the time between issuing a crq and transmitting data depends on the m pD72103A?s system configuration. the time between transmit fifo write and the start of data transmission can be specified in the range 0 to 1020 m s (when operating clock is 8 mhz) via the hold parameter setting (in the operation mode setting lcw command). the range for a 5-mhz operating clock is 0 to 1632 m s. related reference see 3.1 initial settings and 3.2 start of communication control operation and flag synchronization setup in this manual.
125 appendix c questions and answers about the m pD72103A operations when commands are issued from m pD72103A q.4 (1) is the following diagram a correct illustration of the dma operation that occurs when a transmit command is issued? description of dma processing (2) the user?s manual does not specifically say what is written to the cmds field during the period between when the m pD72103A reads a command and when an actual frame is transmitted. please explain how the cmds value changes according to the command being executed. (3) if a command is set (cmds = 00) while another command is being executed, can the second command be executed without issuing a crq? (4) suppose that there is an attempt to report a data transmit complete lsw while the data transmit lcw command is being continuously issued. in this case, which has priority: the timing by which the m pD72103A reads the next data transmit lcw command or the timing by which the data transmit completion lsw is written? a.4 (1) yes, the diagram is correct. (2) cmds is written to 0ch after the command is received. when the transmission has been completed, either fdh or feh is written to cmds. (3) yes, the second command can be executed. since each command can be executed once it has been read, it is possible to execute a new command that is written during execution of another command without issuing a crq. (4) if a command read request and a status write request occur internally at the same time, the status write request takes priority. therefore, the data transmit lsw also takes priority. related reference see 2.5.1 command table in this manual. 200 s command read 1 command read 2 frame transmission cmds write cmds write hi-z cmds = 00 cmds ? cmds fe cmds 0c end of processing data transmission complete lsw crq occurs m
126 appendix c questions and answers about the m pD72103A processing when int pin is not used q.5 does leaving the m pD72103A?s int output as active (h) cause any problems for the controller operations? a.5 leaving the m pD72103A?s int output as active does not affect the controller operations. related reference see 1.5 pin functions in this manual. dma request q.6 these questions concern dma requests. (1) in the m pD72103A, how much data must accumulate in the txfifo and rxfifo before a dma request is issued? (2) in the m pD72103A, if dma requests are issued (asynchronously) from both the txfifo and the rxfifo, which is selected: the transmit dma or the receive dma? a.6 (1) concerning the rxfifo, a dma request is issued when four bytes of data have accumulated (when dmab = 0) or when the end of the frame is reached. as for the txfifo, a dma request is issued whenever there is even one byte of empty space. (2) the receive dma takes priority.
127 appendix c questions and answers about the m pD72103A dma transfer time and application program processing time q.7 because the m pD72103A has an on-chip dma function, a bus is dedicated for dma transfer with the host processor, which reduces the bus occupancy time for executing ordinary application programs. what are the dma transfer time and (minimum) application program processing time under the following conditions? conditions transfer rate : 64 kbps transfer data : 1024 bits system clock : 8 mhz a.7 the m pD72103A?s dma controller sets the hldrq signal as active once per 4 m s (minimum). the dma transfer time uses 4 clocks per byte and operates using either four-byte or eight-byte blocks as set by the dmab parameter note . consequently, when using 4-byte transfer mode (dmab = 0), the transfer time is about 16 clocks (or 2 m s when operating at 8 mhz). for 64-kbps transfers, the m pD72103A?s bus occupancy time can be calculated as follows. 1 ? 64000 (bps) 8 (bit) 4 (byte) = 500 m s during this 500- m s transmission period for transmit/receive data, two dma transfers are performed: one transmit and one receive (the period for each is 2 m s). accordingly, when expressed as a ratio relative to the bus occupancy periods for the m pD72103A and the host processor, the bus occupancy period for an application program would be 500 : 4 (or, as a percentage, 0.8%). actually, the ratio is a little larger than 500 : 4, due to the time required for reading the command, writing the status, etc. this has not created any problems during free running tests that nec has performed using an evaluation board. note the dmab parameter belongs to the operation mode setting lcw command. related reference see 2.2 dmac (direct memory access controller) in this manual.
128 appendix c questions and answers about the m pD72103A what is the priority ranking among dma controller operations? q.8 what are the dma controller?s operations in a situation where the data transmit lcw command is executed while a frame is being received and while the m pD72103A?s status table is use-enabled? a.8 (1) in this situation, the m pD72103A performs a receive dma operation. the m pD72103A?s dma controller uses the following three dma channels. dma requests for sending command/status data are processed via firmware. the following is a flow chart of dma request processing. has command for sending dma request been issued? (transmit command processing) no yes has status for sending dma request been issued? (transmit status processing) no yes 1 2 3 channel for sending receive data to receive buffer channel for sending command/status data channel for sending transmit data from transmit buffer highest priority (h) lowest priority (l)
129 appendix c questions and answers about the m pD72103A cascade connection example q.9 are there any standard methods or caution points concerning cascade connections of several m pD72103A chips? a.9 to control several m pd70103a devices, connect them as slave devices to a dma controller (such as the m pd71071). when using this method, we recommend using a priority rotation mode to suppress receive overrruns and transmit underruns. aen pin immediately after reset q.10 when a reset occurs while the reset signal is active, the aen pin goes to high level. is this the correct operation? a.10 when a system reset is performed using the reset signal, the status is as shown in table 1-1 after four system clocks. the status prior to the four system clocks is undefined. check whether or not the system clocks have been input. interrupt occurrence immediately after the int pin goes inactive q.11 after an interrupt occurs (int pin = h), if another interrupt occurs during the brief period when the cclrint bit is set and the int pin is being set as inactive, what happens to the int pin? a.11 if the clrint signal conflicts with the setting of the internal int signal to make the int pin active, setting of the int signal takes priority. therefore, the int pin may not become inactive when clrint is issued. accordingly, we recommend using a level trigger to detect the int signal in such cases. confirmation of unused pins q.12 does having the clrint pin, crq pin, int pin, astb pin, and ready pin set as unused pins cause any problems under the following conditions? all control and status registers are used for processing related to interrupt detection and int pin reset operations control register is used for processing related to issuing crq no-wait processing of dma transfers a.12 there is no problem in the clrint pin, crq pin, int pin, astb pin, and ready pin set as unused pins. for any input pin, the corresponding pin function should be disabled when the pin is not used. clrint pin or crq pin : connect to gnd ready pin : connect to v dd
130 appendix c questions and answers about the m pD72103A test pin usage/operation status q.13 regarding the test pin, when the manual says when using/operating this pin, which pin status is it referring to? what is this pin used for, and what is its operation when pulled down? a.13 when using/operating refers to when a user is using the m pD72103A. however, the test pin is used only during nec?s pre-shipment inspections. the lsi will not operate if this pin is pulled down. regarding use of the cmos buffer for the txd pin q.14 although the txd pin?s high-level signal voltage specification is v oh = 0.7v dd (i oh = e400 m a), when driving one cmos buffer, the i oh value is only about e1 m a. therefore, do you think that a cmos buffer can be used instead of a ttl? a.14 the v ih rating for a high-speed cmos device is 0.7v dd with no margin, but it is possible to connect such a device to the m pD72103A. under the standard rating of v dd = 4.5 v and when i oh = e400 m a, the v oh value is about 4.34 v (reference value). number of dma blocks transferred during transmit/receive q.15 during one dma transfer, data can be transferred in either 4-byte or 8-byte units. does this also apply for transmit/receive data? a.15 the 4-byte or 8-byte unit refers to the rating for the maximum number of bytes per dma transfer. under certain conditions, the number of bytes per dma may be fewer. for example, when a frame that is 19 bytes long is received, if dma transfer is in 4-byte mode, there will be four cycles of 4-byte transfers followed by one cycle during which the remaining three bytes are transferred. the same is true when issuing commands and reporting status. crq pin input q.16 to control the crq pin, is it enough simply to change the pin mode from l to h to l when issuing a command? a.16 yes, that is sufficient.
131 appendix c questions and answers about the m pD72103A minimum pulse width of clrint pin q.17 when generating signals via a pld and inputting them to the clrint pin, how does the m pD72103A respond if a signal having a pulse width less than the rated value (min. 100 ns) is illegally input to the clrint pin? a.17 depending on the signal?s pulse width, the characteristics of the lsi?s internal transistors, the ambient temperature, the power supply voltage, and other use environment conditions, a crq pin acknowledge in preparation for command execution is possible, but the m pD72103A would not execute any operation except reading the command. connection with v25+ ( m pd70325) q.18 does using the v25+ and the m pD72103A in combination cause a problem for the m pD72103A?s bus release operation? a.18 t dhqha refers to the time period between when the m pD72103A sets hldrq signal as inactive and when the v25+ sets the hldak signal as inactive, and t dhac refers to the time until the v25+ enters bus master mode. the minimum value for t dhqha is about three clocks (although it is not mentioned in the manual, there is no problem because three internal clocks are used to generate a signal) and the minimum value for t dhac is 1 clock e 50 ns. if the v25+ clock and the m pD72103A?s clock are the same, the time period between when the m pD72103A?s hldrq signal goes inactive to when the aen signal goes inactive is only about one clock, which means there should not be any problem. use these specifications as a reference for design.
132 appendix c questions and answers about the m pD72103A host interface sequence for issuing mset command q.19 the figure below shows the sequence by which the mset command is issued, as described in this manual (figure 2-1). what is the maximum time period that the m pD72103A requires for each of the operations indicated by (1), (2), and (3) in the figure? (1) the period between when the m pD72103A is reset and when the status register?s frdy bit is set to 0 (2) the period between when one byte of mset command data is written to the port 3 address and when the status register?s frdy bit is set to 0 (3) the period between when a crq interrupt occurs and when the status register?s crqurdy bit is set to 0 start read frdy in status register frdy = 0 no yes write 5 to port 1 address write one byte of mset command data to port 3 address read frdy in status register frdy = 0 no yes has all of mset command been written? no read crqurdy bit in status register crqurdy = 0 no crq interrupt yes yes end 10-ms wait (when system clock = 8 mhz) during this period, data is written one byte at a time from lcw (0) in the "memory area setting lcw" command. (1) (2) (3)
133 appendix c questions and answers about the m pD72103A a.19 there are no maximum time ratings for these, but the following times can be established based on the number of internal firmware instructions. (1) after completion of reset operation (7 clocks after the reset signal goes inactive) (2) 20 clocks after the data write operation (3) 5000 clocks after the crq is issued. however, the crq for the next command can be issued 10 ms after the crqurdy bit is set to 1. related reference see 2.3.1 command issuance in this manual. external memory access q.20 when b/w pin is set to high level (1) when the m pD72103A accesses the cmds at the second byte in the command table, does it access in byte access or word access (a0 and ube are both low)? (2) does the m pD72103A use byte access mode or word access mode when accessing the status table?s stsn field? a.20 (1) it uses byte access mode. (2) it uses byte access mode. related reference see 1.5 pin functions in this manual. command read sequence q.21 when the host processor has set the m pD72103A?s ccrq bit (crq pin) as active, does the m pD72103A always start reading a command from the lcw0 field in the command table? a.21 the m pD72103A reads the command from the area following the command table area used in the previous command execution. for example, the processing flow may be as follows. <1> the host processor writes the operation mode setting lcw command (the address specified by the mset command?s addr parameter), then issues a crq. <2> the m pD72103A reads this command from lcw0 and then executes the operation mode setting lcw command. <3> after the operation mode setting lcw command has been completed, the m pD72103A reads to lcw1. however, when fxh is the cmds (command status field) value in lcw1, the m pD72103A stops reading the command table. <4> the host processor writes a new command to a new table (lcw1: address value is 10h), then issues a crq. related reference see 2.5.1 command table in this manual.
134 appendix c questions and answers about the m pD72103A data transmit lcw q.22 (1) when five data transmit lcw commands are chained and an underrun is detected for one of the data transmit lcw commands, does the m pD72103A report the data transmit completion lsw (txen parameter = 4) and/or the data transmission stop lsw (txur parameter = 1)? also, does the m pD72103A report the data transmit completion lsw after reading the data transmit lcw commands? (2) when frbc = 1 and the data transmit lcw command is issued, is it the lsb in the last transmit data that is transmitted? (3) why is it that the nth data transmit lcw command must be the first to be written when transmitting via a transmit buffer chain? a.22 (1) the following two cases can be considered. if the status table is empty, the m pD72103A reports the data transmit completion lsw or the data transmission stop lsw after each data transmit lcw command is completed. however, when the status table is full, the txur and txen parameters are incremented. when the status becomes empty again, the m pD72103A reports the data transmit completion lsw or the data transmission stop lsw. (2) yes, it is. when frbc = 4, d0 to d4 in the last byte is transmitted. (3) this is due to the operation shown in the following figure.
135 appendix c questions and answers about the m pD72103A remark if a transmit buffer chain frame that includes data transmit lcw (1) to (5) is to be sent but the host processor has not checked for command completion, the m pD72103A divides the frame into two frames, one for data transmit lcw (1) and (2) and one for data transmit lcw (3) to (5), and then transmits them. related reference see the data transmission command description in chapter 4 commands (lcw) of this manual. lcw0 lcw1 lcw2 lcw3 lcw4 lcw5 lcw6 lcw7 lcw8 memory host processor pD72103A (1) write line open lcw (2) issue crq (6) write data transmit lcw (7) issue crq (9) write data transmit lcw (1) (cb = 1) (10) write data transmit lcw (2) (cb = 1) (15) write data transmit lcw (3) (cb = 1) (16) write data transmit lcw (4) (cb = 1) (18) write data transmit lcw (5) (cb = 0) (19) issue crq (3) read line open lcw (12) read data transmit lcw (1) (cb = 1) execute data transmit lcw (1) (5) read lcw1 (no command setting) (8) read data transmit lcw (11) completion of data transmit lcw (cmds < fxh) (13) read data transmit lcw (2) (cb = 1) execute data transmit lcw (2) (14) read lcw4 (no command setting) (17) completion of data transmit lcw (cmds < fxh) (20) read data transmit lcw (3) (cb = 1) execute data transmit lcw (3) (21) read data transmit lcw (4) (cb = 1) execute data transmit lcw (4) (22) read data transmit lcw (5) (cb = 0) execute data transmit lcw (5) (23) read lcw7 (no command setting) (24) completion of data transmit lcw (cmds < fxh) (4) completion of line open lcw (cmds < fxh) m
136 appendix c questions and answers about the m pD72103A issuance of operation mode setting 2 lcw command q.23 does the operation mode setting 2 lcw command need to be issued only when the m pD72103A has received a flag or idle status? a.23 issuance of the operation mode setting 2 lcw is not related to the m pD72103A?s internal status. however, any data received after this command has been issued is not guaranteed. related reference see the operation mode setting 2 lcw command description in chapter 4 commands (lcw) of this manual. interrupt following execution of operation mode setting lcw command q.24 does the int signal become active after the operation mode setting lcw command is executed? a.24 no, it does not become active. after the operation mode setting lcw command is executed, there is no active interrupt signal from the m pD72103A to the host processor. what is the time period between when the line open lcw command is issued and when the line open completion lsw is reported? q.25 setting condition: the timing of line open completion status report is when a flag has been transmitted from a local source (set via loak = 0). given the above setting condition, what is the time period between when the line open command is issued to the m pD72103A and when the line open completion status is reported? a.25 there is no rating for the maximum time, but a value of 1800 clocks can be calculated under the following conditions and based on the number of internal firmware instructions. conditions: 100% bus ownership; no command is issued to the m pD72103A; rxd pin has high-level status (status during which the m pD72103A can only perform the line open task).
137 appendix c questions and answers about the m pD72103A m pD72103A?s operation when status table cannot be used q.26 what are the m pD72103A?s operations when the status table cannot be used (when no stsn with a value of ffh is available)? a.26 since the m pD72103A includes a two-part status buffer, everything except the data reception lsw is retained. if a status report request is issued when the buffer is full, a status table overflow lsw is reported and the buffer is cleared once an empty space is available in the status table. however, any data reception lsw is internally discarded regardless of the buffer?s internal status if the status table is not empty. for details, see also the m pd72103 application note . related reference see the status table overflow description in chapter 5 status (lsw) of this manual. status table q.27 condition: eight lsws are set for the host processor. after executing two commands, the m pD72103A has written to lsw0 and lsw1. <1> at that point, does the m pD72103A write the status to lsw2 when the next command is completed? <2> what kind of processing does the m pD72103A perform if a new status report request for a data reception lsw is generated? <3> if lsw2 cannot be used (if lsw2 in the stsn file is not ffh), does the m pD72103A check the stsn field in lsw3? a.27 the m pD72103A has a status address pointer. this pointer is incremented when the m pD72103A writes a status to the status table. <1> if a new status report request has been generated, the m pD72103A attempts to write a status to lsw2 but cannot because lsw2 cannot be used (it must wait until lsw2 is use-enabled). neither can it write to lsw3 or the other lsws. <2> the data reception lsw is discarded. <3> two following two cases can be considered. if lsw2 is use-disabled (but the other lsws are use-enabled), when a new status report request (any except for data reception lsw) has been generated, the m pD72103A writes a status to the internal status buffer note . after lsw2 becomes use-enabled, the m pD72103A writes the status to lsw2. if three or more new status report requests occur while lsw2 is use-disabled, the m pD72103A sets the status table overflow flag. next, the m pD72103A waits until lsw2 can be used for the status table overflow, after which it reports the status to lsw2. the following is a flow chart of the status reporting operations. note the m pD72103A includes a two-part status buffer.
138 appendix c questions and answers about the m pD72103A status reporting flow chart start new status write request? no is internal status buffer full? no yes no yes yes is internal status buffer full? set overflow flag stsn read address: pointer to status table stsn = ffh? no yes overflow flag = 1? yes no increment pointer increment pointer clear internal status buffer write status to lsw indicated by status pointer write status to internal status buffer write status table overflow lsw related references see ?.5.2 status table ?in this manual. see 1.2.2 status reporting sequence ?in the m pd72103 application note .
139 appendix c questions and answers about the m pD72103A receive buffer overflow table q.28 the following kinds of events occurred when i attempted to operate the m pD72103A. are these operations correct? (1) when the m pD72103A received the next data, the area in the receive buffer table that was to be accessed indicated that the receive buffer had not been released (brdy = ffh) while other areas showed that the receive buffer had been released (brdy = 00). at that point, the receive data was discarded even though the receive buffer had been released for the next area. receive buffer address table (2) after the statistical information read acknowledge status is read to confirm that 1 has been written to flrbw (see <3> in the figure below), data is received while overflow status is still in effect (see <4> in the figure below, where the receive data is discarded). later, the value of flrbw remains 0 at the area (<6> in the figure) where the statistical information read acknowledge status was read (all of the receive data is discarded). if the statistical information read acknowledge status was read when an overflow occurred in the receive buffer address table, why isn?t the statistical information subsequently updated even when data has been discarded several times? 70 00 00 00 01 ff 00 08 01 00 00 0a 01 rba brdy rba brdy rba brdy receive buffer address area to be accessed when the pD72103A receives the next data receive buffer address table overflow occurs (if brdy = ffh) m data has been received, so brdy in the receive buffer address area is accessed to check whether or not the receive buffer has been released. (brdy = 00h: released/brdy = ffh: not released) data has been received, so brdy in the receive buffer address area is accessed to check whether or not the receive buffer has been released. (brdy = 00h: released/brdy = ffh: not released) pD72103A overflow occurs in receive buffer address table discarded discarded < 1 > data reception < 4 > data reception < 7 > data reception < 2 > statistical information read command < 3 > statistical information read acknowledge status (flrbw = 1) < 5 > statistical information read command < 6 > statistical information read acknowledge status (flrbw = 0) < 8 > statistical information read command < 9 > statistical information read acknowledge status (flrbw = 0) m
140 appendix c questions and answers about the m pD72103A a.28 (1) the receive data was discarded because the status table was not empty. since each table in the m pD72103A is a link buffer, each command or status is executed in order starting at the top. if the status table is not empty, the m pD72103A must wait for it to become empty, during which time it reports a status table overflow lsw and then clears the buffer contents note . however, in the case of a data reception lsw, the buffer contents are discarded regardless of the buffer?s internal status unless the status table is empty. therefore, since the status table is not empty during the method (data receive) described in your question, the buffer contents are discarded. note the m pD72103A includes a two-part status buffer. (2) in this case, the statistical information is not updated for the following reasons. the first receive frame is counted when data is received while there is no empty space in the receive buffer address table and status table, but subsequent frames are not counted when data is received while there is no empty space. accordingly, with reference to the timing shown with the question, the count is cleared by the statistical information read command <2>and the count operation is not performed for subsequent receive data, so the flrbw value remains 0 in the statistical information read acknowledge status indicated by <6> and <9>. related references see 2.5.3 receive buffer address table in this manual. see the status table overflow description in chapter 5 status (lsw) of this manual.
141 appendix c questions and answers about the m pD72103A causes of and responses to reception overrun errors q.29 reception overrun errors have occurred when using the m pD72103A under the conditions listed in the following table (occurrence rate: 0.08%). what are the causes of these errors and what responses should be made? use conditions communication mode full duplex system clock 5 mhz transfer rate 2 mbps amount of receive data 500 bytes per frame receive frame interval every 3 ms reception time fill flag reception command chain none amount of transmit data 50 bytes per frame transmit frame interval flag transmit time fill every 100 ms transmit command chain none dma data access unit word unit dma transfer time per block 2 m s (measured), two bus cycles a.29 in the case of 4-byte block transfers (dmab = 0), if the receive dma?s interval is 16 m s, all of the receive data in the receive fifo can be transferred, but the receive dma interval becomes longer if a transmit operation is being performed at the same time. for example, if the receive dma interval is 20 m s, then logically one byte remains in the receive fifo for each receive dma transfer, which eventually causes an overrun in the receive fifo. to avoid this, try one of the following responses. set dma transfers to 8-byte block transfer mode (dmab = 1). set the system clock to 8 mhz and speed up the firmware processing rate. shorten the dma interval. communication operations were performed without problems using nec?s evaluation system, in which the system clock speed is 8 mhz and the transfer rate is 4 mbps. related reference see 3.4.8 cautions regarding overrun errors in this manual.
142 appendix c questions and answers about the m pD72103A what is the m pD72103A?s operation when lrbws are use-disabled? q.30 conditions: four lrbws have been set by the host processor. the m pD72103A receives frames and uses lrbw0. when the m pD72103A starts receiving the next frame, it checks lrbw1. if lrbw1 becomes use-disabled under the above conditions, does the m pD72103A keep searching for an lrbw that has been released? also, is the frame discarded at that point? a.30 the received frame is discarded and the m pD72103A waits until the brdy value (in lrbw1) becomes ffh. the m pD72103A includes three internal receive buffer address fifos and a receive buffer address table (rbat) pointer. the m pD72103A uses this pointer to search for the lrbw indicated by the pointer. for example, after lrbw0 is used to receive the first frame, lrbw1 indicates the rbat pointer. if lrbw1 is used-disabled and the internal receive buffer address fifo is empty, when the m pD72103A receives the next receive frame, it discards the receive data and waits until the brdy value in lrbw1 becomes ffh. also, when the m pD72103A reads the lrbw indicated by the rbat pointer, rba is set to the internal receive buffer address table fifo and the receive buffer address table?s pointer is incremented. related reference see 2.5.3 receive buffer address table in this manual. receive buffer address table q.31 (1) can three receive buffer addresses be stored in the rba fifo? (2) conditions: when the m pD72103A receives a frame, it reads lrbw1 (use-enabled) and stores the value to the internal rba fifo?s receive address. the m pD72103A then increments the pointer to the receive buffer address table. in this case, after the m pD72103A has received a frame, does it read the receive buffer address from the rba fifo and report the receive buffer address in the data receive lsw? (3) if the m pD72103A discard any frames it receives while the 128-byte rxfifo is full and lrbw1 is use- disabled? a.31 (1) yes, they can be stored there. the m pD72103A always reads the lrbw indicated by the pointer. when the brdy (receive buffer status field) value is 00h, the m pD72103A reads the rba and stores the value in the rba fifo (ffh is then written to brdy). (2) yes, that is correct. (3) yes, that is correct. the m pD72103A discards frames as it receives them and continues to read lrbw1. related reference see 2.5.3 receive buffer address table in this manual.
143 appendix c questions and answers about the m pD72103A what does (h), (m), and (l) refer to in this manual? q.32 what does (h), (m), and (l) refer to in connection with the rba in section 2.5.3 receive buffer address table of this manual? a.32 they refer to high, middle, and low values among memory addresses. whenever (h), (m), and (l) appear in this manual, they refer to high, middle, and low values among memory addresses (in intel products, low-order memory addresses are low). related reference see 2.5.3 receive buffer address table in this manual. operation of hldrq signal for mset command q.33 i am using a method whereby the memory area setting lcw command is issued by writing to the internal fifo. when using this method, setting the control register?s ccrq bit causes the hldrq signal to become active. is this operation correct? a.33 yes, it is correct. reception of unmatched address frame during address search q.34 when the auto parameter in the operation mode setting lcw command has been set to 01, receiving a frame that does not contain a setting address field causes addr in the statistical information to be incremented, but is the receive data transferred? a.34 there is no dma transfer of the receive data. maxd setting when not using receive buffer chain q.35 this manual says that maxd is valid when bufc = 1, but can maxd also be used as a discard condition for the buffer even when bufc = 0? a.35 maxd is not used when bufc = 0. the buffer discard condition in this case is rxbs.
144 appendix c questions and answers about the m pD72103A reception during receive status reporting q.36 what happens when new data is received while receive status processing is still being performed? a.36 even while the host is busy processing a previously received frame, data in the next frame to be received can be accumulated in the receive fifo. when that data accumulates beyond a certain amount (threshold value), it is transferred to the receive buffer via a dma transfer. when reception of the next frame is completed (when an fcs check has detected that it is a normal frame), the receive status is written to the status table and, as a final step, the interrupt pin is again set as active. no matter what kind of processing the host is performing, as long as the m pD72103A?s receive block has empty space in its receive buffer and status table it can continue to receive frames and report status. full duplex operation q.37 as part of full duplex communications, is it possible for reception interrupt servicing and transmit command processing to be performed at the same time? if so, does dma access alternate between the transmit data read and receive data write operations? a.37 yes, they can be performed at the same time. however, since receive processing has priority in the m pD72103A, when a transmit command request occurs at the same time, the transmit command processing must wait for completion of receive processing. this means that the two types of processing do not necessarily alternate. fcs error frame processing q.38 when the received frame is normal, it is written to external memory. then, what happens if the received frame is abnormal? a.38 receive data that has been accumulated in the receive fifo before the abnormality was detected is transferred to the receive buffer. for example, in the case of an fcs error the fcs check results are not known until the fcs is received, so all of the data prior to the fcs is temporarily transferred to the receive buffer. in cases where the receive data is discarded, this occurs simply by assigning the receive buffer address pointer as reusable. amount of data retained in fifo q.39 is there a way to externally detect how much data has accumulated in the transmit fifo and receive fifo at any particular time? a.39 no, there is no way to detect that.
145 appendix c questions and answers about the m pD72103A rba size q.40 when the manual says any size up to 16 kbytes can be set for the receive buffer, does that refer to one receive buffer that occupies 16 kbytes starting at the receive buffer address (rba) that is set to the receive buffer address table, or does it mean the entire receive buffer in external memory can be 16 kbytes in size? a.40 unless the receive buffer chain mode is being used, the receive buffer is the 16 kbytes that begin at the receive buffer address set to the receive buffer address table. when using the receive buffer chain mode, since maximum maxd value is 16 kbytes, the receive buffer size must be maxd rxbs (nlrbw e 4). in either case, there is no need to restrict the size of the entire receive buffer in external memory to 16 kbytes. transmit completion lsw report timing q.41 is it correct that the transmit completion lsw is reported after the fcs field is detected? a.41 yes, that is correct. stopping command fetch operation q.42 is the command fetch operation stopped only when the cmds value is ffh? is it ever stopped when cmds is fch, fdh, or feh? a.42 the command fetch operation is stopped if the cmds value is fxh. this means that it is stopped if the cmds value is fch, fdh, or feh (but not ffh). write to command register q.43 the int pin is set as active to facilitate software processing related to the control register. at a certain point, the ccrq bit is set to 1, the cclrint bit is set to 0, and the register is accessed expressly so that a crq can be issued. does it cause a problem when, afterward, the ccrq bit is set to 0, the cclrint bit is set to 1, and the register is accessed so as to set the int pin as inactive? also, is it possible to check the values that have been written to the control register? a.43 no, it does not cause a problem. setting a control register bit to 1 enables the corresponding function to be executed, and setting it to 0 does not affect other bits. there is no way to check the values that have been written to the control register.
146 appendix c questions and answers about the m pD72103A changing auto parameter q.44 after afst is used to set the receive address with auto set to the initial value (01), when the mdse command is used to set auto to 00 during communication (line open status) and to 01 afterward, the frame at the receive address field set via afst is received. why does this happen? a.44 when the mdse command is used to set auto to 00 during communication, all internally set addresses are cleared. later, when auto is set to 01, the receive address has been lost, so the auto = 00 remains. consequently, after changing the auto setting from auto = 00 to auto 1 00, be sure to use the afse command to reset the receive address. status completion detection method q.45 statuses have been written in order to the status table. when host performs status processing, does it proceed in order from the area where the previous status was processed to the next area until it reaches an stsn = ffh setting? a.45 yes, it does. undefined status number q.46 are undefined status numbers reported to stsn? and if they are, can ffh be written to stsn, just like for the normal operation? a.46 undefined statuses are not reported. if one were somehow to be reported and ffh is written to stsn, it would not affect the operation. random write for commands q.47 when executing a series of commands, successive command areas are used. however, when only one command is issued in response to one command request, does it cause a problem to randomly use the command areas? a.47 like the status table, the command table is written to starting from the command table header (lcw0) before a command is executed. therefore, it is not possible to randomly use the command areas. when a command is written, it should always be written to the area that follows the area used for the previous command.
147 appendix c questions and answers about the m pD72103A processing of transmit completion status during reception q.48 what is the status report timing on the transmitting and receiving sides when several transmit commands are written and transmissions are performed for several destinations while issuing only one crq? is a status report done after each command is completed? also, please explain the int pin?s set/reset conditions during this process. a.48 the transmitting side performs a transmit completion status report after each frame has been transmitted. however, if a factor occurs that requires high-priority processing similar to frame receive processing, the number of transmitted frames are internally counted until the high-priority processing is completed. later, when a status report can be made, the transmit completion status is reported. accordingly, it is possible that just one transmit completion status may be used to report completion of several frame transmissions. the receiving side performs a receive completion status report after each frame has been received. the int pin is set as active after each receive status is written. the int pin can be set as inactive only by setting the control register?s cclrint bit to 1 or by inputting a high-level pulse signal to the clrint pin. transmission method for fractional frames q.49 when the operation mode setting lcw command?s bufe parameter has been set to 0, how can the transmit command?s parameters be set to transmit a fractional frame consisting of 16 bytes plus 5 bits (assuming that txbc = 0)? a.49 the fractional bit length can be expressed by setting 5h as the frbc value. however, for the bc parameter be sure to set 11h to include the fractional bits rather than setting 10h (16 in decimal notation). stbc setting when auto 1 0 q.50 can stbc be set to 0 when auto 1 0? a.50 as was indicated in the table that was provided with the description of the operation mode setting lcw command?s stbc parameter, stbc cannot be set to 0 when auto 1 0.
148 appendix c questions and answers about the m pD72103A communication operations is it possible to expand the address recognition function? q.51 when at least three bytes of bits are needed in an address field, can the address field be expanded? a.51 no, it cannot be expanded. the m pD72103A?s address recognition function works for up to two bytes. if there are three or more bytes, they should be processed using host software. related reference see 3.4.4 address field recognition in this manual. what is the relationship between the clk signal and the communication speed? q.52 the frequency range for the m pD72103A?s system clock input is 1 to 16 mhz. does the relationship with communication speed place any restrictions on this input range? a.52 basically, there is no mutual relationship between the clk signal and the communication speed. however, since the clk signal is captured via dma transfer timing, transmit underrun or overrun errors may frequently occur if the clk signal is too slow. accordingly, in such situations it is possible that the system may cease to support communications functions. related reference see 1.5 pin functions in this manual. operation when transmit clock input is lost q.53 when in a mode that uses the txc pin as an input, if the line open operation is performed normally but the signal to be input to the txc pin is lost (due to line breakage, etc.). the other input signals (to txd and rxd, etc.) remain normal. (1) if the above occurs, does the m pD72103A notify the host processor? (2) how would the m pD72103A operate if the above occurred during a transmit operation? (3) how would the m pD72103A operate if the data transmit lcw command is issued after the above occurs? a.53 (1) no, it does not notify the host processor. when the txc signal is fixed at h or l, the result is the same as when a zero baud-rate clk signal is input. accordingly, the user learns of the above event when, after a transmit command has been executed and the timer has been activated, a timeout occurs indicating that input to the txc pin has stopped. (2) the m pD72103A stops the transmit operation. the receiving side receives an abort pattern. (3) the m pD72103A cannot accurately receive a newly issued data transmit command until the txd signal has been input again.
149 appendix c questions and answers about the m pD72103A use of txc and rxc pins when in internal dpll mode q.54 please explain the use of the txc and rxc pins when internal dpll mode has been selected. a.54 when in internal dpll mode, input a clk signal to the rxc pin at 16 times the baud rate. the txc pin functions as an output during internal dpll mode. related reference see 4. serial timing in the data sheet. method for stopping transmit operation q.55 how can a transmit operation be stopped? a.55 perform the following steps to stop transmission when using a transmit command chain. <1> the m pD72103A captures transmit commands from the command table in top-to-bottom order. after capturing a command, it sets 00h to cmds. <2> set 0 to the cb parameter in a command for which the cmds value is not 00h to stop the transmit command chain operation. <3> change the cmdn and cmds values to ffh in the next transmit command. example: if the chain contains eight transmit commands, the following can be done to stop the chain transmission at the sixth transmit command in the chain. after the host processor confirms that the fifth command?s cmds value is not 00h, change the sixth transmit command?s cmdn and cmds parameters to ffh while the cb parameter is set to 0. if the fifth command?s cmds value has already been changed to 00h, use the above operation for the sixth and seventh transmit commands. cautions 1. transmit operations cannot be stopped except when in transmit command chain mode. 2. make sure that the cb parameter value is 0. it is not possible to change the cmdn parameter to ffh. in a transmit buffer chain, the cmdn and cmds values are not checked in the second and subsequent commands, so the transmit operation continues based on the remaining parameters.
150 appendix c questions and answers about the m pD72103A transmit/receive operations q.56 (1) if a line close lcw command is issued while the m pD72103A is transmitting data, does the m pD72103A abort the transmission? (2) what does the m pD72103A do if a line close lcw command is issued while it is receiving data? (3) if a transmission underrun occurs while executing the operation mode setting lcw command (retn = 0), does the m pD72103A continue to execute the data transmit lcw command until a normal end occurs? a.56 (1) the m pD72103A reads and executes one command at a time, so it will not attempt to execute a line close lcw command while a data transmit lcw command is still being executed. consequently, no transmission is aborted. (2) the m pD72103A reads the line close lcw command and immediately executes it, then stops data reception. at that point, the receive frame is discarded. (3) yes, it does. if the retn parameter has been set to 0, the m pD72103A will continue to execute the data transmit lcw command until a normal end occurs. related references see the line close command description in chapter 4 commands (lcw) of this manual. see the operation mode setting command description in chapter 4 commands (lcw) of this manual. abort transmission q.57 (1) when a transmission underrun has occurred, does the m pD72103A automatically transmit an abort pattern? does it attach a flag afterward? (2) what is the length of the abort pattern transmitted by the m pD72103A? a.57 (1) yes, the m pD72103A transmits an abort pattern when a transmission underrun occurs. after it transmits the abort pattern, it transmits a mark if tfil = 1 note or a flag pattern if tfil = 0. the following diagram shows the state transition following occurrence of a transmission underrun. ?? transmit data transmit abort (8 to 13 bits) transmit flag (tfil = 0) or mark (tfil = 1) - transmission underrun occurs note tfil is a parameter in the operation mode setting lcw command. (2) as shown in the above diagram, the abort pattern?s length is 8 to 13 bits. related reference see 3.3.4 transmission underrun in this manual.
151 appendix c questions and answers about the m pD72103A allowable jitter for dpll q.58 what is the percentage of allowable jitter for the m pD72103A?s on-chip dpll? a.58 as was explained in section 3.4.1 reception timing of this manual, the m pD72103A?s on-chip dpll increments or decrements the count position of a divide-by-16 brc counter depending on the counter?s count position and the inversion position of data input to the rxd pin. it generates a reception clock signal that follows the jitter in the receptio n data. in other words, it allows for jitter up to 1/16th of the bit period if there is an edge-based inversion at each bit (if using nrzi format, 0 sets continuous reception). however, during actual communications, it is rare that an edge inversion would occur at every bit. for example, if a flag has been selected as the time fill setting, under nrzi format, up to six consecutive 1 bits (flag pattern) would be input. in other words, if there is one edge per 7 bits, jitter would be (1 ? 16 ? 7 =) 0.9%. if mark has been selected as the time fill setting, there are no edges during mark idle reception, so the dpll cannot provide any effect during this period and, in the worst case, a negative-phase lock may occur. thus, whenever possible, the flag setting should be used for idle mode to enable adjustment for jitter. minimum number of transmitted flags q.59 at least three flags are inserted for a transmit frame. why are at least three flags needed? a.59 this is a restriction imposed by the m pD72103A?s internal circuitry and is not related at all to communication operations. the m pD72103A?s flag transmission circuitry is divided into an end flag transmission circuit, an idle flag transmission circuit (or mark pattern transmission circuit when idle = 1), and a circuit that transmits the next frame?s start flag. consequently, at least three flags are required. dpll lock and flag reception q.60 when using the dpll during reception, can flags be detected if the dpll is not locked? a.60 there is no relationship at all between flag-based synchronization and dpll locking. flag detection is performed by sampling the rxd pin at the clock?s rising edge, and a flag is detected when the sampled pattern is 01 1111 10. there is absolutely no need to lock the dpll?s clock signal in this case. note, therefore, that no temporal relationship between flag-based synchronization and dpll locking is determined. crc polynomial equation and initial value q.61 is the crce16 (x 16 + x 12 + x 5 + 1) format for crc calculations supported? what is the initial setting for the crc calculator? a.61 crce16 is not supported. the initial setting is ffh.
152 appendix c questions and answers about the m pD72103A flow control and sequence control q.62 does the m pD72103A provide sequence control and flow control like the m pd72107 (lapb controller) does? also, are sldc loops supported? a.62 unlike the m pd72107, the m pD72103A does not provide sequence control and flow control. it performs only hdlc framing control. other types of control should be implemented via host software. the m pD72103A does not support sldc loops. transmission steps for transmit crc q.63 what are the steps for sending transmit crc calculation results? a.63 not only the m pD72103A but also every other communication controller that support crc calculations inverts the transmit crc calculation result logic and sends the results starting from the msb. transmit crc example q.64 please show an example of transmit crc calculation results. a.64 shown below are crc calculation results obtained after transmission of each byte of the following transmit data. transmit data 00h 01h 10h ffh crc calculation result e1f0 7078 60f8 ff00 actual data 78 ? f0 f1 ? 71 f9 ? d0 00 ? ff flag search during mark reception q.65 when at least 8 bits of mark status is input to the rxd pin while line open status is in effect, does the m pD72103A?s receive circuit automatically enter flag search mode? also, is there any relationship between the idle monitor timer used during mark status and the receive circuit? a.65 when at least 8 bits of mark status is detected, flag search mode is automatically set. the idle monitor timer and the receive circuit operate independently and therefore do not affect each other.
153 appendix c questions and answers about the m pD72103A handling of tfil parameter for reception q.66 the operation mode setting lcw command has a tfil parameter that relates to transmission, but is there also a setting related to reception? a.66 no, there is no such parameter. in the m pD72103A, reception is continued regardless of whether it is a flag or a mark that is used in idle mode. crc calculation range q.67 which pattern shows the correct range for crc calculations? a.67 pattern <2> shows the correct range for crc calculations for any hdlc device manufactured by nec or any other company. idle pattern when hold 3 1 q.68 when a value of 1 or greater is set as the hold parameter, is it correct to assume that the pattern set by tfil will be sent during the period in which the transmit data is transmitted? a.68 yes, that is correct. stopping/starting flag transmission q.69 is it possible to start and/or stop flag transmission without stopping the receive operation while line open status is in effect? a.69 it is not possible to control this via software, but lapd mode can be used to implement external hardware-based port control. when doing this, be sure that tfil is set to 1. start flag address control information field fcs end flag calculation range pattern < 1 > start flag address control information field fcs end flag calculation range pattern < 2 >
154 appendix c questions and answers about the m pD72103A stopping reception only q.70 is it possible to stop reception only while line open status is in effect? a.70 no, it is not possible to stop reception only. confirmation of receive completion at remote side q.71 when transmit completion status is reported, does that mean that data transmission to the remote side has ended normally? a.71 the transmit completion status is a status that is reported to indicate that a frame has been transmitted from the txd pin without causing any transmission underrun in the m pD72103A and it does not indicate whether or not the remote side has correctly received the transmitted frame. the m pD72103A is an lsi that performs hdlc-type framing only and it does not provide sequence control or flow control functions. confirmation of correct reception at the remote side should be implemented via host software. transmit/receive frame intervals q.72 when transmitting and receiving 6-byte frames in full duplex mode at 2.2 mbps, is it possible to set a transmission interval of 600 m s and an interval ranging from 0 to 300 m s between transmitting and receiving? a.72 during the command handling operation, the internal firmware checks whether or not a crq has been issued when the command reaches the crq program check module within the main routine. if a crq has been issued, processing jumps to the corresponding command?s program. when using loopback mode (transmit/receive interval = 0), a 2- mbps transfer rate, and evaluation of transmit data length as 10 bytes, an average transmission interval of 625 m s is determined. however, this applies to a case in which transmission and reception occur at almost the same time. if there is any fluctuation in the transmit/receive interval, the reception processing is delayed and the time required for confirming the crq (one processing cycle of the main routine) may become longer. therefore, it is impossible to fix the transmission interval at 600 m s.
155 appendix c questions and answers about the m pD72103A other functional comparison with similar products q.73 please provide a chart comparing the functions of the m pd72305, m pd72107, m pd72001, m pD72103A, and m pd72002. a.73 a function comparison chart is shown below.
156 appendix c questions and answers about the m pD72103A manufacturer nec nec nec part number m pd72305 m pD72103A m pd72002 supported standards/ itu-t 1.440 and 1.441 (lapd) hdlc asynchronous (asynchronous) recommendations hdlc control, sequence control cop (character oriented protocol) flow control, multi-link support bop (bit oriented protocol) hdlc, sdlc number of channels 1 1 1 hdlc flag detection/generation ??? frame auto zero fill ??? control crc generating polynomial same as m pD72103A when 16-bit: x 16 + x 12 + x 5 + 1 x 16 + x 12 + x 5 + 1 when 32-bit: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x 1 + 1 crc add/check ??? abort generate/delete ??? address addition/recognition 2-byte addition/recognition 1-byte or 2-byte addition/recognition 1-byte addition/recognition (programmable) maximum transfer rate 4 mbps 8 mbps 2.2 mbps transmit/receive buffers transmit buffer, 16 levels transmit fifo, 32 levels transmit buffer, 2 levels receive buffer, 32 levels receive fifo, 128 levels receive buffer, 4 levels data between frames same as m pD72103A flag pattern is 01111110, selectable as all 1 flag pattern is 01111110, selectable as all 1 dma controller 24-bit address 8/16-bit data transmit dma/receive dma byte/word transfer options 24-bit address (switchable via external pin connection) serial interface same as m pD72103A external channel required for using time external channel required for using time slot interface slot interface processor interface same as m pD72103A connectable to intel/motorola bi-directional connectable to intel/motorola bi-directional interface interface custom software for manufacturer none none none voltage +5 v 10% +5 v 10% +5 v 10% process cmos cmos cmos operating ambient temperature e40 to +85 c e40 to +85 c e10 to +70 c package 64-pin shrink dip, 68-pin qfj, 80-pin qfp 68-pin qfj, 80-pin qfp 40-pin dip, 44-pin qfp, 44-pin qfj, 44-pin tqfp
157 appendix c questions and answers about the m pD72103A manufacturer nec nec part number m pd72107 m pd72001 e11 ea supported standards/recommendations itu-t x.25 (labd) compliant asynchronous (asynchronous) hdlc control, sequence control cop (character oriented protocol) flow control bop (bit oriented protocol) supports itu-t x.75 hdlc, sdlc number of channels 1 2 hdlc flag detection/generation ?? frame auto zero fill ?? control crc generating polynomial same as m pD72103A x 16 + x 12 + x 5 + 1 crc add/check ?? abort generate/delete ?? address addition/recognition 1-byte or 2-byte addition/recognition 1-byte addition/recognition (programmable) maximum transfer rate 4 mbps 2.2 mbps 1.6 mbps transmit/receive buffers transmit buffer, 16 levels transmit buffer, 2 levels 2 receive buffer, 32 levels receive buffer, 4 levels data between frames same as m pD72103A flag pattern is 01111110, selectable as all 1 dma controller 24-bit address transmit dma/receive dma 2 byte/word transfer options (switchable via external pin connection) serial interface same as m pD72103A external channel required for using time slot interface processor interface same as m pD72103A connectable to intel/motorola bi-directional interface custom software for manufacturer none none voltage +5 v 10% +5 v 10% +3.3 v 0.3 v process cmos cmos operating ambient temperature e40 to +85 c e10 to +70 c package 64-pin shrink dip, 68-pin qfj, 80-pin qfp 40-pin dip, 52-pin qfp, 52-pin qfj, 44-pin tqfp note note m pd72001-11 only
158 appendix c questions and answers about the m pD72103A ic replacement q.74 i would like to replace hardware that uses the m pd72107 (lapb controller) with the m pD72103Alp (hdlc controller) and m pd72305l (lapd controller) ics. to do this, which hardware components do i need to change? a.74 no hardware needs to be changed except for the general-purposes input/output pins.
159 appendix c questions and answers about the m pD72103A address/data bus status when reset q.75 (1) what are the statuses of the address and data pins while the reset pin is active? (2) i am using the m pD72103A with byte mode and 4-byte transfer settings. what happens if hldak (the hold acknowledge pin) goes inactive (l) during transmission of the second byte? (3) when hldak goes low while the m pD72103A is in bus master mode, does the m pD72103A release its buses (address/cycle data buses for high-impedance status) during the last dma bus cycle? (4) during a 4-byte block transfer, if hldak goes inactive during a two-byte transfer, what happens to the remaining two bytes? a.75 (1) these statuses are described in the following timing chart. clk reset 4 clk + delay addr data previous status is retained hi-z previous status is retained hi-z
160 appendix c questions and answers about the m pD72103A (2) please refer to the timing chart shown below. as was described in figure 2-5 and figure 2-6 in the user?s manual, the m pD72103A samples at the rising edge of the s0, which comes before s1 in the dma cycle. if high level is maintained for at least the t hha time period, the cycle from s1 to s4 (one bus cycle) operates in bus master mode. when the hldak pin is again sampled at the rising edge of s4, if it is still at high level, the next bus cycle begins. accordingly, if four bus cycles are used for one block transfer, if the hldak pin?s status should be maintained for the t hha time period after the rising edge of s4 during three bus cycles (t hha : 20 ns minimum). see the bus master-mode timing charts shown in the m pD72103A?s data sheet. note check whether or not the next state transition occurs at the rising edge of s4. see the ac characteristics listed in the m pD72103A?s data sheet for information on hldak and hldrq setup and hold times corresponding to s4. (3) yes, that is correct. the m pD72103A uses s4 timing to sample the hldak pin. if the hldak pin is low, the hldrq pin is set as inactive (l) at the end of the s4 timing. related reference see 5. electrical characteristics in the data sheet. (4) the remaining two bytes are transferred via dma transfer 4.5 clocks after the s4 cycle of the previous bus cycle has been completed and when the hldrq signal becomes active. transmit complete timer function q.76 is there a function that will automatically increment a counter when a transmit command is completed and report the status when a specified count value is reached? a.76 no, there is no such function. clk s1 s2 s3 s4 note si si si si s0 hldak t sha t hha hldrq addr previous status is retained hi-z data previous status is retained hi-z transfer status at second byte
161 table d-1. command list (1/2) command symbol byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 page no. byte 8 byte 9 byte 10 byte 11 byte 12 byte 13 byte 14 byte 15 31h bc bc bufa bufa bufa data send dtsd 60 txdt txdt txdt txdt txdt txdt txdt txdt memory -area mset 34h addr (l) addr (m) addr (h) nlcw nlsw nlrbw 63 setting operation 35h stbc time rxbs mode mdst 64 setting rxbs maxd maxd hold retn receive 36h bc af af af af af address field afst 72 setting af af af af af af af line open lopn 37h 74 line close lcls 38h 75 memory area read mard 3ah 76 operation mode read mdrd 3bh 77 appendix d command list 00000000 c frbc txbc b 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000 0000 ftcc dc cfol dmaw mp sidk au le b lsos a otch u oeto t pp r o t lbb tl 0 auu gics xo pff ea dec dk t x u r
appendix d command list 162 table d-1. command list (2/2) command symbol byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 page no. byte 8 byte 9 byte 10 byte 11 byte 12 byte 13 byte 14 byte 15 receive address afrd 3ch 78 field read statistical information sird 3dh 79 read general- purpose gowr 41h 80 output pin write general-purpose input/output gprd 42h 81 pin read statistical information sire 44h sin0 sin1 82 read 2 general-purpose input/output gpre 45h 83 pin read 2 operation mode mdse 46h 84 setting 2 receive 47h bc af af af af af address field afse 85 setting 2 af af af af af af af 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000 gg 000000 oo 21 ff gsa ihu 00 c o t sro t
163 table e-1. status list (1/2) status symbol byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 page no. byte 8 byte 9 byte 10 byte 11 byte 12 byte 13 byte 14 byte 15 31h don?t care bc bc bufa bufa bufa data receive dtrv 88 rxdt rxdt rxdt rxdt rxdt rxdt rxdt rxdt data transmission txur 32h txur 90 stop idle monitor timer tout 33h 91 timeout line open completion loak 37h 92 line close completion lcak 38h 93 data transmission txed 39h txen 94 completion memory 3ah don?t care addr addr addr nlcw nlsw nlrbw area read maak 95 acknowledge don?t care rom version operation 3bh don?t care time rbs mode read mdak 96 acknowledge rbs maxd maxd hold retn appendix e status list c frbc rxbc b ftcc dc cfol dmaw mp sidk au le b lsos a otch u oeto t pp r o t bb tl || uu gics xo ff ea ec dk |||| stbc t x u r
chapter e status list 164 table e-1. status list (2/2) status symbol byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 page no. byte 8 byte 9 byte 10 byte 11 byte 12 byte 13 byte 14 byte 15 receive 3ch don?t care af af af af af address afak 97 field read acknowledge af af af af af af af statistical 3dh count ovrn unrn idle short addr long information siak 98 read acknowledge abort fcs frac flsw flrbw command illegal cilg 3fh ilst lstn lcwn cmdn 101 general- purpose input gi1c 40h 102 pin change detection 1 general- purpose input gi2c 41h 104 pin change detection 2 general-purpose input/output gpak 42h 106 pin read acknowledge status table overflow olsw 43h lstn 108 statistical information siaf 44h sin0 sin1 110 read acknowledge 2 general-purpose input/output gpae 45h 111 pin read acknowledge 2 |||| bc s i gggg || yd i i oo nl2121 cefff f s i gggg || yd i i oo nl2121 cefff f s i gggg || yd i i oo nl2121 cefff f gggg |||| iioo 2121 ffff s i gggg || yd i i oo nl2121 cefff f
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