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1 of 22 092801 features real-time clock (rtc) counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap-year compensation valid up to 2100 96-byte, battery-back ed, nonvolatile (nv) ram for data storage two time-of-day alarms?programmable on combination of seconds, minutes, hours, and day of the week serial interface supports motorola serial peripheral interface (spi) serial data ports or standard 3-wire interface burst mode for reading/writing successive addresses in clock/ram dual-power supply pins for primary and backup power supplies optional trickle charge output to backup supply 2.0v to 5.5v operation optional industrial temperature range: - c to +85 c available in space-efficient, 20-pin tssop package underwriters laboratory (ul) recognized ordering information ds1305 16-pin dip (300-mil) ds1305n 16-pin dip (industrial) ds1305e 20-pin tssop (173-mil) ds1305en 20-pin tssop (industrial) pin assignment ds1305 serial alarm real-time clock www.maxim-ic.com v cc2 120v cc1 v bat 219nc x1 3 18 pf nc 4 17 v ccif x2 5 16 sd0 nc 6 15 sdi int0 7 14 sclk nc 8 13 nc int1 9 12 ce gnd 10 11 sermode ds1305 20-pin tssop (173-mil) v cc2 1 16 v cc1 v bat 215pf x1 3 14 v ccif x2 4 13 sdo nc 5 12 sdi int0 6 11 sclk int1 7 10 ce gnd 8 9 sermode ds1305 16-pin dip (300-mil)
ds1305 2 of 22 pin description v cc1 - primary power supply v cc2 - backup power supply v bat - +3v battery input v ccif - interface logic power supply input gnd - ground x1, x2 - 32,768khz crystal connection int0 - interrupt 0 output int1 - interrupt 1 output sdi - serial data in sdo - serial data out ce - chip enable sclk - serial clock sermode - serial interface mode pf - power-fail output description the ds1305 serial alarm real-time clock provides a full binary-coded decimal (bcd) clock calendar that is accessed via a simple serial interface. th e clock/calendar provides se conds, minutes, hours, day, date, month, and year information. the end of the m onth date is automatically adjusted for months with fewer than 31 days, including correc tions for leap year. the clock oper ates in either the 24-hour or 12- hour format with am/pm indicator. in addition, 96 bytes of nonvolatile ram are provided for data storage. an interface logic power supply input pin (v ccif ) allows the ds1305 to drive sdo and pf pins to a level that is compatible with the interface logic. this allows an easy interface to 3v logic in mixed supply systems. the ds1305 offers dual-power supplies as well as a battery input pin. the dual power supplies support a programmable trickle charge circuit that allows a re chargeable energy source (such as a super cap or rechargeable battery) to be used for a backup supply. the v bat pin allows the device to be backed up by a non-rechargeable battery. the ds1305 is fully operational from 2.0v to 5.5v. two programmable time-of-day alarms are provid ed by the ds1305. each alarm can generate an interrupt on a programmable combina tion of seconds, minutes, hours, and day. ?don?t care? states can be inserted into one or more fields if it is desired for them to be ig nored for the alarm condition. the time-of- day alarms can be programmed to assert two different interrupt outputs or to assert one common interrupt output. both interrupt outputs operate when the device is powered by v cc1 , v cc2 , or v bat . the ds1305 supports a direct interface to motorola spi se rial data ports or standard 3-wire interface. a straightforward address and data format is implemented in which data transfers can occur 1 byte at a time or in multiple-byte burst mode. operation the block diagram in figure 1 shows the main elements of the serial alarm rtc. the following paragraphs describe the function of each pin.
ds1305 3 of 22 ds1305 block diagram figure 1 signal descriptions v cc1 ? dc power is provided to the device on this pin. v cc1 is the primary power supply. v cc2 ? this is the secondary power supply pin. in sy stems using the trickle charger, the rechargeable energy source is connected to this pin. v bat ? battery input for any standard 3v lithium cell or other energy source. ul recognized to ensure against reverse charging current when used in conjunction with a lithium battery. see ?conditions of acceptability? at http://www.maxim-ic.com/techsupport/qa/ntrl.htm . v ccif (interface logic power supply input) ? the v ccif pin allows the ds1305 to drive sdo and pf output pins to a level that is compatible with the interface logic, thus allowing an easy interface to 3v logic in mixed supply systems. this pin is physically connected to the source connection of the p-channel transistors in the output buffers of the sdo and pf pins. sermode (serial interface mode input) ? the sermode pin offers the flexibility to choose between two serial interface modes. when conne cted to gnd, standard 3-wire communication is selected. when connected to v cc , motorola spi communication is selected. sclk (serial clock input) ? sclk is used to synchronize data movement on the serial interface for either the spi or 3-wire interface. sdi (serial data input) ? when spi communication is selected, th e sdi pin is the serial data input for the spi bus. when 3-wire communication is selected, th is pin must be tied to the sdo pin (the sdi and sdo pins function as a single i/o pin when tied together).
ds1305 4 of 22 sdo (serial data output) ? when spi communication is selected, the sdo pin is the serial data output for the spi bus. when 3-wire communication is selected, this pin must be tied to the sdi pin (the sdi and sdo pins function as a single i/o pin when tied together). ce (chip enable) ? the chip enable signal must be asserted high during a read or a write for both 3- wire and spi communication. this pin has an internal 55k pull-down resistor (typical). int0 (interrupt 0 output) ? the int0 pin is an active low output of th e ds1305 that can be used as an interrupt input to a processor. the int0 pin can be programmed to be asserted by only alarm 0 or can be programmed to be asserted by e ither alarm 0 or alarm 1. the int0 pin remains low as long as the status bit causing the interrupt is present and the co rresponding interrupt enable bit is set. the int0 pin operates when the ds1305 is powered by v cc1 , v cc2 , or v bat . the int0 pin is an open drain output and requires an external pull-up resistor. int1 (interrupt 1 output) ? the int1 pin is an active low output of th e ds1305 that can be used as an interrupt input to a processor. the int1 pin can be programmed to be asserted by alarm 1 only. the int1 pin remains low as long as the status bit cau sing the interrupt is present and the corresponding interrupt enable bit is set. the int1 pin operates when the ds1305 is powered by v cc1 , v cc2 , or v bat . the int1 pin is an open drain output and re quires an external pull-up resistor. both int0 and int1 are open drain outputs. the two interrupts a nd the internal clock continue to run regardless of the level of v cc (as long as a power source is present). pf (power fail output) ? the pf pin is used to indicate loss of the primary power supply (v cc1 ). when v cc1 is less than v cc2 or is less than v bat , the pf pin will be driven low. x1, x2 ? connections for a standard 32.768khz quartz crys tal. the internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pf. for more information on crystal selection and crystal layout considerations, please consult application note 58, ?crystal considerations with dallas real-time clocks.? the ds1305 can also be driven by an external 32.768khz oscillator. in this configuration, the x1 pin is connected to the ex ternal oscillator signal and the x2 pin is floated. recommended layout for crystal
ds1305 5 of 22 clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. additional error will be added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscilla tor circuit may result in the clock running fast. see application note 58, ?crystal considerations with dallas r eal-time clocks? for detailed information. clock, calendar, and alarm the time and calendar information is obtained by reading the appropriate register bytes. the rtc registers and user ram are illustrated in figure 2. the time, calendar, and alarm are set or initialized by writing the appropriate register bytes. note that some bits are set to zero. these bits will always read 0 regardless of how they are written. also note that registers 12h to 1fh (read) and registers 92h to 9fh are reserved. these registers will always read 0 regardless of how they are written. the contents of the time, calendar, and alarm registers are in the bcd format. except where otherwise noted, the initial power on state of all registers is not defined. therefore, it is important to enable the oscillator (eosc = 0) and disable write protect (wp = 0) during initial configuration. rtc registers and address map figure 2 hex address read write bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 range 00h 80h 0 10 sec sec 00-99 01h 81h 0 10 min min 00-59 p 01-12 + p/a 12 a 02h 82h 0 24 10 10 hr hours 00-23 03h 83h 0 0 0 0 day 1-7 04h 84h 0 0 10 date date 1-31 05h 85h 0 0 10 month month 01-12 06h 86h 10 year year 00-99 alarm 0 07h 87h m 10 sec alarm sec alarm 00-59 08h 88h m 10 min alarm min alarm 00-59 p 12 a 01-12 + p/a 09h 89h m 24 10 10 hr hour alarm 00-23 0ah 8ah m 0 0 0 day alarm 01-07 alarm 1 0bh 8bh m 10 sec alarm sec alarm 00-59 0ch 8ch m 10 min alarm min alarm 00-59 p 12 a 01-12 + p/a 0dh 8dh m 24 10 10 hr hour alarm 00-23 0eh 8eh m 0 0 0 day alarm 01-07 0fh 8fh control register 10h 90h status register 11h 91h trickle charger register 12-1fh 92-9fh reserved 20-7fh a0-ffh 96 bytes user ram 00-ff note: 1. range for alarm registers does not include mask?m? bits.
ds1305 6 of 22 the ds1305 can be run in either 12-hour or 24-hour m ode. bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. when high, the 12-hour mode is selected. in th e 12-hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20?23 hours). the ds1305 contains two time-of-day alarms. time-of-day alarm 0 can be set by writing to registers 87h to 8ah. time-of-day alarm 1 can be set by writing to registers 8bh to 8eh. the alarms can be programmed (by the intcn bit of the control register) to operate in two different modes; each alarm can drive its own separate interrupt out put or both alarms can drive a common interrupt output. bit 7 of each of the time-of-day alarm registers are mask bits (table 1). when all of the mask bits are logic 0, a time- of-day alarm will only occur once per week when th e values stored in timekeeping registers 00h to 03h match the values stored in the time-of-day alarm registers. an alarm will be generated every day when bit 7 of the day alarm register is set to a logic 1. an al arm will be generated every hour when bit 7 of the day and hour alarm registers is set to a logic 1. similarly, an alarm will be generated every minute when bit 7 of the day, hour, and minute alarm registers is set to a logic 1. when bit 7 of the day, hour, minute, and seconds alarm registers is set to a logic 1, alarm will occur every second.
ds1305 7 of 22 time-of-day alarm mask bits table 1 alarm register mask bits (bit 7) seconds minutes hours days 1 1 1 1 alarm once per second 0 1 1 1 alarm when seconds match 0 0 1 1 alarm when minutes and seconds match 0 0 0 1 alarm hours, minutes and seconds match 0 0 0 0 alarm day, hours, minutes and seconds match special purpose registers the ds1305 has three additional registers (control regist er, status register, and trickle charger register) that control the real-time clock, interrupts, and trickle charger. control register (read 0fh, write 8fh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 eosc wp 0 0 0 intcn aie1 aieo eosc (enable oscillator) ? this bit when set to logic 0 will start the oscillator. when this bit is set to a logic 1, the oscillator is stopped and the ds1305 is pl aced into a low-power standby mode with a current drain of less than 100 nanoamps when power is supplied by v bat or v cc2 . the initial power on state is not defined. wp (write protect) ? before any write operation to the clock or ram, this bit must be logic 0. when high, the write protect bit prevents a write operati on to any register, including bits 0, 1, 2, and 7 of the control register. upon initial power-up, the state of the wp bit is undefined. therefore, the wp bit should be cleared before attempting to write to the device. intcn (interrupt control) ? this bit controls the relationship between the two time-of-day alarms and the interrupt output pins. when the intcn bit is set to a logic 1, a match between the timekeeping registers and the alarm 0 registers will activate the int0 pin (provided that the alarm is enabled) and a match between the timekeeping registers and the alarm 1 registers will activate the int1 pin (provided that the alarm is enabled). when the intcn bit is set to a logic 0, a match between the timekeeping registers and either alarm 0 or alarm 1 will activate the int0 pin (provided that the alarms are enabled). int1 has no function when intcn is set to a logic 0. aie0 (alarm interrupt enable 0) ? when set to a logic 1, this bit permits the interrupt 0 request flag (irqf0) bit in the status register to assert int0 . when the aie0 bit is set to logic 0, the irqf0 bit does not initiate the int0 signal. aie1 (alarm interrupt enable 1) ? when set to a logic 1, this bit permits the interrupt 1 request flag (irqf1) bit in the status register to assert int1 (when intcn = 1) or to assert int0 (when intcn = 0). when the aie1 bit is set to logic 0, the irqf1 bit does not initiate an interrupt signal. status register (read 10h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000000irqf1irqf0
ds1305 8 of 22 irqf0 (interrupt 0 request flag) ? a logic 1 in the interrupt request flag bit indicates that the current time has matched the alarm 0 registers. if the aie0 bit is also a logic 1, the int0 pin will go low. irqf0 is cleared when the address pointer goes to any of the alarm 0 registers during a read or write. irqf1 (interrupt 1 request flag) ? a logic 1 in the interrupt request flag bit indicates that the current time has matched the alarm 1 registers. this flag can be used to generate an interrupt on either int0 or int1 depending on the status of the intcn bit in the control register. if the intcn bit is set to a logic 1 and irqf1 is at a logic 1 (and aie1 bit is also a logic 1), the int1 pin will go low. if the intcn bit is set to a logic 0 and irqf1 is at a logic 1 (and aie1 bit is also a logic 1), the int0 pin will go low. irqf1 is cleared when the address pointer goes to any of the alarm 1 registers during a read or write. trickle charge register (read 11h, write 91h) this register controls the trickle charge characte ristics of the ds1305. the simp lified schematic of figure 3 shows the basic components of the trickle charger. the trickle charge select (tcs) bits (bits 4-7) control the selection of the trickle charger. in orde r to prevent accidental enabling, only a pattern of 1010 will enable the trickle charger. all other patterns will disable the trickle charger. on the initial application of power, the ds1305 powers up with the trickle charger disabled. the diode select (ds) bits (bits 2-3) select whether one diode or tw o diodes are connected between v cc1 and v cc2 . the resistor select (rs) bits select the resistor th at is connected between v cc1 and v cc2 . the resistor and diodes are selected by the rs and ds bits as shown in table 2. programmable trickle charger figure 3
ds1305 9 of 22 trickle charger resistor & diode select table 2 tcs bit 7 tcs bit 6 tcs bit 5 tcs bit 4 ds bit 3 ds bit 2 rs bit 1 rs bit 0 function xxx xxx00 disabled xxx x00xx disabled xxx x11xx disabled 1 0 1 0 0101 1 diode, 2k ? 1 0 1 0 0110 1 diode, 4k ? 1 0 1 0 0111 1 diode, 8k ? 1 0 1 0 1001 2 diodes, 2k ? 1 0 1 0 1010 2 diodes, 4k ? 1 0 1 0 1011 2 diodes, 8k ? diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a syst em power supply of 5v is applied to v cc1 and a super cap is connected to v cc2 . also assume that the trickle charger ha s been enabled with 1 diode and resister r1 between v cc1 and v cc2 . the maximum current i max would,therefore,be calculated as follows: i max = (5.0v - diode drop) / r1 (5.0v - 0.7v) / 2k 2.2ma as the super cap charges, the voltage drop between v cc1 and v cc2 will decrease and, therefore, the charge current will decrease. power control power is provided through the v cc1 , v cc2 , and v bat pins. three different power supply configurations are illustrated in figure 4. conf iguration 1 shows the ds1305 being backed up by a non-rechargeable energy source such as a lithium battery. in this c onfiguration, the system power supply is connected to v cc1 and v cc2 is grounded. the ds1305 will be write protected if v cc1 is less than v bat . the ds1305 will be fully accessible when v cc1 is greater than v bat + 0.2v. configuration 2 illustrates the ds1305 being backed up by a rechargeable energy source. in this case, the v bat pin is grounded, v cc1 is connected to the primary power supply, and v cc2 is connected to the secondary supply (the rechargeable energy source ). the ds1305 will operate from the larger of v cc1 or v cc2 . when v cc1 is greater than v cc2 + 0.2v (typical), v cc1 will power the ds1305. when v cc1 is less than v cc2 , v cc2 will power the ds1305. the ds1305 does not write protect itself in this configuration. configuration 3 shows the ds1305 in battery operate mode where the device is powered only by a single battery. in this case, the v cc1 and v bat pins are grounded and the battery is connected to the v cc2 pin. only these three configurations are allo wed. unused supply pins must be grounded. a typical operating circuit is shown on page 11.
ds1305 10 of 22 power supply configurations for the ds1305 figure 4 configuration 1: backup supply is a nonrechargeable lithium battery configuration 2: backup supply is a rech argeable battery or super capacitor configuration 3: battery operate mode v cctp
ds1305 11 of 22 serial interface the ds1305 offers the flexibility to choose betw een two serial interfa ce modes. the ds1305 can communicate with the spi interface or with a standard 3-wire interface. the interface method used is determined by the sermode pin. when this pin is connected to v cc , spi communication is selected. when this pin is connected to ground, stan dard 3-wire communication is selected. serial peripheral interface (spi) the serial peripheral interface (spi) is a synchronous bus for address and data tr ansfer, and is used when interfacing with the spi bus on specific motorola microcontrollers such as the 68hc05c4 and the 68hc11a8. the spi mode of serial communication is selected by tying the sermode pin to v cc . four pins are used for the spi. the four pins are the sdo (serial data out), sdi (serial data in), ce (chip enable), and sclk (serial clock). the ds1305 is th e slave device in an spi application, with the microcontroller being the master. the sdi and sdo pins are the seri al data input and output pins for the ds1305, respectively. the ce input is used to initiate and ter minate a data transfer. the sclk pin is used to synchronize data movement between the mast er (microcontroller) and the slave (ds1305) devices. the shift clock (sclk), which is generated by the mic rocontroller, is active only during address and data transfer to any device on the spi bus. the inactive clock polarity is programmable in some microcontrollers. the ds1305 deter mines the clock polarity by sampling sclk when ce becomes active. therefore, either sclk polarity can be acco mmodated. input data (sdi) is latched on the internal strobe edge and output data (sdo) is shifted out on the shift edge (see figure 5). there is one clock for each bit transferred. address and data b its are transferred in groups of eight. typical operating circuit
ds1305 12 of 22 serial clock as a function of microcontroller clock polarity (cpol) figure 5 cpha bit polarity (if applicable) may need to be set accordingly. cpol is a bit that is set in the microcontroller?s control register. sdo remains at high z until 8 bits of data are ready to be shifted out during a read. address and data bytes address and data bytes are shifted ms b first into the serial data input (sdi) and out of the serial data output (sdo). any transfer requires the address of the byte to specify a write or read to either a rtc or ram location, followed by one or mo re bytes of data. data is transferred out of the sdo for a read operation and into the sdi for a wr ite operation (see figure 6 and 7). spi single-byte write figure 6 spi single-byte read figure 7 *sclk can be either polarity. ce cpol = 1 sclk data latch (write) shift data out (read) cpol = 0 sclk data latch (write) shift data out (read)
ds1305 13 of 22 the address byte is always the first byte entered after ce is driven high. the most significant bit (a7) of this byte determines if a read or write will take place. if a7 is 0, one or more read cycles will occur. if a7 is 1, one or more write cycles will occur. data transfers can occur 1 byte at a time or in multiple-byte burst mode. after ce is driven high an address is written to the ds1305. after the address, one or more data by tes can be written or read. for a single-byte transfer 1 byte is read or written and then ce is driven low. for a multiple-byte transfer, however, multiple bytes can be read or written to the ds1305 after the address has been written. each read or write cycle causes the rtc register or ram address to automatically increment. incrementing continues until the device is disabled. when the rtc is selected, the address wraps to 00h after incrementing to 1fh (during a read) and wraps to 80h after incrementing to 9fh (during a write). when the ram is selected, the address wraps to 20h afte r incrementing to 7fh (during a read) and wraps to a0h after incrementing to ffh (during a write). spi multiple-byte burst transfer figure 8 3-wire interface the 3-wire interface mode operates similarly to the spi mode. however, in 3-wire mode there is one i/o instead of separate data in and data out signals. the 3-wire interface consists of the i/o (sdi and sdo pins tied together), ce, and sclk pins. in 3-wire m ode, each byte is shifted in lsb first unlike spi mode where each byte is shifted in msb first. as is the case with the spi mode, an address byte is written to the device followed by a single data byte or multiple data bytes. fi gure 9 illustrates a read and write cycle. in 3-wire mode, data is input on the rising edge of sclk and output on the falling edge of sclk.
ds1305 14 of 22 3-wire single-byte transfer figure 9 single byte read single byte write in burst mode, rst is kept high and additional sclk cycles are sent until the end of the burst. *i/o is sdi and sdo tied together. rst sclk rst sclk r/ wa0a1a2 a3a4r/c1 i/o* d0 d1 d2 d3 d4 d5 d6 d7 i/o* r/ wa0a1a2 a3a4r/c1
ds1305 15 of 22 absolute maximum ratings* voltage on any pin relativ e to ground -0.5v to +7.0v storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and f unctional operation of the device at th ese or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. range temperature v cc commercial 0c to +70c 2.0v to 5.5v v cc1 or v cc2 industrial -40c to +85c 2.0v to 5.5v v cc1 or v cc2 recommended dc operating conditions over the operating range* parameter symbol min typ max units notes supply voltage v cc1 , v cc2 v cc1 , v cc2 2.0 5.5 v 7 logic 1 input v ih 2.0 v cc + 0.3 v v cc = 2.0v -0.3 +0.3 logic 0 input v il v cc = 5v -0.3 +0.8 v v bat battery voltage v bat 2.0 5.5 v v ccif supply voltage v ccif 2.0 5.5 v 11 * unless otherwise specified.
ds1305 16 of 22 dc electrical characteristics over the operating range* parameter symbol min typ max units notes input leakage i li -100 +500 a output leakage i lo -1 1 a v cc = 2.0v 0.4 logic 0 output i ol = 1.5ma i ol = 4.0ma v ol v cc = 5v 0.4 v v ccif = 2.0v 1.6 logic 1 output i oh = -0.4ma i oh = -1.0ma v oh v ccif = 5v 2.4 v v cc1 = 2.0v 0.425 v cc1 active supply current i cc1a v cc1 = 5v 1.28 ma 2,8 v cc1 = 2.0v 25.3 v cc1 timekeeping current (osc on) i cc1t v cc1 = 5v 81 a 1,8 v cc1 = 2.0v 25 v cc1 standby current (osc off) i cc1s v cc1 = 5v 80 a 6,8 v cc2 = 2.0v 0.4 v cc2 active supply current i cc2a v cc2 = 5v 1.2 ma 2,9 v cc2 = 2.0v 0.3 v cc2 timekeeping current (osc on) i cc2t v cc2 = 5v 1 a 1,9 v cc2 = 2.0v 200 v cc2 standby current (osc off) i cc2s v cc2 = 5v 200 a 6,9 battery timekeeping current i bat v bat = 3v 400 na 10 battery standby current i bats v bat = 3v 200 na 10 v cc trip point v cctp v bat - 50 v bat + 200 mv trickle charge resistors r1 r2 r3 2 4 8 k k k trickle charge diode voltage drop v td 0.7 v *unless otherwise specified. capacitance (t a = 25 c) parameter symbol condition typ max units notes input capacitance c i 10 pf output capacitance c o 15 pf crystal capacitance c x 6pf
ds1305 17 of 22 3-wire ac electrical characteristics over the operating range* parameter symbol min typ max units notes v cc = 2.0v 200 data to clk setup t dc v cc = 5v 50 ns 3,4 v cc = 2.0v 280 clk to data hold t cdh v cc = 5v 70 ns 3,4 v cc = 2.0v 800 clk to data delay t cdd v cc = 5v 200 ns 3,4,5 v cc = 2.0v 1000 clk low time t cl v cc = 5v 250 ns 4 v cc = 2.0v 1000 clk high time t ch v cc = 5v 250 ns 4 v cc = 2.0v 0.6 clk frequency t clk v cc = 5v dc 2.0 mhz 4 v cc = 2.0v 2000 clk rise and fall t r, t f v cc = 5v 500 ns v cc = 2.0v 4 ce to clk setup t cc v cc = 5v 1 s4 v cc = 2.0v 240 clk to ce hold t cch v cc = 5v 60 ns 4 v cc = 2.0v 4 ce inactive time t cwh v cc = 5v 1 s4 v cc = 2.0v 280 ce to output high z t cdz v cc = 5v 70 ns 3,4 v cc = 2.0v 280 sclk to output high z t ccz v cc = 5v 70 ns 3,4 *unless otherwise specified. timing diagram: 3-wire read data transfer figure 10
ds1305 18 of 22 timing diagram: 3-wire write data transfer figure 11 spi ac electrical characteristics over the operating range* parameter symbol min typ max units notes v cc = 2.0v 200 data to clk setup t dc v cc = 5v 50 ns 5,6 v cc = 2.0v 280 clk to data hold t cdh v cc = 5v 70 ns 5,6 v cc = 2.0v 800 clk to data delay t cdd v cc = 5v 200 ns 5,6,7 v cc = 2.0v 1000 clk low time t cl v cc = 5v 250 ns 6 v cc = 2.0v 1000 clk high time t ch v cc = 5v 250 ns 6 v cc = 2.0v 0.6 clk frequency t clk v cc = 5v dc 2.0 mhz 6 v cc = 2.0v 2000 clk rise and fall t r, t f v cc = 5v 500 ns v cc = 2.0v 4 ce to clk setup t cc v cc = 5v 1 s6 v cc = 2.0v 240 clk to ce hold t cch v cc = 5v 60 ns 6 v cc = 2.0v 4 ce inactive time t cwh v cc = 5v 1 s6 v cc = 2.0v 280 ce to output high z t cdz v cc = 5v 70 ns 5,6 *unless otherwise specified.
ds1305 19 of 22 timing diagram: spi read data transfer figure 12 timing diagram: spi write data transfer figure 13
ds1305 20 of 22 notes: 1. i cc1t and i cc2t are specified with ce set to a logic 0 and eosc bit = 0 (oscillator enabled). 2. i cc1a and i cc2a are specified with ce=v cc , sclk=2mhz at v cc = 5v; sclk = 500khz at v cc = 2.0v, v il = 0v, v ih = v cc , and eosc bit = 0 (oscillator enabled). 3. measured at v ih = 2.0v or v il = 0.8v and 10ms maximu m rise and fall time. 4. measured with 50pf load. 5. measured at v oh = 2.4v or v ol = 0.4v. 6. i cc1s and i cc2s are specified with ce set to a logic 0. the eosc bit must be set to logic 1 (oscillator disabled). 7. v cc = v cc1 , when v cc1 > v cc2 + 0.2v (typical); v cc = v cc2 , when v cc2 > v cc1 . 8. v cc2 = 0v. 9. v cc1 = 0v. 10. v cc1 < v bat. 11. v ccif must be less than or equal to the largest of v cc1 , v cc2 , and v bat .
ds1305 21 of 22 ds1305 16-pin dip (300-mil) pkg 16-pin dim min max a in mm 0.740 18.80 0.780 19.81 b in mm 0.240 6.10 0.260 6.60 c in mm 0.120 3.05 0.140 3.56 d in mm 0.300 7.62 0.325 8.26 e in mm 0.015 0.38 0.040 1.02 f in mm 0.120 3.05 0.140 3.56 g in mm 0.090 2.29 0.110 2.79 h in mm 0.320 8.13 0.370 9.40 j in mm 0.008 0.20 0.012 0.30 k in mm 0.015 0.38 0.021 0.53
ds1305 22 of 22 ds1305 20-pin tssop dim min max a mm -1.10 a1 mm 0.05 - a2 mm 0.75 1.05 c mm 0.09 0.18 l mm 0.50 0.70 e1 mm 0.65 bsc b mm 0.18 0.30 d mm 6.40 6.90 e mm 4.40 nom g mm 0.25 ref h mm 6.25 6.55 phi 0 8

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