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8-channel, i 2 c, 12-bit sar adc with temperature sensor ad7291 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 12-bit sar adc 8 single-ended analog input channels analog input range: 0 v to 2.5 v 12-bit temperature-to-digital converter temperature sensor accuracy of 1c typical channel sequencer operation specified for v dd of 2.8 v to 3.6 v logic voltage v drive = 1.65 v to 3.6 v internal 2.5 v reference i 2 c-compatible serial interface supports standard and fast speed modes out of range indicator/alert function autocycle mode power-down current: 12 a maximum temperature range: ?40c to +125c 20-lead lfcsp package functional block diagram temp sensor 12-bit successive approximation adc input mux t/h v dd gnd pd/rst scl sda as1 as0 v drive v in7 v in0 control logic i 2 c interface sequencer v ref buf ref ad7291 08711-001 alert figure 1. general description the ad7291 is a 12-bit, low power, 8-channel, successive approximation analog-to-digital converter (adc) with an internal temperature sensor. the part operates from a single 3.3 v power supply and features an i 2 c-compatible interface. the part contains a 9-channel multiplexer and a track-and-hold amplifier than can handle frequencies up to 30 mhz. the device has an on-chip 2.5 v reference that can be disabled to allow the use of an external reference. the ad7291 provides a 2-wire serial interface compatible with i 2 c interfaces. the i 2 c interface supports standard and fast i 2 c interface modes. the ad7291 normally remains in a partial power-down state while not converting and powers up for conversions. the conversion process can be controlled by a command mode where conversions occur across i 2 c write operations or an autocycle mode selected through software control. the ad7291 includes a high accuracy band gap temperature sensor, which is monitored and digitized by the 12-bit adc to give a resolution of 0.25c. the ad7291 offers a programmable sequencer, which enables the selection of a preprogrammable sequence of channels for conversion. on-chip limit registers can be programmed with high and low limits for the conversion results; an out-of-range indicator output (alert) becomes active when the programmed high or low limits are violated by the conversion result. this output can be used as an interrupt. product highlights 1. ideally suited to monitoring system variables in a variety of systems including telecommunications, process control, and industrial control. 2. i 2 c-compatible serial interface, which supports standard and fast modes. 3. automatic partial power-down while not converting to maximize power efficiency. 4. channel sequencer operation. 5. integrated temperature sensor with 0.25c resolution. 6. out of range indicator that can be software disabled or enabled. table 1. ad7291 and related products device resolution interface features ad7291 12-bit i 2 c 8-channel, i 2 c, 12-bit sar adc with temperature sensor ad7298 12-bit spi 8-channel, 1 msps, 12-bit sar adc with temperature sensor
ad7291 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 i 2 c timing specifications ............................................................ 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 11 circuit information ........................................................................ 12 converter operation .................................................................. 12 analog input ............................................................................... 12 adc transfer function ............................................................. 13 temperature sensor operation ................................................ 13 temperature sensor averaging ................................................. 13 v drive ............................................................................................ 14 the internal or external reference .......................................... 14 reset ............................................................................................. 14 internal register structure ............................................................ 15 address pointer register ........................................................... 15 command register (0x00) ........................................................ 17 voltage conversion result register (0x01) ............................ 18 t sense conversion result register (0x02) ................................ 18 t sense average result register (0x03) ...................................... 19 limit registers (0x04 to 0x1e) ................................................. 19 hysteresis register ..................................................................... 20 alert status register a and alert status register b (0x1f and 0x20) ............................................................................................. 20 i 2 c interface .................................................................................... 21 serial bus address byte ............................................................. 21 general i 2 c timing .................................................................... 21 writing to the ad7291 .................................................................. 22 writing two bytes of data to a 16-bit register ..................... 22 writing to multiple registers .................................................... 22 reading data from the ad7291 .................................................. 23 reading two bytes of data from a 16-bit register ............... 23 modes of operation ....................................................................... 24 command mode ........................................................................ 24 autocycle mode .......................................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 1/11revision 0: initial version
ad7291 rev. 0 | page 3 of 28 specifications v dd = 2.8 v to 3.6 v; v drive = 1.65 v to 3.6 v; f scl = 400 khz, fast sclk mode; v ref = 2.5 v internal/external; t a = ?40c to +125c, unless otherwise noted. table 2. parameter min typ max unit 1 f 1 test conditions/comments dynamic performance f in = 1 khz sine wave signal-to-noise ratio (snr) 2 70 71 db signal-to-noise (+ distortion) ratio (sinad) 2 70 71 db total harmonic distortion (thd) 2 ?84 ?78 db spurious-free dynamic range (sfdr) ?85 ?80 db intermodulation distortion (imd) f a = 5.4 khz, f b = 4.6 khz second-order terms ?88 db third-order terms ?88 db channel-to-channel isolation ?100 db f in = 10 khz full power bandwidth 3 30 mhz at 3 db 10 mhz at 0.1 db dc accuracy resolution 12 bits integral nonlinearity (inl) 2 0.5 1 lsb differential nonlinearity (dnl) 2 0.5 0.99 lsb guaranteed no missed codes to 12 bits offset error 2 2 4.5 lsb offset error matching 2 2.5 4.5 lsb offset temperature drift 4 ppm/c gain error 2 1 4 lsb gain error matching 2 1 2.5 lsb gain temperature drift 0.5 ppm/c analog input input voltage ranges 0 v ref v dc leakage current 0.01 1 a input capacitance 3 34 pf when in track 8 pf when in hold reference input/output reference output voltage 4 2.4925 2.5 2.5075 v 0.3% maximum at 25c long-term stability 150 ppm for 1000 hours output voltage hysteresis 50 ppm reference input voltage range 5 1 2.5 v dc leakage current 0.01 1 a external reference applied to pin v ref v ref output impedance 1 reference temperature coefficient 12 35 ppm/c v ref noise 3 60 v rms bandwidth = 10 mhz logic inputs (sda, scl) input high voltage, v inh 0.7 v drive v input low voltage, v inl 0.3 v drive v input current, i in 0.01 1 a v in = 0 v or v drive input capacitance, c in 3 6 pf input hysteresis, v hyst 0.1 v drive v
ad7291 rev. 0 | page 4 of 28 parameter min typ max unit 1 test conditions/comments logic outputs output high voltage, v oh v drive ? 0.3 v v drive < 1.8 v drive ? 0.2 v v drive 1.8 output low voltage, v ol 0.4 v i sink = 3 ma 0.6 v i sink = 6 ma floating state leakage current 0.01 1 a floating state output capacitance 3 8 pf temperature sensorinternal operating range ?40 +125 c accuracy 1 3 c resolution 0.25 c lsb size conversion rate conversion time 3.2 s autocycle update rate 6 50 s throughput rate 22.22 ksps f scl = 400 khz power requirements digital inputs = 0 v or v drive v dd 2.8 3 3.6 v v drive 1.65 3 3.6 v i total 7 , 8 normal mode (operational) 2.9 3.5 ma normal mode (static) 2.9 3.3 ma full power-down mode 0.3 1.6 a t a = ?40c to +25c 1.6 4.5 a t a = >25c to 85c 4.9 12 a t a = >85c to 125c power dissipation 8 normal mode (operational) 8.7 10.5 mw v dd = 3 v, v drive = 3 v 10.4 12.6 mw normal mode (static) 10.4 11.9 mw full power-down mode 1.1 5.8 w t a = ?40c to +25c 5.8 16.2 w t a = >25c to 85c 17.6 43.2 w t a = >85c to 125c 1 all specifications expressed in decibels are referred to full-scale input, fsr, and tested with an input signal at 0.5 db belo w full scale, unless otherwise specified. 2 see the terminology section. 3 sample tested during initial release to ensure compliance. 4 refers to pin v ref specified for 25 o c. 5 a correction factor may be required on the temperature sensor results when using an external v ref (see the temperature sensor averaging section). 6 sampled during initial releas e to ensure compliance; not subject to production testing. 7 i total is the total current flowing in v dd and v drive . 8 i total and power dissipation are specified with v dd = v drive = 3.6 v, unless otherwise noted.
ad7291 rev. 0 | page 5 of 28 i 2 c timing specifications guaranteed by initial characterization. all values were measured with the input filtering enabled. c b refers to the capacitive load on the bus line, with t r and t f measured between 0.3 v drive and 0.7 v drive (see figure 2 ). v dd = 2.8 v to 3.6 v; v drive = 1.65 v to 3.6 v; v ref = 2.5 v internal/external; t a = ?40c to +125c, unless otherwise noted. table 3. limit at t min , t max parameter conditions min typ max unit description f scl standard mode 100 khz serial clock frequency fast mode 400 khz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns t 4 1 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s t 5 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s t 6 standard mode 4 s t hd;sta , hold time for a repeated start condition fast mode 0.6 s t 7 standard mode 4.7 s t buf , bus-free time between a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s t 9 standard mode 1000 ns t rda , rise time of the sda signal fast mode 20 + 0.1 c b 300 ns t 10 standard mode 300 ns t fda , fall time of the sda signal fast mode 20 + 0.1 c b 300 ns t 11 standard mode 1000 ns t rcl , rise time of the scl signal fast mode 20 + 0.1 c b 300 ns t 11a standard mode 1000 ns t rcl1 , rise time of the scl signal after a repeated fast mode 20 + 0.1 c b 300 ns start condition and after an acknowledge bit t 12 standard mode 300 ns t fcl , fall time of the scl signal fast mode 20 + 0.1 c b 300 ns t sp fast mode 0 50 ns pulse width of the suppressed spike t power-up 6 ms power-up and acquisition time 1 a device must provide a data hold time for sda to bridge the undefined region of the scl falling edge. t 6 t 7 t 2 t 11 t 4 t 1 t 12 t 10 t 5 t 9 t 6 t 3 t 8 0 8711-002 scl s sda s = start condition p = stop condition p p s figure 2. 2-wire serial interface timing diagram
ad7291 rev. 0 | page 6 of 28 absolute maximum ratings table 4. parameter rating v dd to gnd1, gnd ?0.3 v to +5 v v drive to gnd1, gnd ? 0.3 v to +5 v analog input voltage to gnd1 ? 0.3 v to +3 v digital input voltage to gnd1 ?0.3 v to v drive + 0.3 v digital output voltage to gnd1 ? 0.3 v to v drive + 0.3 v v ref to gnd1 ?0.3 v to +3 v gnd to gnd1 ?0.3 v to +0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c pb-free temperature, soldering reflow 260(+0)c esd 2 kv 1 transient currents of up to 100 ma do not cause latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 5. thermal resistance package type ja jc unit 20-lead lfcsp 52 6.5 c/w esd caution
ad7291 rev. 0 | page 7 of 28 pin configuration and fu nction descriptions 14 13 12 1 3 4 sda 15 scl as1 alert 11 as0 v in3 v in5 2 v in4 v in6 5 v in7 7 v r e f 6 g n d 1 8 d c a p 9 g n d 1 0 v d d 1 9 v i n 1 2 0 v i n 2 1 8 v i n 0 1 7 p d / r s t 1 6 v d r i v e ad7291 top view (not to scale) 08711-003 notes 1. the exposed metal paddle on the bottom of the lfcsp package should be soldered to pcb ground for proper heat dissipation and performance. figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 to 5, 18 to 20 v in3 , v in4 , v in5 , v in6 , v in7 , v in0 , v in1 , v in2 analog inputs. the ad7291 has eight single-ended analog in puts that are multiplexed into the on-chip track-and- hold amplifier. each input channel can accept analog inp uts from 0 v to 2.5 v. any unused input channels should be connected to gnd1 to avoid noise pickup. 6 gnd1 ground. ground reference point for the internal reference circuitry on the ad7291. all analog input signals and the external reference signals should be referred to this gnd1 voltage. the gnd1 pin should be connected to the ground plane of a system. all ground pins should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. the v ref pin should be decoupled to this ground pin via a 10 f decoupling capacitor. 7 v ref internal reference/external reference supply. the nominal internal reference voltage of 2.5 v appears at this pin. provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a system. decoupling capacitors should be connected to this pin to decouple the reference buffer. for best performance, it is recommended to use a 10 f decoupling capacitor on this pin to gnd1. the internal reference can be disabled and an external reference supplied to this pin if required. the input voltage range for the external reference is 2.0 v to 2.5 v. 8 d cap decoupling capacitor pin. decoupling capacitors (1 f recommended) are connected to this pin to decouple the internal ldo. 9 gnd ground. ground reference point for all analog and digita l circuitry on the ad7291. the gnd pin should be con- nected to the ground plane of the syst em. all ground pins should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. both d cap and v dd pins should be decoupled to this gnd pin. 10 v dd supply voltage, 2.8 v to 3.6 v. this supply should be deco upled to gnd with 10 f and 100 nf decoupling capacitors. 11, 13 as0, as1 logic input. together, the logic state of these two inputs selects a unique i 2 c address for the ad7291. see table 31 for details. the device address depends on the voltage applied to these pins. 12 alert digital output. this pin acts as an out-of-range indicato r and, if enabled, becomes active when the conversion result violates the data high or data low register values. see the limit registers (0x04 to 0x1e) section. 14 sda digital input/output. serial bus bidirectional data. this open- drain output requires a pull-up resistor. the output coding is straight binary for the voltage channels and twos complement for the temperature sensor result. 15 scl digital input. serial i 2 c bus clock. this input requires a pull-up resistor. the data transfer rate in i 2 c mode is compatible with both 100 khz and 400 khz operating modes. 16 v drive logic power supply input. the voltage supplied at this pin determines the voltage at which the interface operates. this pin should be decoupled to gnd. the voltage range on this pin is 1.65 v to 3.6 v and may be less than the voltage at v dd but should never exceed it by more than 0.3 v. 17 pd / rst power-down pin. this pin places the part into a full power-down mode and enables power conservation when operation is not required. this pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a maximum of 100 ns. if the maximum time is exceeded, the part enters power-down mode. when placing the device in full power-down mode, the analog inputs must be returned to 0 v. epad epad exposed paddle. the exposed metal paddle on the bottom of the lfcsp package should be soldered to pcb ground for proper functionality and heat dissipation.
ad7291 rev. 0 | page 8 of 28 typical performance characteristics 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 0.5 1.0 1.5 2.0 2.5 3.0 inl (lsb) v ref (v) 08711-012 inl (positive) inl (negative) t a = 25c v drive = 3v v dd = 3v f s = 22.22ksps f scl = 400khz 0 ?20 ?40 ?60 ?80 ?100 ?120 02k v dd = v drive = 3v f s = 22.22ksps f scl = 400khz f in = 10khz snr = 71.209 thd = ?81.66 4k 6k 8k 10k amplitude (db) frequency (hz) 08711-009 figure 4. typical fft figure 7. inl vs. external v ref 1.0 0.8 0.6 0.4 0.2 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 500 1000 1500 2000 2500 3000 3500 4096 inl (lsb) adc code 08711-010 t a = 25c v drive = 3v v ref = 2.5v v dd = 3v f s = 22.22ksps f scl = 400khz 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 0.5 1.0 1.5 2.0 2.5 3.0 dnl (lsb) v ref (v) 08711-013 dnl (positive) dnl (negative) t a = 25c v drive = 3v v dd = 3v f s = 22.22ksps f scl = 400khz figure 5. typical adc inl figure 8. dnl vs. external v ref 1.0 0.8 0.6 0.4 0.2 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 500 1000 1500 2000 2500 3000 3500 4096 dnl (lsb) adc code 08711-011 t a = 25c v drive = 3v v ref = 2.5v v dd = 3v f s = 22.22ksps f scl = 400khz 11.7 11.6 11.5 11.4 11.3 11.2 0 0.5 1.0 1.5 2.0 2.5 effective number of bits external reference (v) 08711-035 figure 6. typical adc dnl figure 9. effective number of bits vs. v ref , f scl = 400 khz
ad7291 rev. 0 | page 9 of 28 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 current load (ma) v ref (v) v dd = v drive = 3v 08711-021 figure 10. v ref vs. reference output drive 20 25 30 35 40 45 50 55 0 20406080100 tempe r a ture reading (c) time (seconds) 08711-014 figure 11. response to thermal shock from room temperature into 50c stirred oil ?110 ?108 ?106 ?104 ?102 ?100 ?98 ?96 ?94 ?92 ? 90 1k 10k 100k 1m 10m 100m psrr (db) ripple frequency (hz) v dd = 3v v drive = 3v 08711-061 figure 12. psrr vs. supply ripple frequency without supply decoupling 125 120 115 110 105 100 95 90 85 80 75 1 10 100 1k f noise (khz) channel-to-channel isolation (db) 08711-018 v dd = v drive = 3v f scl = 400khz figure 13. channel-to-channel isolation, f in = 10 khz 72 71 70 69 02 2.0 1.5 1.0 0.5 sinad (db) external reference (v) 08711-036 . 5 v drive = 3v v dd = 3v figure 14. sinad vs. reference voltage, f scl = 400 khz, f s = 22.22 ksps ?2.0 ?1.0 ?1.5 ?0.5 0 0.5 1.0 1.5 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) temperature error (c) 08711-017 figure 15. temperature accuracy at 3 v
ad7291 rev. 0 | page 10 of 28 2.5 2.0 1.5 1.0 0.5 0 2.7 2.9 3.1 3.3 3.5 2.8 3.0 3.2 3.4 3.6 total current (a) v dd 08711-037 ?40c +25c +85c +125c v drive = 3v 9.0 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8.0 0 60 120 180 240 300 360 420 scl frequency (khz) power (mw) 08711-062 v drive = 3v v dd = 3v figure 16. power vs. throug hput in normal mode figure 17. full shutdown curren t vs. supply voltage for various temperatures
ad7291 rev. 0 | page 11 of 28 terminology signal-to-noise and distortion ratio (sinad) the measured ratio of signal-to-noise and distortion at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal-to-noise and distortion ratio for an ideal n-bit converter with a sine wave input is given by signal - to -( noise + distortion ) = (6.02 n + 1.76) db thus, the sinad is 74 db for an ideal 12-bit converter. total harmonic distortion (thd) the ratio of the rms sum of harmonics to the fundamental. for the ad7291, it is defined as 1 2 6 2 5 2 4 2 3 2 2 log20)db( v vvvvv thd ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. typically, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m no r n equals zero. for example, second-order terms include (fa + fb) and (fa ? fb), while third- order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7291 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of in termodulation distortion is, like the thd specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in db. aperture delay the measured interval between the sampling clocks leading edge and the point at which the adc takes the sample. aperture jitter this is the sample-to-sample variation in the effective point in time at which the sample is taken. full-power bandwidth the input frequency at which the amplitude of the recon- structed fundamental is reduced by 0.1 db or 3 db for a full-scale input. power supply rejection ratio (psrr) psrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency, f s . the frequency of the input varies from 5 khz to 25 mhz. psrr (db) = 10 log( pf / pf s ) where: pf is the power at frequency, f, in the adc output. pf s is the power at frequency, f s , in the adc output. integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error the deviation of the first code transition (00000) to (00001) from the idealthat is, gnd1 + 1 lsb. offset error match the difference in offset error between any two channels. gain error the deviation of the last code transition (111110) to (111111) from the ideal (that is, v ref ? 1 lsb) after the offset error has been adjusted out. gain error match the difference in gain error between any two channels. track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1 lsb, after the end of conversion.
ad7291 rev. 0 | page 12 of 28 circuit information the ad7291 includes an 8-channel multiplexer, an on-chip track-and-hold amplifier, an analog-to-digital converter (adc), an on-chip oscillator, internal data registers, an internal tempera- ture sensor, and an i 2 c-compatible serial interface, all housed in a 20-lead lfcsp. this package offers considerable space-saving advantages over alternative solutions. the part can be operated from a single supply from 2.8 v to 3.6 v and offers 12 bits of resolution. the ad7291 has eight single-ended input channels and an on-chip 12 ppm reference. the analog input range for the ad7921 is 0 v to v ref . the ad7291 includes a high accuracy band gap temperature sensor, which is monitored and digitized by the 12-bit adc to give a resolution of 0.25c. the ad7291 typically remains in a partial power-down state while not converting. when supplies are first applied, the part powers up in a partial power-down state. power-up is initiated prior to a conversion, and the device returns to partial power- down mode when the conversion is complete. conversions can be initiated by using the autocycle mode or command mode where wake-up and a conversion occur during a write address function. when the conversion is complete, the ad7291 again enters partial power-down mode. in command mode at the beginning of a read, the ad7291 wakes up completely, that is, becomes fully functional and completes the conversion while the address is being read out. in autocylce mode, conversions occur at 50 s intervals; that is, the ad7291 exits partial power-down mode and powers up fully at 50 s intervals. this automatic partial power-down feature allows power saving between conversions. any read or write operation across the i 2 c interface can occur while the device is in partial power-down mode. converter operation the ad7291 is a 12-bit successive approximation adc based around a capacitive dac. figure 18 and figure 19 show simpli- fied schematics of the adc during the acquisition and conversion phase, respectively. the adc comprises control logic, sar, and a capacitive dac that are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. figure 18 shows the acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on the selected v in channel. control logic capacitive dac v in a b sw1 sw2 gnd1 comparator 08711-004 figure 18. adc acquisition phase when the adc starts a conversion (see figure 19 ), sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the control logic and the capacitive dac are used to add and subtract fixed amounts of charge to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 21 shows the transfer functions of the adc. control logic capacitive dace v in a b sw1 sw2 gnd1 comparator 08711-005 figure 19. adc conversion phase analog input figure 20 shows an equivalent circuit of the analog input struc- ture of the ad7291. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the internally generated ldo voltage of 2.5 v (d cap ) by more than 300 mv. this causes the diodes to become forward biased and start conducting current into the substrate. the maximum current these diodes can conduct without causing irreversible damage to the part is 10 ma. capacitor c1, in figure 20 , is typically about 8 pf and can primarily be attributed to pin capacitance. resistor r1 is a lumped component made up of the on resistance of a switch (track-and-hold switch) and the on resistance of the input multiplexer. the total resistance is typically about 155 . capacitor c2 is the adc sampling capacitor and has a capacitance of 34 pf typically. c1 8pf c2 34pf r1 d2 conversion phase: switch open track phase: switch closed d1 d cap (2.5 v ) v in 08711-006 figure 20. equivalent analog input circuit for ac applications, removing high frequency components from the analog input signal is recommended by using an rc low-pass filter on the relevant analog input pin. in applications where harmonic distortion and signal-to-noise ratios are critical, the analog input should be driven from a low imped- ance source. large source impedances significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application performance criteria.
ad7291 rev. 0 | page 13 of 28 adc transfer function the output coding of the ad7291 is straight binary for the analog input channel conversion results and twos complement for the temperature conversion result. the designed code tran- sitions occur at successive lsb values (that is, 1 lsb, 2 lsbs, and so forth). the lsb size is v ref /4096 for the ad7291. the ideal transfer characteristic for the ad7291 for straight binary coding is shown in figure 21 . 111...111 111...110 111...000 011...111 000...010 000...001 000...000 1lsb = v ref /4096 analog input notes 1. v ref is 2.5v. adc code +v ref ? 1lsb 1lsb 0v 08711-007 figure 21. straight binary transfer characteristic temperature sensor operation the ad7291 contains one local temperature sensor. the on-chip, band gap temperature sensor measures the temperature of the ad7291 die. the temperature sensor module on the ad7291 is based on the three current principle (see figure 22 ), where three currents are passed through a diode and the forward voltage drop is measured, allowing the temperature to be calculated free of errors caused by series resistance. i4 i internal sense transistor bias diode v dd 8 i i bias v out+ v out? to adc 08711-008 figure 22. top level structure of internal temperature sensor each input integrates, in turn, over a period of several hundred microseconds. this takes place continuously in the background, leaving the user free to perform conversions on the other channels. when integration is complete, a signal passes to the control logic to initiate a conversion automatically. if the adc is in command mode and performing a voltage conversion, the ad7291 waits for it to complete and then initiates a temperature sensor conversion. if the adc is not performing voltage conversions, temperature conversions occur at 5 ms intervals. in autocycle mode, the conversion is inserted into an appropriate place in the current sequence. if the adc is idle, the conversion takes place immediately. the t sense conversion result register stores the result of the last conversion on the temperature channel; this can be read at any time. theoretically, the temperature measuring circuit can measure temperatures from ?512c to +511c with a resolution of 0.25c. however, temperatures outside t a (the specified tem- perature range for the ad7291) are outside the guaranteed operating temperature range of the device. the temperature sensor is enabled by setting the tsense bit in the command register. temperature sensor averaging the ad7291 incorporates a temperature sensor averaging feature to enhance the accuracy of the temperature measure- ments. the temperature averaging feature is performed continuously in the background provided the tsense bit in the command register is enabled. the temperature is measured each time a t sense conversion is performed and a moving average method is used to determine the result in the t sense average result register. the average result is given by the following equation: () () result current result average previous avgt sense _ 8 1 __ 8 7 + = the average result is then available in the t sense average result register whose content is updated after every t sense conversion. the first t sense conversion result given by the ad7291 after the temperature sensor has been selected in the command register (bit d7) is the actual first t sense conversion result, and this result remains valid until the next t sense conversion is completed and the result register is updated.
ad7291 rev. 0 | page 14 of 28 temperature value format v drive one lsb of the adc corresponds to 0.25c. the temperature reading from the adc is stored in a 12-bit twos complement format, to accommodate both positive and negative tempera- ture measurements. sample temperature values are listed in table 7 . the temperature conversion formulas are as follows: v drive controls the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 1.8 v and 3 v processors. for example, if the ad7291 is operated with a v dd of 3.3 v, the v drive pin can be powered from a 1.8 v supply. this enables the ad7291 to operate with a larger dynamic range with a v dd of 3.3 v while still being able to interface to 1.8 v processors. take care to ensure that v drive does not exceed v dd by more than 0.3 v (see the absolute maximum ratings section). positive temperature = adc code /4 negative temperature = (4096 ? adc code )/4 the previous formulae are for a v ref of 2.5 v only. if an external reference is used, the temperature sensor requires an external reference of between 2 v and 2.5 v for correct operation. the temperature results (in celsius) are calculated using the following formula, where v ext_ref is the value of the external reference voltage. the internal or external reference the ad7291 can operate with either the internal 2.5 v on-chip reference or an externally applied reference. the ext_ref bit in the command register is used to determine whether the internal reference is used. if the ext_ref bit is selected in the command register, an external reference can be supplied through the v ref pin. on power-up, the internal reference is enabled. suitable external reference sources for the ad7291 include ad780, ad1582, adr431 , ref193 , and adr391 . 15.2733.109 10 _ ? ? ? ? ? ? ? + = adccode ve temperatur refext table 7. temperature data format temperature (c) digital output the internal reference circuitry consists of a 2.5 v band gap reference and a reference buffer. when the ad7291 operates in internal reference mode, the 2.5 v internal reference is available at the v ref pin, which should be decoupled to gnd1 using a 10 f capacitor. it is recommended that the internal reference be buffered before applying it elsewhere in the system. ?40 1111 0110 0000 ?25 1111 1001 1100 ?10 1111 1101 1000 ?0.25 1111 1111 1111 0 0000 0000 0000 +0.25 0000 0000 0001 +10 0000 0010 1000 the internal reference is capable of sourcing up to 2 ma of current when the converter is static. the reference buffer requires 5.5 ms to power up and charge the 10 f decoupling capacitor during the power-up time. +25 0000 0110 0100 +50 0000 1100 1000 +75 0001 0010 1100 +100 0001 1001 0000 reset +105 0001 1010 0100 the ad7291 includes a reset feature, which can be used to reset the device and the content of all internal registers including the command register to their default state. to activate the reset operation, the pd / rst pin should be brought low for a minimum of 1 ns and a maximum of 100 ns and be asynchronous to the clock; therefore, it can be triggered at any time. if the pd / rst pin is held low for greater than 100 ns, the part enters full power-down mode. it is imperative that the pd / rst pin be held at a stable logic level at all times to ensure normal operation. +125 0001 1111 0100
ad7291 rev. 0 | page 15 of 28 internal register structure the ad7291 contains 34 internal registers (see figure 23 ) that are used to store conversion results, high and low conversion limits, and information to configure and control the device. there are 33 data registers and one address pointer register. each data register has an address that the address pointer register points to when communicating with it. table 9 details which registers are read, write, or read/write. address pointer register the address pointer register is the register to which the first data byte of every write operation is written automatically; therefore, this register does not have and does not require an address. the address pointer register is an 8-bit register in which the six lsbs are used as pointer bits to store an address that points to one of the ad7291s data registers. the first byte following each write address is to the address pointer register, containing the address of one of the data registers. the six lsbs select the data register to which subsequent data bytes are written. only the six lsbs of this register are used to select a data register. during power-up, the address pointer register contains all 0s, pointing to the command register. table 8. address pointer register d1 d0 p5 p4 p3 p2 p1 p0 0 0 register select sda scl data command register t sense conv result register t sense avg result register ch0 data high register ch1 data low register ch0 hysteresis register ch1 data high register ch1 hysteresis register ch0 data low register ch7 data high register ch7 data low register ch7 hysteresis register t sense hysteresis register t sense data high register t sense data low register alert status register a alert status register b 08711-015 voltage conv result register serial bus interface address pointer register figure 23. ad7291 register structure
ad7291 rev. 0 | page 16 of 28 table 9. ad7291 register addresses hex code p5 p4 p3 p2 p1 p0 registers read/write 0x00 0 0 0 0 0 0 command register write. 0x01 0 0 0 0 0 1 voltage conversion result register read. 0x02 0 0 0 0 1 0 t sense conversion result register read. 0x03 0 0 0 0 1 1 t sense average result register read. 0x04 0 0 0 1 0 0 ch0 data high register read/write. 0x05 0 0 0 1 0 1 ch0 data low register read/write. 0x06 0 0 0 1 1 0 ch0 hysteresis register read/write. 0x07 0 0 0 1 1 1 ch1 data high register read/write. 0x08 0 0 1 0 0 0 ch1data low register read/write. 0x09 0 0 1 0 0 1 ch1 hysteresis register read/write. 0x0a 0 0 1 0 1 0 ch2 data high register read/write. 0x0b 0 0 1 0 1 1 ch2 data low register read/write. 0x0c 0 0 1 1 0 0 ch2 hysteresis register read/write. 0x0d 0 0 1 1 0 1 ch3 data low register read/write. 0x0e 0 0 1 1 1 0 ch3 data high register read/write. 0x0f 0 0 1 1 1 1 ch3 hysteresis register read/write. 0x10 0 1 0 0 0 0 ch4 data high register read/write. 0x11 0 1 0 0 0 1 ch4 data low register read/write. 0x12 0 1 0 0 1 0 ch4 hysteresis register read/write. 0x13 0 1 0 0 1 1 ch5 data high register read/write. 0x14 0 1 0 1 0 0 ch5 data low register read/write. 0x15 0 1 0 1 0 1 ch5 hysteresis register read/write. 0x16 0 1 0 1 1 0 ch6 data high register read/write. 0x17 0 1 0 1 1 1 ch6 data low register read/write. 0x18 0 1 1 0 0 0 ch6 hysteresis register read/write. 0x19 0 1 1 0 0 1 ch7 data high register read/write. 0x1a 0 1 1 0 1 0 ch7 data low register read/write. 0x1b 0 1 1 0 1 1 ch7 hysteresis register read/write. 0x1c 0 1 1 1 0 0 t sense data high register read/write. 0x1d 0 1 1 1 0 1 t sense data low register read/write. 0x1e 0 1 1 1 1 0 t sense hysteresis register read/write. 0x1f 0 1 1 1 1 1 alert status register a read. 0x20 1 0 0 0 0 0 alert status register b read. 0x3f 1 1 1 1 1 1 factory test mode the user should not access this register.
ad7291 rev. 0 | page 17 of 28 command register (0x00) the command register is a 16-bit write-only register that is us ed to set the operating modes of the ad7291. the bit functions a re outlined in table 10 . a two-byte write is necessary when writing to the command register. msb denotes the first bit in the data stream. during power-up, the default content of the command register is all 0s. table 10. command register bits and default settings at power-up msb lsb channel bit d15 to db8 d7 d6 d5 d4 d3 d2 d1 d0 function ch0 to ch7 tsense dont care noise-delayed bit trial and sampling ext_ref polarity of alert pin (active high/ active low) clear alert reset autocycle mode setting enable = 1 disable = 0 enable = 1 disable = 0 0 enable = 1 disable = 0 enable = 1 disable = 0 active low = 1 active high = 0 enable = 1 disable = 0 enable = 1 disable = 0 enable = 1 disable = 0 table 11. command register bit function descriptions bit mnemonic comment d15 to d8 ch0 to ch7 these 8-channel address bits select the analog input channel(s) to be converted. a 1 in any of bit d15 to bit d8 selects a channel for conversion. if more than one channel bit is set to 1, the ad7291 sequences through the selected channels, starting with the lowest channel. all unused channels should be set to 0. a channel or sequence of channels for conversion must be selected in the command register, prior to initiating a conversion. d7 tsense this bit enables temperature conversions, which occur in the background at 5 ms intervals. the results can be read from the t sense conversion result register (0x02) and the t sense average result register (0x03). for details, refer to the temperature sensor operation section. d6 dont care d5 noise- delayed bit trial and sampling when this function is enabled, it delays the critical sa mpling intervals and bit trials when there is activity on the i 2 c bus, thus ensuring improved dc performance of the ad7291. when this feature is enabled, the conversion time may vary. this bit is disabled on power- up, and it is recommended to write a 1 to enable this feature for normal operation. d4 ext_ref writing a logic 1 to this bit enables the use of an external reference. the input voltage range for the external reference is 2 v to 2.5 v. the external reference should not exceed 2.5 v or the device performance will be adversely affected. during power-up, the default co nfiguration has the internal reference enabled. d3 polarity of alert pin this bit determines the active polari ty of the alert pin. the alert pin is configured for active low operation if this bit is set to 1 and active high if this bit is set to 0. the default configuration on power-up is active high (0). d2 clear alert this bit clears the content of the alert status register. once the content of both alert status registers is cleared, this bit should be reprogrammed to a logic 0 to ensure that future alerts are detected. d1 reset setting this bit resets the contents of all internal re gisters in the ad7291 to their default states including the command register itself. this bit is automatically returned to 0 once the reset is completed to enable the internal registers to be reprogrammed. d0 autocycle mode writing a 1 to this bit enables the autocycle mode of ope ration. in this mode, the ch annels selected in bit d15 to bit d8 are continuously converted by the ad7291. this function is used in conjunction with the limit registers, which can be programmed to issue an alert if the conversion result exceeds the preset limit for any channel selected for conversion.
ad7291 rev. 0 | page 18 of 28 table 12. channel selection bits for command register d15 d14 d13 d12 d11 d10 d9 d8 selected analog input channel comments 0 0 0 0 0 0 0 0 no channel selected 0 0 0 0 0 0 0 1 convert on channel 7 (v in7 ) 0 0 0 0 0 0 1 0 convert on channel 6 (v in6 ) 0 0 0 0 0 1 0 0 convert on channel 5 (v in5 ) 0 0 0 0 1 0 0 0 convert on channel 4 (v in4 ) 0 0 0 1 0 0 0 0 convert on channel 3 (v in3 ) 0 0 1 0 0 0 0 0 convert on channel 2 (v in2 ) 0 1 0 0 0 0 0 0 convert on channel 1 (v in1 ) 1 0 0 0 0 0 0 0 convert on channel 0 (v in0 ) if more than one channel is selected, the ad7291 converts the selected channels starting with the lowest channel in the sequence. table 13. t sense data format input d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) value (c) ?512 +256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25 sample delay and bit trial delay ideally, no i 2 c bus activity should occur while an adc conversion is taking place. however, this may not be possible, for example, when operating in autocycle mode. it is therefore recommended to enable the noise delayed bit trial and sampling function by writing a 1 to bit d5 in the command register. this mechanism delays critical sample intervals and bit trials while there is activity on the i 2 c bus. this results in a quiet period for each bit decision, and conversion results are less susceptible to interference from external noise. on power-up, the bit trial and sample interval delay mechanism is not enabled. it is recommended that this feature should be enabled for normal operation. when enabled, the ad7291 delays the bit trials, mitigating against the effect of activity on the i 2 c bus. in cases where there is excessive activity on the interface lines, enabling these bits may cause the overall conversion time to increase. the ad7291 also incorporates functionality that allows it to reject glitches shorter than 50 ns. this feature improves the noise susceptibility of the device. voltage conversion resu lt register (0x01) the voltage conversion result register is a 16-bit read-only register that stores the conversion result from the adc in straight binary format. a 2-byte read is necessary to read data from this register. table 14 and table 15 show the contents of the first and second bytes of data to be read from the ad7291. each ad7291 conversion result consists of four channel address bits (see table 1 4 and table 15 ) and the 12-bit data result. bit d15 to bit d12 are the channel address bits that identify the adc channel that corresponds to the subsequent result. bit d11 to bit d0 contain the most recent adc result. table 14. conversion value register (first read) msb d15 d14 d13 d12 d11 d10 d9 d8 add3 add2 add1 add0 b11 b10 b9 b8 table 15. conversion value register (second read) lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 table 16. channel address bits for the result register add2 add2 add1 add0 analog input channel 0 0 0 0 v in0 0 0 0 1 v in1 0 0 1 0 v in2 0 0 1 1 v in3 0 1 0 0 v in4 0 1 0 1 v in5 0 1 1 0 v in6 0 1 1 1 v in7 1 0 0 0 t sense 1 0 0 1 t sense average result temperature value format the temperature reading from the adc is stored in an 11-bit twos complement format, d11 to d0, to accommodate both positive and negative temperature measurements. the tem- perature data format is provided in table 13 . t sense conversion result register (0x02) the t sense result register is a 16-bit read-only register used to store the adc data generated from the internal temperature sensor. this register stores the temperature readings from the adc in a 12-bit twos complement format, d11 to d0, and uses bit d15 to bit d12 to store the channel address bits. conversions take place approximately every 5 ms. table 13 details the temperature data format that applies to the internal temperature sensor.
ad7291 rev. 0 | page 19 of 28 table 17. t sense conversion result register (first read) msb d15 d14 d13 d12 d11 d10 d9 d8 add3 add2 add1 add0 b11 b10 b9 b8 table 18. t sense result register (second read) l sb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 t sense average result register (0x03) the t sense average result register is a 16-bit read-only register used to store the average result from the internal temperature sensor. this register stores the average temperature readings from the adc in an 11-bit twos complement format, d11 to d0, and uses bit d15 to bit d12 to store the channel address bits. the t sense average result register is updated after every t sense conversion is completed. the first t sense average conversion result given by the ad7291 after averaging is enabled is the actual first t sense conversion result. table 13 details the temperature data format, which applies to the internal temperature sensor. see the temperature sensor averaging section for more details. table 19. t sense average result register (first read) msb d15 d14 d13 d12 d11 d10 d9 d8 add3 add2 add1 add0 b11 b10 b9 b8 table 20. t sense average result register (second read) l sb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 limit registers (0x04 to 0x1e) the ad7291 has nine pairs of limit registers. each pair stores high and low conversion limits for each analog input channel and the internal temperature sensor. each pair of limit registers has one associated hysteresis register. all 27 registers are 16 bits wide; only the 12 lsbs of the registers are used for the ad7291. the four msbs, d15 and d12, in these registers should contain 0s. during power-up, the contents of the data high register for each analog voltage channel is full scale (0x0fff), while the default contents of the data low voltage channels registers is zero scale (0x0000). the output coding of the ad7291 is twos complement for the temperature conversion result. the default content for the t sense data high register is 0x07ff, while the default content of the t sense data low register is 0x0800. the ad7291 signals an alert in hardware if the conversion result moves outside the upper or lower limit set by the limit registers. data high register the data high registers for ch0 to ch7 and the internal temperature sensor are 16-bit read/write registers; only the 12 lsbs of each register are used. bit d15 to bit d12 are not used in the register and are set to 0s. this register stores the upper limit that activates the alert output. if the value in the conversion result register is greater than the value in the data high register, an alert occurs for that channel. when the conversion result returns to a value at least n lsbs below the data high register value, the alert output pin is reset. the value of n is taken from the hysteresis register associated with that channel. the alert pin can also be reset by writing to bit d2 in the command register. table 21. data high register (first read/write) msb d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 22. data high register (second read/write) lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 data low register the data low register for each channel is a 16-bit read/write register; only the 12 lsbs of each register are used. bit d15 to bit d12 are not used in the register and are set to 0s. the register stores the lower limit that activates the alert output. if the value in the t sense conversion result register is less than the value in the data low register, an alert occurs for that channel. when the conversion result returns to a value at least n lsbs above the data low register value, the alert output pin is reset. the value of n is taken from the hysteresis register associated with that channel. the alert output pin can also be reset by writing to bit d2 in the command register. table 23. data low register (first read/write) msb d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 24. data low register (second read/write) lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0
ad7291 rev. 0 | page 20 of 28 hysteresis register each analog input channel and the internal temperature sensor has its own hysteresis register, which is a 16-bit read/write register. only the 12 lsbs are used. bit d15 to bit d12 are not used in the register and are set to 0s. the hysteresis register stores the hysteresis value, n , when using the limit registers. each pair of limit registers has a dedicated hysteresis register. the hysteresis value determines the reset point for the alert pin if a violation of the limits occurs. for example, if a hysteresis value of eight lsbs is required on the upper and lower limits of channel 0, the 16-bit word, 0000 0000 0000 1000, should be written to the hysteresis register of ch0, the address of which is 0x06 (see table 25 and table 26). during power-up, the hysteresis registers content defaults to all zeros (0x0000). if a hysteresis value is required, that value must be written to the hysteresis register for the channel in question. table 25. hysteresis register (first read/write byte) msb d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 26. hysteresis register (second read/write byte) lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 alert status register a and alert status register b (0x1f and 0x20) the alert status registers are 16-bit, read-only registers that provide information on an alert event. if a conversion result activates the alert pin, as described in the limit registers (0x04 to 0x1e) section, the alert status register can be read to gain further information. there are two alert status registers in the ad7291; alert status register a, which stores alerts for the analog voltage conversion channels (see table 27 and table 28) and alert status register b, which stores alerts for the internal temperature sensor only (see table 29 and table 30). both alert status registers contain two status bits per channel, one corresponding to the data high limit and the other to the data low limit. the bit with a status of 1 shows where the violation occurredthat is, on which channeland whether the violation occurred on the upper or lower limit. if a second alert event occurs on the other channel between receiving the first alert and interrogating the alert status register, the corres- ponding bit for that alert event is also set. the entire contents of the alert status register can be cleared by writing 1 to bit d2 in the command register. for example, if bit d14 in alert status register a is set to 1, the lower limit on channel 7 (register 0x1a) has been violated, while if bit d11 is set 1, the upper limit on channel 5 has been violated (register 0x13). the tsense high and tsense_avg high alerts are determined by comparison with the t sense data high register (register 0x1c). likewise, the tsense low and tsense_avg low alerts are determined by comparison with the t sense data low register (register 0x1d). table 27. alert status register a (first read byte) d15 d14 d13 d12 d11 d10 d9 d8 ch7 high ch7 low ch6 high ch6 low ch5 high ch5 low ch4 high ch4 low table 28. alert status register a (second read byte) d7 d6 d5 d4 d3 d2 d1 d0 ch3 high ch3 low ch2 high ch2 low ch1 high ch1 low ch0 high ch0 low table 29. alert status register b (first read byte) d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 0 0 0 0 table 30. alert status regi ster b (second read byte) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 tsense_avg high tsense_avg low tsense high tsense low
ad7291 rev. 0 | page 21 of 28 i 2 c interface control of the ad7291 is carried out via the i 2 c compatible serial bus. the ad7291 is connected to this bus as a slave device under the control of a master device such as the processor. serial bus address byte the first byte the user writes to the device is the slave address byte. similar to all i 2 c-compatible devices, the ad7291 has a 7-bit serial address. the three msbs of this address are set to 010. the four lsbs are user-programmable by the three-state input pins, as0 and as1, as shown in table 31 . in table 31 , h means tie the pin to v drive , l means tie the pin to gnd, and nc refers to a pin left floating. note that in this final case, the stray capacitance on the pin must be less than 30 pf to allow correct detection of the floating state; therefore, any pcb trace must be kept as short as possible. table 31. slave address control using three-state input pins slave address (a6 to a0) as1 as0 binary hex h h 010 0000 0x20 h nc 010 0010 0x22 h l 010 0011 0x23 nc h 010 1000 0x28 nc nc 010 1010 0x2a nc l 010 1011 0x2b l h 010 1100 0x2c l nc 010 1110 0x2e l l 010 1111 0x2f general i 2 c timing figure 24 shows the timing diagram for general read and write operations using an i 2 c-compliant interface. when no device is driving the bus, both scl and sda are high. this is known as the idle state. when the bus is idle, the master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line (sda) while the serial clock line (scl) remains high. this indicates that a data stream follows. the master device is responsible for generating the clock. data is sent over the serial bus in groups of nine bitseight bits of data from the transmitter followed by an acknowledge bit (ack) from the receiver. data transitions on the sda line must occur during the low period of the clock signal and remain stable during the high period. the receiver should pull the sda line low during the acknowledge bit to signal that the preceding byte has been received correctly. if this is not the case, cancel the transaction. the first byte that the master sends must consist of a 7-bit slave address, followed by a data direction bit. each device on the bus has a unique slave address; therefore, the first byte sets up communication with a single slave device for the duration of the transaction. the transaction can be used either to write to a slave device (data direction bit = 0) or to read data from it (data direction bit = 1). in the case of a read transaction, it is often necessary first to write to the slave device (in a separate write transaction) to tell it from which register to read. reading and writing cannot be combined in one transaction. when the transaction is complete, the master can keep control of the bus, initiating a new transaction by generating another start bit (high-to-low transition on sda while scl is high). this is known as a repeated start (sr). alternatively, the bus can be relinquished by releasing the scl line followed by the sda line. this low-to-high transition on sda while scl is high is known as a stop bit (p), and it leaves the i 2 c bus in its idle state (no current is consumed by the bus). the example in figure 24 shows a simple write transaction with an ad7291 as the slave device. in this example, the ad7291 register pointer is being set up for a future read transaction. p7 p6 p5 p4 p3 p2 p1 p0 start cond by master ack. by ad7291 slave address byte ack. by ad7291 scl sd a register address stop by master user programmable 5 lsbs r/w a6 a5 a4 a3 a2 a1 a0 0 8711-040 figure 24. general i 2 c timing
ad7291 rev. 0 | page 22 of 28 writing to the ad7291 writing two bytes of data to a 16-bit register al l registers on the ad7921 are 16-bit registers; therefore, two bytes of data are required to write a value to any one of these registers. writing two bytes of data to a register consists of the following sequence (see figure 25 ): 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a register address. the slave asserts an acknowledge on sda. 5. the master sends the first data byte (most significant). 6. the slave asserts an acknowledge on sda. 7. the master sends the second data byte (least significant). 8. the slave asserts an acknowledge on sda. 9. the master asserts a stop condition on sda to end the transaction. writing to multiple registers wr iting to multiple address registers consists of the following steps (see figure 26 ): 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device (ad7291) asserts an acknowledge on sda. 4. the master sends a register address, for example, the ch1 data high register address. 5. the slave (ad7291) asserts an acknowledge on sda. 6. the master sends the first data byte. 7. the slave (ad7291) asserts an acknowledge on sda. 8. the master sends the second data byte. 9. t he slave (ad7291) asserts an acknowledge on sda. 10. the master sends a second register address, for example, the command register. 11. the slave (ad7291) asserts an acknowledge on sda. 12. the master sends the first data byte. 13. the slave (ad7291) asserts an acknowledge on sda. 14. the master sends the second data byte. 15. the slave (ad7291) asserts an acknowledge on sda. 16. the master asserts a stop condition on sda to end the transaction. the previous example details writing to two registers only (the ch1 data high register address and the command register). however, the ad7291 can read from multiple registers in one write operation as shown in figure 26 . 0 8711-059 s slave address 0 sa reg pointer sa data[15:8] sa p data[7:0] sa from master to slave from slave to master s = start condition sr = repeated start p = stop condition sa = slave acknowledge a = not acknowledge figure 25. writing two bytes of data to a 16-bit register 08711-019 s ... ... 0 sa sa slave address point to ch1 data high reg (0x04) p sa sa sa data[7:0] data[15:8] point to command reg (0x00) data[15:8] sa sa data[7:0] from master to slave from slave to master s = start condition sr = repeated start p = stop condition sa = slave acknowledge a = not acknowledge figure 26. writing to multiple registers
ad7291 rev. 0 | page 23 of 28 reading data from the ad7291 reading two bytes of data from a 16-bit register reading the contents from any of the 16-bit registers is a 2-byte read operation. in this protocol, the first part of the transaction writes to the register pointer. when the register address has been set up, any number of reads can be performed from that particular register without having to write to the address pointer register again. when the required number of reads is completed, the master should not acknowledge the final byte. this tells the slave to stop transmitting, allowing a stop condition to be asserted by the master. further reads from this register can be performed in a future transaction without having to rewrite to the register pointer. if a read from a different address is required, the relevant register address has to be written to the address pointer register and, again, any number of reads from this register can then be performed. in the following example, the master device reads three lots of 2-byte data from a slave device but as many lots consisting of two bytes can be read as required. this protocol assumes that the particular register address has been set up by a single-byte write operation to the address pointer register. re ading two bytes of data from a 16-bit register consists of the following sequence (see figure 27 ): 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts an acknowledge on sda. 4. the master receives a data byte. 5. the master asserts an acknowledge on sda. 6. the master receives a second data byte. 7. the master asserts an acknowledge on sda. 8. the master receives a data byte. 9. t he master asserts an acknowledge on sda. 10. the master receives a second data byte. 11. the master asserts an acknowledge on sda. 12. the master receives a data byte. 13. the master asserts an acknowledge on sda. 14. the master receives a second data byte. 15. the master asserts a not acknowledge on sda to notify the slave that the data transfer is complete. 16. the master asserts a stop condition on sda to end the transaction. 08711-060 s a p ... ... 1 a a a a a a slave address data[7:0] data[7:0] data[7:0] data[15:8] data[15:8] data[15:8] from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = not acknowledge figure 27. reading three lots of two bytes of data from the conversion result register
ad7291 rev. 0 | page 24 of 28 modes of operation when supplies are first applied to the ad7291, the adc powers up in partial power-down mode and normally remains in this partial power-down state while not converting. once the master addresses the ad7291, it exits partial power-down. there are two methods of initiating a conversion on the ad7291: command mode and autocycle mode. command mode in command mode, the ad7291 converts on demand on either a single channel or a sequence of channels. writing in the command register puts the part into command mode. this is the default mode of operation and allows a conversion to be automatically selected any time a write operation occurs to the command register. to enter this mode, the required combina- tion of channels is written into the command register (register 0x00). following the write operation, the ad7291 must be addressed again to indicate that a read operation is required. the read then takes place from the voltage or temperature conversion result register. for the first conversion to occur, the address pointer written to the ad7291 must point to the voltage conversion result register or t sense conversion result register. the conversion is completed while the first four channel address bits are read. the next conversion in the sequence takes place once the next read from the result register is initiated. when operating the device in fast mode, the acquisition and conversion times combined take approximately 4.45 s (1.25 s acquisition time plus 3.2 s conversion time). when in command mode, the part cycles through the selected channels from the lowest selected channel in the sequence to the next lowest until all the channels in the sequence are converted. to exit the command mode, the master should not acknowledge the final byte of data. this stops the ad7291 transmitting, allowing the master to assert a stop condition on the bus. on the receipt of a stop condition, the ad7291 stops converting and enters partial power-down mode, but the content of the command register is preserved. once the part is readdressed and a read is initiated from the voltage conversion register, the ad7291 begins converting on the previously selected sequence of channels. the conversion sequence starts converting the first selected channel in the sequence; that is, if channel 1, channel 2, and channel 3 are selected and a stop condition occurs after the channel 1 result is read, on resumption of conversions, channel 1 is reconverted and the conversion sequence continues.
ad7291 rev. 0 | page 25 of 28 th e example in figure 28 shows the command mode convert- ing on a sequence of channels including v in0 , v in1 , and v in2 . 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device (ad7291) asserts an acknowledge on sda. 4. the master sends the command register address (0x00). 5. the slave asserts an acknowledge on sda. 6. the master sends the first data byte (0xe0) to the command register, which selects the v in0 , v in1 , and v in2 channels. 7. the slave asserts an acknowledge on sda. 8. the master sends the second data byte (0x20) to the com- mand register. 9. t he slave asserts an acknowledge on sda. 10. the master sends the result register address (0x01). 11. the slave asserts an acknowledge on sda. 12. the master sends the 7-bit slave address followed by the write bit (high). 13. the slave (ad7291) asserts an acknowledge on sda. 14. the master receives a data byte, which contains the channel address bits and the four msbs of the converted result for channel v in0 . 15. the master then asserts an acknowledge on sda. 16. the master receives the second data byte, which contains the eight lsbs of the converted result for channel v in0 . the master then asserts on acknowledge on sda. 17. step 11 and step 12 repeat for channel v in1 and channel v in2 . 18. once the master has received the results from all the selected channels, the slave again converts and outputs the result for the first channel in the selected sequence. step 12 to step 14 are repeated. 19. the master asserts a not acknowledge on sda and a stop condition on sda to end the conversion and exit command mode. to change the conversion sequence, rewrite a new sequence to the command mode. if a new write to the command register is performed while an existing conversion sequence is underway, the existing conversion sequence is terminated and the next conversion performed is the first selected channel from the new sequence. the maximum throughput that can be achieved using this mode with a 400 khz i 2 c clock is (400 khz/18) = 22.2 ksps. 08711-016 s sa p ... ... 0 sa sa sa command = 0xe0 command = 0x20 a v in0 [11:8] a point to result reg (0x01) sr 1 sa sa ch ad (0000) ... a v in2 [11:8] * * * * a a ... ... a v in0 [7:0] ... ........ a * = position of sampling start slave address point to command reg (0x00) v in0 [7:0] a ch ad (0001) a ... v in1 [7:0] v in1 [11:8] v in0 [11:8] slave address v in2 [7:0] v in2 [7:0] ch ad (0010) ch id (0000) from master to slave from slave to master s = start condition sr = repeated start p = stop condition sa = slave acknowledge a = not acknowledge figure 28. command mode operation
ad7291 rev. 0 | page 26 of 28 autocycle mode the ad7291 can be configured to convert continuously on a programmable sequence of channels, making it the ideal mode of operation for system monitoring. this mode is useful for monitoring signals, such as battery voltage and temperature, alerting only when the limits are violated. conversions take place in the background approximately every 50 s, and are transparent to the master. the acquisition and conversion times combined for any channel take approximately 3.6 s. typically, this mode is used to automatically monitor a selection of channels with either the limit registers programmed to signal an out-of-range condition via the alert function or the minimum/maximum recorders tracking the variation over time of a particular channel. reads and writes can be performed at any time (the adc voltage conversion result register, register 0x01, contains the most recent conversion result). during power-up, this mode is disabled. to enable this mode, write to bit d0 in the command register (register 0x00) and select the desired channels for conversion by writing to the corresponding channel bits (bit d15 to bit d8). if more than one channel bit is set in the configuration register, the adc automatically cycles through the channel sequence starting with the lowest channel and working its way up through the sequence. once the sequence is complete, the adc starts converting on the lowest channel again, continuing to loop through the sequence until this mode is exited. once a conversion is completed, the conversion result is compared with the content of the limit registers, and alert status registers are automatically updated. if a violation of the limit registers is found, the alert pin is asserted with the polarity determined by bit d3 in the command register. if a command mode conversion is required while the autocycle mode is active, it is necessary to disable the autocycle mode before proceeding to the command mode. this is achieved by setting bit d0 of the command register to 1. when the command mode conversion is co mplete, the user can reenable autocycle mode by setting bit d0 to 1 in the command register. in autocycle mode, the ad7291 does not enter partial power- down on receipt of a stop condition; therefore, conversions and alert monitoring continue to function.
ad7291 rev. 0 | page 27 of 28 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 020509-b bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indi c ator 2.75 2.60 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 29. 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad7291bcpz ?40c to +125c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-8 ad7291bcpz-rl7 ?40c to +125c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-8 EVAL-AD7291SDZ evaluation board 1 z = rohs compliant part.
ad7291 rev. 0 | page 28 of 28 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08711-0-1/11(0)

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