View GLS55LC200-60-C-TQWE_1025854.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet ?2010 greenliant systems, ltd. s71365-04-000 05/10 www.greenliant.com features: ? compactflash associati on specification revi- sion 3.0 standard interface ? host interface: 16-bit access ? supports up to pio mode-6 ? supports up to multi-word dma mode-4 ? supports up to ultra dma mode-4 ? interface for standard nand flash media ? flash media interface: single or dual 8-bit access - supports up to 4 flash media devices per channel - supports up to 8 flash media devices directly ? supports single-level cell (slc) or multi-level cell (mlc) flash media - 2 kbyte and 4 kbyte program page size ? 3.3v power supply and nand flash interface ? 5.0v or 3.3v host interface through v ddq pins ? low current operation: ? active mode: 25 ma/35 ma (3.3v/5.0v) (typical) ? sleep mode: 80 a/100 a (3.3v/5.0v) (typical) ? power management unit ? immediate disabling of unus ed circuitry without host intervention ? zero wake-up latency ? 20-byte unique id for enhanced security ? factory pre-programmed 10-byte unique id ? user-programmable 10-byte id ? programmable, multitasking nand interface ? firmware storage in embedded superflash ? ? pre-programmed embedded firmware ? performs self-initializati on on first system power-on ? executes industry standard compactflash com- mands ? implements advanced wear-leveling algorithms to substantially increase t he longevity of flash media ? embedded flash file system ? built-in hardware ecc ? corrects up to 8 random single-bit errors per 512-byte sector ? built-in internal system clock ? multi-tasking technology enables fast sustained write performance (host to flash) ? supports up to 30 mbyte/sec ? fast sustained read performance (flash to host) ? up to 30 mbyte/sec ? automatic recognition and initialization of flash media devices ? seamless integration into a standard smt manufacturing process ? 5 sec. (typical) for flash drive recognition and setup ? commercial and industrial temperature ranges ? 0c to 70c for commercial operation ? -40c to +85c for industrial operation ? packages available ? 100-lead tqfp ? 14mm x 14mm ? all non-pb (lead-free) devices are rohs compliant product description the gls55lc200 nand controller is the core of a high- performance, flash media-bas ed, data storage system. the controller recognizes the control, address, and data signals on the cf bus and translates them into memory accesses for standard nand-ty pe flash media. using both single level cell (slc) and mu lti-level cell (mlc) flash media, this technology supports solid state mass storage applications by offering new, expanded functionality while enabling smaller, lighter designs with lower power con- sumption. the nand controller supports standard cf protocols with up to pio mode-6, multi-word dma mode-4, and ultra dma mode-4 interface. the cf interface is widely used in products such as portable and desktop computers, digital cameras, music players, handheld data collection scan- ners, pdas, handy terminal s, personal communicators, audio recorders, monitoring devices, and set-top boxes. the nand controller uses superflash? memory technol- ogy, and is factory pre-programmed with an embedded flash file system. upon initial power-on, the gls55lc200 recognizes the flash media dev ices, sets up a bad block table, executes all the nece ssary handshaking routines for flash media support, and, finally, performs the low-level for- mat. this process typically takes about 3 second plus 0.5 seconds per gigabyte of drive capacity, allowing a 4 gbyte flash drive to be fully initia lized in about 5 seconds. for added manufacturing flexibility, system debug, re-initializa- tion, and user customization can be accomplished through the cf interface. nand controller gls55lc200 gls55lc100mcompact flash card controller
2 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 the gls55lc200 high-performance nand controller offers sustained read and write performance up to 30 mbyte/sec. the gls55lc200 directly supports up to eight flash media devices with appropriate output load- ing and frequency. the nand controller comes pre-programmed with a 10- byte unique serial id. for even greater system security, the user has the option of progra mming an additional 10 bytes of id space to create a unique, 20-byte id. the nand controller comes packaged in an industry-stan- dard 100-lead tqfp package for easy integration into an smt manufacturing process.
data sheet nand controller gls55lc200 3 ?2010 greenliant systems, ltd. s71365-04-000 05/10 general description the nand controller contains a microcontroller and embedded flash file system in tegrated in a tqfp package. refer to figure 1 for the nand controller block diagram. the controller interfaces with the host system allowing data to be written to and read from the flash media. performance-optimi zed nand controller the nand controller translates standard cf signals into flash media data and control signals. the following compo- nents contribute to the controller?s operation. microcontroller unit (mcu) the mcu coordinates all related components to complete requested operations. internal direct me mory access (dma) the nand controller uses internal dma which allows instant data transfer from buffer to flash media. this increases the data transfer rate by eliminating the micro- controller overhead associated with the traditional, firm- ware-based approach. power management unit (pmu) the power management unit co ntrols the power consump- tion of the nand controller. it reduces the power con- sumption of the nand controlle r by putting circuitry not in operation into sleep mode. the pmu has zero wake-up latency. sram buffer the nand controller performs as an sram buffer to opti- mize the host?s data transfer to and from the flash media. embedded flash file system the embedded flash file system is an integral part of the nand controller. it contains mcu firmware that performs the following tasks: 1. translates host side signals into flash media writes and reads. 2. provides flash media wear-leveling to spread the flash writes across all memory address spaces to increase the longevity of flash media. 3. keeps track of data file structures. error correction code (ecc) the nand controller uses bch error detection code (edc) and error correction code (ecc) algorithms which correct up to eight random single-bit errors for each 512-byte block of data. high performance is achieved through hardware-based error detection and correction. serial communication interface (sci) the serial communication interface (sci) is designed to provide trace information during debugging process. to aid in validation, always prov ide the sci access to pcb design. programmable, multi-t asking nand interface the multi-tasking interface enables fast, sustained write and read performance by allowing multiple read, program, and erase operations to multiple flash media devices. the programmable nand interface enables timely support of fast changing nand technology.
4 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 functional blocks figure 1: nand c ontroller b lock d iagram 1365 b1.2 host cf bus nand controller multi-tasking interface sci embedded flash file system mcu ecc internal dma sram buffer pmu nand flash media nand flash media dual channel
data sheet nand controller gls55lc200 5 ?2010 greenliant systems, ltd. s71365-04-000 05/10 pin assignments the signal/pin assignments are listed in table 1. low active signals have a ?#? suffix. pin types are input, output, or input/output. signals whose source is the host are desig nated as inputs while signals that the nand controller sources are outputs. figure 2: p in a ssignments for 100- lead tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 reset v ss (io) d7 d6 d5 d4 v ddq (io) d3 d2 d1 d0 v ss (io) oe# inpack# a3 a4 a5 a6 iord# reg# intrq a1 a0 ce1# v ss (core) tie_dn dnu v ss (io) dnu fwe# fce5# fale fce4# fcle fce6# v ss (io) fce3# fce2# v dd (io) fce0# dnu fre# dnu v reg dnu fce1# scid out scid in sciclk v dd (cor e) fce7# v ss (io) fad0 fad8 fad1 fad9 fad2 fad10 fad3 fad11 v ss (io) dnu v dd (io) fad4 fad12 fad5 fad13 fad6 fad14 fad7 fad15 dnu dnu dnu por# 1365 100-tqfp p2.1 dasp# v ss (io) d8 d9 d10 d11 v ddq (io) d12 d13 d14 d15 v ss (io) we# wait# a10 a9 a8 a7 iowr# csel# iocs16# pdiag# a2 ce2# v ss (core) note: dnu means do not use, must be left unconnected. 100-lead tqfp top view
6 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 table 1: p in a ssignments (1 of 6) signal name 100-lead pin type i/o type 1 name and functions host interface a 10 -a 0 (memory card mode) 61 60 59 58 18 17 16 15 53 22 23 ii1z these address lines, along with the reg# signal, are used to select the following: the i/o port address r egisters within the nand, the memory mapped port address registers within the nand, a byte in the card?s information structure and its configuration control and status registers. a 10 -a 0 (pc card i/o mode) this signal is the same as the pc card memory mode signal. a 2 -a 0 (true ide mode) 53 22 23 in true ide mode only a[2:0] are used to select the one of eight regis- ters in the task file. a 10 -a 3 61 60 59 58 18 17 16 15 the remaining address lines should be grounded by the host. bvd1 (memory card mode) 54 i/o i1u, o1 this signal is asserted high as bvd1 is not supported. stschg# (pc card i/o mode) this signal is asserted low to alert the host to changes in the ready and write protect states, while the i/o interface is configured. its use is con- trolled by the card config and status register. pdiag# (true ide mode) in the true ide mode, this input/ou tput is the pass diagnostic signal in the master/slave handshake protocol. bvd2 (memory card mode) 75 i/o i1u, o6 this signal is asserted high as bvd2 is not supported. spkr# (pc card i/o mode) this output line is always driven to a high state in i/o mode since the nand controller does not support the audio function. dasp# (true ide mode) in the true ide mode, this input/output is the disk active/slave present signal in the master/slave handshake protocol. ce1#, ce2# (memory card mode) 24 52 ii2u card enable: these input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being per- formed. ce2# always accesses the odd byte of the word. ce1# accesses the even byte or the odd byte of the word depending on a 0 and ce2#. a multiplexing scheme based on a 0 , ce1#, ce2# allows 8- bit hosts to access all data on d 0 -d 7 . ce1#, ce2# (pc card i/o mode) card enable: this signal is the same as the pc card memory mode signal. cs0#, cs1# (true ide mode) in the true ide mode cs0# is the ch ip select for the task file registers while cs1# is used to select the alte rnate status register and the device control register.
data sheet nand controller gls55lc200 7 ?2010 greenliant systems, ltd. s71365-04-000 05/10 csel# (memory card mode) 56 i i1u this signal is not used for this mode. csel# (pc card i/o mode) this signal is not used for this mode. csel# (true ide mode) this internally pulled up signal is used to configure this device as a mas- ter or a slave when configured in the true ide mode. when this pin is grounded, this device is configured as a master. when the pin is open, this device is configured as a slave. d 15 -d 0 (memory card mode) 65 66 67 68 70 71 72 73 3 4 5 6 8 9 10 11 i/o i1z, o2 these lines carry the data, commands and status information between the host and the controller. d 0 is the lsb of the ev en byte of the word. d 8 is the lsb of the odd byte of the word. d 15 -d 0 (pc card i/o mode) this signal is the same as the pc card memory mode signal. d 15 -d 0 (true ide mode) in true ide mode, all task file operations occur in byte-mode on the low order bus d 7 -d 0 while all data transfers are 16 bit using d 15 -d 0 . inpack# (memory card mode) 14 o o1 this signal is not used in this mode. inpack# (pc card i/o mode) the input acknowledge signal is a sserted by the nand when the card is selected and responding to an i/o read cycle at the address that is on the address bus. this signal is used by the host to control the enable of any input data buffers between the nand and the cpu. dmarq (true ide mode) in true ide mode dma request to host. iord# (memory card mode) 19 i i2u this signal is not used in this mode. iord# (pc card i/o mode) this is an i/o read strobe generated by the host. this signal gates i/o data onto the bus from the nand when the card is configured to use the i/o interface. iord# (true ide mode) in true ide mode, this signal has the same function as in pc card i/o mode. hdmardy# (true ide mode) hdmardy#: in ultra dma mode when dma read is active, this signal is asserted by the host to indicate that the host is ready to receive ultra dma data-in bursts. the host may negate hdmardy# to pause an ultra dma transfer. hstrobe (true ide mode) hstrobe: when dma write is active, this signal is the data-out strobe generated by the host. both the rising and falling edges of hstrobe cause data to be latched by the device. the host may stop generating hstrobe edges to pause an ultra dma data-out burst. table 1: p in a ssignments (c ontinued ) (2 of 6) signal name 100-lead pin type i/o type 1 name and functions
8 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 iowr# (memory card mode) 57 i i2u this signal is not used in this mode. iowr# (pc card i/o mode) the i/o write strobe pulse is used to clock i/o data on the card data bus into the nand controller registers when the nand is configured to use the i/o interface. iowr# (true ide mode) in true ide mode, this signal has the same function as in pc card i/o mode. stop (true ide mode) when ultra dma mode protocol is active, the assertion of this signal causes the termination of the ultra dma burst oe# (memory card mode) 13 i i2u this is an output enable strobe gener ated by the host interface. it is used to read data from the nand in memory mode and to read the cis and configuration registers. oe# (pc card i/o mode) in pc card i/o mode, this signal is used to read the cis and configura- tion registers. atasel# (true ide mode) to enable true ide mode this input should be grounded by the host. ready (memory card mode) 21 o o1 in memory mode this signal is set high when the nand is ready to accept a new data transfer operation and held low when the card is busy. at power up and at reset, the ready signal is held low (busy) until the nand has completed its power up or reset function. no access of any type should be made to the nand during this time. ireq# (pc card i/o mode) i/o operation - after the nand has been configured for i/o operation, this signal is used as interrupt reque st. this line is strobed low to gen- erate a pulse mode interrupt or held low for a level mode interrupt. intrq (true ide mode) in true ide mode signal is the active high interrupt request to the host. reg# (memory card mode) 20 i i2u this signal is used during memory cycles to distinguish between com- mon memory and register (attribute) memory attribute memory select accesses. high for common memory , low for attribute memory. reg# (pc card i/o mode) the signal must also be active (low) during i/o cycles when the i/o address is on the bus. dmack (true ide mode) in true ide mode dma acknowledge - input from host. reset (memory card mode) 1ii2u when the pin is high, this signal resets the nand. the nand is reset only at power up if this pin is left high or open from power-up. the nand is also reset when the soft-reset bit in the card configuration option register is set. reset (pc card i/o mode) this signal is the same as the pc card memory mode signal. reset# (true ide mode) in the true ide mode this input pin is the active low hardware reset from the host. table 1: p in a ssignments (c ontinued ) (3 of 6) signal name 100-lead pin type i/o type 1 name and functions
data sheet nand controller gls55lc200 9 ?2010 greenliant systems, ltd. s71365-04-000 05/10 wait# (memory card mode) 62 o o1 the wait# signal is driven low by the nand to signal the host to delay completion of a memory or i/ o cycle that is in progress. wait# (pc card i/o mode) this signal is the same as the pc card memory mode signal. iordy# (true ide mode) in true ide mode, except in ultra dma modes, this signal may be used as iordy. ddmardy# (true ide mode) when ultra dma mode dma write is active, this signal is asserted by the host to indicate that the device is read to receive ultra dma data-in bursts. the device may negate ddmardy# to pause an ultra dma transfer. dstrobe (true ide mode) when ultra dma mode dma write is acti ve, this signal is the data-out strobe generated by the device. both the rising and falling edges of dstrobe cause data to be latched by the host. the device may stop generating dstrobe edges to pause an ultra dma data-out burst. we# (memory card mode) 63 i i2u this is a signal driven by the host and used for strobing memory write data to the registers of the nand wh en the card is configured in the memory interface mode. it is also us ed for writing the configuration reg- isters. we# (pc card i/o mode) in pc card i/o mode, this signal is used for writing the configuration registers. we# (true ide mode) in true ide mode this input signal is not used and should be connected to v dd by the host. wp (memory card mode) 55 o o2 the nand does not have a write protect switch. this signal is held low after the completion of the reset initialization sequence. iois16# (pc card i/o mode) when the nand is configured for i/o op eration pin 55 is used for the i/ o# selected is 16-bit port (iois1 6#) function. a low signal indicates that a 16 bit or odd byte only op eration can be performed at the addressed port. iocs16# (true ide mode) in true ide mode this output signal is asserted low when this device is expecting a word data transfer cycle. table 1: p in a ssignments (c ontinued ) (4 of 6) signal name 100-lead pin type i/o type 1 name and functions
10 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 flash media interface fre# 84 o o5 active low flash media chip read fwe# 96 o o5 active low flash media chip write fcle 92 o o5 active high flash media chip command latch enable fale 94 o o5 active high flash media chip address latch enable fad15 46 i/o i3u/o5 flash media chip high byte address/data bus pins fad14 44 fad13 42 fad12 40 fad11 35 fad10 33 fad9 31 fad8 29 fad7 45 i/o i3u/o5 flash media chip low byte address/data bus pins fad6 43 fad5 41 fad4 39 fad3 34 fad2 32 fad1 30 fad0 28 fce7# 26 o o4 active low flash media chip enable pin fce6# 91 fce5# 95 fce4# 93 fce3# 89 fce2# 88 fce1# 80 fce0# 86 serial communication interface (sci) sciclk 77 i i3u sci interface clock scid in 78 i i3u sci interface data input scid out 79 o o4 sci interface data output miscellaneous v dd (core) 76 pwr v dd (3.3v) v dd (io) 38 87 pwr v dd (3.3v) v ddq (io) 7 69 pwr v ddq (5v/3.3v) for host interface v reg 82 o external capacitor pin. connect this pin with a 4.7uf capacitor to ground. table 1: p in a ssignments (c ontinued ) (5 of 6) signal name 100-lead pin type i/o type 1 name and functions
data sheet nand controller gls55lc200 11 ?2010 greenliant systems, ltd. s71365-04-000 05/10 v ss (core) 25 51 pwr ground for core v ss (io) 2 12 27 36 64 74 90 98 pwr ground for i/o por# 50 i analog input 2 power-on reset (por): active low tie_dn 100 pin must be connected to v ss dnu 3 37 47 48 49 81 83 85 97 99 do not use, must be left unconnected. t0-0.0 1365 1. ixu = input with on-chip pull-up. ixz = input without on-chip pull-up. 2. analog input for supply voltage detection 3. all dnu pins should not be connected. table 1: p in a ssignments (c ontinued ) (6 of 6) signal name 100-lead pin type i/o type 1 name and functions
12 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 capacity specification table 2 shows the default capacity and specific settings fo r heads, sectors, and cylinders. users can change the default settings in the drive id table (see table 20) for customization. if the total number of bytes is less than the default, the remaining space could be used as spares to increase the flash drive endurance. it should also be noted that if the total flash drive capacity exceeds the total default number of bytes, the flash drive endurance will be reduced. functional specifications table 4-2 shows the performance and the ma ximum capacity supported by gls55lc200. table 2: default nand settings capacity 1 1. these flash drive capacities can only be manufactured by using the specified versi on of the compact flash card controller. total bytes cylinders 2 2. cylinders, heads, and sectors can be re-configured from the default settings during the manufacturing process. heads 2 sectors 2 max lba 128 mb 128,450,560 490 16 32 250,880 256 mb 256,901,120 980 16 32 501,760 512 mb 512,483,328 993 16 63 1,000,944 1 gb 1,024,966,656 1986 16 63 2,001,888 2 gb 2,048,901,120 3970 16 63 4,001,760 4 gb 4,110,188,544 7964 16 63 8,027,712 6 gb 6,146,703,360 11910 16 63 12,005,280 8 gb 8,195,604,480 15880 16 63 16,007,040 16 gb 16,391,208,960 16383 3 3. cylinders, heads, and sectors are not applicable fo r these capacities. only lba addressing applies. 16 63 32,014,080 32 gb 32,001,048,576 16383 3 16 63 62,502,048 t0-0.5 1365 table 3: functional specification functions gls55lc200 nand supported capacity up to 32 gb nand performance-sustained write speed up to 30.0 mb/sec nand performance-sustained read speed up to 30.0 mb/sec t0-0.0 1365
data sheet nand controller gls55lc200 13 ?2010 greenliant systems, ltd. s71365-04-000 05/10 manufacturing support the nand controller firmware contains a list of supported standard nand flash media devices. upon initial power- on, the controller scans all connected flash media devices and reads their device id. if the device id matches the listed flash media devices in the nand controller, the controller performs drive recognition based on the algorithm provided by the flash media suppliers. this includes sett ing up the bad block table, executing all the necessary handshaking routines for flash media support, and, finally, performing the low-level format. please contact greenliant for the most current list of supported nand flash media devices. in the event that the nand flash media device id is not recognized by the nand controller, the user has an option of adding this device to the controller device table th rough the manufacturing interface provided by greenliant. please contact greenliant for the nand controller manufacturing interface soft ware. if the drive in itialization fails, and a visual inspection is unable to determine the pr oblem, the gls55lc200 nand controller provides a compre- hensive interface for manufacturing flow debug. this inte rface not only allows debug of the failure and manual reset of the initialization process, but also a llows customization of user definable options. cf interface the compactflash interface can be used for manufacturi ng support. greenliant provides an example of a dos- based solution (an executable routine downloadable from greenliant?s web site) for manufacturing debug and rework. serial communication interface (sci) for additional manufactur ing flexibility, the sci bus can be used to report manufactu ring errors. the sci consists of 3 active signals: scid out , scid in , and sciclk. power-on and bro wn-out reset characteristics power-on and brown-out reset circuitry reset the device to a known state. power-on reset asserts when the device is turned on. brown-out reset asserts when the detected voltage falls below an acceptable level. for more information about the power-on and brown-out reset timing, see figure 3 and table 4. figure 3: power-on and brown-out reset timing table 4: power-on and brown-out reset timing item symbol min max units v dd /por# rise time 1 1. v dd rise time should be greater than or equal to por# rise time. t r 200 ms v dd /por# fall time 2 2. v dd fall time should be slower t han or equal to por# fall time. t f 200 ms t0-0.0 1365 1365 f01.0 v dd / por# t r 90% 10% t f 90% 10%
14 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 card configuration the nands are identified by appropriate information in th e card information structure (cis). the following config- uration registers are used to coordinate the i/o spaces and the interrupt level of cards that are located in the sys- tem. in addition, these registers provide a method for ac cessing status information about the nand that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to replace status information that appears on dedicated pins in memory cards that have alternate use in i/o cards. note: the location of the card configuration registers should always be read from the cis locations 0000h to 0198h. no writes should be performed to the nand attribute memory except to the card configuration register addresses. all other attribute memory locations are reserved. table 5: registers and memory space decoding ce2# ce1# reg# oe# we# a 10 a 9 a 8 -a 4 a 3 a 2 a 1 a 0 selected space 1 1 x x x x x xx xxxxstandby x 0 0 0 1 0 1 xx x x x 0 configuration registers read 1 0 1 0 1 x x xx xxxxcommon memory r ead (8 bit d 7 -d 0 ) 0 1 1 0 1 x x xx xxxxcommon memory r ead (8 bit d 15 -d 8 ) 0 0 1 0 1 x x xx x x x 0 common memory read (16 bit d 15 -d 0 ) x 0 0 1 0 0 1 xx x x x 0 configuration registers write 1 0 1 1 0 x x xx xxxxcommon memory write (8 bit d 7 -d 0 ) 0 1 1 1 0 x x xx xxxxcommon memory write (8 bit d 15 -d 8 ) 0 0 1 1 0 x x xx x x x 0 common memory write (16 bit d 15 -d 0 ) x 0 0 0 1 0 0 xx x x x 0 card information structure read 1 0 0 1 0 0 0 xx x x x 0 invalid access (cis write) 1 0 0 0 1 x x xx x x x 1 invalid access (odd attribute read) 1 0 0 1 0 x x xx x x x 1 invalid access (odd attribute write) 0 1 0 0 1 x x xx xxxxinvalid access (odd attribute read) 0 1 0 1 0 x x xx xxxxinvalid access (odd attribute write) t0-0.0 1365 table 6: configuration registers decoding ce2# ce1# reg# oe# we# a 10 a 9 a 8 -a 4 a 3 a 2 a 1 a 0 selected register x 0 0 0 1 0 1 00 0 0 0 0 configuration option reg read x 0 0 1 0 0 1 00 0 0 0 0 configuration option reg write x 0 0 0 1 0 1 00 0 0 1 0 card status register read x 0 0 1 0 0 1 00 0 0 1 0 card status register write x 0 0 0 1 0 1 00 0 1 0 0 pin replacement register read x 0 0 1 0 0 1 00 0 1 0 0 pin replacement register write x 0 0 0 1 0 1 00 0 1 1 0 socket and copy register read x 0 0 1 0 0 1 00 0 1 1 0 socket and copy register write t0-0.0 1365
data sheet nand controller gls55lc200 15 ?2010 greenliant systems, ltd. s71365-04-000 05/10 attribute memory function attribute memory is a space where nand identification a nd configuration information are stored. this memory is limited to 8-bit wide accesses, only at even addresses. the card configuration registers are also located in this space. for the attribute memory read function , signals reg# and oe# must be active and we# inactive during the cycle. as in the main memory read functions, the signals ce 1# and ce2# control the even byte and odd byte address, but only the even byte data is valid during the attribut e memory access. refer to table 7 below for signal states and bus validity for the attribute memory function. note: the ce# signal or both the oe# signal and the we# signal must be de-asserted between consecutive cycle operations. configuration option register (address 200h in attribute memory) the configuration option register is used to configure the cards interface, address decoding and interrupt and to issue a soft reset to the nand. sreset soft reset - setting this bit to one (1), waiting the minimum reset width time and returning to zero (0) places the nand in the reset state. setting this bit to one (1) is equivalent to asse rtion of the reset signal except that the sreset bit is not cleared. returning this bit to zero (0 ) leaves the nand in the same un-configured reset state as following power-up and hardware reset. this bit is set to zero (0) by power-up and hardware reset. using the pcmc ia soft reset is considered a hard reset by the ata commands. contrast with soft reset in the device control register. levlreq this bit is set to one (1) when level mode interrupt is selected, and zero (0) when pulse mode is selected. set to zero (0) by reset. conf5-conf0 configuration index. set to zero (0) by reset. it?s used to select operation mode of the nand as shown below. note: conf5 and conf4 are reserved and must be written as (0). table 7: attribute memory function function mode reg# ce2# ce1# a 10 a 9 a 0 oe# we# d 15 -d 8 d 7 -d 0 standby mode x v ih v ih x x x x x high z high z read byte access cis rom (8 bits) v il v ih v il v il v il v il v il v ih high z even byte write byte access cis (8 bits) (invalid) v il v ih v il v il v il v il v ih v il don?t care even byte read byte access configuration (8 bits) v il v ih v il v il v ih v il v il v ih high z even byte write byte access configuration (8 bits) v il v ih v il v il v ih v il v ih v il don?t care even byte read word access cis (16 bits) v il v il v il v il v il xv il v ih not valid even byte write word access cis (16 bits) (invalid) v il v il v il v il v il xv ih v il don?t care even byte read word access configuration (16 bits) v il v il v il v il v ih xv il v ih not valid even byte write word access configuration (16 bits) v il v il v il v il v ih xv ih v il don?t care even byte t0-0.0 1365 operationd7d6d5d4d3d2d1d0 r/w sreset levlreq conf5 conf4 conf3 conf2 conf1 conf0
16 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 changed indicates that one or both of the pin re placement register crdy or cwprot bits are set to one (1). when the changed bit is set, pin 46 (stschg#) is held low if the sigchg bit is a one (1) and the nand is configured for the i/o interface. sigchg this bit is set and reset by the host to enable and disable a state-change ?signal? from the status register, the changed bit control pi n 46 the changed status signal. if no state change signal is desired, this bit should be set to zero (0) and pin 46 (stschg#) signal will be held high while the na nd is configured for i/o. iois8 the host sets this bit to a one (1) if the nand is to be configured in an 8-bit i/o mode. the nand is always configured for both 8- and 16-bit i/o, so this bit is ignored. xe#: this bit has value 0 and is not writable. audio: this bit should always be zero for nands. pwrdwn this bit indicates whether the host requests the nand to be in the power saving or active mode. when the bit is one (1), the nand enters a power down mode. when zero (0), the host is requesting the nand to enter the active mode. the pcmcia ready value becomes busy when this bit is chan ged. ready will not bec ome ready until the power state requested has been entered. the nand automatically powers down when it is idle and powers back up when it receives a command. int this bit represents the internal state of the interrupt request. this value is available whether or not i/o interface has been configured. this signal remains true until the condition which caused the interrupt request has been serviced. if interrupts are disabled by the -ien bit in the device contro l register, this bit is a zero (0). table 8: card configurations conf5 conf4 conf3 conf2 co nf1 conf0 disk card mode 0 0 0 0 0 0 memory mapped 0 0 0 0 0 1 i/o mapped, any 16 byte system decoded boundary 0 0 0 0 1 0 i/o mapped, 1f0h-1f7h/3f6h-3f7h 0 0 0 0 1 1 i/o mapped, 170h-177h/376h-377h t0-0.0 1365 table 9: card configuration and status register organization operationd7d6d5d4d3d2d1d0 read changed sigchg iois8 xe# audio pwrdwn int 0 write 0 sigchg iois8 xe# audio pwrdwn 0 0
data sheet nand controller gls55lc200 17 ?2010 greenliant systems, ltd. s71365-04-000 05/10 pin replacement register (addre ss 204h in attribute memory) crdy/bsy# this bit is set to one (1) when the bit rdy/bsy# changes state. this bit can also be written by the host. cwprot this bit is set to one (1) when the rwprot changes state. this bit may also be written by the host. rdy/bsy# this bit is used to determ ine the internal state of the rdy/bsy# signal. this bit may be used to determine the state of the ready/-busy as this pin has been reallocated for use as interrupt request on an i/o card. when written, this bi t acts as a mask for writing the corresponding bit crdy/bsy#. wprot: this bit is always zero (0). when written, this bit acts as a mask for writing the corresponding bit cwprot. mrdy/bsy# this bit acts as a mask for writing the co rresponding bit crdy/bsy#. mwprot: this bit when written acts as a mask for writing the corresponding bit cwprot. socket and copy regi ster (address 206h in attribute memory) this register contains additional config uration information. this re gister is always written by the system before writ- ing the card?s configuration index register. reserved this bit is reserved for future standardiz ation. this bit must be set to zero (0) by the software when the register is written. drive # this bit indicates the drive number of the card for twin card configuration. twin card configuration is currently not supported x the socket number is ignored by the nand. operation d7 d6 d5 d4 d3 d2 d1 d0 read 0 0 crdy/bsy# cwprot 1 1 rdy/bsy# wprot write 0 0 crdy/bsy# cwprot 0 0 mrdy/bsy# mwprot table 10: pin replacement changed bit/mask bit values initial value of (c) status written by host final ?c? bit comments ?c? bit ?m? bit 0 x 0 0 unchanged 1 x 0 1 unchanged x 0 1 0 cleared by host x 1 1 1 set by host t0-0.0 1365 socket and copy register organization: operationd7d6d5d4d3d2d1d0 read reserved 0 0 drive # 0 0 0 0 write0 0 0drive #xxxx
18 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 i/o transfer function i/o function the i/o transfer to or from the nand can be either 8 or 16 bits. when a 16-bit accessible port is addressed, the signal iois16# is asserted by the nand. otherwise, the iois16# signal is de-asserted. when a 16 bit transfer is attempted, and the iois16# signal is not asserted by the nand, the system must generate a pair of 8-bit refer- ences to access the word?s even byte and odd byte. the nand permits both 8 and 16 bit accesses to all of its i/o addresses, so iois16# is asserted for a ll addresses to which the nand responds. common memory transfer function common memory function the common memory transfer to or from the nand can be either 8 or 16 bits. the nand permits both 8 and 16 bit accesses to all of its common memory addresses. table 11: i/o function function code reg# ce2# ce1# a 0 iord# iowr# d 15 -d 8 d 7 -d 0 standby mode x v ih v ih x x x high z high z byte input access (8 bits) v il v ih v il v il v il v ih high z even byte v il v ih v il v ih v il v ih high z odd byte byte output access (8 bits) v il v ih v il v il v ih v il don?t care even byte v il v ih v il v ih v ih v il don?t care odd byte word input access (16 bits) v il v il v il v il v il v ih odd byte even byte word output access (16 bits) v il v il v il v il v ih v il odd byte even byte i/o read inhibit v ih x x x v il v ih don?t care don?t care i/o write inhibit v ih x x x v ih v il high z high z high byte input only (8 bits) v il v il v ih x v il v ih odd byte high z high byte output only (8 bits) v il v il v ih x v ih v il odd byte don?t care t0-0.0 1365 table 12: common memory function function code reg# ce2# ce1# a 0 oe# we# d 15 -d 8 d 7 -d 0 standby mode x v ih v ih x x x high z high z byte read access (8 bits) v ih v ih v il v il v il v ih high z even byte v ih v ih v il v ih v il v ih high z odd byte byte-write access (8 bits) v ih v ih v il v il v ih v il don?t care even byte v ih v ih v il v ih v ih v il don?t care odd byte word read access (16 bits) v ih v il v il x v il v ih odd byte even byte word-write access (16 bits) v ih v il v il x v ih v il odd byte even byte odd byte read only (8 bits) v ih v il v ih x v il v ih odd byte high z odd byte-write only (8 bits) v ih v il v ih x v ih v il odd byte don?t care t0-0.0 1365
data sheet nand controller gls55lc200 19 ?2010 greenliant systems, ltd. s71365-04-000 05/10 true ide mode i/o transfer function true ide mode i/o function the nand can be configured in a true ide mode of operat ion. the nand is configured in this mode only when the oe# input signal is grounded by the host during the power off to power on cycle. in this true ide mode the pcmcia protocol and co nfiguration are disabled and only i/o operatio ns to the task file and data register are allowed. in this mode no memory or attribute register s are accessible to the host. nands permit 8 bit data accesses if the user issues a set feature command to put the device in 8-bit mode. note: removing and reinserting the nand while the host co mputer?s power is on will reconfigure the compact- flash to pc card ata mode from the original true ide mode. to configure the nand in true ide mode, the 50-pin socket must be power cycled with the na nd inserted and oe# (out put enable) asserted. table 13 defines the function of the operations for the true ide mode. table 13: true ide mode i/o function function code ce2# ce1# a 0 -a 2 iord# iowr# d 15 -d 8 d 7 -d 0 invalid mode v il v il x x x high z high z standby mode v ih v ih x x x high z high z task file write v ih v il 1-7h v ih v il don?t care data in task file read v ih v il 1-7h v il v ih high z data out data register write v ih v il 0 v ih v il odd byte in even byte in data register read v ih v il 0 v il v ih odd byte out even byte out control register write v il v ih 6h v ih v il don?t care control in alt status read v il v ih 6h v il v ih high z status out t0-0.0 1365
20 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 software interface cf-ata drive register se t definition and protocol the nand can be configured as a high performance i/o device through: 1. standard pc-at disk i/o address spaces 1f0h-1f7h, 3f6h-3f7h (primary); 170h-177h, 376h-377h (secondary) wit h irq 14 (or other available irq) 2. any system decoded 16 byte i/o block using any available irq 3. memory space the communication to or from the nand is done using th e task file registers which provide all the necessary reg- isters for control and status informat ion. the compactflash interface connects peripherals to the host using four register mapping methods. the following is a detailed description of these methods. i/o primary and secondary address configura- tions note: address lines which are not indicated are ignored by t he nand for accessing all the registers in this table. table 14: i/o configurations standard configurations config index i/o or memory address description 0 memory 0h-fh, 400h-7ffh memory mapped 1 i/o xx0h-xxfh i/o mapped 16 contiguous registers 2 i/o 1f0h-1f7h, 3f6h-3f7h primary i/o mapped 3 i/o 170h-177h, 376h-377h secondary i/o mapped t0-0.0 1365 table 15: primary and secondary i/o decoding reg# a 9 -a 4 a 3 a 2 a 1 a 0 iord#=0 iowr#=0 note 01f(17) h 0 0 0 0 even rd data even wr data 1,2 1.register 0 is accessed with ce1# low and ce2# low (and a 0 = don?t care) as a word register on the combined odd data bus and even data bus (d 15 -d 0 ). this register may also be accessed by a pair of byte accesses to the offset 0 with ce1# low and ce2# high. note that the address space of this word register overlaps t he address space of the error and feature byte-wide registers which lie at offset 1. when accessed twice as byte r egister with ce1# low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd by te of the equivalent word access. 2.a byte access to register 0 with ce1# high and ce2# lo w accesses the error (read) or feature (write) register. 0 1f(17)h 0 0 0 1 error register features 1,2 0 1f(17)h 0 0 1 0 sector count sector count 0 1f(17)h 0011sector no. sector no. 0 1f(17)h 0 1 0 0 cylinder low cylinder low 0 1f(17)h 0 1 0 1 cylinder high cylinder high 0 1f(17)h 0 1 1 0 select card/head select card/head 0 1f(17)h 0 1 1 1 status command 0 3f(37)h 0 1 1 0 alt status device control t0-0.0 1365
data sheet nand controller gls55lc200 21 ?2010 greenliant systems, ltd. s71365-04-000 05/10 contiguous i/o mapped addressing when the system decodes a contiguous block of i/o registers to select the nand, the registers are accessed in the block of i/o space decoded by the system as follows: note: address lines which are not indicated are ignored by t he nand for accessing all the registers in this table. memory mapped addressing when the nand registers are accessed via memory references, the registers appear in the common memory space window: 0-2 kbyte as follows: table 16: contiguous i/o decoding reg# a 3 a 2 a 1 a 0 offset iord#=0 iowr#=0 notes 0 0000 0 even rd data even wr data 1 1.register 0 is accessed with ce1# low and ce2# low (and a 0 = don?t care) as a word register on the combined odd data bus and even data bus (d15-d0). this register may also be accessed by a pair of byte accesses to the offset 0 with ce1# low and ce2# high. note that the address space of this word register overla ps the address space of the error and feature byte-wide registers that lie at offset 1. when accessed twice as byte register with ce1# low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of th e equivalent word access. a byte access to register 0 with ce1# high and ce2# low accesses the error (read) or feature (write) register. 0 0001 1 error features 2 2.registers at offset 8, 9, and d are non-overlappi ng duplicates of the regi sters at offset 0 and 1. register 8 is equivalent to register 0, while register 9 access es the odd byte. therefore, if the registers are byte accessed i n the order 9 then 8 the data will be transferred odd byte then even byte. repeated byte accesses to register 8 or 0 will access consec utive (even then odd) bytes from the data buffer. repeated word accesses to register 8, 9, or 0 will ac cess consecutive words from the data buffer. r epeated byte accesses to register 9 are no t sup- ported. however, repeated alternating byte accesses to registers 8 then 9 will access consecutiv e (even then odd) bytes from th e data buffer. byte accesses to register 9 access only the odd byte of the data. 0 0010 2 sector count sector count 0 0011 3 sector no. sector no. 0 0100 4 cylinder low cylinder low 0 0101 5 cylinder high cylinder high 0 0110 6 select card/head select card/head 0 0111 7 status command 0 1000 8 dup. even rd data dup. even wr data 2 0 1001 9 dup. odd rd data dup. odd wr data 2 0 1101 d dup. error dup. features 2 0 1110 e alt status device ctl t0-0.0 1365 table 17: memory mapped decoding reg# a 10 a 9 -a 4 a 3 a 2 a 1 a 0 offset oe#=0 we#=0 notes 1 0 x 0 0 0 0 0 even rd data even wr data 1,2 1 0 x 0 0 0 1 1 error features 1,2 1 0 x 0 0 1 0 2 sector count sector count 1 0 x 0 0 1 1 3 sector no. sector no. 1 0 x 0 1 0 0 4 cylinder low cylinder low 1 0 x 0 1 0 1 5 cylinder high cylinder high 1 0 x 0 1 1 0 6 select card/head select card/head
22 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 true ide mode addressing when the nand is configured in the true ide mode, the i/ o decoding is as follows: 1 0 x 0 1 1 1 7 status command 1 0 x 1 0 0 0 8 dup. even rd data dup. even wr data 2 1 0 x 1 0 0 1 9 dup. odd rd data dup. odd wr data 2 1 0 x 1 1 0 1 d dup. error dup. features 2 1 0 x 1 1 1 0 e alt status device ctl 1 0 x 1 1 1 1 f drive address reserved 1 1 x x x x 0 8 even rd data even wr data 3 1 1 x x x x 1 9 odd rd data odd wr data 3 t0-0.0 1365 1.register 0 is accessed with ce1# low and ce2# low as a word r egister on the combined odd data bus and even data bus (d15-d0). this register may also be accessed by a pair of byte accesses to the offset 0 with ce1# low and ce2# high. note that the addres s space of this word register overlaps the address space of the er ror and feature byte-wide register s that lie at offset 1. when accessed twice as byte register with ce1# low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. a byte access to address 0 with ce1# high and ce2# low accesses the error (read) or feature (write) register. 2.registers at offset 8, 9 and d are non-overlappi ng duplicates of the regi sters at offset 0 and 1. register 8 is equivalent to register 0, while register 9 access es the odd byte. therefore, if the registers are byte accessed i n the order 9 then 8 the data will be transferred odd byte then even byte. repeated byte accesses to register 8 or 0 will access consec utive (even then odd) bytes from the data buffer. repeated word accesses to register 8, 9 or 0 will acce ss consecutive words from the data buffer. repeated byte accesses to register 9 are not sup- ported. however, repeated alternating byte accesses to registers 8 then 9 will access consecutiv e (even then odd) bytes from th e data buffer. byte accesses to register 9 access only the odd byte of the data. 3.accesses to even addresses between 400h and 7ffh access register 8. accesses to odd addresses between 400h and 7ffh access register 9. this 1 kbyte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space. some hosts, such as the x86 processors, must increment both t he source and destination addresse s when executing the memory to memory block move instruction. some pcmcia socket adapter s also have auto incrementing address logic embedded within them. this address window allows these hosts and adapters to function efficiently. note that this entire window accesses the data register fifo and does not allow random access to the data buffer within the nand. a word access to address at offset 8 will provide even data on the low-order byte of the data bus, along with odd data at offset 9 on the high-order byte of the data bus. table 17: memory mapped decoding reg# a 10 a 9 -a 4 a 3 a 2 a 1 a 0 offset oe#=0 we#=0 notes table 18: true ide mode i/o decoding ce2# ce1# a 2 a 1 a 0 iord#=0 iowr#=0 1 0 0 0 0 rd data wr data 1 0 0 0 1 error register features 1 0 0 1 0 sector count sector count 1 0 0 1 1 sector no. sector no. 1 0 1 0 0 cylinder low cylinder low 1 0 1 0 1 cylinder high cylinder high 1 0 1 1 0 select card/hea d select card/head 1 0 1 1 1 status command 0 1 1 1 0 alt status device control
data sheet nand controller gls55lc200 23 ?2010 greenliant systems, ltd. s71365-04-000 05/10 cf-ata registers the following section describes the hardware registers us ed by the host software to issue commands to the com- pactflash device. these registers are often co llectively referred to as the ?task file.? note: in accordance with the pcmc ia specification: each of the registers below which is located at an odd offset address may be accessed at its normal address and al so the corresponding even address (normal address -1) using data bus lines (d15-d8) when ce1# is high a nd ce2# is low unless iois16# is high (not asserted) and an i/o cycle is being performed. data register (address - 1f0h[170h];offset 0,8,9) the data register is a 16 bit r egister, and it is used to trans- fer data blocks between the nand data buffer and the host. this register overlaps the error register. the table below describes the combinations of data register acce ss and is provided to assist in understanding the over- lapped data register and error/feature register rather than to attempt to define general pcmcia word and byte access modes and operations. see the pcmcia pc card standard release 2.0 for definitions of the card access- ing modes for i/o and memory cycles. note: because of the overlapped registers, access to the 1f 1h, 171h or offset 1 are not defined for word (ce2#=0 and ce1#=0) operations. these accesses are treated as accesses to the word data register. the dupli- cated registers at offsets 8, 9 and dh have no restrict ions on the operations that can be performed by the socket. error register (read only) this register contains additional information about the source of an error when an error is indicated in bit 0 of the status register. the bits are defined as follows: symbol function bit 7 (icrc/bbk)this bit is set when a bad block is detected. during an ultra-dma transfer, this bit is set on detection of a crc error. bit 6 (unc) this bit is set when an uncorrectable error is encountered. bit 5 this bit is 0. bit 4 (idnf) the requested sector id is in error or cannot be found. bit 3 this bit is 0. bit 2 (abrt) this bit is set if the command ha s been aborted because of an nand controller status condition: (not ready, write fault, etc.) or when an invalid command has been t0-0.0 1365 table 18: true ide mode i/o decoding ce2# ce1# a 2 a 1 a 0 iord#=0 iowr#=0 data register ce2# ce1# a 0 offset data bus word data register 0 0 x 0,8,9 d 15 -d 0 even data register 1 0 0 0,8 d 7 -d 0 odd data register 1 0 1 9 d 7 -d 0 odd data register 0 1 x 8,9 d 15 -d 8 error / feature register 1 0 1 1, dh d 7 -d 0 error / feature register 0 1 x 1 d 15 -d 8 error / feature register 0 0 x dh d 15 -d 8 d7 d6 d5 d4 d3 d2 d1 d0 reset value bbk unc 0 idnf 0 abrt 0 amnf 0000 0000b
24 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 issued. it is required that the host retry any media acce ss command (such as read-sectors and write-sectors) t hat ends with an error condition. bit 1 this bit is 0. bit 0 (amnf) this bit is set in case of a general error. feature register (address - 1f1h[171h]; offset 1, 0dh write only) this register provides information regard- ing features of the nand that the host can utilize. this r egister is also accessed on data bits d15-d8 during a write operation to offset 0 with ce2# low and ce1# high. sector count register (address - 1f2h[172h]; offset 2) this register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the nand. if the value in this regis- ter is zero, a count of 256 sectors is specified. if the command was successful, this register is zero at command completion. if not successfully completed, the register co ntains the number of sectors that need to be transferred in order to complete the request. sector number (lba 7-0) register (address - 1f3h[173h]; offset 3) this register contains the starting sector number or bits 7-0 of the logical block address (lba) for any nand data access for the subsequent command. cylinder low (lba 15-8) register (address - 1f4h[174h]; offset 4) this register contains the low order 8 bits of the starting cylinder address or bi ts 15-8 of then logical block address. cylinder high (lba 23-16) register (address - 1f5h[175h]; offset 5) this register contains the high order bits of the starting cylinder address or bits 23-16 of the logical block address. this register is also accessed on data bits d15-d8 duri ng a write operation to offset 0 with ce2# low and ce1# high. drive/head (lba 27-24) register (address 1f6h[176h]; offset 6) the drive/head register is used to select the drive and head. it is also used to select lba addr essing instead of cylinder/head/sector addressing. the bits are defined as follows: symbol function bit 7 this bit is set to 1. bit 6 lba is a flag to select either cylinde r/head/sector (chs) or logical block address mode (lba). when lba=0, cylinder/head/s ector mode is selected. when lba=1, logical block address is selected. in logical block mode, the logical block address is interpreted as follows: lba7-lba0: sector number register d7-d0. lba15-lba8: cylinder low register d7-d0. lba23-lba16: cylinder high register d7-d0. lba27-lba24: drive/head register bits hs3-hs0. bit 5 this bit is set to 1. bit 4 (drv) drv is the drive number. when drv=0, drive (card) 0 is selected. when drv=1, drive (card) 1 is selected. the nand is set to be ca rd 0 or 1 using the copy field (drive #) of the pcmcia socket & copy configuration register. d7 d6 d5 d4 d3 d2 d1 d0 reset value 1 lba 1 drv hs3 hs2 hs1 hs0 1010 0000b
data sheet nand controller gls55lc200 25 ?2010 greenliant systems, ltd. s71365-04-000 05/10 bit 3 (hs3) when operating in the cylinder, head, sect or mode, this is bit 3 of the head number. it is bit 27 in the logical block address mode. bit 2 (hs2) when operating in the cylinder, head, sect or mode, this is bit 2 of the head number. it is bit 26 in the logical block address mode. bit 1 (hs1) when operating in the cylinder, head, sect or mode, this is bit 1 of the head number. it is bit 25 in the logical block address mode. bit 0 (hs0) when operating in the cylinder, head, sect or mode, this is bit 0 of the head number. it is bit 24 in the logical block address mode. status & alternate status registers (address 1f7h[177h]&3f6h[376h]; offsets 7 & e) these registers return the nand status when read by the host. reading the status register does clear a pending interrupt while reading the auxiliary status register does not. the me aning of the status bits are described as follows: symbol function bit 7 (busy) the busy bit is set when the nand has access to the command buffer and registers and the host is locked out from accessing the co mmand register and buffer. no other bits in this register are valid when this bit is set to a 1. bit 6 (rdy) rdy indicates whether the device is capa ble of performing nand operations. this bit is cleared at power up and remains cleared until the nand is ready to accept a command. bit 5 (dwf) this bit, if set, indicates a write fault has occurred. bit 4 (dsc) this bit is set when the nand is ready. bit 3 (drq) the data request is set when the nand requires that information be transferred either to or from the host through the data register. bit 2 (corr) this bit is set when a correctable data error has been encountered and the data has been corrected. this condition does not terminate a multi-sector read operation. bit 1 (idx) this bit is always set to 0. bit 0 (err) this bit is set when the previous command has ended in some type of error. the bits in the error register contain additional informati on describing the error. it is required that the host retry any media access command (s uch as read sectors and write sectors) that ends with an error condition. device control register (address - 3f6h[376h]; offset e) this register is used to control the nand interrupt request and to issue an ata soft reset to the card. this register can be written even if the device is busy. the bits are defined as follows: symbol function bits 7-3 these bits are ignored by the nand. bit 2 (sw rst) this bit is set to 1 in order to force the nand to perform an ata disk controller soft reset operation. this does not change t he pcmcia card configuration registers (sections to ) as a hardware reset does. the card remains in reset until this bit is reset to ?0.? d7 d6 d5 d4 d3 d2 d1 d0 reset value busy rdy dwf dsc drq corr 0 err 1000 0000b d7 d6 d5 d4 d3 d2 d1 d0 reset value xxxxxsw rst-ien0 0000 1000b
26 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 bit1(-ien) the interrupt enable bit enables interrupts when the bit is 0. when the bit is 1, interrupts from the nand are disabled. this bit also co ntrols the int bit in the configuration and status register. this bit is set to 0 at power-on and reset. bit0 this bit is ignored by the nand. cf-ata command description this section defines the software requirements and the format of the commands the host sends to the nands. commands are issued to the nand by loading the requir ed registers in the command block with the supplied parameters, and then writing the command code to the command register. the manner in which a command is accepted varies. there are three classes (see table 19 ) of command acceptance, all dependent on the host not issuing commands unless the nand is not busy (bsy=0). table 19 summarizes the cf-ata command set with the paragraphs that follow describing the individual com- mands and the task file for each. table 19: nand controller command set (1 of 2) command code fr 1 sc 2 sn 3 cy 4 dh 5 lba 6 check-power-mode e5h or 98h - - - - d 8 - execute-drive-diagnostic 90h - - - - d - erase-sector(s) c0h -yyyy y flush-cache e7h - - - - d - format-track 50h - y 7 -yy 8 y identify-drive ech - - - - d - idle e3h or 97h - y - - d - idle-immediate e1h or 95h - - - - d - initialize-drive-parameters 91h - y - - y - nop 00h - - - - d - read-buffer e4h - - - - d - read-dma c8h or c9h - yyyy y read-multiple c4h -yyyy y read-sector(s) 20h or 21h - yyyy y read-verify-sector(s) 40h or 41h - yyyy y recalibrate 1xh - - - - d - request-sense 03h - - - - d - security-disable-password f6h - - - - d - security-erase-prepare f3h - - - - d - security-erase-unit f4h - - - - d - security-freeze-lock f5h - - - - d - security-set-password f1h - - - - d - security-unlock f2h - - - - d - seek 7xh - - y y y y set-features efh y - - - d - set-multiple-mode c6h - y - - d - set-sleep-mode e6h or 99h - - - - d - standby e2h or 96h - - - - d - standby-immediate e0h or 94h - - - - d -
data sheet nand controller gls55lc200 27 ?2010 greenliant systems, ltd. s71365-04-000 05/10 identify-drive - ech the identify-drive command enables the host to receive parameter info rmation from the nand controller. this command has the same protocol as the read-sector(s) command. the parameter words in the buffer have the arrangement and meanings defined in table 20. all reserved bits or words are zero. table 20 gives the definition for ea ch field in the identi fy-drive information. translate-sector 87h -yyyy y write-buffer e8h - - - - d - write-dma cah or cbh -yyyy y write-multiple c5h -yyyy y write-multiple-without-erase cdh - yyyy y write-sector(s) 30h or 31h -yyyy y write-sector(s)-without-erase 38h - yyyy y write-verify 3ch -yyyy y t0-0.1 1365 1.fr - features register 2.sc - sector count register 3.sn - sector number register 4.cy - cylinder registers 5.dh - drive/head register 6.lba - logical block address mode suppor ted (see command descriptions for use) 7.y - the register contains a valid parameter for this command. 8.for the drive/head register:y means both the nand controller and head parameters are used; d means only the nand controller parameter is valid and not the head parameter. bit -> 76543210 command (7) ech c/d/h (6) xdrive x cyl high (5) x cyl low (4) x sec num (3) x sec cnt (2) x feature (1) x table 20: identify-drive information (1 of 2) word address default value 1 total bytes data field type information 0 848ah 2 general configuration bit 1 bbbbh 2 2 default number of cylinders 2 0000h 2 reserved 3 bbbbh 2 2 default number of heads 4 xxxxh 2 reserved 5 xxxxh 2 reserved 6 bbbbh 2 2 default number of sectors per track 7-8 bbbbh 3 4 number of sectors per device (word 7 = msw, word 8 = lsw) 9 xxxxh 2 vendor unique 10-14 eeeeh 4 10 user-programmable serial number in ascii table 19: nand controller command set (continued) (2 of 2) command code fr 1 sc 2 sn 3 cy 4 dh 5 lba 6
28 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 15-19 ddddh 5 10 greenliant preset, unique id in ascii 20 0002h 2 buffer type 21 xxxxh 2 vendor unique 22 xxxxh 2 vendor unique 23-26 aaaah 6 8 firmware revision in ascii. big endian byte order in word 27-46 cccch 7 40 user definable model number 47 8001h 2 maximum number of sectors on read/write-multiple command 48 0000h 2 reserved 49 0b00h 2 capabilities 50 0000h 2 reserved 51 0200h 2 pio data transfer cycle timing mode 52 0000h 2 reserved 53 0007h 2 translation parameters are valid 54 nnnnh 2 current numbers of cylinders 55 nnnnh 2 current numbers of heads 56 nnnnh 2 current sectors per track 57-58 nnnnh 4 current capacity in sectors (lbas) (word 57 = lsw, word 58 = msw) 59 01xxh 2 multiple sector setting 60-61 nnnnh 4 total number of sectors addressable in lba mode 62 0000h 2 reserved 63 0x07h 2 dma data transfer is supported in nand controller 64 0003h 2 advanced pio transfer mode supported 65 0078h 2 120 ns cycle time support for multi-word dma mode-2 66 0078h 2 120 ns cycle time support for multi-word dma mode-2 67 0078h 2 pio mode-4 supported 68 0078h 2 pio mode-4 supported 69-79 0000h 22 reserved 80-81 0000h 4 reserved ? nand does not return an ata version 82 706ah 2 features/command sets supported 83 400ch 2 features/command sets supported 84 4000h 2 features/command sets supported 85-87 xxxxh 6 features/command sets enabled 88 xx1fh 2 udma modes 89 xxxxh 2 time required for securi ty erase unit completion 90 xxxxh 2 time required fo r enhanced security erase unit completion 91-127 0000h 74 reserved 128 xxxxh 2 security status 129-159 0000h 62 vendor unique bytes 160-162 0000h 6 reserved 163 xx12h 2 cf advanced true ide timing mode capabilities and settings 164 001bh 2 cf advanced pc card i/o and memory timing mode capability 165-255 0000h 184 reserved t0-0.4 1365 1. xxxx = this field is subject to change by the host or the device. 2. bbbb - default value set by controller. t he selections could be user programmable. table 20: identify-drive information (continued) (2 of 2) word address default value 1 total bytes data field type information
data sheet nand controller gls55lc200 29 ?2010 greenliant systems, ltd. s71365-04-000 05/10 word 0: general configuration word 0 indicates the general characteri stics of the device. depending on the desired configuration, this field can utilize standard or al ternate configur ation values. in standard configuration, when word 0 of the ident ify drive information is 848ah, then the device acts as a compactflash storage card, operating in compliance with the cfa sp ecification and command sets. pcmcia operation modes should only repo rt 848ah value if they are always intended as removable devices. bit function 15-0 standard configuration value 848ah: this is the recommended value. to use the compactflash as the root storage device, some systems require bit 6 of word 0 to be set to ?1.? this configuration is necessary when all the disk storage in a host is replaced by the cf in true ide mode. to allow for this alternate configuration, the following values for word 0 are valid. bit function 15-0 cf preferred alternate configuration values 044ah: alternate value of word 0. this value turns on ata device and turns off the removable media and removable device while preserving all retired bits. 0040h: this value turns on ata device and tu rns off the removable media and removable device while zeroing all retired bits. 15-12 configuration flag 8h: word 0 = 848ah 0h: bits [11:0] are set as described in below. the cf supports the cfa command set and report that in bit 2 of word 83. all other values for bits [15:12] are prohibited. word 1: default nu mber of cylinders this field contains the number of translated cylinders in the default translation mode. this value will be the same as the number of cylinders. word 3: default number of heads this field contains the number of tr anslated heads in the default translation mode. 3. n - calculated data based on product configuration 4. eeee - the default value is ?0000000000? 5. dddd - unique number of each device 6. aaaa - any unique greenliant firmware revision 7. cccc - default value is ?xxxmb nand? or ?xxxgb nand? where xxx is the flash drive capacity. the user has an option to change the model number during manufacturing. bit name definition 11-8 retired retired ata bit definitions. the value of these bits should be either the preferred value of ?0h? or the value of ?4h?. 7 removable media device 1: card contains media that can be removed during opera- tion 2: card contains non-removable media 6 not removable control- ler and/or device 1: card is non-removable during operation 2: card can be removed during operation. 5-0 retired/reserved retired ata bit definiti ons. these value of these bits should either be ?00h? or ?0ah?. bit 2 = ?0? bit 0 = ?0? (reserved) t0-0.0 1365
30 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 word 6: default number of sectors per track this field contains the number of sectors per track in the default translation mode. word 7-8: number of sectors this field contains the number of sect ors per nand controller. this double word value is also the first invalid addres s in lba translation mode. this field is only required by cf feature set support. word 10-19: serial number the contents of this field are right justif ied and padded with spaces (20h). the right- most ten bytes are a greenliant preset, unique id. the left-most ten bytes are a user-programmable value with a default value of spaces. word 20: buffer type this field defines th e buffer capability: 0002h: a dual ported multi-sector bu ffer capable of simultaneous data transfers to or from the host and the nand controller. word 23-26: firmware revision this field contains the revision of the firmware for this product. word 27-46: model number this field is reserved for the model number for this product. word 47: read-/write-multiple sector count this field contains the maximum number of sectors that can be read or written per interrupt using the read-multipl e or write-multiple command s. only value of ?1? is supported. word 49: capabilities bitfunction 13 standby timer 0: forces sleep mode when host is inactive. 11 iordy support 1: nand controller supports pio mode-4. 9 lba support 1: nand controller supports lba mode addressing. 8 dma support 1: dma mode is supported. word 51: pio data transfer cycle timing mode this field defines the mode for pio data transfer. nand controller supports up to pio mode-4. word 53: translation parameters valid bitfunction 0 1: words 54-58 are valid and reflect the cu rrent number of cylinders, heads and sectors. 1 1: words 64-70 are valid to support pio mode-3 and 4. 2 1: words 88 are valid to support ultra dma data transfer. word 54-56: current number of cylinders, heads, sectors/track these fields contains the current number of user addressable cylinders, heads, and sect ors/track in the current translation mode. word 57-58: cu rrent capacity this field contains the pr oduct of the current cylinders times heads times sectors. word 59: multiple sector setting this field contains a validity flag in the od d byte and the current number of sectors that can be transferred per interrupt for read/write multiple in the even byte. the odd byte is always 01h which indicates that the even byte is always valid.
data sheet nand controller gls55lc200 31 ?2010 greenliant systems, ltd. s71365-04-000 05/10 the even byte value depends on the value set by the se t multiple command. the even byte of this word by default contains a 00h which indicates that read/write mu ltiple commands are not valid. word 60-61: total sectors addressable in lba mode this field contains the number of sectors addressable for the nand controller in lba mode only. word 63: multi-word dma transfer mode this field identifies the multi-word dma transfer modes supported by the nand controller and indicates the mode that is curr ently selected. only one dm a mode can be selected at any given time. bit function 15-11 reserved 10 multi-word dma mode 2 selected 1: multi-word dma mode 2 is selected and bits 8 and 9 are cleared to 0 0: multi-word dma mode 2 is not selected. 9 multi-word dma mode 1 selected 1: multi-word dma mode 1 is selected and 8 and 10 should be cleared to 0. 0: multi-word dma mode 1 is not selected. 8 multi-word dma mode 0 selected 1: multi-word dma mode 0 is selected and bits 9 and 10 are cleared to 0. 0: multi-word dma mode 0 is not selected. 7-3 reserved 2 multi-word dma mode 2 supported 1: multi-word dma mode 2 and below are supported and bits 0 and 1 are set to 1. 1 multi-word dma mode 1 supported 1: multi-word dma mode 1 and below are supported. 0 multi-word dma mode 0 supported 1: multi-word dma mode 0 is supported. word 64: advanced pio data transfer mode bits (7:0) is defined as the pio data and register transfer supported field. if this field is suppor ted, bit 1 of word 53 shall be set to one. this field is bit signific ant. any number of bits may be set to one in this field by the device to indi cate the pio modes the device is capable of supporting. of these bits, bits (7:2) are reserved for future pio modes. bit function 0 1: nand controller supports pio mode-3. 1 1: nand controller supports pio mode-4. word 65: minimum multi-word dm a transfer cycle time per word this field defines the minimum multi-word dma transfer cycle time per word. this field defines, in nanoseconds, the minimum cycle time that the nand controller supports when performi ng multi-word dma transfers on a per word basis. greenliant?s nand controller supports up to multi-word dma mode-2, so this field is set to 120ns. word 66: device recommende d multi-word dma cycle time this field defines the nand controller recommended multi-word dma transfer cycle time. this field defines, in nanoseconds , the minimum cycle time per word during a single sector host transfer while pe rforming a multiple sector read dma or write dma command for any location on the media under nominal condi tions. if a host runs at a faster cycle rate by operating at a cycle time of less t han this value, the nand controller may negate dmarq for flow control. the rate at which dmarq is negated could result in reduced throughput despite the faster cycle rate. transfer at
32 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 this rate does not ensure that flow control will not be used, but implies that higher performance may result. greenliant?s nand controller supports up to multi-wo rd dma mode-2, so this field is set to 120 ns. word 67: minimum pio transfer cycle time without flow control this field defines, in nanoseconds, the minimum cycle time that, if used by the host, the device guarantees data integrity during the transfer without utilization of iordy flow cont rol. if this field is s upported, bit 1 of word 53 shall be set to one.the nand controller?s minimum cycle time is 1 20 ns. a value of 0078h is reported. word 68: minimum pio transfer cycle time with iordy this field defines, in na noseconds, the minimum cycle time that the devi ce supports while performi ng data transfers while utilizing iord y flow control. if this field is supported, bit 1 of word 53 shall be set to one. the nand controller?s minimum cycle time is 120 ns, e.g., pio mode-4. a value of 0078h is reported. words 82-84: features/command sets supported words 82, 83, and 84 indicate the features and command sets supported. a value of 706bh is reported. word 82 bit function 15 0: obsolete 14 1: nop command is supported 13 1: read buffer command is supported 12 1: write buffer command is supported 11 0: obsolete 10 0: host protected area feature set is not supported 9 0: device reset command is not supported 8 0: service interrupt is not supported 7 0: release interrupt is not supported 6 1: look-ahead is supported 5 1: write cache is supported 4 0: packet command feature set is not supported 3 1: power management feature set is supported 2 0: removable media feat ure set is not supported 1 1: security mode feature set is supported 0 0: smart feature set is not supported word 83 the values in this word should not be depended on by host implementers. bit function 15 0: provides indication th at the features/command sets supported words are not valid 14 1: provides indication that the feat ures/command sets supported words are valid 13-9 0: reserved 8 0: set-max security extension is not supported 7-5 0: reserved 4 0: removable media status feature set is not supported 3 1: advanced power management feature set is supported 2 1: cfa feature set is supported
data sheet nand controller gls55lc200 33 ?2010 greenliant systems, ltd. s71365-04-000 05/10 1 0: read dma queued and write dma queued commands are not supported 0 0: download microcode command is not supported word 84 the values in this word should not be depended on by host implementers. bit function 15 0: provides indication that the feat ures/command sets supported words are valid 14 1: provides indication that the feat ures/command sets supported words are valid 13-0 0: reserved words 85-87: features/command sets enabled words 85, 86, and 87 indicate features/command sets enabled. the host can enable/disable the feat ures or command set only if they are supported in words 82-84. word 85 bit function 15 0: obsolete 14 0: nop command is not enabled 1: nop command is enabled 13 0: read buffer command is not enabled 1: read buffer command is enabled 12 0:write buffer command is not enabled 1: write buffer command is enabled 11 0: obsolete 10 1: host protected area feature set is enabled 9 0: device reset command is not enabled 8 0: service interrupt is not enabled 7 0: release interrupt is not enabled 6 0: look-ahead is not enabled 1: look-ahead is enabled 5 0: write cache is not enabled 1: write cache is enabled 4 0: packet command feature set is not enabled 3 0: power management feature set is not enabled 1: power management feature set is enabled 2 0: removable media feat ure set is not enabled 1 0: security mode feature set has not been ena bled via the security set password command 1: security mode feature set has been enabl ed via the security set password command 0 0: smart feature set is not enabled word 86 bit function 15-9 0: reserved 8 0: set-max security extension not supported 7-5 0: reserved 4 0: removable media status feature set is not enabled 3 0: advanced power management feature set is not enabled
34 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 2 0: cfa feature set is disabled 1 0: read dma queued and write dma queued commands are not enabled 0 0: download microcode command is not enabled word 87 the values in this word should not be depended on by host implementers. bit function 15 0: provides indication that the feat ures/command sets supported words are valid 14 1: provides indication that the feat ures/command sets supported words are valid 13-0 0: reserved word 88: udma modes bitfunction 15-13 reserved 12 1: ultra dma mode 4 is selected 0: ultra dma mode 4 is not selected 11 1: ultra dma mode 3 is selected 0: ultra dma mode 3 is not selected 10 1: ultra dma mode 2 is selected 0: ultra dma mode 2 is not selected 9 1: ultra dma mode 1 is selected 0: ultra dma mode 1 is not selected 8 1: ultra dma mode 0 is selected 0: ultra dma mode 0 is not selected 7-5 reserved 4 1: ultra dma mode 4 and below are supported 3 1: ultra dma mode 3 and below are supported 2 1: ultra dma mode 2 and below are supported 1 1: ultra dma mode 1 and below are supported 0 1: ultra dma mode 0 is supported word 89: time required for se curity erase unit completion word 89 specifies the time required for the security erase unit command to complete. word 90: time required for enhanced security erase unit completion word 90 specifies the time required for the enhanced security erase unit command to complete. value time 0 value not specified 1-254 (value * 2) minutes 255 >508 minutes value time 0 value not specified 1-254 (value * 2) minutes
data sheet nand controller gls55lc200 35 ?2010 greenliant systems, ltd. s71365-04-000 05/10 word 128: security status bitfunction 8 security level 1: security mode is enabled and the security level is maximum 0: and security mode is enabled, indi cates that the security level is high 5 enhanced security erase unit feature supported 1: enhanced security erase unit feature set is supported 4expire 1: security count has expired and security unlock and security erase unit are command aborted until a power-on reset or hard reset 3 freeze 1: security is frozen 2lock 1: security is locked 1 enable/disable 1: security is enabled 0: security is disabled 0 capability 1: nand controller supports security mode feature set 0: nand controller does not s upport security mode feature set word 163: cf advanced true ide timing mode capabilities and settings this word describes the capabilities and current settings for cf modes utilizing the true ide interface. four separate fields determine support and selection options in the advanced pio and advanced multi-word dma timing modes. for information on the older modes, see ?word 63: multi-word dma transfer mode? on page 31 and ?word 64: advanced pio data transfer mode? on page 31. when the identity drive command executes, the device returns 0492h. bit function 2-0 advanced true ide pio mode support indicates the maximum true ide pio mode supported by the card 5-3 advanced true ide multi-word dma mode support indicates the maximum true ide multi-wo rd dma mode supported by the card 255 >508 minutes value time 0 specified in word 64 1 pio mode 5 2 pio mode 6 3-7 reserved value time 0 specified in word 63 1 multiword dma mode 3 2 multiword dma mode 4 3-7 reserved value time
36 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 8-6 advanced true ide pio mode selected indicates the current true id e pio mode selected on the card 11-9 advanced true ide multi-word dma mode selected indicates the current true ide multi-word dma mode selected on the card 15-12 reserved set-features - efh this command is used by the host to establish or se lect certain features. table 21 defines all features that are supported. value time 0 specified in word 64 1 pio mode 5 2 pio mode 6 3-7 reserved value time 0 specified in word 63 1 multiword dma mode 3 2 multiword dma mode 4 3-7 reserved bit ->76543210 command (7) efh c/d/h (6) x drive x cyl high (5) x cyl low (4) x sec num (3) x sec cnt (2) config feature (1) feature table 21: features supported feature operation 01h enable 8-bit data transfers. 02h 1 enable write cache 03h set transfer mode based on value in sector count register. table 22 defines the values. 09h enable extended power operations 0ah nop - accepted for backward compatibility. 55h 1 disable read look ahead. 66h disable power-on reset (por) establishment of defaults at software reset. 69h nop - accepted for backward compatibility. 81h disable 8-bit data transfer. 82h 1 disable write cache 89h disable extended power operations 8ah nop - accepted for backward compatibility.
data sheet nand controller gls55lc200 37 ?2010 greenliant systems, ltd. s71365-04-000 05/10 features 01h and 81h are used to enable and clea r 8-bit data transfer mode. if the 01h feature command is issued all data transf ers will occur on the low order d 7 -d 0 data bus and the iocs16# signal will not be asserted for data register accesses. feature 03h allows the host to select the transfer mode by specifying a value in the sector count register. the upper 5 bits define the type of tran sfer and the low order 3 bits encode the mode value. one pio mode is selected at all times. the host may change the selected modes by the set-features command. features 66h and cch c an be used to enable and disable whether the power-on reset (por) defaults will be set when a software reset occurs. 96h nop - accepted for backward compatibility. 97h accepted for backward compatibility. use of this feature is not recommended. 9ah 2 set the host current source capability allows trade-off between current drawn and read/write speed bbh 4 bytes of data apply on read/write-long-sector commands. aah enable read-look-ahead cch enable power-on reset (por) establishment of defaults at software reset. t0-0.0 1365 1. greenliant nand controller does not implement cache operations. these commands are returned with no error. 2. greenliant nand controller has fixed power consumption. the command will be accepted and returned with no error. table 22: transfer mode values mode bits [7:3] bits [2:0] pio default mode 00000b 000b pio default mode, disable iordy 00000b 001b pio flow control transfer mode 00001b mode 1 1. mode = transfer mode number, all other values are not valid multi-word dma mode 00100b mode 1 ultra-dma mode 01000b mode 1 reserved other n/a t0-0.0 1365 table 21: features supported feature operation
38 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 error posting the following table summarizes the valid status and error value fo r all the cf-ata command set. note: v = valid on this command table 23: error and status register error register status register command bbk unc idnf abrt amnf drdy dwf dsc corr err check-power-mode v v v v v execute-drive-diagnostic v v v erase-sector(s) v vvvvvv v flush-cache v vvv v format-track vvvvvv v identify-drive v v v v v idle v vvv v idle-immediate v v v v v initialize-drive-parameters v v v nop v v v v read-buffer v v v v v read-dma vvvvvvvvvv read-multiple v v vvvvvvvv read-sector(s) v v vvvvvvvv read-verify-sectors v v vvvvvvvv recalibrate v v v v v request-sense vvvv security-disable-password v v v v v security-erase-prepare v v v v v security-erase-unit v v v v v security-freeze-lock v v v v v security-set-password v v v v v security-unlock v vvv v seek vv vvv v set-features v v v v v set-multiple-mode v v v v v set-sleep-mode v v v v v stand-by v v v v v stand-by-immediate v v v v v translate-sector v vvvvvv v write-buffer v v v v v write-dma v vvvvvv v write-multiple v vvvvvv v write-multiple -w/o-erase v vvvvvv v write-sector(s) v vvvvvv v write-sector(s)-w/o-erasev vvvvvv v write-verify v vvvvvv v invalid-command-code v v v v v t0-0.0 1365
data sheet nand controller gls55lc200 39 ?2010 greenliant systems, ltd. s71365-04-000 05/10 electrical specifications absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater th an those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress ra ting conditions may affe ct device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d.c. voltage on pins 1 i3, i4, o4, and o5 to ground potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v 1. please refer to table 1 for pin assignment information. transient voltage (<20 ns) on pins 1 i3, i4, o4, and o5 to ground potential . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v d.c. voltage on pins 1 i1, i2, o1, o2, and o6 to ground potential . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v ddq +0.5v transient voltage (<20 ns) on pins 1 i1, i2, o1, o2, and o6 to ground potential . . . . . . . . . . . . -2.0v to v ddq +2.0v package power dissipa tion capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hole lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 2. outputs shorted for no more than one second. no more than one output shorted at a time. table 24: absolute maximum power pin stress ratings parameter symbol conditions input power v ddq v dd -0.3v min to 6.5v max -0.3v min to 4.0v max voltage on any flash media interface pin with respect to v ss -0.5v min to v dd + 0.5v max voltage on all other pins with respect to v ss -0.5v min to v ddq + 0.5v max t0-0.0 1365 table 25: operating range range ambient temperature v dd v ddq 3.3v 3.3v 5v minmaxminmaxminmax commercial 0c to +70c 3.135v 3.465v 3.135v 3.465v 4.5v 5.5v industrial -40c to +85c 3.135 v3.465v3.135v3.465v 4.5v 5.5v table 26: ac conditions of test input rise/fall time . . . . . . . . . . . . . . 10 ns output load media. . . . . . . . . . . . . . . . c l = 100 pf for 3.3v / 80 pf for 3v output load host . . . . . . . . . . . . . . . . . c l = 100 pf see figure 4 note: all ac specifications are guaranteed by design.
40 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 dc characteristics table 27: recommended system power-on timing symbol parameter typical maximum units t pu-initial drive initialization to ready 3 sec + (0.5 sec/ gbyte) 100 sec t pu-ready1 1 host power-on/reset to ready operation 200 1000 ms t pu-write1 1 host power-on/reset to write operation 200 1000 ms t0-0.3 1365 1. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this paramet er. table 28: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 i/o pin capacitance v i/o = 0v 10 pf c in 1 input capacitance v in = 0v 10 pf t0-0.0 1365 1. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this paramet er. table 29: reliability characteristics symbol parameter minimum sp ecification units test method i lth 1 1. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this paramet er. latch up 100 + i dd ma jedec standard 78 t0-0.0 1365 table 30: dc characteristics for media interface v dd = 3.3v symbol type parameter min max units conditions v ih3 i3 input voltage 2.0 v v dd =v dd max v il3 0.8 v dd =v dd min i il3 i3z input leakage current -10 10 ua v in = gnd to v dd , v dd = v dd max i u3 i3u input pull-up current -160 -20 ua v in = gnd, v dd = v dd max v t+4 i4 input voltage schmitt trigger 2.0 v v dd = v dd max v t-4 0.8 v dd = v dd min i il4 i4z input leakage current -10 10 ua v in = gnd to v dd , v dd = v dd max v oh4 o4 output voltage 2.4 v i oh4 =i oh4 min v ol4 0.4 i ol4 =i ol4 max i oh4 output current -2 ma v dd =v dd min i ol4 output current 2 ma v dd =v dd min v oh5 o5 output voltage 2.4 v i oh5 =i oh5 min v ol5 0.4 i ol5 =i ol5 max i oh5 output current -4 ma v dd =v dd min i ol5 output current 4 ma v dd =v dd min t0-0.0 1365
data sheet nand controller gls55lc200 41 ?2010 greenliant systems, ltd. s71365-04-000 05/10 table 31: dc characteristics for host interface v ddq = 3.3v or v ddq = 5v symbol type parameter min max units conditions v ih1 i1 input voltage 2.0 v v ddq =v ddq max v il1 0.8 v ddq =v ddq min i il1 i1z input leakage current -10 10 ua v in = gnd to v ddq , v ddq = v ddq max i u1 i1u input pull-up current -150 -6 ua v out = gnd, v ddq = v ddq max v t+2 i2 input voltage schmitt trigger 2.0 v v ddq =v ddq max v t-2 0.8 v ddq =v ddq min i il2 i2z input leakage current -10 10 ua v in = gnd to v ddq , v ddq = v ddq max i u2 i2u input pull-up current -150 -6 ua v out = gnd, v ddq = v ddq max v oh1 o1 output voltage 2.4 v i oh1 =i oh1 min v ol1 0.4 i ol1 =i ol1 max i oh1 output current -4 ma v ddq =v ddq min i ol1 output current 4 ma v ddq =v ddq min v oh2 o2 output voltage 2.4 v i oh2 =i oh2 min v ol2 0.4 i ol2 =i ol2 max i oh2 output current -8 ma v ddq min i ol2 output current 8 ma v ddq min v oh6 o6 output voltage for dasp# pin 2.4 v i oh6 =i oh6 min v ol6 0.4 i ol6 =i ol6 max i oh6 output current for dasp# pin -4 ma v ddq min i ol6 output current for dasp# pin 12 ma v ddq max t0-0.1 1365 table 32: power consumption symbol type parameter min max units conditions i dd 1,2 1. sequential data transfer for 1 sector read data from host interface and write data to media. 2. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this paramet er. pwr power supply current (t a = 0c to +70c) 50 ma v dd =v dd max; v ddq =v ddq max i dd 1,2 pwr power supply current (t a = -40c to +85c) 100 ma v dd =v dd max; v ddq =v ddq max i sp pwr sleep/standby/idle current (t a = 0c to +70c) 700 a v dd =v dd max; v ddq =v ddq max i sp pwr sleep/standby/idle current (t a = -40c to +85c) 950 a v dd =v dd max; v ddq =v ddq max t0-0.1 1365
42 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 ac characteristics figure 4: ac input/output reference waveforms media side interface timing specifications note: all ac specifications are guaranteed by design. 1365 f02.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <10 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test table 33: gls55lc200 timing specifications symbol parameter min max units t cls fcle setup time 30 - ns t clh fcle hold time 20 - ns t cs fce# setup time 30 - ns t ch fce# hold time for command/data write cycle 20 - ns t chr fce# hold time for sequential read last cycle 15 - ns t wp fwe# pulse width 16 - ns t wh fwe# high hold time 10 - ns t wc write cycle time 30 - ns t als fale setup time 30 - ns t alh fale hold time 20 - ns t ds fad[15:0] setup time 15 - ns t dh fad[15:0] hold time 5 - ns t rp fre# pulse width 16 - ns t rr ready to fre# low 20 - ns t res fre# data setup time 4 - ns t rc read cycle time 30 - ns t reh fre# high hold time 10 - ns t0-0.0 1365
data sheet nand controller gls55lc200 43 ?2010 greenliant systems, ltd. s71365-04-000 05/10 figure 5: media command latch cycle figure 6: media address latch cycle fcle fce# fwe# fale f ad[15:0] or fad[7:0] command t ds t dh t alh t wp t clh t cls t cs t ch 1365 f25 .1 t als fce# fwe# fale fad[15:0] or fad[7:0] t cs t wc 1365 f26.0 a byte0 a byte1 a byte2 t ds t ds t dh t dh t dh t dh t dh t ds t ds t ds t als t alh t wp t wh t wh t wc fcle t wp t wp t wp t wh t wh t wc t wc a byte3 a byte4
44 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 figure 7: media data loading latch cycle figure 8: media data read cycle fcle fce# fale fwe# f ad[15:0] or fad[7:0] 1365 f27.0 t ds t dh t wp t wp t wp t wh t ds t ds t dh t dh t wc d in 0d in 1d in final t ch t chr 1365 f28.0 f rbybsy# fce# fre# fad[15:0] or fad[7:0] d out 0 d out final d out 1 t rr t res t reh t res t rp t res t rc
data sheet nand controller gls55lc200 45 ?2010 greenliant systems, ltd. s71365-04-000 05/10 appendix differences between cf-ata and pc card- ata/true ide this section details differences betw een cf-ata vs. pc card ata and the differences between cf-ata vs. true ide. electrical differences ttl compatibility cf is not ttl compatible, it is a purely cmos in terface. refer to sectio n 2.3.2 of this specifi- cation. pull up resistor input leakage current the minimum pull up resistor input leakage current is 50k ohms rather than the 10k ohms stated in the pcmcia specification. functional differences additional set features codes in cf-ata the following set features codes are not pc card ata or true ide, but provide additional functionality in cf-ata. ? 69h, accepted for backward compatibility ? 96h, accepted for backward compatibility ? 97h, accepted for backward compatibility ? 9ah, set the host curr ent source capability additional commands in cf-ata the following commands are not standard pc card ata commands, but pro- vide additional functionality in cf-ata. the command codes for the commands below are defined as vendor unique in pc card ata/true ide. ? c0h, erase-sectors ? 87h, translate-sector the command codes for the commands below are defin ed as reserved in pc card ata/true ide: ? 03h, request-sense ? 38h, write-without-erase ? cdh, write-mult iple-without-erase idle timer the idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value spec- ified in pc card ata/true ide. recovery from sleep mode for cf devices, recovery from sleep mo de is accomplished by simply issuing another command to the device. a hardware or software reset is not required.
data sheet nand controller gls55lc200 46 ?2010 greenliant systems, ltd. s71365-04-000 05/10 product ordering information valid combinations valid combinations for gls55lc200 GLS55LC200-60-C-TQWE gls55lc200-60-i-tqwe note: valid combinations are those products in mass production or will be in mass production. consult your greenliant sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. gls 55 lc 200 - 60 - c - tqw e xx xx xxx -xx -x -xx x x environmental attribute e 1 = non-pb package modifier w = 100 leads package type tq = tqfp operation temperature c = commercial: 0c to +70c i = industrial: -40c to +85c frequency 60 = 60 mhz device number 200 = udma/cf controller function c = compactflash controller voltage l = 3.3v product series 55 = nand controller 1. environmental suffix ?e? denotes non-pb solder. greenliant non-pb solder devic es are ?rohs compliant?.
47 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 packaging diagram figure 9: 100-lead thin qu ad flat pack (tqfp) greenliant package code: tqw .45 .75 1.00 nominal 0 ? - 7 ? .95 1.05 .05 .15 detail note: 1. complies with jedec publication 95 ms-026 variant aed dimensions although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 mm. 4. package body dimensions do not include mold flash. maximum allowable mold flash is 0.25 mm. top view 100-tqfp-tqw-0 0.17 0.27 0.50 bsc pin #1 identifier 14.00 bsc 16.00 bsc 14.00 bsc 16.00 bsc .09 .20 1.10 0.10 1mm
data sheet nand controller gls55lc200 48 ?2010 greenliant systems, ltd. s71365-04-000 05/10 table 34: revision history number description date 00 ? initial release of data sheet jan 2008 01 ? changed fwp# to dnu in pin assignment fi gure, page 8 and pin assignment table, page 13 ? in table 33, removed t chr and t rhz . edited min/max values ? edited figure 6 and figure 8 ? deleted f5h, wear-level from 10.1.2.2 ?additional commands in cf-ata? on page 45 ? edited text in 6.0 ?power-on and brown-out reset characteristics? on page 13 may 2008 02 ? globally changed product name from compac tflash card controlle r to nand controller may 2009 03 ? transferred from sst to greenliant may 2010 04 ? in table 1 on page 10, added ?connect this pin with a 4.7uf capacitor to ground.? to vreg ?external capacitor pin?. oct 2010
49 data sheet nand controller gls55lc200 ?2010 greenliant systems, ltd. s71365-04-000 05/10 pcmcia standard compactflash memory cards are fully electrically compatible with the pcmcia specifications listed below. these specifications may be obtained from: pcmcia 2635 north first st. ste. 209 san jose, ca 95131 usa phone: 408-433-2273 fax: 408-433-9558 compactflash specification compactflash memory cards are fully compatible with the compactflash specification published by the compact- flash association. contact t he compactflash association for more information. compactflash association p.o. box 51537 palo alto, ca 94303 usa ? 2010 greenliant systems, ltd. all rights reserved. greenliant, the greenliant logo , and nandrive are trademarks of greenliant systems, ltd. all trademarks and registered trademarks are the property of their respective owners. some content is reproduced from the compac tflash specification (2.0) by permission of the compactflash association. other content is reproduced from the ata/atapi-6 (t13/1410d revision 3b) specif ication by permission of the national committee for information technology standards. these specifications are subj ect to change without notice. superflash is a registered trademar k of silicon storage technology, inc, a wholly owned subsidiary of microchip technology inc.

▲Up To Search▲

Price & Availability of GLS55LC200-60-C-TQWE

	To Download GLS55LC200-60-C-TQWE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .