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infineon technologies 1 10.01 hys 72dxx5xxgr low profile registered ddr-i sdram-modules 2.5 v low profile 184-pin registered ddr-i sdram modules 128mb, 256mb, 512mb, 1gbyte & 2gbyte modules pc1600 & pc2100 the hys72dxx5x0gr are low profile versions of the standard registered dimm modules with 1.2? inch (30,40 mm) height for 1u server applications. the low profile dimm versions are available as 16m x 72 (128mb), 32m x 72 (256mb), 64m x 72 (512mb), 128m x 72 (1 gb) and 256m x 72 (2gb). the memory array is designed with double data rate synchronous drams for ecc applications. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. 184-pin registered 8-byte dual-in-line ddr-i sdram module for ?1u? pc, workstation and server main memory applications one bank 16m x 72, 32m 72, 64m x 72 and two bank 128m 72 and 256m x 72 organization jedec standard double data rate synchronous drams (ddr-i sdram) with a single + 2.5 v ( 0.2 v) power supply built with ddr-i sdrams in 66-lead tsopii package programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible re-drive for all input signals using register and pll devices. serial presence detect with e 2 prom low profile modules form factor: 133.35 mm x 30,40 mm (1.2?) x 4.00 mm (6,80 mm with stacked components) based on jedec standard reference card layouts rawcard ?l?, ?m? gold plated contacts performance: -7 -8 unit component speed grade ddr266a ddr200 module speed grade pc2100 pc1600 f ck clock frequency (max.) @ cl = 2.5 143 125 mhz f ck clock frequency (max.) @ cl = 2 133 100 mhz target datasheet rev. 0.6 (10.01)
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 2 10.01 ordering information type compliance code description sdram technology module height pc2100 (cl=2) : hys72d16500gr-7 pc2100r-20330-l one bank 128 mb reg. dimm 128 mbit (x8) 1.2 ? hys 72d32501gr-7 pc2100r-20330-m one bank 256 mb reg. dimm 128 mbit (x4) 1.2 ? hys 72d32500gr-7 pc2100r-20330-l one bank 256 mb reg. dimm 256 mbit (x8) 1.2 ? hys 72d64500gr-7 pc2100r-20330-m one bank 512 mb reg. dimm 256 mbit (x4) 1.2 ? hys 72d128520gr-7 pc2100r-20330- *) two banks 1 gbyte reg. dimm 256 mbit (x4) (stacked) 1.2 ? hys 72d256520gr-7 pc2100r-20330-*) two banks 2 gbyte reg. dimm 512 mbit (x4) (stacked) 1.2 ? pc1600 (cl=2): hys72d16500gr-8 pc1600r-20220-l one bank 128 mb reg. dimm 128 mbit (x8) 1.2 ? hys 72d32501gr-8 pc1600r-20220-m one bank 256 mb reg. dimm 128 mbit (x4) 1.2 ? hys 72d32500gr-8 pc1600r-20220-l one bank 256 mb reg. dimm 256 mbit (x8) 1.2 ? hys 72d64500gr-8 pc1600r-20220-m one bank 512 mb reg. dimm 256 mbit (x4) 1.2 ? hys 72d128520gr-8 pc1600r-20220-*) two banks 1 gbyte reg. dimm 256 mbit (x4) (stacked) 1.2 ? hys 72d256520gr-8 pc1600r-20220-*) two banks 2 gbyte reg. dimm 512 mbit (x4) (stacked) 1.2 ? notes: 1. all part numbers end with a place code (not shown), designating the silicon-die revision. reference information available on request. example: hys 72d32500gr-8-a, indicating rev.a die are used for sdram components. 2. the compliance code is printed on the module labels and describes the speed sort fe. ? pc2100r ? , the latencies (f.e. ? 20330 ? means cas latency = 2.5, trcd latency = 3 and trp latency =3 ) and the raw card used for this module 3. *) n.d.y..
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 3 10.01 pin definitions and functions a0 - a11,a12 address inputs (a12 for 256mb & 512mb based modules) v dd power (+ 2.5 v) ba0, ba1 bank selects v ss ground dq0 - dq63 data input/output v ddq i/o driver power supply cb0 - cb7 check bits (x72 organization only) v ddid vdd indentification flag ras row address strobe v ddspd eeprom power supply cas column address strobe v ref i/o reference supply we read/write input scl serial bus clock cke0, cke1 clock enable sda serial bus data line dqs0 - dqs8 sdram low data strobes sa0 - sa2 slave address select ck0, ck0 differential clock input nc no connect dm0 - dm8 dqs9 - dqs17 sdram low data mask/ high data strobes du don ? t use cs0 - cs1 chip selects reset reset pin (forces register inputs low) *) *) for detailed description of the power up and power management on ddr registered dimms see the application note at the end of this datasheet address format density organization memory banks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 128 mb 16m x 72 1 (128mb) 16m x 8 9 12/2/10 4k 64 ms 15.6 s 256 mb 32m x 72 1 (128 mb) 32m x 4 18 12/2/11 4k 64 ms 15.6 s 256 mb 32m x 72 1 (256mb) 32m x 8 9 13/2/10 8k 64 ms 7.8 s 512 mb 64m 72 1 (256mb) 64m 4 18 13/2/11 8k 64 ms 7.8 s 1 gb 128m 72 2 (256mb) 64m 4 36 (stacked) 13/2/11 8k 64 ms 7.8 s 2 gb 256m x 72 2 (512mb) 128m 4 36 (stacked) 13/2/12 8k 64 ms 7.8 s
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 4 10.01 pin configuration pin# symbol pin# symbol pin# symbol symbol 1 vref 48 a0 93 vss 140 dm8/dqs17 2 dq0 49 cb2 94 dq4 141 a10 3 vss 50 vss 95 dq5 142 cb6 4 dq1 51 cb3 96 vddq 143 vddq 5 dqs0 52 ba1 97 dm0/dqs9 144 cb7 6dq2 key 98 dq6 key 7 vdd 53 dq32 99 dq7 145 vss 8 dq3 54 vddq 100 vss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 reset 56 dqs4 102 nc 148 vdd 11 vss 57 dq34 103 nc 149 dm4/dqs13 12 dq8 58 vss 104 vddq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 vss 15 vddq 61 dq40 107 dm1/dqs10 153 dq44 16 du 62 vddq 108 vdd 154 ras 17 du 63 we 109 dq14 155 dq45 18 vss 64 dq41 110 dq15 156 vddq 19 dq10 65 cas 111 cke1 157 cs0 20 dq11 66 vss 112 vddq 158 cs1 21 cke0 67 dqs5 113 nc 159 dm5/dqs14 22 vddq 68 dq42 114 dq20 160 vss 23 dq16 69 dq43 115 nc / a12 161 dq46 24 dq17 70 vdd 116 vss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 vss 72 dq48 118 a11 164 vddq 27 a9 73 dq49 119 dm2/dqs11 165 dq52 28 dq18 74 vss 120 vdd 166 dq53 29 a7 75 du 121 dq22 167 nc 30 vddq 76 du 122 a8 168 vdd 31 dq19 77 vddq 123 dq23 169 dm6/dqs15 32 a5 78 dqs6 124 vss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 vss 80 dq51 126 dq28 172 vddq 35 dq25 81 vss 127 dq29 173 nc 36 dqs3 82 vddid 128 vddq 174 dq60 37 a4 83 dq56 129 dm3/dqs12 175 dq61 38 vdd 84 dq57 130 a3 176 vss 39 dq26 85 vdd 131 dq30 177 dm7/dqs16 40 dq27 86 dqs7 132 vss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 vss 88 dq59 134 cb4 180 vddq 43 a1 89 vss 135 cb5 181 sa0 44 cb0 90 nc 136 vddq 182 sa1 45 cb1 91 sda 137 ck0 183 sa2 46 vdd 92 scl 138 ck0 184 vddspd 47 dqs8 139 vss note: a12 is used for 256mbit and 512mbit based modules only
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 5 10.01 block diagram: one bank 16m x 72 & 32m x 72 ddr-i sdram dimm module (x8 components) hys72d16500gr & hys72d32500gr on raw card l pck pck dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm d0 dm0/dqs9 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm4/dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm7/dqs16 rs 0 cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 7 i/o 6 i/o 1 i/o 0 d8 i/o 5 i/o 4 i/o 3 i/o 2 cs dqs8 dm8/dqs17 dqs dqs dqs dqs dqs ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams cs0 rs 0 -> cs : sdrams d0-d8 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d8 a0-a12 ra0-ra12 -> a0-a12: sdrams d0 - d8 ras rras -> ras : sdrams d0 - d8 cas rcas -> cas : sdrams d0 - d8 cke0 rcke0 -> cke: sdrams d0 - d8 we rw e -> we : sdrams d0 - d8 r e g i s t e r reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, adress and control resistors: 22 ohms. 4. vddid strap connections strap out (open): vdd = vddq 5. sdram placement alternates between the back and front of the dimm. v dd, v ss d0 - d8 d0 - d8 v ddq d0 - d8 d0 - d8 vref v ddid strap: see note 4 v ddspd eeprom a0 serial pd a1 a2 sa0 sa1 sa2 scl sda
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 6 10.01 block diagram: one bank 32m x 72 and 64m x 72 ddr-i sdram dimm modules (x4 comp.) hys72d32501gr & hys72d64500gr on raw card m rs 0a dqs4 dqs6 dqs2 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq56 dq57 dq58 dq59 dqs d0 dqs dqs dqs dqs dqs dqs dqs0 d1 d2 d3 d4 d5 d7 dq48 dq49 dq50 dq51 dqs d6 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq60 dq61 dq62 dq63 dqs d9 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dm0/dqs9 d10 d11 d12 d13 d14 d16 dq52 dq53 dq54 dq55 dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 cb0 cb1 cb2 cb3 dqs d8 cb4 cb5 cb6 cb7 dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs vss dqs1 dqs3 dqs8 dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dqs5 dqs7 dm6/dqs15 dm5/dqs14 dm4/dqs13 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm7/dqs16 dm8/dqs17 rs 0b ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d17 a0-a11,a12 ra0-ra11,ra12 -> a0-a11,a12: sdrams d0 - d17 ras rras -> ras : sdrams d0 - d17 cs0 cas rcas -> cas : sdrams d0 - d17 cke0 rcke0a -> cke: sdrams d0 - d8 we rwe -> we : sdrams d0 - d17 r e g i s t e r rckeb -> cke: sdrams d9 - d17 pck pck reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, adress and control resistors: 22 ohms. 4. vddid strap connections strap out (open): vdd = vddq 5. sdram placement alternates between the back and front of the dimm. v dd, v ss v ddq vref v ddid strap: see note 4 v ddspd eeprom d0 - d17 d0 - d17 d0 - d17 rs 0 -> cs : sdrams d0-d17
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 7 10.01 block diagram: two bank 128m x 72 and 256m x 72 ddr-i sdram dimm modules (x4 comp.) hys72d128520gr and hys72d256520gr on raw card (t.b.d.) pc k pc k rs 0 dqs4 dqs6 dqs2 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq56 dq57 dq58 dq59 dqs d0 dqs dqs dqs dqs dqs dqs dqs0 d1 d2 d3 d4 d5 d7 dq48 dq49 dq50 dq51 dqs d6 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq60 dq61 dq62 dq63 dqs d9 dqs dqs dqs dqs dqs dqs dm0/dqs9 d10 d11 d12 d13 d14 d16 dq52 dq53 dq54 dq55 dqs d15 ck0, ck 0 --------- pll* cs cs cs cs cs cs cs cs cs cs cs s cs cs cs cs cs1 rs 1 -> cs : sdrams d18 -d35 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d35 a0-a12 ra0-ra12 -> a0-a12: sdrams d0 - d35 ras rras -> ras : sdrams d0 - d35 cs0 rs 0 -> cs : sdrams d0-d17 v ss dqs1 dqs3 dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dqs5 dqs7 dm6/dqs15 dm5/dqs14 dm4/dqs13 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm7/dqs16 * wire per clock loading table/wiring diagrams rs 1 cas rcas -> cas : sdrams d0 - d35 cke0 rcke0 -> cke: sdrams d0 - d17 we rwe -> we : sdrams d0 - d35 r e g i s t e r rcke1 -> cke: sdrams d18 - d35 dqs d18 dqs dqs dqs dqs dqs dqs d19 d20 d21 d22 d23 d25 dqs d24 cs cs cs cs cs cs cs cs dm dm dm dm dm dm dm dm dqs d27 dqs dqs dqs dqs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 d29 d30 d31 d32 d34 dqs d33 cs cs cs cs cs s cs cs dm dm dm dm dm dm dm dm cb0 cb1 cb2 cb3 dqs d8 cs dm dqs8 dqs d26 cs dm cb4 cb5 cb6 cb7 dqs d17 cs dm dm8/dqs17 dqs d35 cs dm cke1 reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, adress and control resistors: 22 ohms. 4. vddid strap connections strap out (open): vdd = vddq 5. sdram placement alternates between the back and front of the dimm. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v dd, v ss v ddq vref v ddid strap: see note 4 v ddspd eeprom d0 - d35 d0 - d35 d0 - d35
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 8 10.01 absolute maximum ratings parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ? 0.5 3.6 v power supply voltage on v dd /v ddq to v ss v dd, v ddq ? 0.5 3.6 v storage temperature range t stg -55 +150 o c power dissipation (per sdram component) p d ? 1w data out current (short circuit) i os ? 50 ma permanent device damage may occur if ? absolute maximum ratings ? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability supply voltage levels parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 2.3 2.5 2.7 v - output supply voltage v ddq 2.3 2.5 2.7 v 1) input reference voltage v ref 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v2) termination voltage v tt v ref ? 0.04 v ref v ref +0.04 v 3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v 1 under all conditions, v ddq must be less than or equal to v dd 2 peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 3 v tt of the transmitting device must track v ref of the receiving device. dc operating conditions (sstl_2 inputs) ( v ddq = 2.5 v, t a=70 c, voltage referenced to v ss) parameter symbol limit values unit notes min. max. dc input logic high v ih (dc) v ref +0.18 v ddq +0.3 v 1) dc input logic low v il (dc) ? 0.30 v ref ? 0.18 v ? input leakage current i il ? 55 a1) output leakage current i ol ? 55 a2) 1) the relationship between the v ddq of the driving device and the v ref of the receiving device is what determines noise margins. however, in the case of v ih (max) (input overdrive), it is the v ddq of the receiving device that is referenced. in the case where a device is implemented such that it supports sstl_2 inputs but has no sstl_2 outputs (such as a translator), and therefore no v ddq supply voltage connection, inputs must tolerate input overdrive to 3.0 v (high corner v ddq + 300 mv). 2) for any pin under test input of 0 v v in v ddq + 0.3 v. values are shown per ddr-sdram component.
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 9 10.01 operating, standby and refresh currents (pc1600) sym- bol parameter/condition hys72d16500 gr-8 hys72d32501 gr-8 hys72d32500 gr-8 hys72d64500 gr-8 hys72d128520 gr-8 hys72d256520 gr-8 unit notes dram technology: 128 256 512 mb i dd0 operating current - one bank active - precharge ; t rc = t rc min ; t ck = 10 ns; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once per every two cycles tbd. tbd. 815 1401 1668 tbd. ma 1,3 i dd1 operating current - one bank active / read / precharge ; burst = 4; reads; refer to the detailed test conditions in the component datasheet tbd. tbd. 899 1552 2022 tbd. ma 1,3 i dd2p precharge power-down standby current : all banks idle; power-down mode; cke v il max ; t ck = 10 ns tbd. tbd. 442 578 862 tbd. ma 1,4 i dd2f precharge floating standby current : cs v ih min , all banks idle; cke v ih min ; t ck = 10 ns, address and other control inputs changing once per clock cycle, v in = v ref for dq, dqs and dm. tbd. tbd. 573 845 1390 tbd. ma 1,4 i dd2q precharge quiet standby current : cs v ih min , all banks idle; cke v ih min ; t ck = 10 ns,address and other control inputs stable at v ih min or v il max ; v in = v ref for dq, dqs and dm. tbd. tbd. 573 845 1390 tbd. ma 1,4 i dd3p active power-down standby current : one bank active; power-down mode; cke v il max ; t ck = 10 ns tbd. tbd. 426 566 824 tbd. ma 1,4 i dd3n active standby current : one bank; active / precharge;cs v ih min ; cke v ih min ; t rc = t ras max ; t ck = 10 ns; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd. tbd. 712 1152 1645 tbd. ma 1,4 i dd4r operating current - burst read: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2; t ck = 10 ns; i out = 0ma tbd. tbd. 1529 2167 2661 tbd. ma 1,3 i dd4w operating current - burst write: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl = 2; t ck = 10 ns tbd. tbd. 1126 1824 2380 tbd. ma 1,3 i dd5 auto-refresh current : t rc = t rfc min, distributed refresh tbd. tbd. 1299 2350 4647 tbd. ma 1,3 i dd6 self-refresh current with pll-on : cke 0.2v, pll on, address and control signals toggling tbd. tbd. 364 417 550 tbd. ma 1,2,4 i dd6a self-refresh current with pll-off : cke 0.2v, pll off, no toggling of address and control signals tbd. tbd. tbd. tbd. tbd. tbd. ma 1,2,4 i dd7 operating current - four bank operation ; four bank inter- leaving with bl=4; refer to the detailed test conditions in the component datasheet tbd. tbd. 2346 3869 4201 tbd. ma 1,3 1. i dd currents are measured after the device is properly initialized. typical values are obtained from characterisation data mea- sured at vdd = 2.5 v and r.t. with an input slew rate = 1v/ns. 2. enables on-chip refresh and address counters. 3. for two bank modules only : the other bank is in idd3n mode 4. for two bank modules only : both banks operate in the same current mode
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 10 10.01 operating, standby and refresh currents (pc2100) sym- bol parameter/condition hys72d16500 gr-7 hys72d32501 gr-7 hys72d32500 gr-7 hys72d64500 gr-7 hys72d128520 gr-7 hys72d256520 gr-7 unit notes dram technology: 128 256 512 mb i dd0 operating current - one bank active - precharge ; t rc = t rc min ; t ck = 7.5 ns; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once per every two cycles tbd. tbd. tbd. tbd. tbd. tbd. ma 1,3 i dd1 operating current - one bank active / read / precharge ; burst = 4; reads; refer to the detailed test conditions in the component datasheet tbd. tbd. tbd. tbd. tbd. tbd. ma 1,3 i dd2p precharge power-down standby current : all banks idle; power-down mode; cke v il max ; t ck = 7.5 ns tbd. tbd. tbd. tbd. tbd. tbd. ma 1,4 i dd2f precharge floating standby current : cs v ih min , all banks idle; cke v ih min ; t ck = 7.5 ns, address and other control inputs changing once per clock cycle, v in = v ref for dq, dqs and dm. tbd. tbd. tbd. tbd. tbd. tbd. ma 1,4 i dd2q precharge quiet standby current : cs v ih min , all banks idle; cke v ih min ; t ck = 7.5 ns,address and other control inputs stable at v ih min or v il max ; v in = v ref for dq, dqs and dm. tbd. tbd. tbd. tbd. tbd. tbd. ma 1,4 i dd3p active power-down standby current : one bank active; power-down mode; cke v il max ; t ck = 7.5 ns tbd. tbd. tbd. tbd. tbd. tbd. ma 1,4 i dd3n active standby current : one bank; active / precharge;cs v ih min ; cke v ih min ; t rc = t ras max ; t ck = 7.5 ns; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd. tbd. tbd. tbd. tbd. tbd. ma 1,4 i dd4r operating current - burst read: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2; t ck = 7.5 ns; i out = 0ma tbd. tbd. tbd. tbd. tbd. tbd. ma 1,3 i dd4w operating current - burst write: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl = 2; t ck = 7.5 ns tbd. tbd. tbd. tbd. tbd. tbd. ma 1,3 i dd5 auto-refresh current : t rc = t rfc min, distributed refresh tbd. tbd. tbd. tbd. tbd. tbd. ma 1,3 i dd6 self-refresh current : cke 0.2v tbd. tbd. tbd. tbd. tbd. tbd. ma 1,2,4 i dd6a self-refresh current with pll-off : cke 0.2v, pll off, no toggling of address and control signals tbd. tbd. tbd. tbd. tbd. tbd. ma 1,2,4 i dd7 operating current - four bank operation ; four bank inter- leaving with bl=4; refer to the detailed test conditions in the component datasheet tbd. tbd. tbd. tbd. tbd. tbd. ma 1,3 1. i dd currents are measured after the device is properly initialized. typical values are obtained from characterisation data mea- sured at vdd = 2.5 v and r.t. with an input slew rate = 1v/ns. 2. enables on-chip refresh and address counters. 3. for two bank modules only : the other bank is in idd3n mode 4. for two bank modules only : both banks operate in the same current mode
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 11 10.01 electrical characteristics & ac timing for ddr-i components (for reference only) (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) symbol parameter ddr266a -7 ddr200 -8 unit notes min max min max t ac dq output access time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4 t dqsck dqs output access time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4 t ch ck high-level width 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 t ck 1-4 t hp clock half period min (t cl, t ch) min (t cl, t ch) ns 1-4 t ck clock cycle time cl = 2.5 7 12 8 12 ns 1-4 t ck cl = 2.0 7.5 12 10 12 ns 1-4 t dh dq and dm input hold time 0.5 0.6 ns 1-4 t ds dq and dm input setup time 0.5 0.6 ns 1-4 t ipw control and addr. input pulse width (each input) 2.2 2.5 ns 1, 10 t dipw dq and dm input pulse width (each input) 1.75 2 ns 1-4,11 t hz data-out high-impedence time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4, 5 t lz data-out low-impedence time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4, 5 t dqss write command to 1st dqs latching transition 0.75 1.25 0.75 1.25 t ck 1-4 t dqsq dqs-dq skew (for dqs & associated dq signals) + 0.5 + 0.6 ns 1-4 t qhs data hold skew factor + 0.75 + 1.0 ns 1-4 t qh data output hold time from dqs t hp -t qhs t hp -t qhs ns 1-4 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 t ck 1-4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 14 16 ns 1-4 t wpres write preamble setup time 0 0 ns 1-4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 t ck 1-4, 6 t wpre write preamble 0.25 0.25 t ck 1-4 t is address and control input setup time fast slew rate 0.9 1.1 ns 2-4, 10,11 slow slew rate 1.0 1.1 ns t ih address and control input hold time fast slew rate 0.9 1.1 ns slow slew rate 1.0 1.1 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck 1-4 t rpst read postamble 0.40 0.60 0.40 0.60 t ck 1-4 t ras active to precharge command 45 120,000 50 120,000 ns 1-4 t rc active to active/auto-refresh command period 65 70 ns 1-4 t rfc auto-refresh to active/auto-refresh command period 75 80 ns 1-4 t rcd active to read or write delay 20 20 ns 1-4
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 12 10.01 t rp precharge command period 20 20 ns 1-4 t rrd active bank a to active bank b command 15 15 ns 1-4 t wr write recovery time 15 15 ns 1-4 t dal auto precharge write recovery + precharge time (twr/tck) + (trp/tck) t ck 1-4,9 t wtr internal write to read command delay 1 1 t ck 1-4 t xsnr exit self-refresh to non-read command 75 80 ns 1-4 t xsrd exit self-refresh to read command 200 200 t ck 1-4 t refi average periodic refresh interval 128mb based 15.6 15.6 s1-4, 8 256 & 512 mb based 7.8 7.8 s1-4, 8 1. input slew rate >=1v/ns for ddr266 and = 1v/ns for ddr200. 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. ck/ck slew rate are >= 1.0 v/ns. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. for each of the terms, if not already an integer, round to the next highest integer. tck is equal to the actual system clock cycle time. 10. these parameters guarantee device timing, but they are not necessarily tested on each device 11. fast slew rate >= 1.0 v/ns , slow slew rate >= 0.5 v/ns and < 1v/ns for command/address and ck & ck slew rate >1.0 v/ ns, measured between voh(ac) and vol(ac) electrical characteristics & ac timing for ddr-i components (for reference only) (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) symbol parameter ddr266a -7 ddr200 -8 unit notes min max min max
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 13 10.01 spd codes for pc1600 modules ?-8? byt e# description spd entry value hex 128mbyte one bank 256mbyte one bank*) 256mbyte one bank**) 512 mbyte one bank 1 gbyte two banks 2 gbyte two banks 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type ddr-sdram 07 3 number of row addresses 12/13 0c 0c 0d 0d 0d 0d 4 number of column addresses 10/ 11/12 0a 0b 0a 0b 0b 0c 5 number of dimm banks 1 / 2 01 01 01 01 02 02 6 module data width 72 48 7 module data width (cont ? d) 0 00 8 module interface levels sstl_2.5 04 9 sdram cycle time at cl = 2.5 8 ns 80 10 sdram access time from clock at cl = 2.5 0.8 ns 80 11 dimm config ecc 02 12 refresh rate/type self-refresh, 15.6 / 7.8 s 80 80 82 82 82 82 13 sdram width, primary x4 / x8 08 04 08 04 04 04 14 error checking sdram data width x4 / x8 08 04 08 04 04 04 15 minimum clock delay for back-to-back random column address t ccd =1clk 01 16 burst length supported 2, 4 & 8 0e 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 2.5 0c 19 cs latencies cs latency = 0 01 20 we latencies write latency = 1 02 21 sdram dimm module attributes 26 22 sdram device attributes: general c0 23 min. clock cycle time at cas latency = 2 10.0 ns a0 24 access time from clock for cl = 2 0.8 ns 80 25 minimum clock cycle time at cl = 1.5 not supported 00 26 access time from clock at cl = 1.5 not supported 00 27 minimum row precharge time 20 ns 50 28 minimum row active to row active delay t rrd 15 ns 3c 29 minimum ras to cas delay t rcd 20 ns 50 30 minimum ras pulse width t ras 50 ns 32 31 module bank density (per bank) 128 / 256 / 512 mbyte 20 40 40 80 80 01 32 addr. and command setup time 1.1 ns b0 33 addr. and command hold time 1.1 ns b0 34 data input setup time 0.6 ns 60 35 data input hold time 0.6 ns 60
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 14 10.01 36-40 superset information ? 00 41 minimum core cycle time trc 70 ns 46 42 min. auto refresh cmd cycle time trfc 80 ns 50 43 maximum clock cycle time tck 12 ns 30 44 max. dqs-dq skew tddsq 0.6 ns 3c 45 x-factor tqhs 1.0 ns a0 46-61 superset information - 00 62 spd revision revision 0.0 00 63 checksum for bytes 0 - 62 ? 9c b5 bf f8 f9 7b 64 manufacturers jedec id code ? c1 65-71 manufacturer infineo(n) 72 module assembly location 73-90 module part number 91-92 module revision code 93-94 module manufacturing date 95-98 module serial number 99- 127 superset information 128- 256 open for customer use note: 256mbyte one bank *) = hys72d32501gr (128mbit based) , one bank **) = hys72d32/500gr (256mbit based) byt e# description spd entry value hex 128mbyte one bank 256mbyte one bank*) 256mbyte one bank**) 512 mbyte one bank 1 gbyte two banks 2 gbyte two banks
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 15 10.01 spd codes for pc2100 modules ? -7 ? byt e# description spd entry value hex 128mbyte one bank 256mbyte one bnk**) 256mbyte one bank**) 512 mbyte one bank 1 gbyte two banks 2 gbyte two banks 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type ddr-sdram 07 3 number of row addresses 12/13 0c 0c 0d 0d 0d 0d 4 number of column addresses 10/ 11 /12 0a 0b 0a 0b 0b 0c 5 number of dimm banks 1 / 2 01 01 01 01 02 02 6 module data width 72 48 7 module data width (cont ? d) 0 00 8 module interface levels sstl_2.5 04 9 sdram cycle time at cl = 2.5 7 ns 70 10 access time from clock at cl = 2.5 0.75 ns 75 11 dimm config ecc 02 12 refresh rate/type self-refresh, 15.6 / 7.8 s 80 80 82 82 82 82 13 sdram width, primary x4 / x8 08 04 08 04 04 04 14 error checking sdram data width x4 / x8 08 04 08 04 04 04 15 minimum clock delay for back-to-back random column address t ccd =1clk 01 16 burst length supported 2, 4 & 8 0e 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 2.5 0c 19 cs latencies cs latency = 0 01 20 we latencies write latency = 1 02 21 sdram dimm module attributes 26 22 sdram device attributes: general c0 23 min. clock cycle time at cas latency = 2 7.5 ns 75 24 access time from clock for cl = 2 0.75 ns 75 25 minimum clock cycle time at cl = 1.5 not supported 00 26 access time from clock at cl = 1.5 not supported 00 27 minimum row precharge time 20 ns 50 28 minimum row active to row active delay t rrd 15 ns 3c 29 minimum ras to cas delay t rcd 20 ns 50 30 minimum ras pulse width t ras 45 ns 2d 31 module bank density (per bank) 128 / 256/ 512 mbyte 20 40 40 80 80 01 32 addr. and command setup time 0.9 ns 90 33 addr. and command hold time 0.9 ns 90 34 data input setup time 0.5 ns 50 35 data input hold time 0.5 ns 50 36-40 superset information ? 00
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 16 10.01 41 minimum core cycle time trc 65 ns 41 42 min. auto refresh cmd cycle time trfc 75 ns 4b 43 maximum clock cycle time tck 12 ns 30 44 max. dqs-dq skew tddsq 0.5 ns 32 45 x-factor tqhs 0.75 ns 75 46-61 superset information - 00 62 spd revision revision 0.0 00 63 checksum for bytes 0 - 62 ? a7 c0 ca 03 04 86 64 manufacturers jedec id code ? c1 65-71 manufacturer infineo(n) 72 module assembly location 73-90 module part number 91-92 module revision code 93-94 module manufacturing date 95-98 module serial number 99- 127 superset information 128- 256 open for customer use note: 256mbyte one bank *) = hys72d32501gr (128mbit based) , one bank **) = hys72d32500gr (256mbit based) byt e# description spd entry value hex 128mbyte one bank 256mbyte one bnk**) 256mbyte one bank**) 512 mbyte one bank 1 gbyte two banks 2 gbyte two banks
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 17 10.01 package outlines raw card l module package ddr-i registered dimm modules 1.2 ? low profile raw card l 128mb & 256mb (one physical bank, 9 components) note: all outline dimensions and tolerances are in accordance with the jedec standard l-dim-184-13 raw card l reg. 1u *) on ecc modules only detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 1.27 4.0 max. + 0.1 - detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r pll register register 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 1.2" / 30.4 max. pin 1 + 0.15 - 6.62 49.53 4.0 front view 144 145 184 17.78 3 10.0 3 pin 93 2.5d backside view
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 18 10.01 package outlines raw card m l-dim-184-12 raw card m reg. 1u *) on ecc modules only detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 1.27 4.0 max. + 0.1 - detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r pll 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 1.2" / 30.4 max. pin 1 + 0.15 - 6.62 49.53 4.0 front view 144 145 184 17.78 3 10.0 3 pin 93 2.5d backside view register register module package ddr-i registered dimm modules 1.2 ? low profile raw card m 256mb & 512 mb (one physical bank, 18 components) note: all outline dimensions and tolerances are in accordance with the jedec standard
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 19 10.01 package outlines raw card with stacked components module package ddr-i registered dimm modules 1.2 ? low profile raw card (t.b.d.) 1gb & 2gb(two physical banks, 36 components) note: all outline dimensions and tolerances are in accordance with the jedec standard l-dim-184-14 raw card reg. 1u *) on ecc modules only detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 1.27 6.8 max. + 0.1 - detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r pll 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 1.2" / 30.4 max. pin 1 + 0.15 - 6.62 49.53 4.0 front view 144 145 184 17.78 3 10.0 3 pin 93 2.5d backside view register register
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 20 10.01 application note: power up and power management on ddr registered dimms (according to jedec ballot jc-42.5 item 1173) 184-pin double data rate (ddr) registered dimms include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. one feature is externally controlled via a system- generated reset signal; the second is based on module detection of the input clocks. these enhancements permit the modules to power up with sdram outputs in a high-z state (eliminating risk of high current dissipa- tions and/or dotted i/os), and result in the powering-down of module support devices (registers and phase- locked loop) when the memory is in self-refresh mode. the new reset pin controls power dissipation on the module ? s registers and ensures that cke and other sdram inputs are maintained at a valid ? low ? level during power-up and self refresh. when reset is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. the reset pin, located on dimm tab #10, is driven from the system as an asynchronous signal according to the attached details. using this function also permits the system and dimm clocks to be stopped during memory self refresh operation, while ensuring that the sdrams stay in self refresh mode. the function for reset is as follows: as described in the table above, a low on the reset input ensures that the clock enable (cke) signal(s) are maintained low at the sdram pins (cke being one of the 'q' signals at the register output). holding cke low maintains a high impedance state on the sdram dq, dqs and dm outputs ? where they will remain until acti- vated by a valid ? read ? cycle. cke low also maintains sdrams in self refresh mode when applicable. the ddr pll devices automatically detect clock activity above 20mhz. when an input clock frequency of 20mhz or greater is detected, the pll begins operation and initiates clock frequency lock (the minimum operat- ing frequency at which all specifications will be met is 95mhz). if the clock input frequency drops below 20mhz (actual detect frequency will vary by vendor), the pll vco (voltage controlled oscillator) is stopped, outputs are register inputs register outputs reset ck ck data in (d) data out (q) h rising falling h h h rising falling l l h l or h l or h x qo h high z high z x illegal input conditions l x or hi-z x or hi-z x or hi-z l x : don ? t care, hi-z : high impedance, qo: data latched at the previous of ck risning and ck falling
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 21 10.01 made high-z, and the differential inputs are powered down ? resulting in a total pll current consumption of less than 1ma. use of this low power pll function makes the use of the pll reset (or g pin) unnecessary, and it is tied inactive on the dimm. this application note describes the required and optional system sequences associated with the ddr regis- tered dimm 'reset ' function. it is important to note that all references to cke refer to both cke0 and cke1 for a 2-bank dimm. because reset applies to all dimm register devices, it is therefore not possible to uniquely control cke to one physical dimm bank through the use of the reset pin. power-up sequence with reset ? required 1. the system sets reset at a valid low level. this is the preferred default state during power-up. this input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that cke is at a stable low-level at the ddr sdrams. 2. the power supplies should be initialized according to the jedec-approved initialization sequence for ddr sdrams. 3. stabilization of clocks to the sdram the system must drive clocks to the application frequency (pll operation is not assured until the input clock reaches 20mhz). stability of clocks at the sdrams will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. once a stable clock is received at the dimm pll, the required pll stabilization time (assuming power to the dimm is stable) is 100 microseconds. when a stable clock is present at the sdram input (driven from the pll), the ddr sdram requires 200 sec prior to sdram operation. 4. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm con- nector). cke must be maintained low and all other inputs should be driven to a known state. in general these com- mands can be determined by the system designer. one option is to apply an sdram ? nop ? command (with cke low), as this is the first command defined by the jedec initialization sequence (ideally this would be a ? nop deselect ? command). a second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. the system switches reset to a logic ?high? level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, setting the reset timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 5. it is also a functional requirement that the registers maintain a low state at the cke outputs to guarantee that the ddr sdrams continue to receive a low level on cke. register activation time (t (act) ), from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 7. the system can begin the jedec-defined ddr sdram power-up sequence (according to the jedec- pproved initialization sequence). self refresh entry (reset low, clocks powered off) ? optional self refresh can be used to retain data in ddr sdram dimms even if the rest of the system is powered down and the clocks are off. this mode allows the ddr sdrams on the dimm to retain data without external clocking. self refresh mode is an ideal time to utilize the reset pin, as this can reduce register power consumption (reset low deactivates register ck and ck, data input receivers, and data output drivers).
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 22 10.01 1. the system applies self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: the commands reach the ddr sdram one clock later due to the additional register pipelining on a registered dimm. after this command is issued to the sdram, all of the address and control and clock input conditions to the sdram are don ? t cares ? with the exception of cke. 2. the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that cke, and all other control and address signals, are a stable low- level at the ddr sdrams. since the reset signal is asynchronous, setting the reset timing in relation to a specific clock edge is not required. 3. the system turns off clock inputs to the dimm. (optional) a. in order to reduce dimm pll current, the clock inputs to the dimm are turned off, resulting in high-z clock inputs to both the sdrams and the registers. this must be done after the reset deactivate time of the reg- ister (t (inact) ). the deactivate time defines the time in which the clocks and the control and address sig- nals must maintain valid levels after reset low has been applied and is specified in the register and dimm documentation. b. the system may release dimm address and control inputs to high-z. this can be done after the reset deactivate time of the register. the deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after reset low has been applied. it is highly recommended that cke continue to remain low during this operation. 4. the dimm is in lowest power self refresh mode. self refresh exit (reset low, clocks powered off) ? optional 1. stabilization of clocks to the sdram. the system must drive clocks to the application frequency (pll operation is not assured until the input clock reaches ~20mhz). stability of clocks at the sdrams will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. once a stable clock is received at the dimm pll, the required pll stabilization time (assuming power to the dimm is stable) is 100 microseconds. 2. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm con- nector). cke must be maintained low and all other inputs should be driven to a known state. in general these com- mands can be determined by the system designer. one option is to apply an sdram ? nop ? command (with cke low), as this is the first command defined by the jedec self refresh exit sequence (ideally this would be a ? nop deselect ? command). a second option is to apply low levels on all of the register inputs, to be con- sistent with the state of the register outputs. 3. the system switches reset to a logic ? high ? level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, reset timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows the clock receivers, input receivers, and output drivers suffi- cient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 2. it is also a functional requirement that the registers maintain a low state at the cke out- puts to guarantee that the ddr sdrams continue to receive a low level on cke. register activation time (t (act) ), from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 5. system can begin the jedec-defined ddr sdram self refresh exit procedure. self refresh entry (reset low, clocks running) ? optional
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 23 10.01 although keeping the clocks running increases power consumption from the on-dimm pll during self refresh, this is an alternate operating mode for these dimms. 1. system enters self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: the commands reach the ddr sdram one clock later due to the additional register pipelining on a registered dimm. after this command is issued to the sdram, all of the address and control and clock input conditions to the sdram are don ? t cares ? with the exception of cke. 2. the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that cke is a stable low-level at the ddr sdrams. 3. the system may release dimm address and control inputs to high-z. this can be done after the reset deactivate time of the register (t (inact) ). the deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after reset low has been applied. it is highly recommended that cke continue to remain low during the operation. 4. the dimm is in a low power, self refresh mode. self refresh exit (reset low, clocks running) ? optional 1. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm con- nector). cke must be maintained low and all other inputs should be driven to a known state. in general these com- mands can be determined by the system designer. one option is to apply an sdram ? nop ? command (with cke low), as this is the first command defined by the self refresh exit sequence (ideally this would be a ? nop deselect ? command). a second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. the system switches reset to a logic ? high ? level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows the clock receivers, input receivers, and output drivers suffi- cient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 1. it is also a functional requirement that the registers maintain a low state at the cke out- puts in order to guarantee that the ddr sdrams continue to receive a low level on cke. this activation time, from asynchronous switching of reset from low to high, until the registers are stable and ready to accept an input signal, is t (act ) as specified in the register and dimm documentation. 4. the system can begin jedec defined ddr sdram self refresh exit procedure. self refresh entry/exit (reset high, clocks running) ? optional as this sequence does not involve the use of the reset function, the jedec standard sdram specification explains in detail the method for entering and exiting self refresh for this case. self refresh entry (reset high, clocks powered off) ? not permissible in order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on cke, or the clocks are powered off and reset is asserted low according to the
hys 72dxx5xxgr registered ddr-i sdram-modules infineon technologies 24 10.01 sequence defined in this application not e. in the case where reset remains high and the clocks are powered off, the pll drives a high-z clock input into the register clock input. without the low level on reset an unknown dimm state will result.

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