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data sheet description the m pd78p018f is a member of the m pd78018f subseries within the 78k/0 series. the internal mask rom of the m pd78018f is replaced with one-time prom or eprom. because the m pd78p018f can be programmed by users, it is suited for applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and time- to-market of new products. caution the m pd78p018fdw and 78p018fkk-s are not guaranteed to maintain the reliability level required for mass production of the customers devices. use only experimentally or for evaluation purposes during trial manufacture. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m pd78018f, 78018fy subseries user's manual: u10659e 78k/0 series user's manualCinstructions: u12326e features pin compatible with mask rom version (except v pp pin) internal prom: 60 kbytes note 1 m pd78p018fdw, 78p018fkk-s: re-programmable (suited for system evaluation) m pd78p018fcw, 78p018fgc-ab8, 78p018fgk-8a8: programmable only once (suited for small-scale production) internal high-speed ram: 1024 bytes note 1 internal expansion ram: 1024 bytes note 2 internal buffer ram: 32 bytes operable over same supply voltage range as mask rom version: v dd = 1.8 to 5.5 v (except an a/d converter) qtop tm microcontroller supported note s 1 . the capacities of internal prom and internal high-speed ram can be changed by means of the internal memory size switching register (ims). 2 . the capacity of the internal expansion ram can be changed by means of the internal expansion ram size switching register (ixs). remark s 1 . qtop microcontroller is a general term for microcontrollers that incorporate one-time prom and are totally supported by nec's programming service (from programming to marking, screening and verification). 2 . for differences between the prom version and mask rom versions, refer to 1. differences between m pd78p018f and mask rom versions . in this document, the term prom is used in parts common to one-time prom versions and eprom versions. mos integr a ted circuit m pd78p018f 8-bit single-chip microcontroller the mark shows major revised points. the information in this document is subject to change without notice. 1994 documen t no. u10955ej3v0ds00 (3rd edition) date published november 1998 n cp(k) printed in japan
2 m pd78p018f ordering information part number package internal rom m pd78p018fcw 64-pin plastic shrink dip (750 mils) one-time prom m pd78p018fdw 64-pin ceramic shrink dip (with window) (750 mils) eprom m pd78p018fgc-ab8 64-pin plastic qfp (14 14 mm) one-time prom m pd78p018fgk-8a8 64-pin plastic lqfp (12 12 mm) one-time prom m pd78p018fkk-s 64-pin ceramic wqfn (14 14 mm) eprom quality grade part number package quality grade m pd78p018fcw 64-pin plastic shrink dip (750 mils) standard m pd78p018fdw 64-pin ceramic shrink dip (with window) (750 mils) not applicable m pd78p018fgc-ab8 64-pin plastic qfp (14 14 mm) standard m pd78p018fgk-8a8 64-pin plastic lqfp (12 12 mm) standard m pd78p018fkk-s 64-pin ceramic wqfn (14 14 mm) not applicable please refer to "quality grade on nec semiconductor devices" (document number c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
3 m pd78p018f 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. note under planning 80-pin 80-pin basic subseries for driving fip, display output total: 34 pd78044h m pd78044f m n-ch open drain was added to the pd78044f, display output total: 34 m pd78083 m pd780024y m pd780024 m pd780034y m pd780034 m pd78014h m pd78018f m pd78018fy m control fip tm drive 100-pin lcd drive bus interface supported 42/44-pin 80-pin 100-pin 100-pin 100-pin 78k/0 series basic subseries for driving lcds, on-chip uart y subseries products are compatible with i 2 c bus. products under development products in mass production 80-pin 100-pin pd78054 m pd78054y m pd78064b m pd78064 m pd78064y m emi-noise reduced version of the pd78078 m i/o and fip c/d of the pd78044f were enhanced, display output total: 53 m emi-noise reduced version of the pd78064 m pd78058f m pd78058fy m pd780058y note m pd780058 m pd78070a m pd78070ay m pd78078 m pd78078y m 80-pin pd780308 m meter control pd780955 m pd780958 m pd780973 m pd780308y m sio of the pd78064 was enhanced and rom, ram capacity expanded m 100-pin 80-pin 100-pin 80-pin on-chip j1850 (class2) controller pd78075b m 100-pin pd780018ay m 100-pin 64-pin 64-pin 64-pin 64-pin timer was added to the pd78054 and external interface was enhanced m rom-less version of the pd78078 m emi-noise reduced version of the pd78054 m uart and d/a converter were added to the pd78018f and i/o was enhanced m a/d converter of the pd780024 was enhanced m pd780065 m 80-pin ram capacity of pd780024 was expanded serial i/o of the pd78018f was enhanced m serial i/o of the pd78054 was enhanced and emi-noise was reduced m m emi-noise reduced version of the pd78018f m serial i/o of the pd78078y was enhanced and the function is limited m basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) pd780988 m inverter control 100-pin on-chip inverter control circuit and uart. emi-noise was reduced i/o and fip c/d of the pd78044h were enhanced, display output total: 48 pd780232 m 80-pin for panel control. on-chip fip c/d. display output total: 53 m 64-pin on-chip dcan controller on-chip dcan/iebus controller iebus tm controller is added to pd78054. emi-noise was reduced. ultra-low power consumption and on-chip uart for industrial meter control on-chip controller/driver for automotive meter drive m pd780208 m pd780228 m 80-pin 80-pin 80-pin 80-pin pd78098b m pd780948 m pd780701y m pd780833y m
4 m pd78p018f the major functional differences among subseries are shown below. function rom timer 8-bit 10-bit 8-bit v dd external serial interface i/o min. subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v available m pd78078 48 k to 60 k m pd78070a 61 2.7 v m pd780058 24 k to 60 k 2 ch 3 ch (time-division 68 1.8 v uart: 1 ch) m pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v m pd780034 8 k to 32 k 8 ch 3 ch (uart: 1 ch, time- 51 1.8 v m pd780024 8 ch division 3-wire: 1 ch) m pd78014h 2 ch 53 m pd78018f 8 k to 60 k m pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter m pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v available control fip drive m pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v m pd780228 48 k to 60 k 3 ch 1 ch 72 4.5 v m pd780232 16 k to 24 k 4 ch 2 ch 40 m pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v m pd78044f 16 k to 40 k 2 ch lcd drive m pd780308 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 3 ch (time-division 57 2.0 v uart: 1 ch) m pd78064b 32 k 2 ch (uart: 1 ch) m pd78064 16 k to 32 k bus interface m pd78098b 40 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 69 2.7 v supported m pd780948 60 k 2 ch 79 4.0 v meter m pd780973 24 k to 32 k 3 ch 1 ch 1 ch 1 ch 5 ch 2 ch (uart: 1 ch) 56 4.5 v control m pd780955 40 k 6 ch 1 ch 2 ch (uart: 2 ch) 50 2.2 v m pd780958 48 k to 60 k 4 ch 2 ch 2 ch (uart: 1 ch) 69 note 16-bit timer: 2 channels 10-bit timer: 1 channel
5 m pd78p018f function overview item function internal prom 60 kbytes note 1 memory high-speed ram 1024 bytes note 1 expansion ram 1024 bytes note 2 buffer ram 32 bytes memory space 64 kbytes general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution minimum instruction execution time cycle modification function provided. time when main system 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (@10.0-mhz operation) clock selected when subsystem 122 m s (@32.768-khz operation) clock selected instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulate (set, reset, test, boolean operation) ? bcd adjust, etc. i/o ports total: 53 ? cmos input: 2 ? cmos i/o: 47 ? n-channel open-drain i/o (15-v withstand voltage): 4 a/d converter ? 8-bit resolution 8 channels ? operable over a wide power supply voltage range: v dd = 2.2 to 5.5 v serial interface ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable: 1 channel ? 3-wire serial i/o mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel timer ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel timer output 3 (14-bit pwm output 1) clock output 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (@10.0-mhz operation with main system clock), 32.768 khz (@32.768-khz operation with subsystem clock) buzzer output 2.4 khz, 4.9 khz, 9.8 khz (@10.0-mhz operation with main system clock) vectored maskable internal: 8, external: 4 interrupt non-maskable internal: 1 source software 1 test input internal: 1, external: 1 supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 64-pin plastic shrink dip (750 mils) ? 64-pin ceramic shrink dip (with window) (750 mils) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) ? 64-pin ceramic wqfn (14 14 mm) notes 1. the internal prom and internal high-speed ram capacities can be changed with the internal memory size switching register (ims). 2. the internal expansion ram capacity can be changed with the internal expansion ram size switching register (ixs).
6 m pd78p018f 1 p20/si1 2 p21/so1 3 p22/sck1 4 p23/stb 5 p24/busy 6 p25/si0/sb0 7 p26/so0/sb1 8 p27/sck0 9 p30/to0 10 p31/to1 11 p32/to2 12 p33/ti1 13 p34/ti2 14 p35/pcl 15 p36/buz 16 p37 17 v ss 18 p40/ad0 19 p41/ad1 20 p42/ad2 21 p43/ad3 22 p44/ad4 23 p45/ad5 24 p46/ad6 25 p47/ad7 26 p50/a8 27 p51/a9 28 p52/a10 29 p53/a11 30 p54/a12 31 p55/a13 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ss p04/xt1 xt2 v pp x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0/ti0 reset p67/astb p66/wait p65/wr p64/rd p63 p62 p61 p60 p57/a15 p56/a14 pin configuration (top view) (1) normal operating mode 64-pin plastic shrink dip (750 mils) m pd78p018fcw ? 64-pin ceramic shrink dip (with window) (750 mils) m pd78p018fdw cautions 1. connect v pp pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss .
7 m pd78p018f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p11/ani1 p10/ani0 av ss p04/xt1 xt2 v pp x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0/ti0 reset p67/astb p66/wait p37 v ss p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/sck0 p26/so0/sb1 p25/si0/sb0 p24/busy p23/stb p22/sck1 p21/so1 p20/si1 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p65/wr 64-pin plastic qfp (14 14 mm) m pd78p018fgc-ab8 ? 64-pin plastic lqfp (12 12 mm) m pd78p018fgk-8a8 ? 64-pin ceramic wqfn (14 14 mm) m pd78p018fkk-s cautions 1. connect v pp pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss .
8 m pd78p018f a8 to a15: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input astb: address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground busy: busy buz: buzzer clock intp0 to intp3: interrupt from peripherals p00 to p04: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 pcl: programmable clock reset: reset rd: read strobe sb0, sb1: serial bus sck0, sck1: serial clock si0, si1: serial input so0, so1: serial output stb: strobe ti0 to ti2: timer input to0 to to2: timer output v dd : power supply v pp : programming power supply v ss : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock)
9 m pd78p018f 1 2 3 4 5 6 7 8 9 d0 10 d1 11 d2 12 d3 13 d4 14 d5 15 d6 16 d7 17 v ss 18 a0 19 a1 20 a2 21 a3 22 a4 23 a5 24 a6 25 a7 26 a8 27 a16 28 a10 29 a11 30 a12 31 a13 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss v dd v ss (l) open v pp (l) open v dd a9 reset ce oe a14 (l) (l) (l) (l) a15 (l) pgm (l) (2) prom programming mode 64-pin plastic shrink dip (750 mils) m pd78p018fcw ? 64-pin ceramic shrink dip (with window) (750 mils) m pd78p018fdw cautions 1. (l): independently connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: leave open.
10 m pd78p018f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss (l) open v pp (l) open v dd a9 reset d7 v ss d0 d1 d2 d3 d4 d5 d6 a0 a1 a2 a3 a4 a5 a6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss v dd a7 a8 a16 a10 a11 a12 a13 v ss a14 oe ce (l) (l) (l) (l) (l) (l) pgm (l) a15 64-pin plastic qfp (14 14 mm) m pd78p018fgc-ab8 ? 64-pin plastic lqfp (12 12 mm) m pd78p018fgk-8a8 ? 64-pin ceramic wqfn (14 14 mm) m pd78p018fkk-s cautions 1. (l): independently connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: leave open. a0 to a16: address bus ce: chip enable d0 to d7: data bus oe: output enable pgm: program reset: reset v dd : power supply v pp : programming power supply v ss : ground
11 m pd78p018f 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer serial interface 0 serial interface 1 a/d converter interrupt control watch timer buzzer output clock output control to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17 av dd av ss av ref intp0/p00- intp3/p03 buz/p36 pcl/p35 78k/0 cpu core prom (60 kbytes) ram (2048 bytes) v dd v ss v pp port0 port1 port2 port3 port4 port5 port6 external access system control p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p04 xt2 block diagram
12 m pd78p018f contents 1. differences between m pd78p018f and mask rom versions ................................... 13 2. pin functions ................................................................................................................ .............. 14 2.1 pins during normal operating mode ................................................................................................... 14 2.2 pins during prom programming mode .............................................................................................. 16 2.3 pin i/o circuits and recommended connection of unused pins ................................................... 17 3. internal memory size switching register (ims) ......................................................... 19 4. internal expansion ram size switching register (ixs) ........................................... 20 5. prom programming .................................................................................................................. 21 5.1 operating modes ............................................................................................................................... ...... 21 5.2 prom write procedure .......................................................................................................................... 23 5.3 prom read procedure .......................................................................................................................... 27 6. program erasure (for m pd78p018fdw, 78p018fkk-s) .................................................. 28 7. opaque film on erasure window (for m pd78p018fdw, 78p018fkk-s) ................... 28 8. one-time prom version screening .................................................................................... 28 9. electrical specifications .................................................................................................... 29 10. characteristic curve (reference value) .................................................................... 58 11. package drawings ................................................................................................................... 59 12. recommended soldering conditions .............................................................................. 64 appendix a. development tools .............................................................................................. 65 appendix b. related documents .............................................................................................. 71
13 m pd78p018f 1. differences between m pd78p018f and mask rom versions the m pd78p018f is a single-chip microcontroller with an on-chip one-time prom or eprom that has program write, erase, and rewrite capability. it is possible to make all the functions except for prom specification and mask option of p60 to p63 pins, the same as those of mask rom versions ( m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, and 78018f) by setting the internal memory size switching register (ims) and the internal expansion ram size switching register (ixs). differences between the m pd78p018f and mask rom versions are shown in table 1-1. table 1-1. differences between m pd78p018f and mask rom versions parameter m pd78p018f mask rom versions internal rom type one-time prom or eprom mask rom internal rom capacity 60 kbytes m pd78011f: 8 kbytes m pd78012f: 16 kbytes m pd78013f: 24 kbytes m pd78014f: 32 kbytes m pd78015f: 40 kbytes m pd78016f: 48 kbytes m pd78018f: 60 kbytes internal high-speed ram capacity 1024 bytes m pd78011f: 512 bytes m pd78012f: 512 bytes m pd78013f: 1024 bytes m pd78014f: 1024 bytes m pd78015f: 1024 bytes m pd78016f: 1024 bytes m pd78018f: 1024 bytes internal expansion ram capacity 1024 bytes m pd78011f: no m pd78012f: no m pd78013f: no m pd78014f: no m pd78015f: 512 bytes m pd78016f: 512 bytes m pd78018f: 1024 bytes internal rom, internal high-speed ram capacity changeable yes note 1 no with internal memory size switching register (ims) internal expansion ram capacity changeable with yes note 2 no internal expansion ram size switching register (ixs) ic pin no yes v pp pin yes no mask option of p60 to p63 pins pull-up resistor is not pull-up resistor can be incorporated. incorporated by mask option. electrical specifications, recommended soldering conditions see respective data sheet of individual products. notes 1. the internal prom capacity becomes 60 kbytes and the internal high-speed ram capacity becomes 1024 bytes by input of reset. 2. the internal expansion ram capacity becomes 1024 bytes by input of reset. caution there are differences in noise immunity and noise radiation between the prom and mask rom versions. when pre-producing an application set with the prom version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version.
14 m pd78p018f 2. pin functions 2.1 pins during normal operating mode (1) port pins (1/2) pin name i/o function after alternate reset function p00 input port 0 input only input intp0/ti0 p01 input/ 5-bit i/o port input/output can be specified in 1-bit units. input intp1 p02 output when used as an input port, an on-chip pull-up resistor can be intp2 p03 connected by software. intp3 p04 note 1 input input only input xt1 p10 to p17 input/ port 1 input ani0 to ani7 output 8-bit input/output port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be connected by software. note 2 p20 input/ port 2 input si1 p21 output 8-bit input/output port. so1 p22 input/output can be specified in 1-bit units. sck1 p23 when used as an input port, an on-chip pull-up resistor can be connected by stb p24 software. busy p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 input/ port 3 input to0 p31 output 8-bit input/output port. to1 p32 input/output can be specified in 1-bit units. to2 p33 when used as an input port, an on-chip pull-up resistor can be connected by ti1 p34 software. ti2 p35 pcl p36 buz p37 p40 to p47 input/ port 4 input ad0 to ad7 output 8-bit input/output port. input/output can be specified in 8-bit units. when used as an input port, an on-chip pull-up resistor can be connected by software. test input flag (krif) is set to 1 by falling edge detection. notes 1. when using the p04/xt1 pin as an input port, set bit 6 (frc) of the processor clock control register (pcc) to 1. do not use the internal feedback resistor of the subsystem clock oscillator. 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input, set port 1 to input mode. this causes the internal pull-up resistor is automatically disabled.
15 m pd78p018f (1) port pins (2/2) pin name i/o function after alternate reset function p50 to p57 input/ port 5 input a8 to a15 output 8-bit input/output port. leds can be driven directly. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be connected by software. p60 input/ port 6 n-ch open-drain input/output port. input p61 output 8-bit input/output port. leds can be driven directly. p62 input/output can be specified in p63 1-bit units. p64 when used as an input port, an on-chip rd p65 pull-up resistor can be connected by wr p66 software. wait p67 astb (2) non-port pins (1/2) pin name i/o function after alternate reset function intp0 input/ external interrupt request input by which the valid edge (rising edge, falling input p00/ti0 intp1 edge, or both rising edge and falling edge) can be specified. p01 intp2 p02 intp3 falling edge detection external interrupt request input. p03 si0 input serial interface serial data input. input p25/sb0 si1 p20 so0 output serial interface serial data output. input p26/sb1 so1 p21 sb0 input/ serial interface serial data input/output. input p25/si0 sb1 output p26/so0 sck0 input/ serial interface serial clock input/output. input p27 sck1 output p22 stb output serial interface automatic transmit/receive strobe output. input p23 busy input serial interface automatic transmit/receive busy input. input p24 ti0 input external count clock input to 16-bit timer (tm0). input p00/intp0 ti1 external count clock input to 8-bit timer (tm1). p33 ti2 external count clock input to 8-bit timer (tm2). p34 to0 output 16-bit timer (tm0) output (shared as 14-bit pwm output). input p30 to1 8-bit timer (tm1) output. p31 to2 8-bit timer (tm2) output. p32 pcl output clock output (for main system clock, subsystem clock trimming). input p35 buz output buzzer output. input p36
16 m pd78p018f (2) non-port pins (2/2) pin name i/o function after alternate reset function ad0 to ad7 input/ low-order address/data bus at external memory expansion. input p40 to p47 output a8 to a15 output high-order address bus at external memory expansion. input p50 to p57 rd output external memory read operation strobe signal output. input p64 wr external memory write operation strobe signal output. p65 wait input wait insertion at external memory access. input p66 astb output strobe output which latches the address information output at port 4 and port 5 input p67 to access external memory. ani0 to ani7 input a/d converter analog input. input p10 to p17 av ref input a/d converter reference voltage input. av dd a/d converter analog power supply. connect to v dd . av ss a/d converter ground potential. connect to v ss . reset input system reset input. x1 input main system clock oscillation crystal connection. x2 xt1 input subsystem clock oscillation crystal connection. input p04 xt2 v dd positive power supply. v pp high voltage applied during program write/verify. in normal operating mode, connect to v ss directly. v ss ground potential. 2.2 pins during prom programming mode pin name i/o function reset input sets prom programming mode. when +5 v or +12.5 v is applied to the v pp and low level is applied to reset pin, microcontroller is shifted to prom programming mode. v pp input applies high voltage during prom programming mode setting and program write/verify. a0 to a16 input address bus d0 to d7 input/ data bus output ce input prom enable input/program pulse input. oe input read strobe input to prom. pgm input program/program inhibit input in prom programming mode. v dd positive power supply v ss ground potential
17 m pd78p018f 2.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 2-1. for the input/output circuit configuration of each type, see figure 2-1. table 2-1. types of pin i/o circuits pin name input/output i/o recommended connection when not used circuit type p00/intp0/ti0 2 input connect to v ss . p01/intp1 8-a input/output independently connect to v ss via a resistor. p02/intp2 p03/intp3 p04/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11 input/output independently connect to v dd or v ss via a resistor. p20/si1 8-a p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0 to p47/ad7 5-e independently connect to v dd via a resistor. p50/a8 to p57/a15 5-a independently connect to v dd or v ss via a resistor. p60 to p63 13-d independently connect to v dd via a resistor. p64/rd 5-a independently connect to v dd or v ss via a resistor. p65/wr p66/wait p67/astb reset 2 input xt2 16 leave open. av ref connect to v ss . av dd connect to v dd . av ss connect to v ss . v pp connect directly to v ss .
18 m pd78p018f pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd input enable pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd in schmitt-triggered input with hysteresis characteristic pullup enable data output disable in/out n-ch v ref input enable pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd open drain xt1 (threshold voltage) v p-ch n-ch p-ch dd v p-ch + comparator dd data output disable n-ch in/out v dd rd middle-voltage input buffer feedback cut-off xt2 p-ch p-ch type 11 type 10-a type 13-d type 16 type 8-a type 5-a type 2 type 5-e figure 2-1. pin input/output circuits
19 m pd78p018f 3. internal memory size switching register (ims) this register is used to disable the use of part of the internal memory by software. by setting this register (ims), it is possible to get the same memory map as that of the mask rom versions with a different internal memory (rom, ram). ims is set with an 8-bit memory manipulate instruction. reset input sets ims to cfh. figure 3-1. internal memory size switching register format note when the external device expansion function is used, the internal rom capacity should be set to 56 kbytes or less. table 3-1 shows the setting values of ims which make the memory map the same as that of the mask rom versions. table 3-1. internal memory size switching register setting values target mask rom versions ims setting values m pd78011f 42h m pd78012f 44h m pd78013f c6h m pd78014f c8h m pd78015f cah m pd78016f cch m pd78018f cfh 0 rom3 0 rom2 0 1 rom1 1 0 rom0 selection of internal rom capacity 0 0 8 kbytes 011 0 16 kbytes 24 kbytes 100 0 32 kbytes 101 0 40 kbytes 1 1 0 0 48 kbytes 1 1 1 0 56 kbytes note 1 11 1 60 kbytes setting prohibited other than above ram2 0 1 ram1 1 1 ram0 selection of internal high-speed ram capacity 0 0 512 bytes 1024 bytes setting prohibited other than above ram0 ram1 ram2 rom0 rom2 rom1 rom3 ims fff0h cfh w 54 symbol address after reset r/w 0 76 3 2 0 1
20 m pd78p018f table 4-1 shows the setting values of ixs which make the memory map the same as that of the mask rom versions. table 4-1. internal expansion ram size switching register setting values target mask rom versions ixs setting values m pd78011f 0ch note m pd78012f m pd78013f m pd78014f m pd78015f 0bh m pd78016f m pd78018f 0ah note even if a program for the m pd78p018f in which "mov ixs, #0ch" is written is executed in the m pd78011f, 78012f, 78013f, and 78014f, the operations are not affected. 4. internal expansion ram size switching register (ixs) this register is used to disable the use of part of the internal expansion ram capacity by software. by setting this register (ixs), it is possible to get the same memory map as that of the mask rom versions with a different internal expansion ram. ixs is set with an 8-bit memory manipulate instruction. reset input sets ixs to 0ah. figure 4-1. internal expansion ram size switching register format ixram3 ixram2 ixram1 ixram0 selection of internal expansion ram capacity 1 0 1 0 1024 bytes (f400h to f7ffh) 1 0 1 1 512 bytes (f600h to f7ffh) 1 10 0 0 bytes setting prohibited other than above 0 0 0 ixram0 ixram2 ixram1 ixram3 ixs fff4h 0ah w 54 symbol address after reset r/w 0 76 3 2 0 1
21 m pd78p018f 5. prom programming the m pd78p018f has an internal 60-kbyte prom as a program memory. for programming, set the prom programming mode by setting the v pp and reset pins. for the handling of unused pins, refer to pin configu- ration (top view) (2) prom programming mode . caution when writing in a program, use locations 0000h-efffh (specify the last address as efffh). you cannot write in using a prom programmer that cannot specify the addresses to write . 5.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and the low-level signal is applied to the reset pin, the prom programming mode is set. this mode will become the operating mode as shown in table 5-1 when the ce, oe, and pgm pins are set. further, when the read mode is set, it is possible to read the contents of the prom. table 5-1. operating modes of prom programming pin reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit h h high-impedance ll read +5 v +5 v l l h data output output disable l h high-impedance standby h high-impedance : l or h
22 m pd78p018f (1) read mode read mode is set if ce = l, oe = l is set. (2) output disable mode data output becomes high-impedance and is in the output disable mode if oe = h is set. therefore, it allows data to be read from any device by controlling the oe pin, if multiple m pd78p018fs are connected to the data bus. (3) standby mode standby mode is set if ce = h is set. in this mode, data outputs become high-impedance irrespective of the oe status. (4) page data latch mode page data latch mode is set if ce = h, pgm = h, oe = l are set at the beginning of page write mode. in this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) page write mode after 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = h, oe = h. then, program verification can be performed, if ce = l, oe = l are set. if programming is not performed by a one-time program pulse, x (x 10) write and verification operations should be executed repeatedly. (6) byte write mode byte write is executed when a 0.1-ms program pulse (active low) is applied to the pgm pin with ce = l, oe = h. then, program verification can be performed if oe = l is set. if programming is not performed by a one-time program pulse, x (x 10) write and verification operations should be executed repeatedly. (7) program verify mode program verify mode is set if ce = l, pgm = h, oe = l are set. in this mode, check if a write operation is performed correctly, after the write. (8) program inhibit mode program inhibit mode is used when the oe pin, v pp pin, and d0 to d7 pins of multiple m pd78p018fs are connected in parallel and a write is performed to one of those devices. when a write operation is performed, the page write mode or byte write mode described above is used. at this time, a write is not performed to a device which has the pgm pin driven high.
23 m pd78p018f start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 x = 10 ? address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 0.1-ms program pulse verify 4 bytes verify all bytes write end defective product 5.2 prom write procedure figure 5-1. page program mode flow chart g = start address n = program last address
24 m pd78p018f figure 5-2. page program mode timing a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input hi-z
25 m pd78p018f start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 x = 10 ? 0.1-ms program pulse verify verify all bytes write end defective product figure 5-3. byte program mode flow chart g = start address n = program last address
26 m pd78p018f figure 5-4. byte program mode timing cautions 1. v dd should be applied before v pp and cut after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. removing and reinserting while +12.5 v is applied to v pp may adversely affect reliability. a0 to a16 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il data output data input hi-z program program verify
27 m pd78p018f a0 to a16 d0 to d7 ce (input) oe (input) hi-z hi-z data output address input 5.3 prom read procedure the contents of prom are readable to the external data bus (d0 to d7) according to the read procedure shown below. (1) fix the reset pin at low level, supply +5 v to the vpp pin, and handle all other unused pins as shown in pin configuration (top view) (2) prom programming mode. (2) supply +5 v to the vdd and vpp pins. (3) input address of read data into the a0 to a16 pins. (4) read mode (5) output data to d0 to d7 pins. the timings of the above steps (2) to (5) are shown in figure 5-5. figure 5-5. prom read timings
28 m pd78p018f 6. program erasure (for m pd78p018fdw, 78p018fkk-s) the m pd78p018fdw, 78p018fkk-s are capable of erasing (ffh) the contents of data written in a program memory and rewriting. when erasing the contents of data, irradiate light having a wavelength of less than about 400 nm to the erasure window. normally, irradiate ultraviolet rays of 254 nm wavelength. volume of irradiation required to completely erase the contents of data is as follows: ? uv intensity erasing time: 30 w?s/cm 2 or more ? erasing time: 40 min. or longer (when a uv lamp of 12mw/cm 2 is used. however, a longer time may be needed because of deterioration in performance of the uv lamp, contamination of the erasure window, etc.) when erasing the contents of data, set up the uv lamp within 2.5 cm from the erasing window. further, if a filter is provided for a uv lamp, irradiate the ultraviolet rays after removing the filter. 7. opaque film on erasure window (for m pd78p018fdw, 78p018fkk-s) to protect from miserasure by rays other than that of the lamp for erasing eprom contents, or to protect internal circuit other than eprom from malfunction by rays, stick an opaque film on the erasure window when eprom contents erasure is not performed. 8. one-time prom version screening the one-time prom versions ( m pd78p018fcw, 78p018fgc-ab8, 78p018fgk-8a8) cannot be tested com- pletely by nec before it is shipped, because of its structure. it is recommended to perform screening to verify prom after writing necessary data and performing high-temperature storage under the conditions below. storage temperature storage time 125 c 24 hours nec provides for a fee one-time prom writing, marking, screening, and verify service for products designated as qtop microcontrollers. for details, contact an nec sales representative.
29 m pd78p018f 9. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v v pp C0.3 to +13.5 v av dd C0.3 to v dd + 0.3 v av ref C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00 to p04, p10 to p17, p20 to p27, p30 to p37, C0.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, x1, x2, xt2, reset v i2 p60 to p63 open-drain C0.3 to +16 v v i3 a9 prom C0.3 to +13.5 v programming mode output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss C 0.3 to av ref + 0.3 v output current, high i oh per pin C10 ma total for p10 to p17, p20 to p27, p30 to p37 C15 ma total for p01 to p03, p40 to p47, p50 to p57, p60 to p67 C15 ma output current, low i ol note per pin peak value 30 ma rms value 15 ma total for p40 to p47, p50 to p55 peak value 100 ma rms value 70 ma total for p01 to p03, p56, p57, peak value 100 ma p60 to p67 rms value 70 ma total for p01 to p03, p64 to p67 peak value 50 ma rms value 20 ma total for p10 to p17, p20 to p27, peak value 50 ma p30 to p37 rms value. 20 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c note the rms value should be calculated as follows: [rms value] = [peak value] ? duty caution product quality may suffer if the absolute maximum ratings is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
30 m pd78p018f capacitance (t a = 25 c, v dd = v ss = 0 v ) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz unmeasured pins returned to 0 v 15 pf i/o capacitance c io f = 1 mhz p01 to p03, p10 to p17, p20 to p27, 15 pf unmeasured pins p30 to p37, p40 to p47, p50 to p57, returned to 0 v p64 to p67 p60 to p63 20 pf remark unless specified othewise, the characteristics of alternate-function pins are the same as those of port pins. main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter test conditions min. typ. max. unit circuit ceramic oscillation 2.7 v v dd 5.5 v 1 10 mhz resonator frequency (f x ) note 1 1.8 v v dd < 2.7 v 1 5 oscillation after v dd reaches oscillator 4 ms stabilization time note 2 voltage range min. crystal oscillation 2.7 v v dd 5.5 v 1 10 mhz resonator frequency (f x ) note 1 1.8 v v dd < 2.7 v 1 5 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 2 30 external x1 input 1.0 10.0 mhz clock frequency (f x ) note 1 x1 input 45 500 ns high-/low-level width (t xh , t xl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire the area enclosed by the broken line in the above figures as follows to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always keep the ground point of the oscillator capacitor to the same potential as v ss . ? do not ground the capacitor to a ground pattern in which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. x2 x1 m pd74hcu04 x2 x1 c1 c2 r1 v pp x2 x1 c1 c2 v pp
31 m pd78p018f subsystem clock oscillator characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter test conditions min. typ. max. unit circuit crystal oscillation 32 32.768 35 khz resonator frequency (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.2 2 s stabilization time note 2 10 external xt1 input 32 100 khz clock frequency (f xt ) note 1 xt1 input 5 15 m s high-/low-level width (t xth , t xtl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire the area enclosed by the broken line in the above figures as follows to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always keep the ground point of the oscillator capacitor to the same potential as v ss . ? do not ground the capacitor to a ground pattern in which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is a low-amplitude circuit in order to achive a low consumption current, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. xt1 xt2 c4 c3 r2 v pp xt2 xt1 m pd74hcu04
32 m pd78p018f recommended oscillator constants main system clock: ceramic resonator (t a = e40 to +85 c) frequency recommended oscillation manufacturer name oscillator constants voltage range remarks (mh z ) c1 (pf) c2 (pf) min. (v) max. (v) tdk ccr4.0mc3 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type fcr4.0mc5 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type ccr4.19mc3 4.19 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type fcr4.19mc5 4.19 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type ccr5.00mc3 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type fcr5.00mc5 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type ccr8.00mc 8.00 on-chip on-chip 2.7 5.5 on-chip capacitor, surface mounting type fcr8.00mc5 8.00 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type ccr8.38mc 8.38 on-chip on-chip 2.7 5.5 on-chip capacitor, surface mounting type fcr8.38mc5 8.38 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type ccr10.00mc 10.00 on-chip on-chip 2.7 5.5 on-chip capacitor, surface mounting type fcr10.00mc5 10.00 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type murata mfg. csa4.00mg 4.00 30 30 1.8 5.5 insertion type co., ltd. cst4.00mgw 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type csa4.19mg 4.19 30 30 1.8 5.5 insertion type cst4.19mgw 4.19 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type csa5.00mg 5.00 30 30 1.8 5.5 insertion type cst5.00mgw 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type csa8.00mtz 8.00 30 30 2.7 5.5 insertion type cst8.00mtw 8.00 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type csa8.38mtz 8.38 30 30 2.7 5.5 insertion type cst8.38mtw 8.38 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type csa10.00mtz 10.00 30 30 2.7 5.5 insertion type cst10.00mtw 10.00 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. the oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
33 m pd78p018f main system clock: ceramic resonator (t a = e20 to +80 c) frequency recommended oscillation manufacturer name oscillator constants voltage range remarks (mh z ) c1 (pf) c2 (pf) min. (v) max. (v) kyocera pbrc4.00a 4.00 33 33 1.8 5.5 surface mounting type corporation pbrc4.00b 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type kbr-4.00msa 4.00 33 33 1.8 5.5 insertion type kbr-4.00mks 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type pbrc5.00a 5.00 33 33 1.8 5.5 surface mounting type pbrc5.00b 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type kbr-5.00msa 5.00 33 33 1.8 5.5 insertion type kbr-5.00mks 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type kbr-8m 8.00 33 33 2.7 5.5 insertion type kbr-10m 10.00 33 33 2.7 5.5 insertion type caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. the oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
34 m pd78p018f dc characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0.7 v dd v dd v high p35 to p37, p40 to p47, 0.8 v dd v dd v p50 to p57, p64 to p67 v ih2 p00 to p03, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0.8 v dd v dd v p33, p34, reset 0.85 v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 5.5 v 0.7 v dd 15 v (n-ch open-drain) 0.8 v dd 15 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v dd C 0.2 v dd v v ih5 xt1/p04, xt2 4.5 v v dd 5.5 v 0.8 v dd v dd v 2.7 v v dd < 4.5 v 0.9 v dd v dd v 1.8 v v dd < 2.7 v note 0.9 v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3 v dd v low p35 to p37, p40 to p47, 0 0.2 v dd v p50 to p57, p64 to p67 v il2 p00 to p03, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0 0.2 v dd v p33, p34, reset 0 0.15 v dd v v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3 v dd v 2.7 v v dd < 4.5 v 0 0.2 v dd v 0 0.1 v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v v il5 xt1/p04, xt2 4.5 v v dd 5.5 v 0 0.2 v dd v 2.7 v v dd < 4.5 v 0 0.1 v dd v 1.8 v v dd < 2.7 v note 0 0.1 v dd v output v oh1 v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v voltage, high i oh = C100 m av dd C 0.5 v output v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v voltage, low i ol = 15 ma p01 to p03, p10 to p17, v dd = 4.5 to 5.5 v, 0.4 v p20 to p27, p30 to p37, i ol = 1.6 ma p40 to p47, p64 to p67 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2 v dd v open-drain pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v note when using xt1/p04 as p04, input the inverse of p04 to xt2. remark unless specified othewise, the characteristics of alternate-function pins are the same as those of port pins.
35 m pd78p018f dc characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p27, 3 m a current, high p30 to p37, p40 to p47, p50 to p57, p60 to p67, reset i lih2 x1, x2, xt1/p04, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p27, C3 m a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, reset i lil2 x1, x2, xt1/p04, xt2 C20 m a i lil3 p60 to p63 C3 note m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low software r v in = 0 v, p01 to p03, p10 to p17, p20 to p27, p30 to p37, 15 40 90 k w pull-up resistor p40 to p47, p50 to p57, p64 to p67 note for p60 to p63, a low-level input leak current of C200 m a (max.) flows only during the 3 clocks (no-wait time) after an instruction has been executed to read out port 6 (p6) or port mode register 6 (pm6). outside the period of 3 clocks following execution a read-out instruction, the current is C3 m a (max.). remark unless specified othewise, the characteristics of alternate-function pins are the same as those of port pins.
36 m pd78p018f dc characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit supply i dd1 10.00-mhz crystal v dd = 5.0 v 10 % note 2 12.0 24.0 ma current note 1 oscillation operation mode v dd = 3.0 v 10 % note 3 1.4 2.8 ma i dd2 10.00-mhz crystal v dd = 5.0 v 10 % note 2 4.0 8.0 ma oscillation halt mode v dd = 3.0 v 10 % note 3 1.4 2.8 ma i dd3 32.768-khz crystal v dd = 5.0 v 10 % 150 300 m a oscillation operation mode note 4 v dd = 3.0 v 10 % 100 200 m a v dd = 2.0 v 10 % 60 120 m a i dd4 32.768-khz crystal v dd = 5.0 v 10 % 25 50 m a oscillation halt mode note 4 v dd = 3.0 v 10 % 5 15 m a v dd = 2.0 v 10 % 2.5 10 m a i dd5 xt1 = v dd v dd = 5.0 v 10 % 2.0 30 m a stop mode, when using feedback v dd = 3.0 v 10 % 1.0 10 m a resistor v dd = 2.0 v 10 % 0.5 10 m a i dd6 xt1 = v dd v dd = 5.0 v 10 % 0.1 30 m a stop mode, when not using v dd = 3.0 v 10 % 0.05 10 m a feedback resistor v dd = 2.0 v 10 % 0.05 10 m a notes 1. refers to the current flowing to the v dd pin. the current flowing to the on-chip pull-up resistors, ports, and a/d converter is not included. 2. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 04h) 4. when main system clock operation is stopped.
37 m pd78p018f ac characteristics (1) basic operation (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time t cy operating on 3.5 v v dd 5.5 v 0.4 64 m s (min. instruction main system clock 2.7 v v dd < 3.5 v 0.8 64 m s execution time) 1.8 v v dd < 2.7 v 2.0 64 m s operating on subsystem clock 40 note 1 122 125 m s ti0 input t tih0 , 3.5 v v dd 5.5 v 2/f sam + 0.1 note 2 m s high-/low-level width t til0 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 2 m s 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 m s ti1, ti2 input f ti1 v dd = 4.5 to 5.5 v 0 4 mhz frequency 0 275 khz ti1, ti2 input t tih1 ,v dd = 4.5 to 5.5 v 100 ns high-/low-level width t til1 1.8 m s interrupt input request t inth , intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 2 m s high-/low-level width t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 2 m s 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 m s intp1 to intp3, v dd = 2.7 to 5.5 v 10 m s kr0 to kr7 20 m s reset low-level width t rsl v dd = 2.7 to 5.5 v 10 m s 20 m s notes 1. value when using an external clock. when a crystal resonator is used, the value becomes 114 m s (min.). 2. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible between f x /2 n+1 , f x /64, and f x /128 (when n= 0 to 4).
38 m pd78p018f t cy vs. v dd (at main system clock operation) 60.0 1.0 0.5 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 5.0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 3.5 5.5 2.7 operation guaranteed range m
39 m pd78p018f (2) read/write operation (t a = e40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. max. unit astb high-level width t asth 0.5 t cy ns address setup time t ads 0.5 t cy C 30 ns address hold time t adh 50 ns data input time from address t add1 (2.5 + 2n)t cy C 50 ns t add2 (3 + 2n)t cy C 100 ns data input time from rd t rdd1 (1 + 2n)t cy C 25 ns t rdd2 (2.5 + 2n)t cy C 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 20 ns t rdl2 (2.5 + 2n)t cy C 20 ns wait input time from rd t rdwt1 0.5 t cy ns t rdwt2 1.5 t cy ns wait input time from wr t wrwt 0.5 t cy ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 100 ns write data hold time t wdh load resistance 3 5 k w 20 ns wr low-level width t wrl (2.5 + 2n)t cy C 20 ns rd delay time from astb t astrd 0.5 t cy C 30 ns wr delay time from astb t astwr 1.5 t cy C 30 ns astb - delay time from t rdast t cy C 10 t cy + 40 ns rd - in external fetch address hold time from t rdadh t cy t cy + 50 ns rd - in external fetch write data output time from rd - t rdwd v dd = 4.5 to 5.5 v 0.5 t cy + 5 0.5 t cy + 30 ns 0.5 t cy + 15 0.5 t cy + 90 ns write data output time from wr t wrwd v dd = 4.5 to 5.5 v 5 30 ns 15 90 ns address hold time from wr - t wradh v dd = 4.5 to 5.5 v t cy t cy + 60 ns t cy t cy + 100 ns rd - delay time from wait - t wtrd 0.5 t cy 2.5 t cy + 80 ns wr - delay time from wait - t wtwr 0.5 t cy 2.5 t cy + 80 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits.
40 m pd78p018f (3) serial interface (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-/low-level t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2 C 50 ns width t kl1 t kcy1 /2 C 100 ns si0 setup time t sik1 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si0 hold time t ksi1 400 ns (from sck0 - ) so0 output delay time t kso1 c = 100 pf note 300 ns from sck0 note c is the load capacitance of the sck0 and so0 output lines. (ii) 3-wire serial i/o mode (sck0... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-/low-level t kh2 , 4.5 v v dd 5.5 v 400 ns width t kl2 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si0 setup time t sik2 v dd = 2.0 to 5.5 v 100 ns (to sck0 - ) 150 ns si0 hold time t ksi2 400 ns (from sck0 - ) so0 output delay time t kso2 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck0 500 ns sck0 rise, fall time t r2 , when external device 160 ns t f2 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used note c is the load capacitance of the so0 output line.
41 m pd78p018f (iii) sbi mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3200 ns 4800 ns sck0 high-/low-level t kh3 ,v dd = 4.5 to 5.5 v t kcy3 /2 C 50 ns width t kl3 t kcy3 /2 C 150 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi3 t kcy3 /2 ns (from sck0 - ) sb0, sb1 output delay t kso3 r = 1 k w ,v dd = 4.5 to 5.5 v 0 250 ns time from sck0 c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy3 ns sck0 from sb0, sb1 t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the load resistance and load capacitance of the sb0, sb1 and sck0 output lines. (iv) sbi mode (sck0... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy4 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3200 ns 4800 ns sck0 high-/low-level t kh4 , 4.5 v v dd 5.5 v 400 ns width t kl4 2.0 v v dd < 4.5 v 1600 ns 2400 ns sb0, sb1 setup time t sik4 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi4 t kcy4 /2 ns (from sck0 - ) sb0, sb1 output delay t kso4 r = 1 k w ,v dd = 4.5 to 5.5 v 0 300 ns time from sck0 c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy4 ns sck0 from sb0, sb1 t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rise, fall time t r4 , when external device 160 ns t f4 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
42 m pd78p018f (v) 2-wire serial i/o mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w , 2.7 v v dd 5.5 v 1600 ns c = 100 pf note 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-level width t kh5 v dd = 2.7 to 5.5 v t kcy5 /2 C 160 ns t kcy5 /2 C 190 ns sck0 low-level width t kl5 v dd = 4.5 to 5.5 v t kcy5 /2 C 50 ns t kcy5 /2 C 100 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 300 ns (to sck0 - ) 2.7 v v dd < 4.5 v 350 ns 2.0 v v dd < 2.7 v 400 ns 500 ns sb0, sb1 hold time t ksi5 600 ns (from sck0 - ) sb0, sb1 output delay t kso5 0 300 ns time from sck0 note r and c are the load resistance and load capacitance of the sck0, sb0 and sb1 output lines. (vi) 2-wire serial i/o mode (sck0... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 2.7 v v dd 5.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-level width t kh6 2.7 v v dd 5.5 v 650 ns 2.0 v v dd < 2.7 v 1300 ns 2100 ns sck0 low-level width t kl6 2.7 v v dd 5.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns sb0, sb1 setup time t sik6 v dd = 2.0 to 5.5 v 100 ns (to sck0 - ) 150 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 - ) sb0, sb1 output delay t kso6 r = 1 k w , 4.5 v v dd 5.5 v 0 300 ns time from sck0 c = 100 pf note 2.0 v v dd < 4.5 v 0 500 ns 0 800 ns sck0 rise, fall time t r6 , when external device 160 ns t f6 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
43 m pd78p018f (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy7 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high-/low-level t kh7 ,v dd = 4.5 to 5.5 v t kcy7 /2 C 50 ns width t kl7 t kcy7 /2 C 100 ns si1 setup time t sik7 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi7 400 ns (from sck1 - ) so1 output delay time t kso7 c = 100 pf note 300 ns from sck1 note c is the load capacitance of the sck1 and so1 output lines. (ii) 3-wire serial i/o mode (sck1... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy8 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high-/low-level t kh8 , 4.5 v v dd 5.5 v 400 ns width t kl8 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si1 setup time t sik8 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi8 400 ns (from sck1 - ) so1 output delay time t kso8 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck1 500 ns sck1 rise, fall time t r8 , when external device 160 ns t f8 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used note c is the load capacitance of the so1 output line.
44 m pd78p018f (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high-/low-level t kh9 ,v dd = 4.5 to 5.5 v t kcy9 /2 C 50 ns width t kl9 t kcy9 /2 C 100 ns si1 setup time t sik9 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi9 400 ns (from sck1 - ) so1 output delay time t kso9 c = 100 pf note 300 ns from sck1 stb - from sck1 - t sbd t kcy9 /2 C 100 t kcy9 /2 + 100 ns strobe signal t sbw 2.7 v v dd 5.5 v t kcy9 C 30 t kcy9 + 30 ns high-level width 2.0 v v dd < 2.7 v t kcy9 C 60 t kcy9 + 60 ns t kcy9 C 90 t kcy9 + 90 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal 2.7 v v dd < 4.5 v 150 ns detection timing) 2.0 v v dd < 2.7 v 200 ns 300 ns sck1 from busy t sps 2t kcy9 ns inactive note c is the load capacitance of the sck1 and so1 output lines.
45 m pd78p018f (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high-/low-level t kh10 , 4.5 v v dd 5.5 v 400 ns width t kl10 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si1 setup time t sik10 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi10 400 ns (from sck1 - ) so1 output delay time t kso10 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck1 500 ns sck1 rise, fall time t r10 , when external device expansion 160 ns t f10 function is used when external device expansion 1000 ns function is not used note c is the load capacitance of the so1 output line.
46 m pd78p018f ac timing test point (excluding x1, xt1 input) clock timing ti timing 0.8 v dd 0.2 v dd test points 0.8 v dd 0.2 v dd x1 input v ih4 (min.) v il4 (max.) 1/f x t xl t xh xt1 input v ih5 (min.) v il5 (max.) 1/f xt t xtl t xth ti0 t til0 t tih0 ti1,ti2 1/f ti1 t til1 t tih1
47 m pd78p018f read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 operation code t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add1 hi-z t ads t asth t adh t rdd1 operation code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd lower 8-bit address
48 m pd78p018f external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add2 hi-z t ads t asth t adh t rdd2 read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl t rdh t rdl2 hi-z lower 8-bit address a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add2 t ads t asth t adh t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z hi-z lower 8-bit address
49 m pd78p018f serial transfer timing 3-wire serial i/o mode: sbi mode (bus release signal transfer): sbi mode (command signal transfer): si0,si1 so0,so1 m = 1, 2, 7, 8 n = 2, 8 t kcym t klm t khm t sikm t ksim input data t ksom output data t fn t rn sck0,sck1 sck0 sb0, sb1 t ksb t sbl t sbh t sbk t kcy3, 4 t kl3, 4 t kh3, 4 t sik3, 4 t ksi3, 4 t kso3, 4 t r4 t f4 sck0 sb0, sb1 t ksb t sbk t kcy3, 4 t kl3, 4 t kh3, 4 t sik3, 4 t ksi3, 4 t kso3, 4 t r4 t f4
50 m pd78p018f 2-wire serial i/o mode: 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing): note the signal is not actually driven low here; it is shown as such to indicate the timing. sck0 sb0, sb1 t kcy5,6 t kl5,6 t kh5,6 t r6 t f6 t kso5,6 t sik5,6 t ksi5,6 so1 sck1 si1 stb d2 d1 d0 d2 d1 d0 t sik9,10 t ksi9,10 t kso9,10 t kh9,10 t f10 t r10 t kl9,10 t kcy9,10 t sbw t sbd d7 d7 sck1 busy 7 8 910 10 + n t bys t byh t sps 1 (active high) note note note
51 m pd78p018f a/d converter characteristics (t a = e40 to +85 c, av dd = v dd = 2.2 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error note 2.7 v av ref av dd 0.6 % 2.2 v av ref < 2.7 v 1.4 % conversion time t conv 2.7 v av ref av dd 19.1 200 m s 2.2 v av ref < 2.7 v 38.2 200 m s sampling time t samp 24/f x m s analog input voltage v ian av ss av ref v reference voltage av ref 2.2 av dd v av ref resistance r airef 414 k w note overall error excluding quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply v dddr 1.8 5.5 v voltage data retention supply i dddr v dddr = 1.8 v 0.1 10 m a current subsystem clock stops and feedback resistor disconnected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 18 /f x ms wait time release by interrupt request note ms note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 13 /f x and 2 15 /f x to 2 18 /f x is possible. data retention timing (stop mode release by reset) v dd stop instruction execution reset v dddr internal reset operation halt mode operating mode t wait t srel data retention mode stop mode
52 m pd78p018f data retention timing (standby release signal : stop mode release by interrupt request signal) interrupt request input timing reset input timing v dd stop instruction execution standby release signal (interrupt request) v dddr halt mode operating mode t srel t wait data retention mode stop mode t intl t inth t intl intp0 to intp2 intp3 t rsl reset
53 m pd78p018f prom programming characteristics dc characteristics (1) prom write mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note conditions min. typ. max. unit input voltage, high v ih v ih 0.7 v dd v dd v input voltage, low v il v il 0 0.3 v dd v output voltage, high v oh v oh i oh = C1 ma v dd C 1.0 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a v pp supply voltage v pp v pp 12.2 12.5 12.8 v v dd supply voltage v dd v cc 6.25 6.5 6.75 v v pp supply current i pp i pp pgm = v il 50 ma v dd supply current i dd i cc 50 ma note corresponding m pd27c1001a symbol (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbol note conditions min. typ. max. unit input voltage, high v ih v ih 0.7 v dd v dd v input voltage, low v il v il 0 0.3 v dd v output voltage, high v oh1 v oh1 i oh = C1 ma v dd C 1.0 v v oh2 v oh2 i oh = C100 m av dd C 0.5 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a output leakage current i lo i lo 0 v out v dd , oe = v ih C10 +10 m a v pp supply voltage v pp v pp v dd C 0.6 v dd v dd + 0.6 v v dd supply voltage v dd v cc 4.5 5.0 5.5 v v pp supply current i pp i pp v pp = v dd 100 m a v dd supply current i dd i cca1 ce = v il , v in = v ih 50 ma note corresponding m pd27c1001a symbol
54 m pd78p018f ac characteristics (1) prom write mode (a) page program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note conditions min. typ. max. unit address setup time (to oe )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to oe )t ces t ces 2 m s input data setup time (to oe )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s t ahl t ahl 2 m s t ahv t ahv 0 m s input data hold time (from oe - )t dh t dh 2 m s data output float delay time from oe - t df t df 0 250 ns v pp setup time (to oe )t vps t vps 1.0 ms v dd setup time (to oe )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe pulse width during data latching t lw t lw 1 m s pgm setting time t pgms t pgms 2 m s ce hold time t ceh t ceh 2 m s oe hold time t oeh t oeh 2 m s note corresponding m pd27c1001a symbol (b) byte program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note conditions min. typ. max. unit address setup time (to pgm )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to pgm )t ces t ces 2 m s input data setup time (to pgm )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s input data hold time (from pgm - )t dh t dh 2 m s data output float delay time from oe - t df t df 0 250 ns v pp setup time (to pgm )t vps t vps 1.0 ms v dd setup time (to pgm )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe hold time t oeh 2 m s note corresponding m pd27c1001a symbol
55 m pd78p018f (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbol note conditions min. typ. max. unit data output time from address t acc t acc ce = oe = v il 800 ns data output delay time from ce t ce t ce oe = v il 800 ns data output delay time from oe t oe t oe ce = v il 200 ns data output float delay time from oe - t df t df ce = v il 060ns data hold time from address t oh t oh ce = oe = v il 0ns note corresponding m pd27c1001a symbol (3) prom programming mode setting (t a = 25 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit prom programming mode setup time t sma 10 m s prom write mode timing (page program mode) t oe a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input hi? hi? hi? t ah t oeh t oes t ceh t pw t ahv t df t ces t ahl t as t dh t lw t vds t vps t ds t pgms
56 m pd78p018f prom write mode timing (byte program mode) cautions 1. v dd must be applied before v pp and cut off after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. removing and reinserting while +12.5 v is applied to v pp may adversely affect reliability. prom read mode timing notes 1. when reading within the t acc range, the oe input delay time from the ce fall time must be maximum of t acc C t oe . 2. t df is the time from the point at which either oe or ce (whichever is first) reaches v ih . pgm program program verify t as t ds t vps t vds t oeh t ces t pw t dh hi-z hi-z hi-z t df t ah t oes t oe oe ce v dd v pp d0 to d7 v pp v dd v dd + 1.5 v dd v ih v il v ih v il v ih v il a0 to a16 data input data output oe ce d0 to d7 a0 to a16 t ce t acc t oe hi-z hi-z t oh t df effective address data output note 1 v ih v il v ih v il note 1 note 2
57 m pd78p018f prom programming mode setting timing a0 to a16 effective address t sma reset v dd v pp v dd 0 v dd 0
58 m pd78p018f 10. characteristic curve (reference value) i dd vs. v dd (main system clock: 10.0 mhz) 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 supply voltage v dd [v] supply current i dd [ma] 5678 t a = 25 c pcc = 00h pcc = 01h pcc = b0h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillation, xt1 halt) halt (x1 halt, xt1 oscillation) f x = 10.0 mhz f xt = 32.768 khz
59 m pd78p018f 11. package drawings a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2 0.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15 0.50 0.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126 0.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mils) remark the dimensions and materials of es versions are the same as those of mass-produced versions.
60 m pd78p018f 64 pin ceramic shrink dip (750 mils) notes 1) each lead centerline is located within 0.25 mm (0.010 inch) of its true position (t.p.) at maximum material condition. item millimeters inches b c a l 18.8 0.740 2) item "k" to center of leads when formed parallel. 58.68 max. 2.310 max. 1.78 max. 0.070 max. 1.778 (t.p.) 0.070 (t.p.) h 1.0 min. 0.039 min. d 0.46 0.05 0.018 0.002 f 0.8 min. 0.031 min. g 3.5 0.3 0.138 0.012 k i 3.0 0.118 j 5.08 max. 0.200 max. 19.05 (t.p.) 0.750 (t.p.) p64dw-70-750a-1 n 0.25 0.010 s 0~15 0~15 m 0.25 0.05 0.010 +0.002 ?.003 r 0.350 f 8.89 f j i h g m r c b f d s m n 64 33 132 a k l
61 m pd78p018f remark the dimensions and materials of es versions are the same as those of mass-produced versions. 64 pin plastic qfp (14 14) item millimeters inches i j 0.8 (t.p.) 0.15 0.006 0.031 (t.p.) a 17.6 0.4 0.693 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.6 0.4 0.693 0.016 f g 1.0 1.0 0.039 0.039 h 0.37 0.015 p64gc-80-ab8-4 l 0.8 0.2 0.031 +0.009 ?.008 m 0.17 0.007 n 0.10 0.004 +0.08 ?.07 +0.08 ?.07 q 0.1 0.1 0.004 0.004 r s 2.85 max. 5 5 5 5 0.113 max. +0.003 ?.004 note 1. controlling dimension millimeter. 2. each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. m q r k m l p g f hi s detail of lead end k 1.8 0.2 0.071 0.008 p 2.55 0.1 0.100 0.004 +0.003 ?.004 48 49 32 64 1 17 16 33 s a b cd j ns
62 m pd78p018f remark the dimensions and materials of es versions are the same as those of mass-produced versions. 64 pin plastic lqfp (12 12) item millimeters inches d f g k i j 1.125 1.125 1.4 0.2 0.65 (t.p.) 0.13 14.8 0.4 q 0.583 0.016 0.044 0.044 0.055 0.008 0.005 0.026 (t.p.) p64gk-65-8a8-1 a f note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. c 12.0 0.2 0.472 m 0.15 0.006 0.125 0.075 0.005 0.003 +0.004 ?.003 +0.009 ?.008 a 14.8 0.4 0.583 0.016 h0.30 0.10 0.012 +0.004 ?.005 l0.6 0.2 0.024 +0.008 ?.009 n0.10 0.004 p 1.4 0.055 s r 1.7 max. 5 5 0.067 max. 5 5 +0.10 ?.05 b 12.0 0.2 0.472 +0.009 ?.008 m 48 49 32 64 1 17 16 33 b g hi j c d p n l k m detail of lead end s q r
63 m pd78p018f 64 pin ceramic wqfn b z a u c d u1 f g t m j hi r 1 64 s q w k x64kw-80a1 item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. 14.0 0.18 13.4 13.4 14.0 0.18 1.84 3.56 max. 0.51 0.1 0.08 0.8 (t.p.) 1.0 0.15 c 0.3 1.0 1.0 r 3.0 10.8 1.4 0.75 0.15 0.10 0.551 0.007 0.528 0.528 0.551 0.007 0.072 0.141 max. 0.02 0.004 0.003 0.031 (t.p.) 0.039 c 0.012 0.039 0.039 r 0.118 0.425 0.055 0.03 0.004 a b c d f g h i j k q r s t u u1 w z +0.007 ?.006 +0.006 ?.007
64 m pd78p018f 12. recommended soldering conditions the m pd78p018f should be soldered and mounted under the following recommended conditions. for the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales represen- tative. table 12-1. surface mounting type soldering conditions (1) m pd78p018fgc-ab8: 64-pin plastic qfp (14 14 mm) soldering method soldering conditions symbol infrared rays reflow ir35-00-3 vps vp15-00-3 wave soldering ws60-00-1 partial heating (2) m pd78p018fgk-8a8: 64-pin plastic lqfp (12 12 mm) soldering method soldering conditions symbol infrared rays reflow ir35-107-2 vps vp15-107-2 wave soldering ws60-107-1 partial heating note maximum allowable time from taking the soldering packages out of dry pack to soldering. storage conditions: 25 c and relative humidity of 65% or less. caution do not use different soldering methods together (except for partial heating). table 12-2. insertion type soldering conditions m pd78p018fcw: 64-pin plastic shrink dip (750 mils) m pd78p018fdw: 64-pin ceramic shrink dip (with window) (750 mils) soldering method soldering conditions wave soldering (pin only) solder temperature: 260 c or below, time: 10 seconds max. partial heating pin temperature: 300 c or below, time: 3 seconds max. (per pin row) caution apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less, exposure limit: 7 days note (after 7 days, prebake 125 c for 10 hours) package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less, exposure limit: 7 days note (after 7 days, prebake 125 c for 10 hours) solder temperature: 260 c, time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after 7 days, prebake 125 c for 10 hours) pin temperature: 300 c or below, time: 3 seconds max. (per pin row) package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: three times or less solder temperature: 260 c, time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) pin temperature: 300 c or below, time: 3 seconds max. (per pin row)
65 m pd78p018f appendix a. development tools the following development tools are available for system development using the m pd78p018f. also refer to (5) cautions on using development tools . (1) language processing software ra78k/0 78k/0 series common assembler package cc78k/0 78k/0 series common c compiler package df78014 device file for m pd78018f subseries cc78k/0-l 78k/0 series common c compiler library source file (2) prom writing tools pg-1500 prom programmer pa-78p018cw programmer adapter connected to pg-1500 pa-78p018gc pa-78p018gk pa-78p018kk-s pg-1500 controller pg-1500 control program (3) debugging tool ? when using in-circuit emulator ie-78k0-ns ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs, c bus supported ) ie-70000-cd-i-a pc card and interface cable when using notebook pc of pc-9800 series as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when using ibm pc/at tm compatible as host machine (isa bus supported) ie-70000-pci-if adapter when using pc that incorporates pci bus as host machine ie-78018-ns-em1 emulation board for m pd78018f subseries np-64cw emulation probe for 64-pin plastic shrink dip (cw type) np-64gc emulation probe for 64-pin plastic qfp (gc-ab8 type) np-64gk emulation probe for 64-pin plastic lqfp (gc-8a8 type) tgk-064sbw conversion adapter for connecting target system board designed to mount a 64-pin plastic lqfp (gk- 8a8 type) and np-64gk. ev-9200gc-64 socket to be mounted on target system board manufactured for 64-pin plastic qfp (gc-ab8 type) id78k0-ns note integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df78014 device file for m pd78018f subseries
66 m pd78p018f when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs, c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at compatible as host machine (isa bus supported) ie-78000-r-sv3 interface adapter and cable when using ews as host machine ie-70000-pci-if adapter when using pc that incorporates pci bus as host machine ie-78018-ns-em1 emulation board for m pd78018f subseries ie-78k0-r-ex1 emulation probe conversion board to use ie-78018-ns-em1 on ie-78001-r-a ep-78240cw-r emulation probe for 64-pin plastic shrink dip (cw type) ep-78240gc-r emulation probe for 64-pin plastic qfp (gc-ab8 type) ep-78012gk-r emulation probe for 64-pin plastic lqfp (gk-8a8 type) tgk-064sbw conversion adapter for connecting target system board designed to mount a 64-pin plastic lqfp (gk- 8a8) and np-64gk. ev-9200gc-64 socket to be mounted on target system board manufactured for 64-pin plastic qfp (gc-ab8 type) id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df78014 device file for m pd78018f subseries (4) real-time os rx78k/0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
67 m pd78p018f (5) cautions on using development tools ? the id-78k0-ns, id78k0, and sm78k0 are used in combination with the df78014. ? the cc78k/0 and rx78k/0 are used in combination with the ra78k/0 and the df78014. ? the np-64cw, np64gc, and np-64gk are products made by naitou densei machidaseisakusho (+81-44- 822-3813). contact an nec dealer regarding the purchase of these products. ? the tgk-064sbw is a product made by tokyo eletech corporation. for further information, connect to: daimaru kogyo, ltd. tokyo electronics dept. (+81-3-3820-7112) osaka electronics dept. (+81-6-244-6672) ? for third party development tools, see the 78k/0 series selection guide (u11126e) . ? the host machines and oss supporting each software are as follows. host machine pc ews [os] pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatible sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k/0 ? note ? cc78k/0 ? note ? pg-1500 controller ? note id78k0-ns ? id78k0 ?? sm78k0 ? rx78k/0 ? note ? mx78k0 ? note ? note dos-based software
68 m pd78p018f drawing of conversion socket (ev-9200gc-64) and recommended footprint figure a-1. drawing of ev-9200gc-64 (for reference only) a f 1 e ev-9200gc-64 b d c m n l k r q i h p o s t j g no.1 pin index ev-9200gc-64-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s t 18.8 14.1 14.1 18.8 4-c 3.0 0.8 6.0 15.8 18.5 6.0 15.8 18.5 8.0 7.8 2.5 2.0 1.35 0.35 0.1 2.3 1.5 0.74 0.555 0.555 0.74 4-c 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014 0.091 0.059 +0.004 ?.005 f f f f
69 m pd78p018f figure a-2. recommended footprint of ev-9200gc-64 (for reference only) f e d g h i j k l c b a 0.031 0.591=0.472 0.031 0.591=0.472 ev-9200gc-64-p1e item millimeters inches a b c d e f g h i j k l 19.5 14.8 14.8 19.5 6.00 0.08 6.00 0.08 0.5 0.02 2.36 0.03 2.2 0.1 1.57 0.03 0.768 0.583 0.583 0.768 0.236 0.236 0.197 0.093 0.087 0.062 0.8 0.02 15=12.0 0.05 0.8 0.02 15=12.0 0.05 f f f +0.002 ?.001 +0.003 ?.002 +0.002 ?.001 +0.003 ?.002 +0.004 ?.003 +0.004 ?.003 +0.001 ?.002 f f f +0.001 ?.002 +0.004 ?.005 +0.001 ?.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution
70 m pd78p018f drawing of conversion adapter (tgk-064sbw) figure a-3. drawing of tgk-064sbw (for reference only) item millimeters inches b 1.85 0.073 c 3.5 0.138 a 0.3 0.012 d 2.0 0.079 h 5.9 0.232 i 0.8 0.031 j 2.4 0.094 e 3.9 0.154 f 1.325 g 1.325 0.052 0.052 item millimeters inches b 0.65x15=9.75 0.026x0.591=0.384 c 0.65 0.026 a 18.4 0.724 d h 0.65x15=9.75 0.026x0.591=0.384 i 11.85 0.467 j 18.4 0.724 e 10.15 0.400 f 12.55 0.494 k c 2.0 c 0.079 l 12.45 0.490 m q 11.1 0.437 r 1.45 0.057 s 1.45 0.057 n 7.7 0.303 o 10.02 p 14.92 0.587 0.394 w 5.3 0.209 x 4-c 1.0 4-c 0.039 y 3.55 0.140 t 4- 1.3 4- 0.051 u1.8 v 5.0 0.197 0.071 z 0.9 0.035 7.75 10.25 0.305 0.404 g 14.95 0.589 f f f f f f f f k 2.7 0.106 tgk-064sbw-g1e ff tgk-064sbw (tqpack064sb + tqsocket064sbw) package dimension (unit: mm) h a h a g z c l q n b c i j k g f e d m x r s w o p protrusion height u t v k j i y e d b f note : product of tokyo eletech corporation.
71 m pd78p018f appendix b. related documents device related documents document name document no. english japanese m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f data sheet u10280e u10280j m pd78p018f data sheet this document u10955j m pd78018f, 78018fy subseries user's manual u10659e u10659j 78k/0 series user's manual - instructions u12326e u12326j 78k/0 series instruction list u10903j 78k/0 series instruction set u10904j m pd78018f subseries special function register table iem-5594 78k/0 series application note basics (i) u12704e u12704j floating-point arithmetic programs iea-1289 u13482j development tool documents (user's manual) document name document no. english japanese ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly language u11789e u11789j ra78k series structured assembler preprocessor eeu-1402 u12323j cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k/0 c compiler application note programming know-how u13034e u13034j pg-1500 prom programmer u11940e u11940j pg-1500 controller pc-9800 series (ms-dos?) based eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos?) based u10540e eeu-5008 ie-78k0-ns to be prepared to be prepared ie-78001-r-a to be prepared to be prepared ie-78k0-r-ex1 to be prepared to be prepared ie-78018-ns-em1 to be prepared u13289j ep-78240 u10332e eeu-986 ep-78012gk-r eeu-1538 eeu-5012 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specification id78k/0-ns integrated debugger windows based reference u12900e u12900j id78k/0 integrated debugger ews based reference u11151j id78k/0 integrated debugger pc based reference u11539e u11539j id78k/0 integrated debugger windows based guide u11649e u11649j caution the contents of the above related documents are subject to change without notice. the latest documents should be used for design.
72 m pd78p018f embedded software documents (user's manual) document name document no. english japanese 78k/0 series real-time os basics u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 basics u12257e u12257j other documents document name document no. english japanese nec ic package manual (cd-rom) c13388e semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to quality assurance for semiconductor devices mei-1202 microcomputer product series guide u11416j caution the contents of the above related documents are subject to change without notice. the latest documents should be used for design.
73 m pd78p018f [memo]
74 m pd78p018f notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
75 m pd78p018f regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j98. 8
m pd78p018f the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. fip, iebus, and qtop are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. license not needed: m pd78p018fdw, 78p018fkk-s the customer must judge the need for license: m pd78p018fcw, 78p018fgc-ab8, 78p018fgk-8a8 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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