1 1-888-intersil or 321-724-7143 | copyright intersil corporation 1999 a complete analog-to-digital converter operating from a single 3.3v power supply introduction the current data acquisition marketplace has an ever increasing demand for integrated circuits capable of operating with a single 3.3v power supply. the intersil HI-5812 12-bit sampling analog-to-digital converter has proven capable of meeting this market demand and can assist system designers with their 3.3v requirements. the intersil hi-5813, which will be our 3.3v, 12-bit adc with guaranteed 3.3v parameters, is scheduled to be introduced in the fall of 1993. features the intersil HI-5812 is a fast, low power, 12-bit successive approximation analog-to-digital converter capable of operat- ing from a single 3.3v to 6v supply. typical supply current is 1.9ma (when operating with a 5v supply), and the device can operate from either an external clock or from its own internal clock. it is offered over the full industrial temperature range in 24 lead narrow body plastic dip, narrow body ceramic dip, and wide body plastic soic packages. theory of operation the HI-5812 uses capacitor charge balancing to approxi- mate the analog input. the heart of the converter is a capacitor network with a common node connected to a comparator and the second terminal of each capacitor is individually switchable to the analog input, v ref +, or v ref -. a complete conversion takes 15 clock cycles. the ?st three clock cycles are used to auto-balance the comparator at the capacitor common node. the switchable terminal of every capacitor in the network is connected to the analog input during this time. during the fourth clock period, all capacitors are disconnected from the input. the capacitor representing the msb is then connected to the v ref + terminal and the remaining capacitors to v ref -. after the charge balances out, the capacitor common node will indicate whether the input was above 1/2 of ((v ref +) - (v ref -)). at the end of the fourth clock period the comparator output is stored and the msb capacitor is either connected to v ref + (if the comparator output is high) or connected to v ref -. this allows the next comparison to be at either 3/4 or 1/4 of ((v ref +) - (v ref -)). a similar procedure is used during clock periods ?e through ?teen to test the capacitors representing the remaining bits. at the end of each clock cycle the comparator result is stored and each capacitor either connected to v ref + or v ref -. typical 3.3v performance at room temperature, the HI-5812 will typically exhibit eleven bit linearity under the following operating conditions: (1) v dd =v ref + = 3.3v and (2) maximum clock frequency f clkmax = 600khz (which equates to a conversion time of t c =25 s). refer to figure 1 through figure 10 for typical performance curves. note that all data shown was taken at room tempera- ture (+25 o c). power supply current , at reduced supply voltage (3.3v), is typically 500 a and remains relatively independent of the applied external clock frequency (figure 1.) offset and gain errors remain below 2lsbs up to f clk = 600khz (figure 2 and figure 3). both differential and integral linearity also remain below 2lsbs with f clk up to 600khz or 25 s conversion time (figure 4 and figure 5). typical overall 12-bit performance is achievable with f clk up to 500khz or 30 s conversion time. figure 6 and figure 7 are spectral plots of the HI-5812 output with a 1khz sine wave input and clock frequencies of 500khz and 600khz respectively. the plots show that the noise ?or is between -90db and -100db and all harmonics are below -80db for both clock frequencies. figure 8, figure 9 and figure 10 illustrate signal-to-noise + distortion (sinad) vs frequency, total harmonic distortion (thd) vs frequency, and effective number of bits (enob) vs frequency respectively. as expected, each of these parameters degrades with increasing clock frequency. in particular, enob decreases from 11.1 bits at f clk = 500khz to 10.2 bits at f clk = 750khz. figure 11 shows the test circuit used for this 3.3v characterization. conversion time (figure 4 and figure 5). typical overall 12-bit performance is achievable with f clk up to 500khz or 30 s conversion time. figure 6 and figure 7 are spectral plots of the HI-5812 output with a 1khz sine wave input and clock frequencies of 500khz and 600khz respectively. the plots show that the noise ?or is between -90db and -100db and all harmonics are below -80db for both clock frequencies. figure 8, figure 9 and figure 10 illustrate signal-to-noise + distortion (sinad) vs frequency, total harmonic distortion (thd) vs frequency, and effective number of bits (enob) vs frequency respectively. as expected, each of these parameters degrades with increasing clock frequency. in particular, enob decreases from 11.1 bits at f clk = 500khz to 10.2 bits at f clk = 750khz. figure 11 shows the test circuit used for this 3.3v characterization. conclusions the capacitor charge balancing technique used by the HI-5812 lends itself well to operation at reduced supply voltages. optimal performance is determined by the clock frequencies applied. slower clocks allow for additional conversion time and allows the comparator to meet the higher accuracy requirements imposed by both the reduced headroom and the reduced lsb size. eleven bit performance can typically be obtained with clock frequencies less than 600khz (equating to t c = 25 s) and twelve bit performance can typically be achieved with f clk = 500khz (t c = 30 s). application note august 1993 an9326
2 figure 1. dynamic power supply current vs clock frequency v ref = v dd = 3.3v figure 2. offset error (in lsb) vs clock frequency v dd = v ref = 3.3v figure 3. gain error (in lsb) vs clock frequency v ref = v dd = 3.3v figure 4. worst case differential linearity error vs clock frequency v ref = v dd = 3.3v figure 5. integral inearity error vs clock fre- quency v ref = v dd = 3.3v figure 6. spectral plot (f clk = 500khz) 0.60 0.55 0.50 0.45 0.40 f clk (khz) ma 100 200 250 500 600 2.0 1.5 1.0 0.5 lsb 0.0 f clk (khz) 100 200 250 500 600 0.5 0.0 -0.5 -1.0 -1.5 f clk (khz) lsb 100 200 250 500 600 f clk (khz) 100 200 250 500 600 lsb 2.0 1.0 0.0 3.0 2.0 1.0 0.0 lsb f clk (khz) 100 200 250 500 600 11.27 69.4db -81.4dbc enob = sinad = thd = 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 db application note 9326
3 figure 7. spectral plot (f clk = 600khz) figure 8. typical signal to noise + distortion (sinad) v ref = v dd = 3.3v, f in = 1khz figure 9. total harmonic distortion v ref = v dd = 3.3v, f in = 1khz figure 10. effective number of bits v ref = v dd = 3.3v, f in = 1khz 10.84 67.2db 77.3db enob = sinad = thd = 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 db 72 70 68 66 64 62 60 500 600 750 db f clk -68 -70 -72 -74 -76 -78 -80 500 600 750 f clk dbc 11.8 9.0 9.4 9.8 10.2 10.6 11.0 11.4 bits 500 600 750 f clk application note 9326
4 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 figure 11. 0.01 f 0.1 f 10 f 4.7 f v ref+ v in v aa +v dd d11 d0 drdy oem oel str t clk 0.1 f v ref- v aa- v ss +3.3v output data 750khz clock 0.001 f 0.1 f 4.7 f analog input . . . application note 9326
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