2048k x 8 sram module cym1481a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 october 1990 - revised april 16, 2001 1cym1481a features ? high-density 16-megabit sram modules high-speed cmos srams ? access time of 70 ns low active power ? 605 mw (max.), 2m x 8 double-sided smd technology ttl-compatible inputs and outputs small footprint sip ? pcb layout area of 0.72 sq. in. 2v data retention (l version) functional description the cym1481a is a high-performance 16-megabit static ram module organized as 2048k words by 8 bits. these modules are constructed from four 512k x 8 srams in plastic sur- face-mount packages on an epoxy laminate board with pins. on-board decoding selects one of the srams from the high-order address lines, keeping the remaining devices in standby mode for minimum power consumption. an active low write enable signal (we ) controls the writ- ing/reading operation of the memory. when ms and we inputs are both low, data on the eight data input/output pins is writ- ten into the memory location specified on the address pins. reading the device is accomplished by selecting the device and enabling the outputs ms and oe active low while we remains inactive or high. under these conditions, the content of the location addressed by the information on the address pins is present on the eight data input/output pins. the input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (we ) is high. / logic block diagram pin configuration 1481-1 i/o 0 ?i/o 7 a 0 ?a 18 oe a 19 ?a 20 we ms sip top view 1 of 4 decoder 8 2 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 36 35 34 33 32 31 a 20 i/o 3 i/o 2 we v cc a 19 i/o 0 a 1 a 2 a 3 a 4 gnd i/o 5 a 10 a 11 a 5 a 13 a 14 ms a 15 a 16 a 12 a 18 a 6 i/o 1 gnd a 0 a 7 a 8 a 9 i/o 7 i/o 4 i/o 6 a 17 v cc oe 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 19 selection guide cym1481a maximum access time (ns) 70 85 100 120 maximum operating current (ma) 110 110 110 110 maximum standby current (ma) 64 64 64 64
cym1481a 2 maximum ratings (above which the useful life may be impaired.) storage temperature ?55 c to +125 c ambient temperature with power applied0 c to +70 c supply voltage to ground potential?0.3v to +7.0v dc voltage applied to outputs in high z state?0.3v to +7.0v dc input voltage?0.3v to +7.0v output current into outputs (low)20 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% electrical characteristics over the operating range 1481a parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ?1.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 2.0 ma 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ?0.3 0.8 v i ix input load current gnd < v i < v cc ?20 +20 a i oz output leakage current gnd < v o < v cc , output disabled ?20 +20 a i cc v cc operating supply current v cc = max., ms < v il , i out = 0 ma 110 ma i sb1 automatic ms power-down current max. v cc , ms > v ih , min. duty cycle = 100% 64 ma i sb2 automatic ms power-down current max. v cc , ms > v cc ? 0.2v, v in > v cc ? 0.2v, or v in < 0.2v standard 32 ma l version ?100, ?120 500 a l version ?85 1600 a capacitance [1] parameter description test conditions cym1481am ax. unit c ina input capacitance (a 0?16 , oe , we ) t a = 25 c, f = 1 mhz, v cc = 5.0v 125 pf c inb input capacitance (a 17?20 , ms ) 25 pf c out output capacitance 165 pf note: 1. tested on a sample basis.
cym1481a 3 ac test loads and waveforms 1481-3 1481-4 90% 10% 3.0v gnd 90% 10% all input pulses 5v output including jig and scope 5v output 5 pf including jig and scope (a) (b) <10ns <10 n s output r1 2530 ? r2 2830 ? 1340 ? equivalent to: th venin equivalent 2.64v 100 pf r1 2530 ? r2 2830 ? 1481-2 switching characteristics over the operating range [2] 1481a-70 1481a?85 1481a?100 1481a?120 parameter description min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 70 85 100 120 ns t aa address to data valid 70 85 100 120 ns t oha data hold from address change 5 10 10 10 ns t ams ms low to data valid 70 85 100 120 ns t doe oe low to data valid 40 45 50 60 ns t lzoe oe low to low z 5 5 5 5 ns t hzoe oe high to high z [3] 30 30 35 45 ns t lzms ms low to low z [4] 5 10 10 10 ns t hzms ms high to high z [3, 4] 30 30 35 45 ns write cycle [5] t wc write cycle time 70 85 100 120 ns t sms ms low to write end 65 75 90 100 ns t aw address set-up to write end 65 75 90 100 ns t ha address hold from write end 5 7 7 7 ns t sa address set-up to write start 0 5 5 5 ns t pwe we pulse width 65 65 75 85 ns t sd data set-up to write end 30 35 40 45 ns t hd data hold from write end 0 5 5 5 ns t hzwe we low to high z [3] 30 30 35 40 ns t lzwe we high to low z 5 5 5 5 ns notes: 2. test conditions assume signal transition time of 10 s or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v, output loading of 1 ttl load, and 100-pf load capacitance. 3. t hzoe , t hzms , and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads and waveforms. transition is measured 500 mv from steady-state voltage. 4. at any given temperature and voltage condition, t hzms is less than t lzms for any given device. these parameters are guaranteed and not 100% tested. 5. the internal write time of the memory is defined by the overlap of ms low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write.
cym1481a 4 data retention characteristics (l version only) 1481a-70 1481a?85 1481a?100 148a1?120 parameter description test conditions min. max. min. max. min. max. unit v dr v cc for retention data 2 2 2 v i ccdr data retention current v dr = 3.0v, ms > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 800 800 250 a t cdr [6] chip deselect to data retention time 0 0 0 ns t r operation recovery time 5 5 5 ns data retention waveform 1481-6 4.5v 4.5v cs v cc t cdr v dr > 2v data retention mode v dr t r v ih v ih switching waveforms notes: 6. guaranteed, not tested. 7. device is continuously selected. oe , ms = v il . 8. address valid prior to or coincident with ms transition low. read cycle no. 1 previous data valid data valid t rc t aa t oha 1481-7 address dataout [7, 8]
cym1481a 5 notes: 9. we is high for read cycle. 10. data i/o is high impedance if oe = v ih . switching waveforms (continued) read cycle no. 2 data valid t rc t ams t doe t lzoe t lzms high impedance t hzoe t hzms high impedance 1481-8 data out oe ms [8, 9] writecycleno.1 t wc data valid data undefined high impedance t sms t aw t sa t pwe t ha t hd t hzwe t lzwe t sd ms we 1481-9 address data in data i/o [5 , 10]
cym1481a 6 note: 11. if ms goes high simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) writecycleno.2 t wc data valid data undefined high impedance t sms t aw t pwe t ha t hd t hzwe t sd ms we 1481-10 address data in data i/o t sa [5 , 10 , 11]
cym1481a 7 document #: 38-m-00041-*d truth table ms we oe input/outputs mode h x x high z deselect/power-down l h l data out read l l x data in write l h h high z deselect ordering information speed (ns) ordering code package type package type operating range 70 cym1481aps-70c ps10 36-pin sip module commercial CYM1481ALPS-70C 85 cym1481aps?85c ps10 36-pin sip module commercial cym1481alps?85c 100 cym1481aps?100c ps10 36-pin sip module commercial cym1481alps?100c 120 cym1481aps?120c ps10 36-pin sip module commercial cym1481alps?120c
cym1481a ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 36-pin sip module ps10
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