1 tm file number 4919 fsgye033r radiation hardened, segr resistant n-channel power mosfet intersil star*power rad hard mosfets have been speci?ally developed for high performance applications in a commercial or military space environment. star*power mosfets offer the system designer both extremely low r ds(on) and gate charge allowing the development of low loss power subsystems. star*power gold fets combine this electrical capability with total dose radiation hardness up to 100 krads while maintaining the guaranteed performance for single event effects (see) which the intersil fs families have always featured. the intersil family of star*power fets includes a series of devices in various voltage, current and package styles. the portfolio consists of star*power and star*power gold products. star*power fets are optimized for total dose and r ds(on) while exhibiting see capability at full rated voltage up to an let of 37. star*power gold fets have been optimized for see and gate charge combining see performance to 80% of the rated voltage for an let of 82 with extremely low gate charge characteristics. this mosfet is an enhancement-mode silicon-gate power ?ld effect transistor of the vertical dmos (vdmos) structure. it is speci?ally designed and processed to be radiation tolerant. the mosfet is well suited for applications exposed to radiation environments such as switching regulation, switching converters, power distribution, motor drives and relay drivers as well as other power control and conditioning applications. as with conventional mosfets these radiation hardened mosfets offer ease of voltage control, fast switching speeds and ability to parallel switching devices. reliability screening is available as either txv or space equivalent of mil-prf-19500. formerly available as type ta45222w. features 20a (current limited by package), 30v, r ds(on) = 0.014 ? uis rated total dose - meets pre-rad speci?ations to 100 krad (si) single event - safe operating area curve for single event effects - see immunity for let of 82mev/mg/cm 2 with v ds up to 80% of rated breakdown dose rate - typically survives 3e9 rad (si)/s at 80% bv dss - typically survives 2e12 if current limited to i as photo current - 1.0na per-rad (si)/s typically neutron - maintain pre-rad speci?ations for 3e13 neutrons/cm 2 - usable to 3e14 neutrons/cm 2 symbol packaging smd.5 ordering information rad level screening level part number/brand 10k engineering samples fsgye033d1 100k txv FSGYE033R3 100k space fsgye033r4 tm d g s data sheet september 2000 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000 star*power is a trademark of intersil corporation.
2 absolute maximum ratings t c = 25 o c, unless otherwise speci?d fsgye033r units drain to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v ds 30 v drain to gate voltage (r gs = 20k ? ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v continuous drain current t c = 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 20 (note) a t c = 100 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i d 20 (note) a pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 80 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v gs 24 v maximum power dissipation t c = 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p t 75 w t c = 100 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p t 30 w linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.60 w/ o c single pulsed avalanche current, l = 100 h, (see test figure) . . . . . . . . . . . . . . . . . . . . . . . . i as 70 a continuous source current (body diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i s 20 a pulsed source current (body diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i sm 80 a operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c lead temperature (during soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l (distance >0.063in (1.6mm) from case, 10s max) 300 o c weight (typical) 1.0 (typical) g caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: current limited by package. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 1ma, v gs = 0v 30 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 1ma t c = -55 o c - - 5.5 v t c = 25 o c 2.0 - 4.5 v t c = 125 o c 1.0 - - v zero gate voltage drain current i dss v ds = 24v, v gs = 0v t c = 25 o c--25 a t c = 125 o c - - 250 a gate to source leakage current i gss v gs = 24v t c = 25 o c - - 100 na t c = 125 o c - - 200 na drain to source on-state voltage v ds(on) v gs = 12v, i d = 20a - - 0.280 v drain to source on resistance r ds(on)12 i d = 20a, v gs = 12v t c = 25 o c - 0.012 0.014 ? t c = 125 o c - - 0.023 ? turn-on delay time t d(on) v dd = 15v, i d = 20a, r l = 0.75 ? , v gs = 12v, r gs = 7.5 ? - - 20 ns rise time t r - - 55 ns turn-off delay time t d(off) - - 30 ns fall time t f - - 15 ns total gate charge q g(12) v gs = 0v to 12v v dd = 15v, i d = 20a -3538nc gate charge source q gs -1114nc gate charge drain q gd - 8 10 nc gate charge at 20v q g(20) v gs = 0v to 20v - 60 - nc threshold gate charge q g(th) v gs = 0v to 2v - 4 - nc plateau voltage v (plateau) i d = 20a, v ds = 15v - 5.5 - v input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz - 1850 - pf output capacitance c oss - 1120 - pf reverse transfer capacitance c rss -35-pf thermal resistance junction to case r jc - - 1.67 o c/w fsgye033r
3 source to drain diode speci?ations parameter symbol test conditions min typ max units forward voltage v sd i sd = 20a - - 1.2 v reverse recovery time t rr i sd = 20a, di sd /dt = 100a/ s--80ns reverse recovery charge q rr - 100 - nc electrical speci?ations up to 100k rad t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min max units drain to source breakdown volts (note 3) bv dss v gs = 0, i d = 1ma 30 - v gate to source threshold volts (note 3) v gs(th) v gs = v ds , i d = 1ma 2.0 4.5 v gate to body leakage (notes 2, 3) i gss v gs = 24v, v ds = 0v - 100 na zero gate leakage (note 3) i dss v gs = 0, v ds = 24v - 25 a drain to source on-state volts (notes 1, 3) v ds(on) v gs = 12v, i d = 20a - 0.280 v drain to source on resistance (notes 1, 3) r ds(on)12 v gs = 12v, i d = 20a - 0.014 ? notes: 1. pulse test, 300 s max. 2. absolute value. 3. insitu gamma bias must be sampled for both v gs = 12v, v ds = 0v and v gs = 0v, v ds = 80% bv dss . single event effects (seb, segr) note 4 test symbol environment (note 5) applied v gs bias (v) (note 7) maximum v ds bias (v) (note 6 ) typical let (mev/mg/cm) typical range ( ) single event effects safe operating area seesoa 37 36 -5 30 60 32 -2 30 60 32 -5 22.5 82 28 0 24 82 28 -2 22.5 notes: 4. testing conducted at brookhaven national labs or texas a&m. 5. fluence = 1e5 ions/cm 2 (typ), t = 25 o c. 6. ion species: let = 37, br or kr; let = 60, i or xe; let = 82, au. 7. does not exhibit single event burnout (seb) or single event gate rupture (segr). performance curves unless otherwise speci?d figure 1. single event effects safe operating area figure 2. typical see signature curve 0 0-5 v ds (v) v gs (v) let = 60mev/mg/cm 2 , range = 32 let = 37mev/mg/cm 2 , range = 36 let = 82mev/mg/cm 2 , range = 28 40 10 20 30 -7 -6 -4 -3 -2 -1 temp = 25 o c 40 0 0 v ds (v) let = 82 let = 60 let = 37 30 20 10 4 8 12 16 20 24 v gs (v) fsgye033r
4 figure 3. typical drain inductance required to limit gamma dot current to i as figure 4. maximum continuous drain current vs temperature figure 5. forward bias safe operating area figure 6. basic gate charge waveform figure 7. typical normalized r ds(on) vs junction temperature figure 8. typical output characteristics performance curves unless otherwise speci?d (continued) 300 100 10 limiting inductance (henry) drain supply (v) 1000 ilm = 10a 300a 1e-4 1e-5 1e-6 30 100a 30a 1e-7 1e-3 i d , drain (a) t c , case temperature ( o c) 150 100 50 0 -50 0 12 4 8 16 20 24 10 1 1 10 100 100 i d , drain current (a) 0.1 300 v ds , drain to source voltage (v) area may be limited by r ds(on) operation in this 100 s 1ms 10ms t c = 25 o c charge q gd q g v g q gs 12v 2.5 2.0 1.5 1.0 0.5 0.0 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized r ds(on) pulse duration = 250ms, v gs = 12v, i d = 20a 4 2 0 40 0 v ds , drain to source voltage (v) i d , drain to source current (a) v gs = 6v 30 20 10 50 v gs = 4v 135 fsgye033r
5 figure 9. normalized maximum transient thermal response figure 10. unclamped inductive switching performance curves unless otherwise speci?d (continued) normalized thermal response (z jc ) t, rectangular pulse duration (s) 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 1 0.001 0.01 0.1 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc + t c single pulse 0.01 0.02 0.05 0.1 0.5 0.2 p dm t 1 t 2 10 10 1 0.1 1 10 i as , avalanche current (a) 100 t av , time in avalanche (ms) t av = (l) (i as ) / (1.3 rated bv dss - v dd ) if r = 0 starting t j = 150 o c if r 0 t av = (l/r) ln [(i as *r) / (1.3 rated bv dss - v dd ) + 1] starting t j = 25 o c test circuits and waveforms figure 11. unclamped energy test circuit figure 12. unclamped energy waveforms t p v gs 20v l + - v ds v dd dut vary t p to obtain required peak i as 0v 50 ? 50 ? 50v-150v i as + - electronic switch opens when i as is reached current transformer v dd v ds bv dss t p i as t av fsgye033r
6 screening information screening is performed in accordance with the latest revision in effect of mil-prf-19500, (screening information table). figure 13. resistive switching test circuit figure 14. resistive switching waveforms test circuits and waveforms (continued) v ds dut r gs 0v v gs = 12v v dd r l t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs t on delta tests and limits (jantxv equivalent, jans equivalent) t c = 25 o c, unless otherwise speci?d parameter symbol test conditions max units gate to source leakage current i gss v gs = 24v 20 (note 7) na zero gate voltage drain current i dss v ds = 80% rated value 25 (note 7) a drain to source on resistance r ds(on) t c = 25 o c at rated i d 20% (note 8) ? gate threshold voltage v gs(th) i d = 1.0ma 20% (note 8) v notes: 8. or 100% of initial reading (whichever is greater). 9. of initial reading. screening information test jantxv equivalent jans equivalent unclamped inductive switching v gs(peak) = 20v, l = 0.1mh; limit = 70a v gs(peak) = 20v, l = 0.1mh; limit = 70a thermal response t h = 10ms; v h = 25v; i h = 1a; limit = 74mv t h = 10ms; v h = 25v; i h = 1a; limit = 74mv gate stress v gs = 36v, t = 250 sv gs = 36v, t = 250 s pind optional required pre burn-in tests (note 9) mil-prf-19500 group a, subgroup 2 (all static tests at 25 o c) mil-prf-19500 group a, subgroup 2 (all static tests at 25 o c) steady state gate bias (gate stress) mil-prf-750, method 1042, condition b v gs = 80% of rated value, t a = 150 o c, time = 48 hours mil-prf-750, method 1042, condition b v gs = 80% of rated value, t a = 150 o c, time = 48 hours interim electrical tests (note 9) all delta parameters listed in the delta tests and limits table all delta parameters listed in the delta tests and limits table steady state reverse bias (drain stress) mil-prf-750, method 1042, condition a v ds = 80% of rated value, t a = 150 o c, time = 160 hours mil-prf-750, method 1042, condition a v ds = 80% of rated value, t a = 150 o c, time = 240 hours pda 10% 5% final electrical tests (note 9) mil-prf-19500, group a, subgroup 2 mil-prf-19500, group a, subgroups 2 and 3 note: 10. test limits are identical pre and post burn-in. additional tests parameter symbol test conditions max units safe operating area soa v ds = 24v, t = 10ms 6.8 a thermal impedance ? v sd t h = 100ms; v h = 25v; i h = 1a 165 mv fsgye033r
7 rad hard data packages - intersil power transistors txv equivalent 1. rad hard txv equivalent - standard data package a. certificate of compliance b. assembly flow chart c. preconditioning - attributes data sheet d. group a - attributes data sheet e. group b - attributes data sheet f. group c - attributes data sheet g. group d - attributes data sheet 2. rad hard txv equivalent - optional data package a. certificate of compliance b. assembly flow chart c. preconditioning - attributes data sheet - pre and post burn-in read and record data d. group a - attributes data sheet e. group b - attributes data sheet - pre and post read and record data for intermittent operating life (subgroup b3) - bond strength data (subgroup b3) - pre and post high temperature operating life read and record data (subgroup b6) f. group c - attributes data sheet - pre and post read and record data for intermittent operating life (subgroup c6) - bond strength data (subgroup c6) g. group d - attributes data sheet - pre and post rad read and record data class s - equivalents 1. rad hard ??equivalent - standard data package a. certificate of compliance b. serialization records c. assembly flow chart d. sem photos and report e. preconditioning - attributes data sheet - htrb - hi temp gate stress post reverse bias data and delta data - htrb - hi temp drain stress post reverse bias delta data f. group a - attributes data sheet g. group b - attributes data sheet h. group c - attributes data sheet i. group d - attributes data sheet 2. rad hard max. ??equivalent - optional data package a. certificate of compliance b. serialization records c. assembly flow chart d. sem photos and report e. preconditioning - attributes data sheet - htrb - hi temp gate stress post reverse bias data and delta data - htrb - hi temp drain stress post reverse bias delta data - x-ray and x-ray report f. group a - attributes data sheet - subgroups a2, a3, a4, a5 and a7 data g. group b - attributes data sheet - subgroups b1, b3, b4, b5 and b6 data h. group c - attributes data sheet - subgroups c1, c2, c3 and c6 data i. group d - attributes data sheet - pre and post radiation data fsgye033r
8 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 fsgye033r smd.5 3 pad ceramic leadless chip carrier d 1 e 1 e 2 d 2 b a d e 1 - gate 2 - source 3 - drain 1 2 3 symbol inches millimeters notes min max min max a 0.112 0.124 2.84 3.15 3 b 0.090 0.100 2.28 2.54 - d 0.291 0.301 7.39 7.64 - d 1 0.281 0.291 7.13 7.39 - d 2 0.070 0.080 1.78 2.03 - e 0.395 0.405 10.03 10.28 - e 1 0.220 0.230 5.58 5.84 - e 2 0.115 0.125 2.92 3.17 - notes: 1. no current jedec outline for this package. 2. controlling dimension: inch. 3. measurement prior to pre-solder coating the mounting pads. 4. revision 4dated 5-00.
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