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battery protection microsurf? TS8314 ? bi-directional n-chan nel 2.5v specified microsurf? general description taiwan semiconductor?s new low cost, state of the art microsurf? lateral mosfet process technology in chipscale bondwireless packaging minimizes pcb space and r ds(on) plus provides an ultra- low qg x r ds(on) figure of merit. absolute maximum ratings t a =25c unless otherwise noted symbol parameter ratings units v s1s2 source1-source2 voltage 20 v v gs gate-source voltage +12 / -0.5 v i s1s2 source1-source2 current ? continuous 6.5 a ? pulsed 13 p d power dissipation (steady state) 1.3 w t j , t stg operating and storage junction temperature range -55 to +150 oc thermal characteristics r ja thermal resistance, junction-to-ambient 82 c/w r jr thermal resistance, junction-to-balls 7 microsurf? for battery protection patent pending features ? 6.5a, 20v r ds1(on) equivalent = 15m ? at 4.5 volts ? 5.5a, 20v r ds1(on) equivalent = 22m ? at 2.5 volts ? low profile package: le ss than 0.8m m height when mounted on pcb. ? occupies less than 1/5 the area of tssop-8. ? excellent thermal characteristics. ? integrated gate diodes provide electrostatic discharge (esd) protec tion of 4000v human body model (hbm). ? lead free solder bumps available. bottom: bump side preliminary data sheet for information only 1 8/15/03 rev3 d g2 s1 s1 s2 s2 s2 s1 s1 s1 s2 s2 g1 130 o 130 o
electrical characteristics TS8314 preliminary data sheet t a =25c unless otherwise specified symbol parameter test condition min typ max units v (bd)s1s2s source-to-source breakdown voltage v gs =0v, i s =250a 20 v i s1s2s zero gate voltage source current v s1s2 =20v, v gs =0v, t=150c 50 a i gss gate-body leakage v gs =7v, v s1s2 =0v 100 na i gss gate-body leakage v gs =12v, v s1s2 =0v 10 ma v gs(th) gate threshold voltage v s1s2 =v gs , i s =250a 0.8 1.2 v source-to-source on-state resistance v gs =4.5v, i s =6.5a 2630m ? source-to-source on-state resistance v gs =2.5v, i s =5.5a 3844m ? source-to-source on-state resistance v gs =4.5v, i s =6.5a 1315m ? drain-to-source on-state resistance v gs =2.5v, i s =5.5a 1922m ? c is s input capacitance v s1s2 =20v, v g =0v, f=1mhz 1100 pf c oss output capacitance v s1s2 =20v, v g =0v, f=1mhz 400 pf c rs s reverse transfer capacitance v s1s2 =20v, v g =0v, f=1mhz 300 pf q g total gate charge v gs =5v, i s =8a, v s1s2 =10v 15 nc t rr source-drain reverse recovery time i s =1a, v gs =0v, di/dt=100a/s 40 ns v ss diode forward voltage i s =1a, v gs =0v 0.71 v electrical characteristics r s1s2(on) r ds 1(o n ) equivalent 2 8/15/03 rev3
3 v gs = 2.0v v gs = 1.5v v gs = 2.5v v gs = 3.5v v gs = 4.5v 8/15/03 rev3 TS8314
4 125oc 25oc 0 0.4 0.8 1.2 1.6 2.0 8/15/03 rev3 TS8314
5 v gs = 2.5v v gs = 4.5v v gs = 10v 8/15/03 rev3 TS8314
6 125oc 25oc 8/15/03 rev3 TS8314
7 v gs = 5.0v i d = 5a 8/15/03 rev3 TS8314
8 ciss coss crss 8/15/03 rev3 TS8314
9 qg (nc) 8/15/03 rev3 TS8314
10 tj = 150oc tj = 25oc 8/15/03 rev3 TS8314
dimensional outline and pad layout preliminary data sheet silicon 0.80mm max 0.27mm 0.50mm 0.30mm bump ? 0.37mm 1.60mm bumps are eutectic solder 63/37 sn/pb 2.10mm 0.30mm 0.50mm 11 8/15/03 rev3 TS8314
dimensional outline and pad layout preliminary data sheet ? 0.25mm solder mask ? ~ 0.35mm land pattern recommendation d = drain pad s = source pad g = gate pad 831xxx mark on backside of die xxx = date/lot traceability code 0.50mm 0.50mm s2 s2 s2 g1 s2 s2 s1 s1 s1 s1 s1 g2 12 8/15/03 rev3 TS8314
TS8314 thermal resistance analysis 13 gws8314 thermal analysis 8/15/03 rev3
TS8314 die top view - transparent view for clarity. 1/4 symmetry model fr4 board modeled as 1.6mm thick with 2 oz. copper (0.0712mm) plane for drain and source drain (top plane) cutaway detail adiabatic planes 1.00 in. 1.00 in. source (buried plane) not to scale 14 gws8314 thermal analysis 8/15/03 rev3
finite element model: ? linear thermal elements. combination of tetrahedrals, 6 noded prisms and 8 noded bricks ? heat transfer conditions: ? bottom of fr4 board constrained to 25 degrees c ? power dissipation = 0.4 w per quarter model, in the form of a uniform heat flux at the die junction surface. ? linear thermal conduction analysis. no convection or radiation included in model. ? ~9800k elements. 15 gws8314 thermal analysis 8/15/03 rev3
material properties used for analysis model: taiwan semiconductor TS8314 part material thickness (mm) k (w/mc) fr4 1.60000 2.5 copper layers (2 oz.) 0.07120 390 solder (96.8sn/2.6ag/.6cu) 0.27000 50 silicon 0.64000 150 via (composite of cu and epoxy) see model 210 note: 1. values obtained from http://www.boulder.nist.gov/div 853/lead%20free/part2.htm 2. solder thermal conductivity is best conservative estimate based on composition 16 gws8314 thermal analysis 8/15/03 rev3
cross section of fea model d s d s via: 0.25 mm dia. with 2 oz copper plated hole, filled with conductive epoxy. drain plane source plane 1.00 in x 1.00 in board thicknesses si die (0.64 mm) solder bump (0.27 mm) copper (0.0712 mm) = 2 0z. (2.8 mils) fr4 (1.60 mm total) 17 gws8314 thermal analysis 8/15/03 rev3
breakdown of fr4 layers used in the fe model. total thickness 1.6 mm) this illustration shows the ? symmetry model. the actual fe model uses ? symmetry for efficiency. drain plane (2 oz cu) source plane (2 oz cu) intermediate fr4 plane (0.0345mm) fr4 bulk vias 18 gws8314 thermal analysis 8/15/03 rev3
fea model detail note: ? symmetry used. solder balls use tetrahedral elements. all other elements are either prisms or bricks. temp restraint heat flux at junction 19 gws8314 thermal analysis 8/15/03 rev3
general result: about 56% of the temp drop occurs in the fr4 layers, while 44% occurs in the solder ball. detail 20 gws8314 thermal analysis 8/15/03 rev3
fr4: not including copper planes detail 21 gws8314 thermal analysis 8/15/03 rev3
fr4: source plane detail 22 gws8314 thermal analysis 8/15/03 rev3
intermediate fr4 plane detail 23 gws8314 thermal analysis 8/15/03 rev3
drain fr4 plane detail 24 gws8314 thermal analysis 8/15/03 rev3
vias from solder balls to source plane bottom side top side 25 gws8314 thermal analysis 8/15/03 rev3
solder balls: coolest spots hottest spots top side bottom side 26 gws8314 thermal analysis 8/15/03 rev3
silicon: top side bottom side note: the difference between min and max temperatures is only 1.3c. 27 gws8314 thermal analysis 8/15/03 rev3
summary of results thermal resistance calculations: ? t power = junction t j t fr4 fr4 heat layer * ? t (c) resistance (c/w) junction to bottom of ball (average) 10.5000 6.56250 ball to bottom of drain plane 0.0037 0.00231 drain plane to bottom of intermediate fr4 1.3800 0.86250 intermediate fr4 to bottom of source plane 0.0120 0.00750 souce plane to bottom of fr4 12.5500 7.84375 total junction to bottom of fr4 24.4457 15.27856 * temperatures are taken on the hottest spot in each layer and the node directly underneath it on the opposite side 28 gws8314 thermal analysis 8/15/03 rev3

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