1 ps8435b 07/25/00 product pin configuration product description the pi6c2520 is a low-skew, low-jitter, phase-locked loop (pll) clock driver, distributing low-noise clock signals for networking applications. by connecting the feedback fb_out output to the feedback fb_in input, the propagation delay from the clk_in input to any clock output will be nearly zero. this zero-delay feature allows the clk_in input clock to be distributed, providing 5 banks of 4 clocks and an extra clock for feedback. for test purposes, the pll can be bypassed by strapping av cc to ground. the pi6c2520, which allows a spread spectrum clock in- put, operates at 3.3v v cc and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. each bank of outputs can be enabled or disabled via the 1g, 2g, 3g, 4g, and 5g control inputs. when the g inputs are high, the outputs switch in phase and frequency with clk_in. when the g inputs are low, the outputs are disabled to the logic low state. product features ? low-noise phase-locked loop clock distribution. ? allows clock input to have spread spectrum modulation for emi reduction. the clock outputs track the clock input modulation. ? maximum clock frequency of 125 mhz. ? zero input-to-output delay. ? low jitter: cycle-to-cycle jitter 100ps max. ? on-chip series damping resistor at clock output drivers for low noise and emi reduction. ? operates at 3.3v v cc . ? output-to-output skew less than 200ps. ? package: plastic 56-pin tssop (a). 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2520 low-noise phase-locked loop clock driver with 20 clock outputs block diagram clk_in fb_in av cc 4 5y [0:3] fb_out 5g pll 4 3y [0:3] 3g 4 4y [0:3] 4g 4 2y [0:3] 2g 4 1y [0:3] 1g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 v cc 1 y 0 1 y 1 gnd gnd 1 y 2 1 y 3 v cc 1g gnd av cc clk_in agnd 5g gnd 2g v cc 2 y 0 2 y 1 gnd gnd 2 y 2 2 y 3 v cc v cc 5 y 0 5 y 1 gnd v cc 4 y 0 4 y 1 gnd gnd 4 y 2 4 y 3 v cc 4g gnd av cc fb_in agnd fb_out gnd 3g v cc 3 y 0 3 y 1 gnd gnd 3 y 2 3 y 3 v cc v cc 5 y 3 5 y 2 gnd 56-pin a
pi6c2520 low-noise, phase-locked loop clock driver with 20 clock outputs 2 ps8435b 07/25/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 e m a n n i pr e b m u n n i pe p y tn o i t p i r c s e d n i _ k l c2 1i . m u r t c e p s d a e r p s s w o l l a k l c . t u p n i k c o l c n i _ b f5 4i . t u p n i k c a b d e e fn i _ b f. l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f e h t s e d i v o r p g 19i o t d e l b a s i d e r a ] 3 : 0 [ y 1 s t u p t u o , w o l s i g 1 n e h w . e l b a n e k n a b t u p t u o . d e l b a n e e r a ] 3 : 0 [ y 1 s t u p t u o l l a , h g i h s i g 1 n e h w . e t a t s w o l c i g o l a g 26 1i o t d e l b a s i d e r a ] 3 : 0 [ y 2 s t u p t u o , w o l s i g 2 n e h w . e l b a n e k n a b t u p t u o . d e l b a n e e r a ] 3 : 0 [ y 2 s t u p t u o l l a , h g i h s i g 2 n e h w . e t a t s w o l c i g o l a g 31 4i o t d e l b a s i d e r a ] 3 : 0 [ y 3 s t u p t u o , w o l s i g 3 n e h w . e l b a n e k n a b t u p t u o . d e l b a n e e r a ] 3 : 0 [ y 3 s t u p t u o l l a , h g i h s i g 3 n e h w . e t a t s w o l c i g o l a g 48 4i o t d e l b a s i d e r a ] 3 : 0 [ y 4 s t u p t u o , w o l s i g 4 n e h w . e l b a n e k n a b t u p t u o . d e l b a n e e r a ] 3 : 0 [ y 4 s t u p t u o l l a , h g i h s i g 4 n e h w . e t a t s w o l c i g o l a g 54 1i o t d e l b a s i d e r a ] 3 : 0 [ y 5 s t u p t u o , w o l s i g 5 n e h w . e l b a n e k n a b t u p t u o . d e l b a n e e r a ] 3 : 0 [ y 5 s t u p t u o l l a , h g i h s i g 5 n e h w . e t a t s w o l c i g o l a t u o _ b f3 4o . t u p t u o k c a b d e e ft u o _ b f. k c a b d e e f l a n r e t x e r o f d e t a c i d e d s it u o _ b f s t u p t u o k c o l c e h t s a e u l a v e m a s e h t f o r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h . x y 5 d n a , x y 4 , x y 3 , x y 2 , x y 1 ] 3 : 0 [ y 17 , 6 , 3 , 2o . k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c . r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h t u p t u o h c a e ] 3 : 0 [ y 23 2 , 2 2 , 9 1 , 8 1o . k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c . r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h t u p t u o h c a e ] 3 : 0 [ y 34 3 , 5 3 , 8 3 , 9 3o . k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c . r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h t u p t u o h c a e ] 3 : 0 [ y 40 5 , 1 5 . 4 5 , 5 5o . k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c . r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h t u p t u o h c a e ] 3 : 0 [ y 51 3 , 0 3 , 7 2 , 6 2o . k l c f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c . r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h t u p t u o h c a e v a c c 6 4 , 1 1r e w o p v a . y l p p u s r e w o p g o l a n a c c r o f l l p e h t s s a p y b o t d e s u o s l a e b n a c v a n e h w . s e s o p r u p t s e t c c d n a d e s s a p y b s i l l p , d n u o r g o t d e p p a r t s s i k l c. s t u p t u o e c i v e d e h t o t y l t c e r i d d e r e f f u b s i d n g a4 4 , 3 1d n u o r g y r t i u c r i c g o l a n a e h t r o f e c n e r e f e r d n u o r g e h t s e d i v o r p d n g a . d n u o r g g o l a n a v c c , 0 4 , 3 3 , 2 3 , 5 2 , 4 2 , 7 1 , 8 , 1 6 5 , 9 4 r e w o py l p p u s r e w o p d n g , 9 2 , 8 2 , 1 2 , 0 2 , 5 1 , 0 1 , 5 , 4 3 5 , 2 5 , 7 4 , 2 4 , 7 3 , 6 3 d n u o r gd n u o r g pin functions
pi6c2520 low-noise, phase-locked loop clock driver with 20 clock outputs 3 ps8435b 07/25/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 supply voltage range, v cc ............................................................................................................................... .................... ?0.5v to 4.6v input voltage range, v i (1) ............................................................................................................................... ..................... ?0.5v to 6.5v voltage range applied to any output in the high or low state, v o (1,2) ................................................... ?0.5v to v cc +0.5v input clamp current, i ik (v i <0) ......................................................................................................................... ?50 ma output clamp current, i ok (v o <0 or v o > v cc ) ............................................................................................... 50ma continuous output current, i o (v o - 0 to v cc ) ................................................................................................. 50ma continuous current through each v cc or gnd .............................................................................................. 100ma maximum power dissipation at t a = 55c (in still air) (3) ........................................................................................................ 0.85w storage temperature range, t stg ............................................................................................................................... .... ?65c to 150c absolute maximum ratings (over operating free-air temperature, unless otherwise noted) ? ? stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. this value is limited to 4.6v maximum. 3. maximum package power dissipation is calculated using a junction temperature of 150c and a board trace length of 750 mils. l o b m y sr e t e m a r a p. n i m. x a ms t i n u v c c e g a t l o v y l p p u s36 . 3 v v h i e g a t l o v t u p n i l e v e l - h g i h2 v l i e g a t l o v t u p n i l e v e l - w o l 8 . 0 v i e g a t l o v t u p n i0v c c i h o t n e r r u c t u p t u o l e v e l - h g i h 2 1 ? a m i l o t n e r r u c t u p t u o l e v e l - w o l 2 1 t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o00 7c recommended operating conditions (4) notes: 4. unused inputs must be held high or low to prevent them from floating. function table g xn i _ k l c] 3 : 0 [ y xt u o _ b f lll l lhl h hll l hhh h note: x is from 1 to 5
pi6c2520 low-noise, phase-locked loop clock driver with 20 clock outputs 4 ps8435b 07/25/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 l o b m y sn o i t i d n o c t s e tv c c . n i m. p y t ) 1 ( . x a ms t i n u v , k i e g a t l o v p m a l c t u p n ia m 8 1 ? t a t n e r r u c t u p n iv 39 7 . 0 ?2 . 1 ? v v h o i h o =? a 0 0 1. x a m o t . n i mv c c 2 . 0 ?9 9 . 2 i h o =? a m 2 1 v 3 1 . 26 6 . 2 i h o =? a m 64 . 23 8 . 2 v l o i l o a 0 0 1 =. x a m o t . n i m1 0 . 02 . 0 i l o a m 2 1 = v 3 3 . 08 . 0 i l o a m 6 =5 1 . 05 5 . 0 i , i t n e r r u c t u p n iv = e g a t l o v t u p n i k c o l c c c d n g r o v 6 . 3 5 a i , c c t n e r r u c y l p p u s g o l a n av = e g a t l o v t u p n i k c o l c c c d n g r o0 2 c i v = e g a t l o v t u p n i c c d n g r o v 3 . 3 45 . 3 f p c o v = e g a t l o v t u p t u o c c d n g r o6 d i c c v @ t u p n i e n o c c , v 6 . 0 ? v @ s t u p n i r e h t o c c d n g r o v 6 . 3 o t v 3 . 30 . 40 0 5a electrical characteristics (over recommended operating free-air temperature range, unless otherwise noted) notes: 1. for min. or max. conditions, use the appropriate value specified under recommended operating conditions. r e t e m a r a p) t u p n i ( m o r f) t u p t u o ( o t v c c v 3 . 0 v 3 . 3 = s t i n u . n i m. p y t. x a m t e s a h p r o r r en i _ k l c - z h m 0 0 1 =n i _ b f - 0 7 1 s p t ) o ( k s ) 2 ( t u o b f r o y y n a t u o _ b f r o y y n a 0 0 2 r e t t i j ) k p - k p ( ) z h m 6 6 > n i _ k l c ( f0 0 1 ?0 0 1 e l c y c y t u d n i _ k l c ( f ) z h m 6 65 45 5 % ) z h m 6 6 > n i _ k l c ( f5 45 5 t r % 0 8 o t % 0 2 m o r f d e r u s a e m 7 . 08 . 2 s n t f 2 . 18 . 2 switching characteristics ( over recommended ranges of supply voltage & operating free-air temperature, c l = 22pf) (1,3) notes: 1. these parameters are not production tested. 2. the t sk(o) specification is only valid for equal loading of all outputs. 3. the specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. timing requirements (over recommended ranges of supply voltage and operating free-air temperature). l o b m y sr e t e m a r a p. n i m. x a ms t i n ue t o n f k l c y c n e u q e r f k c o l c5 25 2 1z h m1 d i y c e l c y c y t u d k c o l c t u p n i0 40 6% t n o i t a z i l i b a t s p u r e w o p r e t f a e m i t n o i t a z i l i b a t s1s m
pi6c2520 low-noise, phase-locked loop clock driver with 20 clock outputs 5 ps8435b 07/25/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information load circuit from output under test 22pf 500 w 50% v cc 50% v cc 3v 0v 50% v cc v oh v ol input output t pd t r t f 80% 20% 80% 20% voltage waveforms propagation delay times notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: clk_in 100mhz, z o = 50 ohms, t r 1.2ns, t f 1.2ns. 3. the outputs are measured one at a time with one transition per measurement. clk_in fb_in fb_out any y t phase error t sk(o) any y any y t sk(o) phase error and skew calculations
pi6c2520 low-noise, phase-locked loop clock driver with 20 clock outputs 6 ps8435b 07/25/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 56-pin thin shrink small-outline package (a) .002 .006 seating plane .007 .011 .004 .008 1 56 .236 .244 0.50 0.17 0.27 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 max. 1.20 6.0 6.2 .547 .555 13.9 14.1 .319 8.1 .0197 bsc bsc r e b m u n t r a pn / p g n i r e d r oe g a k c a p 0 2 5 2 c 6 i pa 0 2 5 2 c 6 i pp o s s t n i p - 6 5 ordering information
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