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document number: mc33811 rev. 2.0, 9/2007 freescale semiconductor product preview ? freescale semiconductor, in c., 2007. all rights reserved. *this document contains certain inform ation on a product under development. free- scale reserves the right to change or discontinue this product without notice solenoid monitor integrated circuit (ic) the 33811 is a 5 channel solenoid monitor ic that is used to verify proper electrical and mechanical so lenoid operation. the ic contains five solenoid driver voltage monito ring stages and a serial peripheral interface (spi) for fault communication and setup. the ic has the ability to determine the correct movement of solenoid armatures by analyzing the variation in the voltage profile, across the solenoid driver mosfet, which represents th e actual solenoid current profile. these features, along with cost effective packaging, make the 33811 ideal for powertrain solenoid monitoring applications. features ? typical operating voltage range, 10.5 < vpwr < 15.5 volts ? interfaces to 3.3 and 5 volt microprocessors via spi protocol ? reset pin to initialize all 5 fault outputs ? internal voltage regulator ? internal oscillator ? unique solenoid current profile detection circuitry ? pb-free packaging designated by suffix code eg figure 1. 33811 simplified application diagram solenoid monitor eg suffix (pb_free) 98asb42567b 16-pin soicw 33811 ordering information device temperature range (t a ) package pcz33811eg/r2 -40c to 125c 16 soicw vdd si so sclk cs mosi miso sclk cs v bat solm5 mcu vspi reset 33811 v bat v bat d_gnd solenoid driver v bat v bat v bat out1 out2 out3 out4 out5 vpwr vdd solenoids solm4 solm3 solm1 in1 in2 in3 in4 in5 ports p00 p01 p02 p05 p04 p03 a_gnd solm2
analog integrated circuit device data 2 freescale semiconductor 33811 internal block diagram internal block diagram figure 2. 33811 simplifi ed internal block diagram vpwr, vdd, 5.0 v oscillator si sclk cs so spi interface waveform detection circuitry reset solm1 vpwr vdd d_gnd 15a 15a v dd and clock generator waveform detection circuitry solm3 waveform detection circuitry solm2 waveform detection circuitry solm4 waveform detection circuitry solm5 a_gnd vspi
analog integrated circuit device data freescale semiconductor 3 33811 pin connections pin connections figure 3. 33811 pin connections 1 2 3 4 5 6 16 15 7 8 14 13 12 11 10 9 a_gnd n/c solm1 solm2 solm3 solm4 solm5 vpwr vdd d_gnd reset vspi so si sclk cs table 1. 33811 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 11 . pin number pin name pin function formal name definition 1 vdd power digital voltage supply the vdd pin is the digital logic suppl y voltage used internally in the ic. 2 d_gnd ground digital ground digital ground for the internal control ci rcuits of the ic. this ground should be used for decoupling of the vdd supply. 3 so output serial output data the so output pin is used to transmit serial data from the device to the mcu. the so pin remains tri-state until selected by the active low cs . the serial output data is available to be latched by the mcu on the rising edge of sclk. the so data transitions on falling edge of the sclk. 4 si input serial input data the si input pin is used to receive se rial data from the mcu. the serial input data is latched on the rising edge of sclk, and the input data transitions on the falling edge of sclk. 5 cs input chip select the chip select input pin is an active low signal sent by the mcu to indicate that the device is being addr essed. this input requires cmos logic levels and has an internal active pull-up current source. 6 sclk input serial clock input the sclk input pin is used to clock in and out the serial data on the si and so pins while being addressed by the cs . the sclk signal consists of a 50% duty cycle with cmos logic levels. input data is latched by the device on the rising edge of sclk while output data is changed on the falling edge. sclk is ignored by the device while cs is high. 7 reset input reset input the reset pin, when pulled high, cl ears any fault bits and causes the serial output pin to be tri-stated. the reset pin operates at the cmos levels dictated by the vdd line and the state of the vspi pin. 8 vspi input v spi the vspi pin determines the voltage levels for the spi interface. it must be connected to the same voltage supply (+5 volts or +3.3 volts) as the mcu?s spi interface. 9 vpwr power analog voltage supply the analog voltage supply provides the power for all the input amplifiers and other analog circuitry in the ic. 10 solm5 input solenoid monitor 5 the solenoid monitor input is connected to the solenoid coil at the output driver. it monitors the current wavefo rm through the solenoid coil as it appears as a voltage across the output driver mosfet. 11 solm4 input solenoid monitor 4 the solenoid monitor input is connected to the solenoid coil at the output driver. it monitors the current wavefo rm through the solenoid coil as it appears as a voltage across the output driver mosfet.
analog integrated circuit device data 4 freescale semiconductor 33811 pin connections 12 solm3 input solenoid monitor 3 the solenoid monitor input is connected to the solenoid coil at the output driver. it monitors the current wavefo rm through the solenoid coil as it appears as a voltage across the output driver mosfet. 13 solm2 input solenoid monitor 2 the solenoid monitor input is connected to the solenoid coil at the output driver. it monitors the current wavefo rm through the solenoid coil as it appears as a voltage across the output driver mosfet. 14 solm1 input solenoid monitor 1 the solenoid monitor input is connected to the solenoid coil at the output driver. it monitors the current wavefo rm through the solenoid coil as it appears as a voltage across the output driver mosfet. 15 n/c no connect no connect this pin is not to be used and must be left open in any design. 16 a_gnd ground analog ground the analog ground is the return for the vdd and vpwr supply. table 1. 33811 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 11 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33811 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings supply voltage (continuous) vpwr vdd vspi v pwr v dd v spi -1.5 to 25 -0.3 to 7.0 -0.3 to 7.0 v dc supply voltage (transient) on vpwr v pwrmax -1.5 to 50 v dc cs , si, so, sclk, reset ? -0.3 to v spi v dc solenoid monitor inputs maximum voltage (5ms. maximum duration) v injmxmax 64 v dc frequency of spi operation (v dd = 5.0v) (1) ? 3.2 mhz esd voltage (2) human body model (3) machine model v esd1 v esd2 2000 200 v thermal ratings peak package reflow temperature during reflow (4) , (5) t pprt note 5 c storage temperature t stg -55 to 150 c operating ambient temperature t a -40 to 125 c operating junction temperature t j -40 to 150 c notes 1. this parameter is guaranteed by design but is not production tested. 2. esd testing is performed in accordance with the human body model (hbm) (per aec-q100-002, c zap = 100pf, r zap = 1500 ? ) and the machine model (mm) (per aec-q100-002, c zap = 200pf, r zap = 0 ? ). esd data available upon request. 3. all pins when tested individually. 4. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data 6 freescale semiconductor 33811 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 7.0v v pwr 17v, - 40 c t a 125 c, gnd = 0v, unless othe rwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power input (vpwr, ipwr, ivdd, vdd, idd) analog supply voltage range fully operational v pwr (fo) 10.5 ? 15.5 v digital logic supply voltage range fully operational v dd (fo) 4.75 5.0 5.25 v spi voltage supply voltage range fully operational v spi(fo) 3.0 3.3 5.0 5.25 v supply current from vpwr all outputs disabled (normal & default mode) v pwr = 17v i pwr (on) ? 1.0 5.0 ma supply current from vdd all outputs disabled (normal & default mode) v dd = 5.5v i dd (on) 1.0 5.0 ma positive threshold voltage point a (10.5v < = vpwr < = 15.5v) v+ th_a 0 0.5 1.0 mv positive threshold voltage point a with offset (10.5v < = vpwr < = 15.5v) v+ th_a_offset 1.5 mv positive threshold voltage point b(10.5v < = vpwr < = 15.5v) v+ th_b 1.5 3.0 4.5 mv negative threshold voltage (10.5v < = vpwr < = 15.5v) v- th 0 -0.5 -1.0 mv negative threshold voltage with offset (10.5v < = vpwr < = 15.5v) v- th_offset -1.5 mv logic supply voltage v dd 3.0 ? 5.5 v logic supply current static condition i dd 250 400 700 a spi digital interface (vih, vil, vhys, cin, logicss) input logic high-voltage thresholds (8) v ih 0.7 x v spi ? v spi + 0.3 v input logic low-voltage thresholds (8) v il gnd - 0.3 ? 0.2 x v spi v input logic voltage hysteresis (8) v hys 100 ? 300 mv input logic capacitance (9) c in ? ? 20 pf notes 6. output fault detection thresholds with outputs programmed off. output fault detect thresholds are the same for output open an d shorts. 7. this parameter is guaranteed by design, however is not production tested. 8. parameter applies to si, reset, cs and is guaranteed by design. 9. undervoltage thresholds minimum and maximum include hysteresis.
analog integrated circuit device data freescale semiconductor 7 33811 electrical characteristics static electrical characteristics normal mode input logic pull-down current 0.8v to 5.0v (si) i spipd 5.0 10 25 a cs , reset pull-up current ( cs , reset = 0) i defaultpu -5.0 -10 -25 a sclk, tri-state so output 0.0 v to 5.0 v i sck, i triso -10 ? 10 a cs input current cs = v spi i cs -10 ? 10 a cs leakage current to v spi cs = 5.0v, v spi = 0.0v i cs (lkg) ? ? 10 a so high-state output voltage i sohigh = -1.0ma v sohigh v spi - 0.4 ? ? v so low-state output voltage i solow = 1.0 ma v solow ? ? 0.4 v solenoid monitor input pull-up current (v solm = 0v) i solm_pu -2.5 -5 -12.5 a solenoid monitor input leakage current (v solm = 64v) i solm_lkg -10 ? 10 a table 3. static elec trical characteristics characteristics noted under conditions 7.0v v pwr 17v, - 40 c t a 125 c, gnd = 0v, unless othe rwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33811 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 10.5v v pwr 15.5v, - 40 c t a 125 c, gnd = 0v, unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit spi digital interface timing (10) required high state duration on reset for reset to occur (11) t reset 1.0 ? ? s falling edge of cs to rising edge of sclk required setup time t lead 100 ? ? ns falling edge of sclk to rising edge of cs required setup time t lag 0 50 ns si to rising edge of sclk required setup time t si (su) 16 ? ? ns rising edge of sclk to si required hold time t si (hold) 20 ? ? ns si, cs , sclk signal rise time (12) t r (si) ? 5.0 ? ns si, cs , sclk signal fall time (12) t f (si) ? 5.0 ? ns time from falling edge of cs to so low-impedance (13) t so (en) ? 65 80 ns time from rising edge of cs to so high-impedance (14) t so (dis) ? ? 55 ns time from falling edge of sclk to so data valid (15) t valid ? 65 90 ns sequential transfer rate time required between data transfers t str 1.0 s input capacitance (si, sclk) c input 7 15 pf load capacitance (so) c load 200 pf tri-state output capacitance (so) c tri-state 20 pf waveform detection timings start of activation filter time (16) t begin 200 400 600 s detection window time t window 40 53 66 ms sample time t sam 72 s notes: 10. these parameters are guaranteed by design. production test equipment uses 3.2mhz, 5.0v spi interface. 11. this parameter is guaranteed by desi gn, however it is not production tested. 12. rise and fall time of incoming si, cs , and sclk signals suggested for design consideration to prevent the occurrence of double pulsing. 13. time required for valid output status data to be available on so pin. 14. time required for output states data to be terminated at so pin. 15. time required to obtain valid data out from so following the fall of sclk with 200pf load. 16. 9 s guard band included in maximum limit
analog integrated circuit device data freescale semiconductor 9 33811 electrical characteristics timing diagrams timing diagrams figure 4. spi timing characteristics parallel ports microcontroller 33811 33811 si sclk cs si so sclk cs so sclk miso mosi shift register t so(dis) 0.7 v dd 0.2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t so(en) t si(su) t si(hold) t valid t lag cs sclk si so msb in msb out lsb out 0.7 v dd 0.2 v dd
analog integrated circuit device data 10 freescale semiconductor 33811 electrical characteristics microcontroller parametrics microcontroller parametrics spi - mcu interface description the 33811 device directly interfaces to a 3.3v or 5.0v micro controller unit (mcu) using 16 bit serial peripheral interface (spi) protocol. spi serial clock frequencies up to 3.2mhz may be used when programming and reading output status information (product ion tested at 3.2mhz). figure 5 illustrates the serial peripheral interface (spi) configuration between an mcu and one 33811. command data is sent to the 33811 device through the si input pin. as data is being clo cked into the si pin, status information is being clocked out of the device by the so output pin. the response data received by the mcu during spi communication depends on the previous spi message sent to the device. next so response data is listed at the bottom of each command table. spi integrity check checking the integrity of the spi communication with the initial power-up of the vdd and reset pins is recommended. after initial system start-up or reset, the mcu will write one 16-bit pattern to the 33811. the first 8 bits read by the mcu will be the fault status (so message 1) of the outputs. the second 8 bits will be the same bit pattern sent by the mcu. by the mcu receiving the same bit pattern it sent, bus integrity is confirmed. the second 16-bit pattern the mcu sends to the device is the a command word and will be operated on by the device accordingly on rising edge of cs . important a sclk pulse count strategy has been implemented to ensure integrity of spi communications. spi messages consisting of 16 sclk pulses and multiples of 8 clock pulses thereafter will be acknowledged. spi messages consisting of other than 16 + multiples of 8 sclk pulses will be ignored by the device. figure 5. spi interface with microprocessor two or more 33811 devices may be used in a module system. multiple ics may be sp i-configured in parallel or serial. figures 6 shows the configurations. when using the serial configuration, 32-clock cycles are required to transfer data in / out of the ics. figure 6. spi parallel interface with microprocessor 33811 microcontroller receive buffer parallel ports fault bits 16-bit shift register shift register mosi si miso so sclk cs parallel ports microcontroller 33811 33811 si sclk cs si so sclk cs sclk miso mosi shift register so
analog integrated circuit device data freescale semiconductor 11 33811 functional description functional pin description functional description functional pin description analog voltage supply (vpwr) the vpwr pin is battery input to the 33811 ic. the vpwr pin requires external reverse bat tery and transient protection. maximum input voltage on vpwr is 15.5v for full operation. all ic analog current is provided from the vpwr pin through an internal voltage regulator. the vpwr pin requires adequate decoupling capacitance to the a_gnd pin. digital voltage supply (vdd) the vdd pin is logic supply input to the 33811 ic. maximum input voltage on vdd is 5.25v for full operation. all ic digital logic current except the spi so output pin is provided from the vdd pin. the vdd pin requires adequate decoupling capacitance to the d_gnd pin. spi interface voltage (vspi) the vspi input pin is used to determine communication logic voltage levels between the microprocessor and the 33811 device. current from vspi is used to drive so output and pull-up current for cs and si. vspi must be connected to +5 volts or +3.3 volts for normal operation. analog ground (a_gnd) the analog ground (a_gnd) pin provides a low current analog ground for the ic. the vpwr supply is referenced to the a_gnd pin. the a_gnd pin should be used for decoupling the vpwr pin. digital ground (d_gnd) the digital ground (d_gnd) pin provides a dedicated ground for the vdd and vspi supplies and should be connected to the a_gnd pin. serial clock input (sclk) the system clock (sclk) pi n clocks the internal shift register of the 33811. the si data is latched into the input shift register on the rising edge of sclk signal. the so pin shifts status bits out on the falling edge of sclk. the so data is available for the mcu to read on the rising edge of sclk. with cs in a logic high state, signals on the sclk and si pins will be ignored and the so pin is tri-state. chip select ( cs ) the system mcu selects the 33811 to receive communication using the chip select ( cs ) pin. with the cs in a logic low state, command words may be sent to the 33811 via the serial input (si) pin, and status information is received by the mcu via the serial output (so) pin. the falling edge of cs enables the so output and tr ansfers status information into the so buffer. rising edge of the cs initiates the following operation: 1. disables the so driver (high-impedance) 2. activates the received command word, allowing the 33811 to activate/deactivate output drivers. to avoid any spurious data, it is essential the high-to-low and low-to-high transitions of the cs signal occur only when sclk is in a logic low state. internal to the 33811 device is an active pull-up to v spi on cs . in cases where voltage exists on cs without the application of v spi , no current will flow from cs to the v spi pin. serial input data (si) the si pin is used for serial instruction data input. si information is latched into the input register on the rising edge of sclk. a logic high state present on si will program a one in the command word on the rising edge of the cs signal. to program a comp lete word, 16 bits of information must be entered into the device. serial output data (so) the so pin is the output from the shift register. the so pin remains tri-stated until the cs pin transitions to a logic low state. all normal operating drivers are reported as zero, all faulted drivers are reported as one. the negative transition of cs enables the so driver. the si / so shifting of the data follows a first-in-first-out protocol, with both input and ou tput words transferring the most significant bit (msb) first. reset input (reset) the reset pin is an active high digital input pin used to clear the fault outputs and registers in the device. during normal operation the reset pin should be held low. solenoid monitor input (solm1, solm2, solm3, solm4, solm5) these are the five solenoid monitor inputs that are connected to the solenoid so lenoid driver output pins.
analog integrated circuit device data 12 freescale semiconductor 33811 functional description functional internal block description functional internal block description figure 7. functional internal block diagram power supply and oscillator the 33811 is designed to operate from 10.5v to 15.5v on the vpwr pin. the vpwr pin supplies power to the internal regulator which, in turn, suppli es the analog circuit blocks. the vdd supply is used internally to supply the logic circuitry. the vspi supply is used for setting the spi communication threshold levels by supplying power to the so driver and the si and cs input buffers. the on-chip oscillator is used to set the solenoid sample period window and sample rate. mcu interface: the 33811 device directly interfaces to a 3.3v or 5.0v micro controller unit (mcu) using 16 bit serial peripheral interface (spi) protocol. spi serial clock frequencies up to 3.2mhz may be used when prog ramming and reading output status information. the reset pin is used to place the 33811 into the reset mode. normally the reset pin is held at logic 0 by the mcu. when the m cu raises the reset pin to a logic 1, the 33811 enters the reset mode. the reset initializes the 5 fault outputs. solenoid monitors : solm1 - solm5 these are the five solenoid monitor inputs that are connected to the external soleno id driver output pins. the ic has the ability to determine the correct movement of solenoid armatures by analyzing the variation in the voltage profile, across the solenoid driver mosfet, which represents the actual solenoid current profile.
analog integrated circuit device data freescale semiconductor 13 33811 functional device operation operational modes functional device operation operational modes power supply the 33811 is designed to operate from 10.5v to 15.5v on the vpwr pin. the vpwr pin supplies power to the internal regulator which, in turn, suppli es the analog circuit blocks. the vdd supply is used internally to supply the logic circuitry. the v spi supply is used for setting the spi communication threshold levels by supplying power to the so driver and the si and cs input buffers. this ic architecture provides flexible microprocessor interfacing. normal mode the normal mode of operation occurs when the following conditions are met: 1) device junction temperature is below 125c. 2) v pwr is >10.5v and < 15.5v 3) v dd is > 4.75v and < 5.5v 4) a logic low (0) level is present on the reset pin. 5) v spi is 3.3v or 5.0 volts the major function of the 3 3811 integrated circuit is provide the engine or transmission control mcu with information about the status of up to five solenoids. when a solenoid is activated and operates properly, a unique current profile is produced. this current profile can be observed as a voltage waveform across the solenoid?s low side driver mosfet. the solenoid monitor inputs (solm1-5) on the 33811 are connected to voltage waveform monitoring circuits that are capable of discerning a properly opening and closing solenoid from one that is malfunctioning. when the 33811 determines that an solenoid is malfunctioning, a fault bit is set in the corresponding solenoid spi register. when the mcu interrogates the 33811 via the spi, the solenoid fault will be annunciated by setting the appropriate spi fault bit to a logic one (1). serial output (so) response all fault reporting is accomplished through the spi interface. all logic [1]s received by the mcu from the so pin indicate individual solenoid faults or the ic being held in the reset mode. all logic [0]s received by the mcu from the so pin indicate no fault, or normal operating solenoids. all fault bits are cleared on the positive edge of cs . so bits 15, 14, 13, 12, and 11 represent the fault status of solenoids 4,3,2,1,and 5 respectively. reset mode the reset pin is used to plac e the 33811 into the reset mode. normally the reset pin is held at logic 0 by the mcu. when the mcu raises the reset pin to a logic 1, the 33811 enters the reset mode causing two events to occur: 1) the internal solenoid spi register bits are cleared to 0. 2) the so output pin is tri-st ated, and pulled high by a pull- up resistor, causing all subseq uent spi responses to contain all bits set to logic (1). when the reset pin is brought low again, the so pin will be un-tri-stated and the spi data will again reflect the data contained in the spi register a nd the solenoid fault register. spi communication the 33811 integrated circuit communicates to the mcu via the spi (serial peripheral interface). the spi communication can be between one mcu and one 33811, or it can be between one mcu and several 33811 ics. the mcu can send two different spi messages to the 33811, one 8 bits in length and one 16 bits in length. the 33811 responds by sending back 8 bit or 16 bit messages. when the mcu sends an 8 bit message to the 33811, the 33811 responds by sending only the 8 bit fault status. the fault status contains 5 bits of solenoid status and 3 bits of logic zeros. when the mcu sends a 16 bit interrogate message, the 33811 responds by sending the 8 bit fault status message followed by the last 8 previously sent bits. the 33811 ic does not decode the spi messages from the mcu. it will always respond in the same way, regardless of the contents of the 8 or 16 bits sent. hence, no specific spi commands are defined, and response is limited to either solenoid fault status alone, when an 8 bit message is sent, or the solenoid fault status along with the last 8 bits received when a 16 bit message is sent. the two spi scenarios are outlined in the following diagrams. spi communication summary 1) the spi communications seque nce starts out in step 1 above with the contents of t he mcu spi shift register containing 8 bits of x x x x x x x x and 8 bits of y y y y y y y y . the 33811 spi register contains a previous 8 bit byte of p p p p p p p p and the contents of the solenoid status register of 0 0 0 s5 s1 s2 s3 s4 is transferred into the spi register. the condition shown is prior to the spi transfer. 2) the mcu starts the transfer of data from it?s 16 bit spi register to the 33811?s spi register by setting cs to a logic 0 and by issuing 16 sclk pulses. at the end of the 16 sclk pulses, the mcu brings cs back high to a logic 1. when the transfer is complete the mcu now contains t he contents of the 33811?s spi register and the 33811 contains the contents of the mcu?s spi register.
analog integrated circuit device data 14 freescale semiconductor 33811 functional device operation operational modes 3) step 3 demonstrates an 8 bit spi transfer. the same exchange is performed, however, only 8 sclk pulses are issued and only 8 bits of data are exchanged. 4) when the transfer is comp lete, only the eight bits of solenoid status has been transfe rred to the mcu. the data in the 33811?s spi register lower 8 bits has been overwritten with the data from the mcu?s spi register. 5) step 5 shows the same scenario as step 3 however, before the transfer, the reset pin is brought to a logic 1. this causes all data out of the so pin to be a logical 1. 6) this step shows the contents of the mcu spi register after the transfer. all bits ar e logical 1 because the reset pin was held high for the duration of the transfer waveform detection algorithm three stage current waveform an operational solenoid, once activated, produces a current waveform that consists of three distinct regions. the three regions are categorized by their relationship to a ?dip? in the current that occurs when the solenoid armature moves within the coil. the regions are labeled the ?pre-dip?, ?dip?, and ?post-dip? regions. at this po int, it should be noted that the 33811 does not monitor this current directly. it monitors the voltage across the low-side mosfet driver. when the mosfet is turned on, it can be thought of, to a first approximation, as a resistor with value r ds . hence, any current variation through the solenoid, appears on the mosfet drain, as a voltage va riation, as is predicted by ohm?s law. the 33811 is designed to monitor the voltage across the mosfet and determine if the solenoid is operational or faulty based on the voltage waveform that is produced. activation of the solenoid if the solenoid is not activated, the low side mosfet driver is turned off, so almost the entire supply voltage appears across the mosfet. when the mosfet is activated, the voltage across it drops from the supply voltage to a voltage that depends on the instantaneous current flow through the solenoid and the r ds of the mosfet. this dramatic voltage swing from the supply voltage, to near ground, triggers a timer in the 33811 ic. the time value of this timer is labeled t begin and is 400 to 600 s in duration. if the voltage is still close to ground after t begin , then the solenoid is deemed to be activated and the waveform detection algorithm is started. the pre-dip region after dropping to near ground, the voltage across the mosfet starts to increase as the current through the solenoid begins to increase. the ?pre-dip? region consists of a positive slope region, leading to a voltage maxima or peak, followed by a negative slope region. the 33811 monitors this voltage ramp up by sampling the voltage every 72 s and comparing it to the previous sample. if the new sample exceeds the previous sample by 0.5mv or more, the sampling comparator?s output is auto-zeroed to the new voltage level by adjusting the reference voltage to the input voltage and the sampling cont inues. at some point the voltage will reach a peak and the slope of the voltage curve will turn from positive to negative. the 33811 will continue sampling the voltage as it begins to descend but will not auto- zero the comparator until at least three consecutive samples of 3mv in magnitude have been detected. the dip region once the three descending samples have been detected, sampling and auto-zeroing will continue to try to determine the next inflection point. this ne xt inflection point will be the dip which is caused by the successful travel of the solenoid?s armature. if a dip is not discovered within the total time window of 56 ms. then the solenoid will be said to be faulty and the appropriate spi register fault bit will be set to a logic 1. if the inflection point is discovered then sampling will continue. the post-dip region after the dip has occurred the waveform detection algorithm will continue sampling the voltage for the remainder of the 56ms. time window. if the voltage is still increasing after three sample times, then the solenoid is deemed to be operational and the appropriate spi register fault bit is cleared to a logic 0. the waveform detection logic is then reset back to a state where it look for the next solenoid activation event.
analog integrated circuit device data freescale semiconductor 15 33811 functional device operation operational modes figure 8. valid solenoid waveform
analog integrated circuit device data 16 freescale semiconductor 33811 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. eg suffix 16-pin plastic package 98asb42567b issue f
analog integrated circuit device data freescale semiconductor 17 33811 revision history revision history revision date description of changes 1.0 4/2007 ? initial release ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 5 . ? added notes (4) and (5) to maximum ratings 2.0 7/2007 ? updates to form and style.
mc33811 rev. 2.0 9/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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