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d a c 9 0 4 d a c 9 0 4 14-bit, 165msps digital-to-analog converter features single +5v or +3v operation high sfdr: 20mhz output at 100msps: 64dbc low glitch: 3pv-s low power: 170mw at +5v internal reference: optional ext. reference adjustable full-scale range multiplying option applications communication transmit channels wll, cellular base station digital microwave links cable modems waveform generation direct digital synthesis (dds) arbitrary waveform generation (arb) medical/ultrasound high-speed instrumentation and control video, digital tv description the dac904 is a high-speed, digital-to-analog converter (dac) offering a 14-bit resolution option within the family of high- performance converters. featuring pin compatibility among fam- ily members, the dac908, dac900, and dac902 provide a component selection option to an 8-, 10-, and 12-bit resolution, respectively. all models within this family of dacs support update rates in excess of 165msps with excellent dynamic performance, and are especially suited to fulfill the demands of a variety of applications. the advanced segmentation architecture of the dac904 is optimized to provide a high spurious-free dynamic range (sfdr) for single-tone, as well as for multi-tone signals essential when used for the transmit signal path of communica- tion systems. the dac904 has a high impedance (200k ? ) current output with a nominal range of 20ma and an output compliance of up to 1.25v. the differential outputs allow for both a differential or single-ended analog signal interface. the close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer. utilizing a small geometry cmos process, the monolithic dac904 can be operated on a wide, single-supply range of +2.7v to +5.5v. its low power consumption allows for use in portable and battery-operated systems. further optimization can be realized by lowering the output current with the adjustable full-scale option. for noncontinuous operation of the dac904, a power-down mode results in only 45mw of standby power. the dac904 comes with an integrated 1.24v bandgap refer- ence and edge-triggered input latches, offering a complete converter solution. both +3v and +5v cmos logic families can be interfaced to the dac904. the reference structure of the dac904 allows for additional flexibility by utilizing the on-chip reference, or applying an external reference. the full-scale output current can be adjusted over a span of 2-20ma, with one external resistor, while main- taining the specified dynamic performance. the dac904 is available in so-28 and tssop-28 packages. current sources lsb switches segmented switches +1.24v ref. latches 14-bit data input d13...d0 dac904 fsa bw +v d +v a agnd clk dgnd ref in int/ext i out i out byp pd dac904 sbas095b december 2001 www.ti.com copyright ? 2000, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
dac904 2 sbas095b www.ti.com electrical characteristics at t a = full specified temperature range, +v a = +5v, +v d = +5v, differential transformer coupled output, 50 ? doubly terminated, unless otherwise specified. dac904u, e parameter conditions min typ max units resolution 14 bits output update rate 2.7v to 3.3v 125 165 msps output update rate (f clock ) 4.5v to 5.5v 165 200 msps full specified temperature range, operating ambient, t a 40 +85 c static accuracy (1) t a = +25 c differential nonlinearity (dnl) f clock = 25msps, f out = 1.0mhz 2.5 lsb integral nonlinearity (inl) 3.0 lsb dynamic performance t a = +25 c spurious-free dynamic range (sfdr) to nyquist f out = 1.0mhz, f clock = 25msps 72 79 dbc f out = 2.1mhz, f clock = 50msps 76 dbc f out = 5.04mhz, f clock = 50msps 68 dbc f out = 5.04mhz, f clock = 100msps 68 dbc f out = 20.2mhz, f clock = 100msps 64 dbc f out = 25.3mhz, f clock = 125msps 60 dbc f out = 41.5mhz, f clock = 125msps 55 dbc f out = 27.4mhz, f clock = 165msps 60 dbc f out = 54.8mhz, f clock = 165msps 55 dbc spurious-free dynamic range within a window f out = 5.04mhz, f clock = 50msps 2mhz span 82 dbc f out = 5.04mhz, f clock = 100msps 4mhz span 82 dbc total harmonic distortion (thd) f out = 2.1mhz, f clock = 50msps 75 dbc f out = 2.1mhz, f clock = 125msps 74 dbc two tone f out1 = 13.5mhz, f out2 = 14.5mhz, f clock = 100msps 63 dbc electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. demo board product ordering number comment dac904u dem-dac90xu populated evaluation board without dac. order sample of desired dac90x model separately. dac904e dem-dac904e populated evaluation board including the dac904e. demo board ordering information absolute maximum ratings +v a to agnd ......................................................................... 0.3v to +6v +v d to dgnd ........................................................................ 0.3v to +6v agnd to dgnd ................................................................. 0.3v to +0.3v +v a to +v d ............................................................................... 6v to +6v clk, pd to dgnd ....................................................... 0.3v to v d + 0.3v d0-d13 to dgnd ......................................................... 0.3v to v d + 0.3v i out , i out to agnd .......................................................... 1v to v a + 0.3v bw, byp to agnd ....................................................... 0.3v to v a + 0.3v ref in , fsa to agnd ................................................... 0.3v to v a + 0.3v int/ext to agnd ........................................................ 0.3v to v a + 0.3v junction temperature .................................................................... +150 c case temperature ......................................................................... +100 c storage temperature ..................................................................... +125 c specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity dac904u so-28 dw 40 c to +85 c dac904u dac904u rails, 28 " """" dac904u/1k tape and reel, 1000 dac904e tssop-28 pw 40 c to +85 c dac904e dac904e rails, 52 " """" dac904e/2k5 tape and reel, 2500 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information
dac904 3 sbas095b www.ti.com electrical characteristics (cont.) at t a = +25 c, +v a = +5v, +v d = +5v, differential transformer coupled output, 50 ? doubly terminated, unless otherwise specified. dac904u, e parameter conditions min typ max units dynamic performance (cont.) output settling time (2) to 0.1% 30 ns output rise time (2) 10% to 90% 2 ns output fall time (2) 10% to 90% 2 ns glitch impulse 3pv-s dc-accuracy full-scale output range (3) (fsr) all bits high, i out 2.0 20.0 ma output compliance range 1.0 +1.25 v gain error with internal reference 10 1 +10 %fsr gain error with external reference 10 2 +10 %fsr gain drift with internal reference 120 ppmfsr/ c offset error with internal reference 0.025 +0.025 %fsr offset drift with internal reference 0.1 ppmfsr/ c power-supply rejection, +v a 0.2 +0.2 %fsr/v power-supply rejection, +v d 0.025 +0.025 %fsr/v output noise i out = 20ma, r load = 50 ? 50 pa/ hz output resistance 200 k ? output capacitance i out , i out to ground 12 pf reference reference voltage +1.24 v reference tolerance 10 % reference voltage drift 50 ppmfsr/ c reference output current 10 a reference input resistance 1m ? reference input compliance range 0.1 1.25 v reference small-signal bandwidth (4) 1.3 mhz digital inputs logic coding straight binary latch command rising edge of clock logic high voltage, v ih +v d = +5v 3.5 5 v logic low voltage, v il +v d = +5v 0 1.2 v logic high voltage, v ih +v d = +3v 2 3 v logic low voltage, v il +v d = +3v 0 0.8 v logic high current , i ih (5) +v d = +5v 20 a logic low current, i il +v d = +5v 20 a input capacitance 5pf power supply supply voltages +v a +2.7 +5 +5.5 v +v d +2.7 +5 +5.5 v supply current (6) i va 24 30 ma i va , power-down mode 1.1 2 ma i vd 815ma power dissipation +5v, i out = 20ma 170 230 mw +3v, i out = 2ma 50 mw power dissipation, power-down mode 45 mw thermal resistance, ja so-28 75 c/w tssop-28 50 c/w notes: (1) at output i out , while driving a virtual ground. (2) measured single-ended into 50 ? load. (3) nominal full-scale output current is 32x i ref ; see application section for details. (4) reference bandwidth depends on size of external capacitor at the bw pin and signal level. (5) typicall y 45 a for the pd pin, which has an internal pull-down resistor. (6) measured at f clock = 50msps and f out = 1.0mhz.
dac904 4 sbas095b www.ti.com current sources lsb switches segmented msb switches +1.24v ref. latches 14-bit data input d13.......d0 dac904 fsa bw +v d +v a r set agnd note: (1) optional components. clk dgnd ref in 0.1 f int/ext i out i out byp pd 20pf (1) 50 ? 50 ? 20pf (1) 1:1 v out 0.1 f 0.1 f (1) +5v +5v bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 clk +v d dgnd nc +v a byp i out i out agnd bw fsa ref in int/ext pd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dac904 pin designator description 1 bit 1 data bit 1 (d13), msb 2 bit 2 data bit 2 (d12) 3 bit 3 data bit 3 (d11) 4 bit 4 data bit 4 (d10) 5 bit 5 data bit 5 (d9) 6 bit 6 data bit 6 (d8) 7 bit 7 data bit 7 (d7) 8 bit 8 data bit 8 (d6) 9 bit 9 data bit 9 (d5) 10 bit 10 data bit 10 (d4) 11 bit 11 data bit 11 (d3) 12 bit 12 data bit 12 (d2) 13 bit 13 data bit 13 (d1) 14 bit 14 data bit 14 (d0), lsb 15 pd power down, control input; active high. contains internal pull-down circuit; may be left unconnected if not used. 16 int/ext reference select pin; internal ( = 0) or external ( = 1) reference operation 17 ref in reference input/ouput. see applications section for further details. 18 fsa full-scale output adjust 19 bw bandwidth/noise reduction pin: bypass with 0.1 f to +v a for optimum performance. (optional) 20 agnd analog ground 21 i out complementary dac current output 22 i out dac current output 23 byp bypass node: use 0.1 f to agnd 24 +v a analog supply voltage, 2.7v to 5.5v 25 nc no internal connection 26 dgnd digital ground 27 +v d digital supply voltage, 2.7v to 5.5v 28 clk clock input pin descriptions pin configuration top view so, tssop typical connection circuit
dac904 5 sbas095b www.ti.com timing diagram t 2 t pd t set t h t s t 1 clk d13-d0 i out or i out symbol description min typ max units t 1 clock pulse high time 3 ns t 2 clock pulse low time 3 ns t s data setup time 1.0 ns t h data hold time 1.5 ns t pd propagation delay time 1 ns t set output settling time to 0.1% 30 ns
dac904 6 sbas095b www.ti.com typical characteristics: v d = v a = +5v at t a = +25 c, differential i out = 20ma, 50 ? double-terminated load, sfdr up to nyquist, unless otherwise specified. dac code typical dnl error (lsbs) 10 8 6 4 2 0 2 4 6 8 10 0 2k 4k 6k 8k 10k 12k 14k 16k 16384 typical inl error (lsbs) 10 8 6 4 2 0 2 4 6 8 10 dac code 0 2k 4k 6k 8k 10k 12k 14k 16k 16384 sfdr vs f out at 25msps frequency (mhz) sfdr (dbc) 90 85 80 75 70 65 60 2.0 4.0 6.0 8.0 10.0 12.0 0 0dbfs 6dbfs sfdr vs f out at 50msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 5.0 10.0 15.0 20.0 25.0 0 6dbfs 0dbfs sfdr vs f out at 100msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 50 45 10.0 20.0 30.0 40.0 50.0 0 0dbfs 6dbfs sfdr vs f out at 125msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 50 45 10.0 20.0 30.0 50.0 40.0 60.0 0 0dbfs 6dbfs
dac904 7 sbas095b www.ti.com typical characteristics: v d = v a = +5v (cont.) at t a = +25 c, differential i out = 20ma, 50 ? double-terminated load, sfdr up to nyquist, unless otherwise specified. sfdr vs f out at 165msps frequency (mhz) sfdr (dbc) 80 75 70 65 60 55 50 45 40 20.0 10.0 30.0 40.0 50.0 70.0 60.0 80.0 0 6dbfs 0dbfs sfdr vs f out at 200msps frequency (mhz) sfdr (dbc) 80 75 70 65 60 55 50 45 40 20.0 10.0 30.0 40.0 50.0 70.0 60.0 90.0 80.0 0 6dbfs 0dbfs differential vs single-ended sfdr vs f out at 100msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 50 45 10.0 20.0 30.0 40.0 50.0 0 diff (0dbfs) i out ( 6dbfs) i out (0dbfs) diff ( 6dbfs) x x x x x x x sfdr vs i outfs and f out at 100msps, 0dbfs i outfs (ma) sfdr (dbc) 80 75 70 65 60 55 50 45 40 51020 2 x x x x 2.1mhz 20.2mhz 10.1mhz 5.04mhz 40.4mhz * * * * thd vs f clock at f out = 2.1mhz f clock (msps) thd (dbc) 70 75 80 85 90 95 100 25 50 100 125 150 0 2hd 4hd 3hd x x x x sfdr vs temperature at 100msps, 0dbfs temperature ( c) sfdr (dbc) 85 80 75 70 65 60 55 50 45 20 0 25 70 50 85 40 2.1mhz 10.1mhz 40.4mhz x x x x x x x
dac904 8 sbas095b www.ti.com typical characteristics: v d = v a = +5v (cont.) at t a = +25 c, differential i out = 20ma, 50 ? double-terminated load, sfdr up to nyquist, unless otherwise specified. dual-tone output spectrum frequency (mhz) magnitude (dbm) 0 0 10 20 30 40 50 60 70 80 90 100 5 101520253035404550 f clock = 100msps f out1 = 13.5mhz f out2 = 14.5mhz sfdr = 63dbc amplitude = 0dbfs four-tone output spectrum frequency (mhz) magnitude (dbm) 0 0 10 20 30 40 50 60 70 80 90 100 510152025 f clock = 50msps f out1 = 6.25mhz f out2 = 6.75mhz f out3 = 7.25mhz f out4 = 7.75mhz sfdr = 66dbc amplitude = 0dbfs sfdr vs f out at 25msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 2.0 4.0 6.0 8.0 10.0 12.0 0 0dbfs 6dbfs sfdr vs f out at 50msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 5.0 10.0 15.0 20.0 25.0 0 6dbfs 0dbfs sfdr vs f out at 100msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 50 45 10.0 20.0 30.0 40.0 50.0 0 6dbfs 0dbfs sfdr vs f out at 125msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 50 45 10.0 20.0 30.0 50.0 40.0 60.0 0 0dbfs 6dbfs typical characteristics: v d = v a = +3v at t a = +25 c, differential i out = 20ma, 50 ? double-terminated load, sfdr up to nyquist, unless otherwise specified.
dac904 9 sbas095b www.ti.com sfdr vs f out at 165msps frequency (mhz) sfdr (dbc) 80 75 70 65 60 55 50 45 40 20.0 10.0 30.0 40.0 50.0 70.0 60.0 80.0 0 6dbfs 0dbfs differential vs single-ended sfdr vs f out at 100msps frequency (mhz) sfdr (dbc) 85 80 75 70 65 60 55 50 45 10.0 20.0 30.0 40.0 50.0 0 diff (0dbfs) i out ( 6dbfs) i out (0dbfs) diff ( 6dbfs) typical characteristics: v d = v a = +3v (cont.) at t a = +25 c, differential i out = 20ma, 50 ? double-terminated load, sfdr up to nyquist, unless otherwise specified. i outfs (ma) sfdr (dbc) 80 75 70 65 60 55 50 45 40 51020 2 x x * * * * x x sfdr vs i outfs and f out at 100msps 2.1mhz 5.04mhz 20.2mhz 10.1mhz 40.4mhz thd vs f clock at f out = 2.1mhz f clock (msps) thd (dbc) 70 75 80 85 90 95 100 25 50 100 125 150 0 2hd 4hd 3hd sfdr vs temperature at 100msps, 0dbfs temperature ( c) sfdr (dbc) 80 75 70 65 60 55 50 45 40 20 0 25 70 50 85 40 2.1mhz 10.1mhz 40.4mhz x x x x x x x dual-tone output spectrum frequency (mhz) magnitude (dbm) 0 0 10 20 30 40 50 60 70 80 90 100 5 101520253035404550 f clock = 100msps f out1 = 13.5mhz f out2 = 14.5mhz sfdr = 64dbc amplitude = 0dbfs
dac904 10 sbas095b www.ti.com application information theory of operation the architecture of the dac904 uses the current steering technique to enable fast switching and a high update rate. the core element within the monolithic dac is an array of seg- mented current sources that are designed to deliver a full-scale output current of up to 20ma, as shown in figure 1. an internal decoder addresses the differential current switches each time the dac is updated and a corresponding output current is formed by steering all currents to either output summing node, i out or i out . the complementary outputs deliver a differential output signal that improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise), and double the peak-to-peak output signal swing by a factor of two, compared to single-ended operation. figure 1. functional block diagram of the dac904. pmos current source array lsb switches segmented msb switches +1.24v ref latches and switch decoder logic 14-bit data input d13...d0 dac904 full-scale adjust resistor ref control amp ref buffer bw +v d +v a r set 2k ? clk dgnd ref input 0.1 f int/ext i out i out byp pd 20pf (1) 50 ? 50 ? 20pf (1) 1:1 v out 0.1 f 400pf 0.1 f (1) +3v to +5v analog bandwidth control +3v to +5v digital fsa ref in agnd analog ground digital ground power down (internal pull-down) clock input note: supply bypassing not shown. note: (1) optional. typical characteristics: v d = v a = +3v (cont.) at t a = +25 c, differential i out = 20ma, 50 ? double-terminated load, sfdr up to nyquist, unless otherwise specified. four-tone output spectrum frequency (mhz) magnitude (dbm) 0 0 10 20 30 40 50 60 70 80 90 100 510152025 f clock = 50msps f out1 = 6.25mhz f out2 = 6.75mhz f out3 = 7.25mhz f out4 = 7.75mhz sfdr = 67dbc amplitude = 0dbfs the segmented architecture results in a significant reduction of the glitch energy, and improves the dynamic performance (sfdr) and dnl. the current outputs maintain a very high output impedance of greater than 200k ? . the full-scale output current is determined by the ratio of the internal reference voltage (1.24v) and an external resistor, r set . the resulting i ref is internally multiplied by a factor of 32 to produce an effective dac output current that can range from 2ma to 20ma, depending on the value of r set . the dac904 is split into a digital and an analog portion, each of which is powered through its own supply pin. the digital section includes edge-triggered input latches and the de- coder logic, while the analog section comprises the current source array with its associated switches and the reference circuitry.
dac904 11 sbas095b www.ti.com dac transfer function the total output current, i outfs , of the dac904 is the sum- mation of the two complementary output currents: i outfs = i out + i out (1) the individual output currents depend on the dac code and can be expressed as: i out = i outfs (code/16384) (2) i out = i outfs (16383 code/16384) (3) where code is the decimal representation of the dac data input word. additionally, i outfs is a function of the reference current i ref , which is determined by the reference voltage and the external setting resistor, r set . i outfs = 32 i ref = 32 v ref /r set (4) in most cases the complementary outputs will drive resistive loads or a terminated transformer. a signal voltage will develop at each output according to: v out = i out r load (5) v out = i out r load (6) the value of the load resistance is limited by the output compliance specification of the dac904. to maintain speci- fied linearity performance, the voltage for i out and i out should not exceed the maximum allowable compliance range. the two single-ended output voltages can be combined to find the total differential output swing: (7) vvv code ir outdiff out out outfs load == ? ?? ( ) 2 16383 16384 analog outputs the dac904 provides two complementary current outputs, i out and i out . the simplified circuit of the analog output stage representing the differential topology is shown in figure 2. the output impedance of 200k ? ?? 12pf for i out and i out results from the parallel combination of the differen- tial switches, along with the current sources and associated parasitic capacitances. the signal voltage swing that may develop at the two outputs, i out and i out , is limited by a negative and positive compliance. the negative limit of 1v is given by the break- down voltage of the cmos process, and exceeding it will compromise the reliability of the dac904, or even cause permanent damage. with the full-scale output set to 20ma, the positive compliance equals 1.25v, operating with figure 2. equivalent analog output. i out i out dac904 r l r l +v a +v d = 5v. note that the compliance range decreases to about 1v for a selected output current of i outfs = 2ma. care should be taken that the configuration of the dac904 does not exceed the compliance range to avoid degradation of the distortion performance and integral linearity. best distortion performance is typically achieved with the maximum full-scale output signal limited to approximately 0.5v. this is the case for a 50 ? doubly-terminated load and a 20ma full-scale output current. a variety of loads can be adapted to the output of the dac904 by selecting a suitable transformer while maintaining optimum voltage levels at i out and i out . furthermore, using the differential output configuration in combination with a transformer will be instru- mental for achieving excellent distortion performance. com- mon-mode errors, such as even-order harmonics or noise, can be substantially reduced. this is particularly the case with high output frequencies and/or output amplitudes below full-scale. for those applications requiring the optimum distortion and noise performance, it is recommended to select a full-scale output of 20ma. a lower full-scale range down to 2ma may be considered for applications that require a low power consumption, but can tolerate a reduced performance level. input code (d13 - d0) i out i out 11 1111 1111 1111 20ma 0ma 10 0000 0000 0000 10ma 10ma 00 0000 0000 0000 0ma 20ma table i. input coding versus analog output current. output configurations the current output of the dac904 allows for a variety of configurations, some of which are illustrated below. as men- tioned previously, utilizing the converter s differential outputs will yield the best dynamic performance. such a differential output circuit may consist of an rf transformer (see figure 3) or a differential amplifier configuration (see figure 4). the
dac904 12 sbas095b www.ti.com figure 4. difference amplifier provides differential to single- ended conversion and ac-coupling. the opa680 is configured for a gain of 2. therefore, oper- ating the dac904 with a 20ma full-scale output will produce a voltage output of 1v. this requires the amplifier to operate off of a dual power supply ( 5v). the tolerance of the resistors typically sets the limit for the achievable common- mode rejection. an improvement can be obtained by fine tuning resistor r 4 . this configuration typically delivers a lower level of ac perfor- mance than the previously discussed transformer solution because the amplifier introduces another source of distor- tion. suitable amplifiers should be selected based on their slew-rate, harmonic distortion, and output swing capabilities. high-speed amplifiers like the opa680 or opa687 may be considered. the ac performance of this circuit may be improved by adding a small capacitor, c diff , between the outputs i out and i out , as shown in figure 4 . this will introduce a real pole to create a low-pass filter in order to slew-limit the dac s fast output signal steps that otherwise could drive the amplifier into slew-limitations or into an overload condition; both would cause excessive distortion. the difference ampli- fier can easily be modified to add a level shift for applications requiring the single-ended output voltage to be unipolar, i.e., swing between 0v and +2v. i out i out dac904 r l 26.1 ? r l 28.7 ? r 4 402 ? r 3 200 ? r 2 402 ? r 1 200 ? opa680 c diff +5v v out 5v transformer configuration is ideal for most applications with ac coupling, while op amps will be suitable for a dc-coupled configuration. the single-ended configuration (see figure 6) may be consid- ered for applications requiring a unipolar output voltage. con- necting a resistor from either one of the outputs to ground will convert the output current into a ground-referenced voltage signal. to improve on the dc linearity, an i-to-v converter can be used instead. this will result in a negative signal excursion and, therefore, requires a dual supply amplifier. differential with transformer using an rf transformer provides a convenient way of converting the differential output signal into a single-ended signal while achieving excellent dynamic performance, as shown in figure 3. the appropriate transformer should be carefully selected based on the output frequency spectrum and impedance requirements. the differential transformer configuration has the benefit of significantly reducing com- mon-mode signals, thus improving the dynamic performance over a wide range of frequencies. furthermore, by selecting a suitable impedance ratio (winding ratio), the transformer can be used to provide optimum impedance matching while controlling the compliance voltage for the converter outputs. the model shown in figure 3 has a 1:1 ratio and may be used to interface the dac904 to a 50 ? load. this results in a 25 ? load for each of the outputs, i out and i out . the output signals are ac coupled and inherently isolated because of the transformer's magnetic coupling. as shown in figure 3, the transformer s center tap is con- nected to ground. this forces the voltage swing on i out and i out to be centered at 0v. in this case the two resistors, r s , may be replaced with one, r diff , or omitted altogether. this approach should only be used if all components are close to each other, and if the vswr is not important. a complete power transfer from the dac output to the load can be realized, but the output compliance range should be ob- served. alternatively, if the center tap is not connected, the signal swing will be centered at r s i outfs /2. however, in this case, the two resistors (r s ) must be used to enable the necessary dc-current flow for both outputs. differential configuration using an op amp if the application requires a dc-coupled output, a difference amplifier may be considered, as shown in figure 4. four external resistors are needed to configure the voltage-feed- back op amp opa680 as a difference amplifier performing the differential to single-ended conversion. under the shown configuration, the dac904 generates a differential output signal of 0.5vp-p at the load resistors, r l . the resistor values shown were selected to result in a symmetric 25 ? loading for each of the current outputs since the input impedance of the difference amplifier is in parallel to resistors r l , and should be considered. figure 3. differential output configuration using an rf transformer. i out i out dac904 1:1 adt1-1wt (mini-circuits) r s 50 ? r s 50 ? r l optional r diff
dac904 13 sbas095b www.ti.com figure 5. dual, voltage-feedback amplifier opa2680 forms differential transimpedance amplifier. dual transimpedance output configuration the circuit example of figure 5 shows the signal output currents connected into the summing junction of the opa2680, which is set up as a transimpedance stage, or i-to-v con- verter. with this circuit, the dac s output will be kept at a virtual ground, minimizing the effects of output impedance variations, and resulting in the best dc linearity (inl). how- ever, as mentioned previously, the amplifier may be driven into slew-rate limitations, and produce unwanted distortion. this may occur especially at high dac update rates. the dc gain for this circuit is equal to feedback resistor r f . at high frequencies, the dac output impedance (c d1 , c d2 ) will produce a zero in the noise gain for the opa2680 that may cause peaking in the closed-loop frequency response. c f is added across r f to compensate for this noise-gain peaking. to achieve a flat transimpedance frequency re- sponse, the pole in each feedback network should be set to: 1 24 rc gbp rc ff fd = (8) with gbp = gain bandwidth product of opa, which will give a corner frequency f -3db of approximately: f gbp rc db fd ? = 3 2 (9) 1/2 opa2680 1/2 opa2680 dac904 v out = i out r f v out = i out r f r f1 r f2 c f1 c f2 c d1 c d2 i out i out 50 ? 50 ? 5v +5v the full-scale output voltage is defined by the product of i outfs r f , and has a negative unipolar excursion. to improve on the ac performance of this circuit, adjustment of r f and/or i outfs should be considered. further extensions of this application example may include adding a differential filter at the opa2680 s output followed by a transformer, in order to convert to a single-ended signal. single-ended configuration using a single load resistor connected to the one of the dac outputs, a simple current-to-voltage conversion can be ac- complished. the circuit in figure 6 shows a 50 ? resistor connected to i out , providing the termination of the further connected 50 ? cable. therefore, with a nominal output current of 20ma, the dac produces a total signal swing of 0v to 0.5v into the 25 ? load. different load resistor values may be selected as long as the output compliance range is not exceeded. additionally, the output current, i outfs , and the load resistor may be mutually adjusted to provide the desired output signal swing and performance. figure 6. driving a doubly-terminated 50 ? cable directly. i out i out dac904 25 ? 50 ? 50 ? i outfs = 20ma v out = 0v to +0.5v internal reference operation the dac904 has an on-chip reference circuit that comprises a 1.24v bandgap reference and a control amplifier. ground- ing pin 16, int/ext, enables the internal reference opera- tion. the full-scale output current, i outfs , of the dac904 is determined by the reference voltage, v ref , and the value of resistor r set . i outfs can be calculated by: i outfs = 32 i ref = 32 v ref / r set (10) the external resistor r set connects to the fsa pin (full- scale adjust), see figure 7. the reference control amplifier operates as a v-to-i converter producing a reference current, i ref , which is determined by the ratio of v ref and r set , as shown in equation 10. the full-scale output current, i outfs , results from multiplying i ref by a fixed factor of 32.
dac904 14 sbas095b www.ti.com figure 8. external reference configuration. figure 7. internal reference configuration. digital inputs the digital inputs, d0 (lsb) through d13 (msb) of the dac904 accepts standard-positive binary coding. the digital input word is latched into a master-slave latch with the rising edge of the clock. the dac output becomes updated with the following falling clock edge (refer to the electrical charac- teristic table and timing diagram for details). the best perfor- mance will be achieved with a 50% clock duty cycle, how- ever, the duty cycle may vary as long as the timing specifi- cations are met. additionally, the setup and hold times may be chosen within their specified limits. all digital inputs are cmos compatible. the logic thresholds depend on the applied digital supply voltage such that they are set to approximately half the supply voltage; v th = +v d /2 ( 20% tolerance). the dac904 is designed to operate over a supply range of 2.7v to 5.5v. power-down mode the dac904 features a power-down function that can be used to reduce the supply current to less than 9ma over the specified supply range of 2.7v to 5.5v. applying a logic high to the pd pin will initiate the power-down mode, while a logic low enables normal operation. when left unconnected, an internal active pull-down circuit will enable the normal opera- tion of the converter. grounding, decoupling, and layout information proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. multilayer pc-boards are recommended for best performance since they offer distinct advantages such as minimization of ground impedance, separation of signal layers by ground layers, etc. using the internal reference, a 2k ? resistor value results in a 20ma full-scale output. resistors with a tolerance of 1% or better should be considered. selecting higher values, the con- verter output can be adjusted from 20ma down to 2ma. operating the dac904 at lower than 20ma output currents may be desirable for reasons of reducing the total power consump- tion, improving the distortion performance, or observing the output compliance voltage limitations for a given load condition. it is recommended to bypass the ref in pin with a ceramic chip capacitor of 0.1 f or more. the control amplifier is internally compensated, and its small signal bandwidth is approximately 1.3mhz. for optional ac performance, an additional capacitor (c compext ) should be applied between the bw pin and the analog supply, +v a , as shown in figure 7. using a 0.1 f capacitor, the small-signal bandwidth and output impedance of the control amplifier is further diminished, reducing the noise that is fed into the current source array. this also helps shunting feedthrough signals more effectively, and improving the noise performance of the dac904. external reference operation the internal reference can be disabled by applying a logic high (+v a ) to pin int/ext. an external reference voltage can then be driven into the ref in pin, which in this case functions as an input, as shown in figure 8. the use of an external reference may be considered for applications that require higher accuracy and drift performance, or to add the ability of dynamic gain control. while a 0.1 f capacitor is recommended to be used with the internal reference, it is optional for the external reference operation. the reference input, ref in , has a high input impedance (1m ? ) and can easily be driven by various sources. note that the voltage range of the external refer- ence should stay within the compliance range of the refer- ence input (0.1v to 1.25v). dac904 c compext 0.1 f optional bandlimiting capacitor c comp 400pf +1.24v ref. r set 2k ? 0.1 f int/ext fsa bw +5v +v a ref in current sources i ref = v ref r set ref control amp r set +5v external reference i ref = v ref r set dac904 c compext 0.1 f c comp 400pf +1.24v ref. int/ext fsa bw +5v +v a ref in current sources ref control amp
dac904 15 sbas095b www.ti.com the dac904 uses separate pins for its analog and digital supply and ground connections. the placement of the decou- pling capacitor should be such that the analog supply (+v a ) is bypassed to the analog ground (agnd), and the digital supply bypassed to the digital ground (dgnd). in most cases 0.1 f ceramic chip capacitors at each supply pin are ad- equate to provide a low impedance decoupling path. keep in mind that their effectiveness largely depends on the proximity to the individual supply and ground pins. therefore, they should be located as close as physically possible to those device leads. whenever possible, the capacitors should be located immediately under each pair of supply/ground pins on the reverse side of the pc-board. this layout approach will minimize the parasitic inductance of component leads and pcb runs. further supply decoupling with surface mount tantalum ca- pacitors (1 f to 4.7 f) may be added as needed in proximity of the converter. low noise is required for all supply and ground connections to the dac904. it is recommended to use a multilayer pc- board utilizing separate power and ground planes. mixed signal designs require particular attention to the routing of the different supply currents and signal traces. generally, analog supply and ground planes should only extend into analog signal areas, such as the dac output signal and the refer- ence signal. digital supply and ground planes must be confined to areas covering digital circuitry, including the digital input lines connecting to the converter, as well as the clock signal. the analog and digital ground planes should be joined together at one point underneath the dac. this can be realized with a short track of approximately 1/8 inch (3mm). the power to the dac904 should be provided through the use of wide pcb runs or planes. wide runs will present a lower trace impedance, further optimizing the supply decou- pling. the analog and digital supplies for the converter should only be connected together at the supply connector of the pc-board. in the case of only one supply voltage being available to power the dac, ferrite beads along with bypass capacitors may be used to create an lc filter. this will generate a low-noise analog supply voltage that can then be connected to the +v a supply pin of the dac904. while designing the layout, it is important to keep the analog signal traces separate from any digital line, in order to prevent noise coupling onto the analog signal path.
dac904 16 sbas095b www.ti.com package drawings msoi003e january 1995 revised september 2001 dw (r-pdso-g**) plastic small-outline package 16 pins shown 4040000 / e 08/01 seating plane 0.400 (10,15) 0.419 (10,65) 0.104 (2,65) max 1 0.012 (0,30) 0.004 (0,10) a 8 16 0.020 (0,51) 0.014 (0,35) 0.291 (7,39) 0.299 (7,59) 9 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) pins ** 0.010 (0,25) nom a max dim a min gage plane 20 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 16 0.600 24 0.610 (17,78) 28 0.700 (18,03) 0.710 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 ? 8 (11,51) (11,73) 0.453 0.462 18 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec ms-013
dac904 17 sbas095b www.ti.com package drawings (cont.) mtss001c january 1995 revised february 1999 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 C 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third?party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2001, texas instruments incorporated

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