comtech aha corporation comtech aha corporation product brief aha G709D-10 fec core 10 gb/s itu g.709 reed-solomon decoder after more than 15 years building leading edge reed-solomon ics, aha is licensing its patented technology for the first time. the G709D-10 core implements the 16 block interleaved rs(255,239) code specified by in annex a of the itu g.709 standard. the G709D-10 core is specifically designed to efficiently perform the reed-solomon decoding function specified by the standard. the core requires no configuration, no initialization, and no re-synchronization procedure or includes any unnecessary features that would add area, power or complexity to your design. a complementary g709e rs encoder is also available from aha. features ? itu g.709 compatible reed-solomon core ? input and output data streams are block- interleaved for seamless connection in g.709 system ? 10 gbits/sec operation in 0.18 cmos process ? 140 kgates in 0.18 using a typical standard cell library ? less than 100 ma of dynamic current in umc's 0.18 cmos process ? one-edge, one-clock fully synchronous design without multi-cycle paths ? separate fifo for increased flexibility and simplified ic floor planning ? complete error reporting for bit error rate calculation and feedback into threshold detection circuits figure 1: aha G709D-10 fec reset aha G709D-10 fec fifo ? 64 kbit (available from aha) clk start received_data[63:0] correct_to_zero[10:0] correct_to_one[10:0] status_valid decode_complete uncorrectable[15:0] decoded_data[63:0] fifo_data[63:0]
comtech aha corporation pbg709d10_0203 ? 2003 comtech aha corp. comtech aha corporation 2345 ne hopkins court fax: 509.334.9000 tel: 509.334.1000 e-mail: sales@aha.com www.aha.com pullman, wa 99163-5601 a subsidiary of comtech telecommunications corporation input signals clk - 166 mhz core clock. all inputs are registered on the rising edge. reset - synchronous reset. received_data[63:0] - received data bus. data bus is valid every clock and is registered on the rising edge of clk . the data frame is restarted whenever start is active. the core accepts 8- bytes per transfers start - signal is active to when the first 8 bytes of the g.709 frame in on the received_data bus. must be inactive on all other data transfers in the frame. maybe asserted at anytime of the data frame needs to be reset to the first transfer. fifo_data[63:0] - fifo data. delay version of the received_data data stream. the bus is registered on the rising edge of clk . output signals decode_complete - decoding complete. active when the first 8-byte transfer of the g.709 frame is on the decode_data data bus and inactive on all subsequent transfers. decoded_data[63:0] - decoded data. the first 8- bytes of the corrected g.709 frame are valid when decode_complete is active and the remainder of the frame is available over the subsequent 509 clocks. the data is driven from the rising edge of clk . status_valid - status valid signal. active for a single clk following the completion of the frame to indicate when the uncorrectable , correct-to-zero , and correct_to_one signals are valid. uncorrectable[15:0] - uncorrectable block flags. each bit of the signal corresponds to one of the 16 reed-solomon blocks in the g.709 frame. va l i d w h e n status_valid is active. correct_to_zero[10:0] - number of bits corrected from ?1? to ?0? in the just completed g.709 frame. signal is valid when status_valid is active. correct_to_one[10:0] - number of bits corrected from ?0? to ?1? in the just completed g.709 frame. signal is valid when status_valid is active. deliverables ? g.709d-10 fec core (vhdl) ? timing constraints (designcompiler and ambit format) ? test bench and verification vectors (vhdl) ? single use license to aha?s reed-solomon patents patents design uses one or more of the following us patents: 5,170,399; 5,099,482; 4,873,688; 5,396,502 contact information comtech aha corporation 2345 ne hopkins court pullman wa 99163 (509) 336-7115 sales@aha.com http://www.aha.com
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