comtech aha corporation 2345 ne hopkins court pullman wa 99163 tel: 509.334.1000 fax: 509.334.9000 www.aha.com a subsidiary of comtech telecommunications corporation psfecencodercore_0702 product specification aha g.709-2.5 fec encoder core
comtech aha corporation psfecencodercore_0702 a subsidiary of comtech telecommunications corporation i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 reed solomon code parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.2 output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4.0 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
comtech aha corporation psfecencodercore_0702 a subsidiary of comtech telecommunications corporation page 1 of 2 1.0 introduction this g.709-2.5 core implements the rs(255,239) code specified in annex a of the itu g.709 standard. it is designed to efficiently perform the reed solomon encoding function specified by the standard. the core requires no configuration, no initialization, and no resynchronization procedure. 1.1 features performance: ? itu g.709 compatible reed solomon core ? 2.5 gbits/sec operation in 0.13 micron cmos process with 332 mhz clock ? one-edge, one clock fully synchronous design ? two clock latency ?1k gates ? only initialization is a reset ? 8 bit input and output data interfaces deliverables: ? itu g.709 compatible rs encoder core vhdl ? timing constraints (design compiler and ambit format) ? test bench and verification vectors (vhdl) 2.0 functional description figure 1: block diagram 2.1 encoding uncoded block length is 239 bytes with 16 check bytes and a correction power of 8 bytes per block. latency through the encoder is two clocks. a global reset clears all of the flip-flops involved with generating the parity check bytes. processing begins by applying the first data byte on the data bus, asserting the start signal, and then asserting the clk signal. every input byte is then added with the reg15 output and the sum input to all the galois field constant multipliers (gfmx). the outputs of these multipliers are summed with the previous stage value and clocked into the next register stage. after processing all 239 bytes in this manner the 16 parity check bytes are strobed out. this process of strobing out the parity check bytes reinitializes the register stages in preparation for processing the next block, thus not requiring any additional reset pulses. 2.2 reed solomon code parameters generator polynomial: where is a root of the binary primitive polynomial x 8 + x 4 + x 3 + x 2 + 1 . parity bytes are represented by: where r j (j = 0 to 15) is the parity byte represented by an element out of gf(256) and r 15 corresponds to the byte 240 in the fec sub-row and r 0 to byte 255. ahag709-2.5 fec encoder clk reset start data[7:0] out[7:0] gz () z i ? () i 0 = 15 = rz () r 15 z 15 r 14 z 14 r 1 z 1 r 0 + ? + ? + ? =
comtech aha corporation page 2 of 2 a subsidiary of comtech telecommunications corporation psfecencodercore_0702 3.0 signal descriptions 3.1 input interface 3.2 output interface 4.0 timing diagrams figure 2: functional timing signal type description data[7:0] i data bus. input data bus for information word. start i block start signal. this signal is asserted with the first byte transfer of a block. start signals should be at least 255 clocks apart, but can be more than 255 clocks. clk i system clock. reset i global reset. when active (high) reset forces a reset on all of the flip-flops involved in parity generation. signal type description out[7:0] o output data bus. message bytes are passed through onto this bus followed by the 16 parity check bytes for each 239 byte block that is processed. 123 239 238 237 r15 r14 r13 r12 r1 r2 r0 1 2 1 2 3 4 5 239 1 2 3 4 clk reset start data out
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