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genesys logic, inc. GL813 - usb 2.0 compactflash card reader controller specification 1.2 a pri l 12, 2002 genesys logic, inc. 10f., no.11, ln.155, sec.3, peishen rd., shenkeng, taipei, taiwan tel: 886-2-2664-6655 fax: 886-2-2664-5757 http://www.genesyslogic.com
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 2 of 24 contents 1. general descr iption ......................................................................................... 3 2. feat ures ............................................................................................................ 4 3. function block ................................................................................................. 5 3.1 block diagram .............................................................................................. 5 3.2 functional overview ..................................................................................... 6 4. pinning in formation ......................................................................................... 7 4.1 48-pin lqfp package .................................................................................. 7 4.2 100-pin lqfp package................................................................................. 9 5. functional d escripti on .................................................................................. 15 5.1 transmit o peratio n ..................................................................................... 15 5.2 receive o peratio n...................................................................................... 17 6. electrical ch aracteris tics .............................................................................. 19 6.1 absolute ma ximum ra tings ........................................................................ 19 6.2 recommended oper ating condi tions......................................................... 19 6.3 dc characteristics (digital pins) ................................................................ 19 6.4 dc characterist ics (d+/ d-)......................................................................... 20 6.5 switching char acterist ics ........................................................................... 20 7. package di mension ....................................................................................... 22 7.1 48-pin lqfp pack age ................................................................................ 22 7.2 100-pin lqfp pack age .............................................................................. 23 8. revision history............................................................................................. 24
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 3 of 24 1. general description the GL813 is a high performance, low cost usb2.0 compactflash-single card reader controller. with the integrati on of genesyslogic own design usb 2.0 high speed utmi transceiver, the GL813 has made a conspicuous improvement with full speed usb 1.1 card readers on data transfer rate between pc host and flash memory card. there are totally 4 endpoints in GL813 controller, control, bulk in, bulk out, and interrupt. complies with usb 480mbps spec ification ver. 2.0 and usb storage class specification ver. 1.0. (bulk only protocol), the GL813 can support not only plug and play but also windows me/ 2000/ xp default driver. for the emi consideration, the GL813 uses 12mhz cr ystal and slew-rate controlled pads to reduce the emi issue. the GL813 is 48-pin lqfp package (9mmx9mm) to make the best cost competitive for the high speed single fl ash card reader design and applications. also we provide 100-pin lqfp package (14mmx14mm) with external rom/ flash for design flexibility.
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 4 of 24 2. features complies with universal serial bus specification rev. 2.0. complies with compact flash specification rev. 1.4. complies with usb storage class specificat ion ver.1.0. (bulk only protocol) operating system supported: win xp/ 2000/ me/ 98/ 98se; mac os 9.x/ x. supports 4 endpoints: control/ bulk read/ bulk write/ interrupt. 64/ 512 bytes data payload for full / high speed bulk endpoint. supports 8-bit / 16-bit standard pio mode interface. embedded usb 2.0 utmi transceiver. embedded 7.5 mips risc cpu. supports external rom/ flash modes for design flexibility. (100-pin lqfp) supports power down mode and usb suspend indicator. supports usb 2.0 test mode features. 12mhz external clock to prov ide better emi3.3v power input. 5v tolerance pad for compact flash card interface. supports eeprom to customize usb vid / pid and string descriptors. available in 48-pin (9mmx9mm) / 100-pin (14mmx14mm) lqfp package.
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 5 of 24 3. function block 3.1 block diagram usb2.0 txcvr clkgen utmi logic sie compact flash controller engine cpu control register rxfifo0 txfifo1 txfifo0 control fifo rxfifo1 x40 12mhz
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 6 of 24 3.2 functional overview 3.2.1 usb 2.0 txcvr the usb 2.0 transceiver is the analog circuitry to handle the usb hs/fs signaling. 3.2.2 utmi logic the utmi logic is compliant to intel?s utmi specification 1.01. this block handles the low level usb protocol and signaling. the major jobs of utmi logic is data and clock recovery, nrzi encoding/decoding, bit stuffing/de-stuffing, usb2.0 test modes supporting and serial / parallel conversion. 3.2.3 pll 40xpll block will provide 480mhz for usb hs data transmission. 3.2.4 clkgen clkgen is the clock generator block fo r the logic blocks. it generates 15mhz clock for micro controller, 12mhz for pio mode, and 30mhz clock for utmi, sie, and fifo. 3.2.5 cpu the cpu is the control center of GL813. it?s an 8-bit micro controller operating in 15mhz, 7.5 mips. after receiving a usb command, it decodes the host command, then it re-assigns tasks to the compactflash controller engine, gpio, fifo, and response proper data/ status to usb host. 3.2.6 compactflash controller engine the compactflash controller engine is extended from standard ata/ atapi protocol. it supports pio mode data transfers. 3.2.7 fifos control fifo is used as control read / write fifo. txfifo0 / txfifo1 are two sets of 512-byte ping-pong fifo for bulk read endpoint. it buffers data from compactflash controller engine, and re-direct to usb sie logic. rxfifo0 / rxfifo1 are two sets of 512-byte ping-pong fifo for bulk write endpoint. it buffers data from usb sie logic, and re-direct to compactflash controller engine. 3.2.8 control registers control register configures GL813 to proper operation. for example, cpu can set register to generate wakeup event, enter suspend, transmits proper usb packet to host.
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 7 of 24 4. pinning information 4.1 48-pin lqfp pin # name i/o pad type description 1 cfpwr b tri-state compact flash card power control 2~5 iodd [8:11] i tri-state ide data bus 8~11 6 dvcc1 p power digital vcc 7 dgnd1 p power digital ground 8~11 iodd [12:15] b tri-state ide data bus 12~15 12 do i tri-state do from eeprom 13 cs1_ o tri-state ide chip select 1 GL813 48 lqfp 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 cfpwr iodd[8] iodd[9] iodd[10] iodd[11] dvcc1 dgnd1 iodd[12] iodd[13] iodd[14] !odd[15] do diow_ dior_ iordy intrq da1/ dl da0 cs0_ test cfdet a gnd1 x1 x2 cs1 _ da2/ s k reset# rpu avcc0 dpf dph dmf dmh agnd0 rref avcc1 cfrst cs iodd[7] iodd[6] iodd[5] iodd[4] dvcc2 dgnd2 iodd[3] iodd[2] iodd[1] iodd[0]
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 8 of 24 pin # name i/o pad type description 14 da2 / sk o tri-state ide address 2 / sk to eeprom 15 reset# i pull-high hw reset 16 rpu a u20mia 3.3v output 17 avcc0 p power analog vcc 18 dpf b u20mia full speed dp 19 dph b u20mia high speed dp 20 dmf b u20mia full speed dm 21 dmh b u20mia high speed dm 22 agnd0 p power analog ground 23 rref u20mia reference resister connect (*) 24 avcc1 p power analog vcc 25 x2 b clock crystal output 26 x1 i clock crystal input, 12mhz 27 agnd1 p power analog ground 28 cfdet i tri-state compact flash card detect 29 test i pull-low test mode input 30 cs0_ o tri-state ide chip select 0 31 da0 o tri-state ide address 0 32 da1 / di o tri-state ide address 1 / di to eeprom 33 intrq i tri-state ide interrupt request 34 iordy i tri-state ide io ready 35 dior_ o tri-state ide read signal 36 diow_ o tri-state ide write signal 37~40 iodd [0:3] b tri-state ide data bus 0~3 41 dgnd2 p power digital ground 42 dvcc2 p power digital vcc 4 3~46 iodd [4:7] b tri-state ide data bus 4~7 47 cs o tri-state cs to eeprom 48 cfrst b tri-state compact flash card hw reset (*) rref must be connected with a 510 ohm resister to ground.
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 9 of 24 4.2 100-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GL813 100 lqfp nc nc nc nc gpio8 gpio5 gpio6 iodd8 iodd9 iodd10 iodd11 dvcc1 nc nc dgnd1 iodd12 iodd13 iodd14 iodd15 cblid _ ext0 ext1 ext2 ext3 ext4 ext5 nc nc nc nc ext6 ext7 ext8 ext9 ext10 ext11 ext12 ext13 cs1 _ da2 reset# rpu avcc0 dpf dph dmf dmh agnd0 rref avcc1 nc dior_ iordy dmack_ intrq gpio13 gpio14 gpio15 gpio16 da1 da0 cs0_ gpio17 gpio18 gpio19 ext15 ext14 nc a gnd1 x1 x2 nc nc nc nc gpio7 gpio4 gpio3 gpio2 gpio1 iodd7 iodd6 iodd5 iodd4 dvcc2 dgnd2 iodd3 iodd2 iodd1 iodd0 dmarq gpio9 gpio10 gpio11 gpio12 nc nc nc nc diow_
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 10 of 24 pin # name i/o pad type description 1 nc - - - 2 nc - - - 3 nc - - - 4 nc - - - 5 gpio8 b tri-state gpio8 (*) 6 gpio5 b tri-state gpio5 7 gpio6 b tri-state gpio6 8~11 iodd [8:11] b tri-state ide data bus 8 ~ 11 12 dvcc1 p power digital vcc 13 nc - - - 14 nc - - - 15 dgnd1 p power digital ground 16~19 iodd [12:15] b tri-state ide data bus 12 ~ 15 20 cblid_ i tri-state cable select input 21 nc/ecpurd/eromd0 i pull-low nc: embedded cpu mode ecpurd: read signal when external cpu mode eromd0: data0 when external rom mode 22 nc/ecpuwr/eromd1 i pull-low nc: embedded cpu mode ecpuwr: write signal when external cpu mode eromd1: data1 when external rom mode 23 nc/ecpua5/eromd2 i pull-low nc: embedded cpu mode ecpua5: address5 when external cpu mode eromd2: data2 when external rom mode 24 nc/ecpua4/eromd3 i pull-low nc: when embedded cpu mode ecpua4: address4 when external cpu mode eromd3: data3 when external rom mode 25 nc/ecpua3/eromd4 i pull-low nc: embedded cpu mode ecpua3: address3 when external cpu mode eromd4: data4 when external rom mode
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 11 of 24 pin # name i/o pad type description 26 nc/ecpua2/eromd5 i pull-low nc: embedded cpu mode ecpua2: address2 when external cpu mode eromd5: data5 when external rom mode 27 nc - - - 28 nc - - - 29 nc - - - 30 nc - - - 31 nc/ecpua1/eromd6 i pull-low nc: embedded cpu mode ecpua1: address1 when external cpu mode eromd6: data6 when external rom mode 32 nc/ecpua0/eromd7 i pull-low nc: embedded cpu mode ecpua0: address0 when external cpu mode eromd7: data7 when external rom mode 33 nc/ecpud7/eromd8 b pull-low nc: embedded cpu mode ecpud7: data7 when external cpu mode eromd8: data8 when external rom mode 34 nc/ecpud6/eromd9 b pull-low nc: embedded cpu mode ecpud6: data6 when external cpu mode eromd9: data9 when external rom mode 35 nc/ecpud5/eromd10 b pull-low nc: embedded cpu mode ecpud5: data5 when external cpu mode eromd10: data10 when external rom mode 36 nc/ecpud4/eromd11 b pull-low nc: embedded cpu mode ecpud4: data4 when external cpu mode eromd11: data11 when external rom mode 37 nc/ecpud3/eromd12 b pull-low nc: embedded cpu mode ecpud3: data3 when external cpu mode eromd12: data12 when external rom mode
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 12 of 24 pin # name i/o pad type description 38 nc/ecpud2/eromd13 b pull-low nc: embedded cpu mode ecpud2: data2 when external cpu mode eromd13: data13 when external rom mode 39 cs1_ o tri-state chip select 1 40 da2 o tri-state ide address 2 41 reset# i pull-high reset pin 42 rpu a u20mia 3.3v output 43 avcc0 p power analog vcc 44 dpf b u20mia full speed dp 45 dph b u20mia high speed dp 46 dmf b u20mia full speed dm 47 dmh b u20mia high speed dm 48 agnd0 p power analog ground 49 rref u20mia reference resister connect (*) 50 avcc1 p power analog vcc 51 nc - - - 52 nc - - - 53 nc - - - 54 nc - - - 55 x2 b clock crystal output 56 x1 i clock crystal input, 12mhz 57 agnd1 p power analog ground 58 nc - - - 59 nc/ecpud1/eroma0 b pull-low nc: embedded cpu mode ecpud1: data1 when external cpu mode eroma0: address0 when external rom mode 60 nc/ecpud0/eroma1 b pull-low nc: embedded cpu mode ecpud0: data0 when external cpu mode eroma1: address1 when external rom mode 61 gpio19 b pull-low gpio19 62 gpio18/gpio18/erom a11 b pull-low gpio18: for embedded or external cpu mode eroma11: address11 when external rom mode
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 13 of 24 pin # name i/o pad type description 63 gpio17/gpio17/erom a10 b pull-low gpio17: for embedded or external cpu mode eroma10: address10 when external rom mode 64 cs0_ o tri-state chip select 0 65 da0 o tri-state ide address 0 66 da1 o tri-state ide address 1 67 gpio16/gpio16/erom a9 b pull-low gpio16: for embedded or external cpu mode eroma9: address9 when external rom mode 68 gpio15/gpio15/erom a8 b pull-low gpio15: for embedded or external cpu mode eroma8: address8 when external rom mode 69 gpio14/gpio15/erom a7 b pull-low gpio14: for embedded or external cpu mode eroma7: address7 when external rom mode 70 gpio13/gpio14/erom a6 b pull-low gpio13: for embedded or external cpu mode eroma6: address6 when external rom mode 71 intrq i tri-state ide interrupt input 72 dmack_ o tri-state ide acknowledge 73 iordy i pull-high ide ready 74 dior_ o tri-state ide read signal 75 nc - - - 76 diow_ o tri-state ide write signal 77 nc - - - 78 nc - - - 79 nc - - - 80 nc - - - 81 gpio12/gpio13/erom a5 b pull-low gpio12: for embedded or external cpu mode eroma5: address5 when external rom mode 82 gpio11/gpio12/erom a4 b pull-low gpio11: for embedded or external cpu mode eroma4: address4 when external rom mode
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 14 of 24 pin # name i/o pad type description 83 gpio10/gpio10/erom a3 b pull-low gpio10: for embedded or external cpu mode eroma3: address3 when external rom mode 84 gpio9/gpio9/eroma2 b pull-low gpio9: for embedded or external cpu mode eroma2: address2 when external rom mode 85 dmarq i pull-low ide request 8 6~89 idedd [0:3] b tri-state ide data bus 0~3 90 dgnd2 p power digital ground 91 dvcc2 p power digital vcc 92~95 idedd [4:7] b tri-state ide data bus 4~7 96 gpio1 b pull-high gpio1 97 gpio2 b pull-high gpio2 98 gpio3 b pull-high gpio3 99 gpio4 b pull-low gpio4 100 gpio7 b pull-low gpio 7 (*) (*) when operating in default mode: gpio7 is the ide reset input, gpio8 is used to control the power input of ide device.
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 15 of 24 5. functional description 5.1 transmit operation 5.1.1 transmit state diagram transmit must be asserted to enable any transmissions. the sie asserts txvld to begin a transmission. the sie negates txvld to end a transmission. after the sie asserts txvld it can assume that the transmission has started when it detects txrdy asserted. the sie assumes that the utm has consumed a data byte if txrdy and txvld are asserted. the sie must have valid packet information (pid) asserted on the data bus coincident with the assertion of txvld. depending on the utm implementation, txrdy may be asserted by the transmit state machine as soon as one clk after the assertion of txvld. txvld and txrdy are sampled on the rising edge of clkout. the transmit state machine does not automatically generate packet id?s (pids) or reset !txrdy tx wait send sync tx data load txrdy tx data wait !txrdy send eop !txrdy hrst# !hrst# txvld !txvld tx hold reg empty tx hold reg full tx hold reg empty tx hold reg full eop not done !txvld
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 16 of 24 crc. when transmitting, the sie is always expected to present a pid as the first byte of the data stream and if appropriate, crc as the last bytes of the data stream. the sie must use linest0/1 to verify a bus idle condition before asserting txvld in the tx wait state. 5.1.2 transmit timing for data packet the sie negates txvld to complete a packet. once negated, the transmit state machine will never reassert txrdy until after the eop has been loaded into the transmit shift register. note that the utm transmit state machine can be ready to start another package immediately, however the sie must confirm to the minimum inter-packet delays identified in the usb 2.0 specification. d a t a d a t a d a t a d a t a crc crc pid s yn c pid d a t a d a t a d a t a d a t a c r c c c r c c e o p p clkout txvld data txrdy dp/dm
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 17 of 24 5.2 receive operation 5.2.1 receive state diagram rxactv and rxvld are sampled on the rising edge of clkout. in the rx wait state the receiver is always looking for sync. the macrocell asserts rxactv when sync is detected (strip sync state). the macrocell negates rxactv when an eop is detected (strip eop state). when rxactv is asserted, rxvld will be asserted if the rx holding register is full. rxvld will be negated if the rx holding register was not loaded during the previous byte time. this will occur if 8 stuffed bits have been accumulated. the sie must be ready to consume a data byte if rxactv and rxvld are asserted (rx data state). in fs mode, if a bit stuff error is detected then the receive state machine will negate rxactv and rxvld, and return to the rxwait state. reset !rxactv !rxvld rx wait trip sync rxactv rx data rxvld rx data wait !rxvld strip eop !rxactv !rxvld hrst# !hrst# sync detected data !data !sync sync data data abort 1 !rxactv !rxvld !rxerr terminate !rxactv abort 2 !rxvld !rxerr error rxerr eop detected !data receive error !idle state idle state
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 18 of 24 5.2.2 receive timing for data packet (with crc-16) note that the usb 2.0 transceiver does not decode packet id?s (pids). they are passed to the sie for decoding. this timing example is in hs mode. when a hs/fs utm is in fs mode there are approximately 40 clock cycles every byte ti me. the receive state machine assumes that the sie captures the data on the data bus if rxactv and rxvld are asserted. in fs mode, rxvld will only be asserted for one clock per byte time. note that the receive and transmit sections of the transceiver operate independently. the receiver will receive any packets on the u sb. the transceiver does not identify whether the packet that it is receiving from the upstream or the downstream port. the sie must ignore receive data while it is transmitting. data data data data crc crc pid sync pid data data data data crc crc eop clkout rxactv data rxvld rxerr dp/dm
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 19 of 24 6. electrical characteristics 6.1 absolute maximum ratings symbol description min max unit v cc dc supply voltage -0.3 +3.6 v v i dc input voltage -0.3 v cc + 0.3 v v i/o dc input voltage range for i/o -0.3 v cc + 0.3 v v ai/o dc input voltage for usb d+/d- pins -0.3 v cc + 0.3 v v i/oz dc voltage applied to outputs in high z state -0.3 v cc + 0.3 v v esd static discharge voltage 4000 v t a ambient temperature 0 100 o c 6.2 recommended operating conditions item value supply voltage +3.3v to + 3.6v ground voltage 0v f osc 12 mhz 100 ppm operating temperature 0 o c ~ 70 o c 6.3 dc characteristics (digital pins) symbol description min typ max unit p d power dissipation ma v dd power supply voltage 3 3.3 3.6 v i o dc output sink current excluding d+/ d-/ vcc/ gnd 8 ma v il low level input voltage 0.9 v v ih high level input voltage 2.0 v v tlh low to high threshold voltage 1.3 1.43 1.56 v v thl high to low threshold voltage 1.3 1.43 1.56 v
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 20 of 24 symbol description min typ max unit v hys hysteresis voltage - 0 - v v ol low level output voltage when i ol =8ma 0.4 v v oh high level output voltage when i oh =8ma 2.4 v i olk leakage current for pads with internal pull up or pull down resistor 46 a r dn pad internal pull down resister 79k 105k 152k ohms r up pad internal pull up resister 78k 104k 146k ohms 6.4 dc characteristics (d+/d-) symbol description min typ max unit v ol d+/d- static output low (r l of 1.5k to 3.6v ) 0.3 v v oh d+/d- static output high (r l of 15k to gnd ) 2.8 3.6 v v di differential input sensitivity 0.2 v v cm differential common mode range 0.8 2.5 v v se single-ended receiver threshold 0.2 v c in transceiver capacitance 20 pf i lo hi-z state data line leakage -10 +10 a z drv driver output resistance 28 43 ohms 6.5 switching characteristics symbol description min typ max unit f x1 x1 crystal frequency 11.97 12 12.03 mhz t cyc x1 cycle time 83.3 ns t x1l x1 clock low time 0.45t cyc ns t x1h x1 clock high time 0.45t cyc ns t r30pf output pad rise time from 10% to 90% swing with 30pf loading ns t f30pf output pad fall time from 10% to 90% swing with 30pf loading ns
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 21 of 24 symbol description min typ max unit t r50pf output pad rise time from 10% to 90% swing with 50pf loading ns t f50pf output pad fall time from 10% to 90% swing with 50pf loading ns t rusb d+/d- rise time with 50pf loading 4 20 ns t fusb d+/d- fall time with 50pf loading 4 20 ns
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 22 of 24 7. package dimension 7.1 48-pin lqfp symbol min max a 1.6 a1 0.05 0.15 a2 1.35 1.45 c1 0.09 0.16 d 9.00bsc d1 7.00bsc e 9.00bsc e1 7.00bsc e 0.5bsc b 0.17 0.27 l 0.45 0.75 l1 1 ref
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 23 of 24 7.2 100-pin lqfp
GL813 - usb2.0 compactflash card reader controller ?2001-2002 genesys logic inc.?all rights reserved. page 24 of 24 8. revision history version description date 1.0 first draft 2002/03/20 1.1 correction and supplement of electrical characteristics data 2002/04/03 1.2 add 100-pin lqfp package related data 2002/04/12

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