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pcf2113x lcd controllers/drivers d a t a sh eet product speci?cation supersedes data of 1997 apr 04 file under integrated circuits, ic12 2001 dec 19 integrated circuits
2001 dec 19 2 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x contents 1 features 1.1 note 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 lcd supply voltage generator 7.2 lcd bias voltage generator 7.3 oscillator 7.4 external clock 7.5 power-on reset 7.6 power-down mode 7.7 registers 7.8 busy flag 7.9 address counter (ac) 7.10 display data ram (ddram) 7.11 character generator rom (cgrom) 7.12 character generator ram (cgram) 7.13 cursor control circuit 7.14 timing generator 7.15 lcd row and column drivers 7.16 reset function 8 instructions 8.1 clear display 8.2 return home 8.3 entry mode set 8.4 display control (and partial power-down mode) 8.5 cursor or display shift 8.6 function set 8.7 set cgram address 8.8 set ddram address 8.9 read busy flag and read address 8.10 write data to cgram or ddram 8.11 read data from cgram or ddram 9 extended function set instructions and features 9.1 new instructions 9.2 icon control 9.3 bit im 9.4 bit ib 9.5 direct mode 9.6 voltage multiplier control 9.7 screen configuration 9.8 display configuration 9.9 temperature control 9.10 set v lcd 9.11 reducing current consumption 10 interfaces to microcontroller 10.1 parallel interface 10.2 i 2 c-bus interface 11 limiting values 12 handling instructions 13 dc characteristics 14 ac characteristics 15 device protection circuits 16 application information 16.1 general application information 16.2 4-bit operation, 1-line display using internal reset 16.3 8-bit operation, 1-line display using internal reset 16.4 8-bit operation, 2-line display 16.5 i 2 c-bus operation, 1-line display 17 bonding pad information 18 tray information 19 package outline 20 soldering 20.1 introduction to soldering surface mount packages 20.2 reflow soldering 20.3 wave soldering 20.4 manual soldering 20.5 suitability of surface mount ic packages for wave and reflow soldering methods 21 data sheet status 22 definitions 23 disclaimers 24 bare die disclaimer 25 purchase of philips i 2 c components
2001 dec 19 3 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 1 features single-chip lcd controller/driver 2-line display of up to 12 characters + 120 icons, or 1-line display of up to 24 characters + 120 icons 5 7 character format plus cursor; 5 8 for kana (japanese) and user defined symbols icon mode: reduced current consumption while displaying icon blink function on-chip: C configurable 4, 3 or 2 voltage multiplier generating lcd supply voltage, independent of v dd , programmable by instruction (external supply also possible) C temperature compensation of on-chip generated v lcd : - 0.16 to - 0.24 %/k (programmable by instruction) C generation of intermediate lcd bias voltages C oscillator requires no external components (external clock also possible). display data ram: 80 characters character generator rom: 240, 5 8 characters character generator ram: 16, 5 8 characters; 3 characters used to drive 120 icons, 6 characters used if icon blink feature is used in application 4 or 8-bit parallel bus and 2-wire i 2 c-bus interface cmos compatible 18 row and 60 column outputs multiplex rates 1 : 18 (for normal operation), 1 : 9 (for single line operation) and 1 : 2 (for icon only mode) uses common 11 code instruction set (extended) logic supply voltage range v dd1 - v ss1 = 1.8 to 5.5 v (chip may be driven with two battery cells) v lcd generator supply voltage range v dd2 - v ss2 = 2.2 to 4.0 v display supply voltage range v lcd - v ss2 = 2.2 to 6.5 v direct mode to save current consumption for icon mode and mux 1 : 9 (depending on v dd2 value and lcd liquid properties) very low current consumption (20 to 200 m a): C icon mode: <25 m a C power-down mode: <2 m a. 1.1 note icon mode is used to save current. when only icons are displayed, a much lower operating voltage v lcd can be used and the switching frequency of the lcd outputs is reduced. in most applications it is possible to use v dd as v lcd . 2 applications telecom equipment portable instruments point-of-sale terminals. 3 general description the pcf2113x is a low power cmos lcd controller and driver, designed to drive a dot matrix lcd display of 2-line by 12 or 1-line by 24 characters with 5 8 dot format. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd bias voltages, resulting in a minimum of external components and lower system current consumption. the pcf2113x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire i 2 c-bus. the chip contains a character generator and displays alphanumeric and kana (japanese) characters. the letter x in pcf2113x characterizes the built-in character set. various character sets can be manufactured on request.
2001 dec 19 4 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 4 ordering information type number package name description version pcf2113au/10/f4 - chip on ?exible ?lm carrier - pcf2113du/10/f4 - chip on ?exible ?lm carrier - pcf2113du/f4 - chip in tray - pcf2113dh/f4 lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1 pcf2113du/2/f4 - chip with bumps in tray - pcf2113eu/2/f4 - chip with bumps in tray - pcf2113wu/2/f4 - chip with bumps in tray -
2001 dec 19 5 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 5 block diagram handbook, full pagewidth mge990 cursor and data control shift register 5 12 bit data latches column drivers 60 5 60 character generator ram (128 5) (cgram) 16 characters character generator rom (cgrom) 240 characters display data ram (ddram) 80 characters/bytes address counter (ac) instruction decoder instruction register(ir) row drivers shift register 18-bit bias voltage generator v lcd generator v lcdsense busy flag data register (dr) i/o buffer oscillator timing generator display address counter power-on reset v dd1 v lcd2 v ss1 t1 v lcd1 v ss2 t2 t3 v dd2 v dd3 c1 to c60 r1 to r18 osc pd pcf2113x db0 to db3/sa0 db4 to db7 e r/w rs scl sda 18 18 60 5 7 7 7 8 7 7 8 8 8 fig.1 block diagram.
2001 dec 19 6 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 6 pinning symbol pin pcf2113dh pa d (1) pcf2113xu type description v dd1 1 1 p supply voltage 1 for all except v lcd generator osc 2 2 i oscillator/external clock input; note 2 pd 3 3 i power-down select input; for normal operation pd is low t3 - 4 i test pad; open circuit and not user accessible t1 4 5 i test pin; must be connected to v ss1 t2 - 6 i test pad; must be connected to v ss1 v ss1 5 7 p ground 1 for all except v lcd generator v ss2 6 8 p ground 2 for v lcd generator v lcd2 79ov lcd output if v lcd is generated internally; note 7 v lcdsense - 10 i input (v lcd ) for voltage multiplier regulation; notes 3 and 7 v lcd1 8 11 i input for generation of lcd bias levels; note 7 r9 to r16 9 to 16 12 to 19 o lcd row driver outputs 9 to 16 r18 17 20 o lcd row driver output 18 c60 to c53 18 to 25 21 to 28 o lcd column driver outputs 60 to 53 dummy pad - 29 - dummy pad - 30 - c52 to c28 26 to 50 31 to 55 o lcd column driver outputs 52 to 28 dummy pad - 56 - dummy pad - 57 - c27 to c3 51 to 75 58 to 82 o lcd column driver outputs 27 to 3 dummy pad - 83 - dummy pad - 84 - c2 76 85 o lcd column driver output 2 c1 77 86 o lcd column driver output 1 r8 to r1 78 to 85 87 to 94 o lcd row driver outputs 8 to 1 r17 86 95 o lcd row driver output 17 scl 87 96 i i 2 c-bus serial clock input; note 4 sda 88 97 i/o i 2 c-bus serial data input/output; note 4 e 89 98 i data bus clock input; note 4 rs 90 99 i register select input r/ w 91 100 i read/write input db7 92 101 i/o 8-bit bidirectional data bus bit 7; note 5 db6 93 102 i/o 8-bit bidirectional data bus bit 6 db5 94 103 i/o 8-bit bidirectional data bus bit 5 db4 95 104 i/o 8-bit bidirectional data bus bit 4 db3/sa0 96 105 i/o 8-bit bidirectional data bus bit 3 or i 2 c-bus address pin; notes 4 and 5 db2 97 106 i/o 8-bit bidirectional data bus bit 2 db1 98 107 i/o 8-bit bidirectional data bus bit 1
2001 dec 19 7 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x notes 1. bonding pad location information is given in chapter 17. 2. when the on-chip oscillator is used this pad must be connected to v dd1 . 3. in the lqfp100 version this signal is connected internally and can not be accessed at any pin. 4. when the i 2 c-bus is used, the parallel interface pin e must be low. in the i 2 c-bus read mode db7 to db0 should be connected to v dd1 or left open-circuit. when the parallel bus is used, the pins scl and sda must be connected to v ss1 or v dd1 ; they must not be left open-circuit. when the 4-bit interface is used without reading out from the pcf2113x (r/ w is set permanently to logic 0), the unused ports db0 to db4 can either be set to v ss1 or v dd1 instead of leaving them open-circuit. 5. db7 may be used as the busy flag, signalling that internal operations are not yet completed. in 4-bit operations the four higher order lines db7 to db4 are used; db3 to db0 must be left open-circuit except for i 2 c-bus operations (see note 4). 6. v dd2 and v dd3 should always be equal. 7. when v lcd is generated internally, pins v lcd1 , v lcd2 and v lcdsense must be connected together. when external v lcd is supplied, pin v lcd2 should be left open-circuit to avoid any stray current, pins v lcd1 and v lcdsense must be connected together. db0 99 108 i/o 8-bit bidirectional data bus bit 0 v dd2 100 109 p supply voltage 2 for v lcd generator; note 6 v dd3 - 110 p supply voltage 3 for v lcd generator; notes 3 and 6 symbol pin pcf2113dh pa d (1) pcf2113xu type description
2001 dec 19 8 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 77 76 r6 r7 r8 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 c27 v dd1 osc pd t1 v ss1 v ss2 v lcd2 v lcd1 r9 r10 r11 r12 r13 r14 r15 r16 r18 c60 c59 c58 c57 c56 c55 c54 c53 c47 c46 c45 c44 c43 c42 c41 c40 c39 c38 c37 c36 c35 c34 c33 c32 c31 c30 c29 c28 v dd2 db0 db1 db2 db3/sa0 db4 db5 db6 db7 r/w rs e sda scl r17 r1 r2 r3 r4 r5 c52 c51 c50 c49 c48 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pcf2113x mge989 fig.2 pin configuration (lqfp100).
2001 dec 19 9 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 7 functional description 7.1 lcd supply voltage generator the lcd supply voltage may be generated on-chip. the v lcd generator is controlled by two internal 6-bit registers: v a and v b . the nominal lcd operating voltage at room temperature is given by the relationship: v op(nom) = (integer value of register 0.08) + 1.82 7.1.1 p rogramming ranges programmed value: 1 to 63. voltage: 1.90 to 6.86 v. t ref =27 c. values producing more than 6.5 v at operating temperature are not allowed. operation above this voltage may damage the device. when programming the operating voltage the v lcd tolerance and temperature coefficient must be taken into account. values below 2.2 v are below the specified operating range of the chip and are therefore not allowed. value 0 for v a and v b switches the generator off (i.e. v a = 0 in character mode, v b = 0 in icon mode). usually register v a is programmed with the voltage for character mode and register v b with the voltage for icon mode. when v lcd is generated on-chip the v lcd pins should be decoupled to v ss with a suitable capacitor. the generated v lcd is independent of v dd and is temperature compensated. when the v lcd generator and the direct mode are switched off, an external voltage may be supplied at connected pins v lcd1 and v lcd2 .v lcd1 and v lcd2 may be higher or lower than v dd2 . during direct mode (program dm register bit) the internal v lcd generator is turned off and the v lcd2 output voltage is directly connected to v dd2 . this reduces the current consumption during icon mode and mux 1 : 9 (depending on v dd2 value and lcd liquid properties). the v lcd generator ensures that, as long as v dd is in the valid range (2.2 to 4 v), the required peak voltage v op = 6.5 v can be generated at any time. 7.2 lcd bias voltage generator the intermediate bias voltages for the lcd display are also generated on-chip. this removes the need for an external resistive bias chain and significantly reduces the system current consumption. the optimum value of v lcd depends on the multiplex rate, the lcd threshold voltage (v th ) and the number of bias levels. using a 5-level bias scheme for 1 : 18 maximum rate allows v lcd < 5 v for most lcd liquids. the intermediate bias levels for the different multiplex rates are shown in table 1. these bias levels are automatically set to the given values when switching to the corresponding multiplex rate. table 1 bias levels as a function of multiplex rate; note 1 note 1. the values in the table are given relative to v lcd - v ss , e.g. 3 / 4 means 3 / 4 (v lcd - v ss ). multiplex rate number of levels v 1 v 2 v 3 v 4 v 5 v 6 1:18 5 v lcd 3 / 4 1 / 2 1 / 2 1 / 4 v ss 1:9 5 v lcd 3 / 4 1 / 2 1 / 2 1 / 4 v ss 1:2 4 v lcd 2 / 3 2 / 3 1 / 3 1 / 3 v ss
2001 dec 19 10 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 7.3 oscillator the on-chip oscillator provides the clock signal for the display system. no external components are required and the osc pin must be connected to v dd1 . 7.4 external clock if an external clock is to be used this input is at the osc pin. the resulting display frame frequency is given by: only in the power-down mode is the clock allowed to be stopped (osc connected to v ss ), otherwise the lcd is frozen in a dc state. 7.5 power-on reset the on-chip power-on reset block initializes the chip after power-on or power failure. this is a synchronous reset and requires 3 oscillator cycles to be executed. 7.6 power-down mode the chip can be put into power-down mode by applying an external active high level to the pd pin. in power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all lcd outputs are internally connected to v ss ). during power-down, information in the rams and the chip state are preserved. instruction execution during power-down is possible when pin osc is externally clocked. 7.7 registers the pcf2113x has two 8-bit registers, an instruction register (ir) and a data register (dr). the register select (rs) signal determines which register will be accessed. the instruction register stores instruction codes such as display clear, cursor shift, and address information for the display data ram (ddram) and character generator ram (cgram).the instruction register can be written to but not read from by the system controller. the data register temporarily stores data to be read from the ddram and cgram. when reading, data from the ddram or cgram corresponding to the address in the instruction register is written to the data register prior to being read by the read data instruction. 7.8 busy ?ag the busy flag indicates the internal status of the pcf2113x. a logic 1 indicates that the chip is busy and further instructions will not be accepted. the busy flag is output to pin db7 when bit rs = 0 and bit r/ w=1. instructions should only be written after checking that the busy flag is at logic 0 or waiting for the required number of cycles. 7.9 address counter (ac) the address counter assigns addresses to the ddram and cgram for reading and writing and is set by the commands set cgram address and set ddram address. after a read/write operation the address counter is automatically incremented or decremented by 1. the address counter contents are output to the bus (db6 to db0) when bit rs = 0 and bit r/ w=1. 7.10 display data ram (ddram) the ddram stores up to 80 characters of display data represented by 8-bit character codes. ram locations which are not used for storing display data can be used as general purpose ram. the basic ram to display addressing scheme is shown in fig.3. with no display shift the characters represented by the codes in the first 24 ram locations starting at address 00h in line 1 are displayed. figures 4 and 5 show the display mapping for right and left shift respectively. when data is written to or read from the ddram, wrap-around occurs from the end of one line to the start of the next line. when the display is shifted each line wraps around within itself, independently of the others. thus all lines are shifted and wrapped around together. the address ranges and wrap-around operations for the various modes are shown in table 2. f frame f osc 3 072 ------------- = table 2 address space and wrap-around operation mode 1 24 2 12 1 12 address space 00 to 4f 00 to 27; 40 to 67 00 to 27 read/write wrap-around (moves to next line) 4f to 00 27 to 40; 67 to 00 27 to 00 display shift wrap-around (stays within line) 4f to 00 27 to 00; 67 to 40 27 to 00
2001 dec 19 11 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth 00 01 02 03 04 15 16 17 18 19 4c 4d 4e 4f non-displayed ddram addresses 64 65 66 67 40 41 42 43 44 49 4a 4b 4c 4d 00 01 02 03 04 09 0a 0b 0c 0d 24 25 26 27 non-displayed ddram address line 1 line 2 mge991 ddram address 2-line display 12345 222324 12345 101112 12345 101112 display position ddram address 1-line display fig.3 ddram to display mapping; no shift. handbook, halfpage mge992 27 00 01 02 03 67 40 41 42 43 08 09 0a 48 49 4a ddram address line 1 line 2 2-line display 1 2 3 4 5 22 23 24 1 2 3 4 5 10 11 12 1 2 3 4 5 10 11 12 4f 00 01 02 03 14 15 16 display position ddram address 1-line display fig.4 ddram to display mapping; right shift. handbook, halfpage 01 04 05 41 42 43 44 45 0a 0b 0c 4a 4b 4c ddram address line 1 line 2 2-line display 1 2 3 4 5 22 23 24 1 2 3 4 5 10 11 12 1 2 3 4 5 10 11 12 01 04 05 02 03 02 03 16 17 18 display position ddram address 1-line display mge993 fig.5 ddram to display mapping; left shift.
2001 dec 19 12 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 7.11 character generator rom (cgrom) the cgrom generates 240 character patterns in a 5 8 dot format from 8-bit character codes. figures 7, 8, 9 and 10 show the character sets that are currently implemented. 7.12 character generator ram (cgram) up to 16 user defined characters may be stored in the cgram. some cgram characters (see fig.16) are also used to drive icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both icon rows are used in the application; 0 if no icons are driven by the icon rows). the cgrom and cgram use a common address space, of which the first column is reserved for the cgram (see fig.7). figure 11 shows the addressing principle for the cgram. 7.13 cursor control circuit the cursor control circuit generates the cursor underline and/or cursor blink as shown in fig.6 at the ddram address contained in the address counter. when the address counter contains the cgram address the cursor will be inhibited. 7.14 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not disturbed by operations on the data buses. 7.15 lcd row and column drivers the pcf2113x contains 18 row and 60 column drivers, which connect the appropriate lcd bias voltages in sequence to the display in accordance with the data to be displayed. r17 and r18 drive the icon rows. the bias voltages and the timing are selected automatically when the number of lines in the display is selected. figures 12, 13, 14 and 15 show typical waveforms. unused outputs should be left unconnected. mga801 cursor 5 x 7 dot character font alternating display cursor display example blink display example fig.6 cursor and blink display examples.
2001 dec 19 13 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mge994 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 fig.7 character set a in cgrom.
2001 dec 19 14 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mgd688 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 fig.8 character set d in cgrom.
2001 dec 19 15 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mgd689 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 fig.9 character set e in cgrom.
2001 dec 19 16 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mgu204 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 fig.10 character set w in cgrom.
2001 dec 19 17 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mge995 76543210 6543210 43210 higher order bits lower order bits lower order bits higher order bits lower order bits higher order bits 00000000 0000000 0 001 000 010 000 011 0 100 0 00 101 00 0 110 000 111 00000 000 000 001 0 0 0 010 00 00 011 100 101 00 00 110 00 00 111 00000 001 00000001 0001 00000010 00001111 00001111 00001111 00001111 01 0 0000 100 101 110 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111 character codes (ddram data) cgram address character patterns (cgram data) 43210 0 000 111 000 0 00 10 00 0 1 000 1 1 1 00 1 1 1 111 1 1 1 1 000 1 101 000 111 0 11 11 01 0 0 010 0 1 0 00 0 1 1 010 0 1 0 0 000 character code (cgram data) character pattern example 1 cursor position character pattern example 2 character code bits 0 to 3 correspond to cgram address bits 3 to 6. cgram address bits 0 to 2 designate the character pattern line position. the 8th line is the cursor position and display is performed by logical or with the cursor. data in the 8th position will appear in the cursor position. character pattern column positions correspond to cgram data bits 0 to 4, as shown in this figure. as shown in figs 7 and 8, cgram character patterns are selected when character code bits 4 to 7 are all logic 0. cgram data = logic 1 corresponds to selection for display. only bits 0 to 5 of the cgram address are set by the set cgram address command. bit 6 can be set using the set ddram address co mmand in the valid address range or by using the auto-increment feature during cgram write. all bits 0 to 6 can be read using the read busy flag and address counter command. fig.11 relationship between cgram addresses, data and display patterns.
2001 dec 19 18 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mge996 state 1 (on) state 2 (off) frame n + 1 frame n 123 18123 18 row 1 v lcd v 2 v 3 /v 4 v 5 v ss row 9 v lcd v 2 v 3 /v 4 v 5 v ss row 2 v lcd v 2 v 3 /v 4 v 5 v ss col1 v lcd v 2 v 3 /v 4 v 5 v ss col2 v lcd v 2 v 3 /v 4 v 5 v ss 0 v state 1 v op 0.5v op 0.25v op - 0.25v op - 0.5v op - v op 0 v state 2 v op 0.5v op 0.25v op - 0.25v op - 0.5v op - v op r1 r2 r3 r4 r5 r6 r7 r8 r9 fig.12 mux 1 : 18 lcd waveforms; character mode.
2001 dec 19 19 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mgu217 state 1 (on) state 2 (off) frame n + 1 frame n 123 912 3 9 row 1 v lcd v 2 v 3 /v 4 v 5 v ss row 2 v lcd v 2 v 3 /v 4 v 5 v ss row 3 v lcd v 2 v 3 /v 4 v 5 v ss col1 v lcd v 2 v 3 /v 4 v 5 v ss col2 v lcd v 2 v 3 /v 4 v 5 v ss 0 v state 1 v op 0.5v op 0.25v op - 0.25v op - 0.5v op - v op 0 v state 2 v op 0.5v op 0.25v op - 0.25v op - 0.5v op - v op r1 r2 r3 r4 r5 r6 r7 r8 r9 fig.13 mu x1:9 lcd waveforms; character mode. r10 to r18 to be left open.
2001 dec 19 20 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mge997 frame n + 1 frame n v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss col 4 off/off col 3 on/on col 2 off /on col 1 on/off row 1 to 16 row 18 row 17 only icons are driven (mux 1 : 2) fig.14 mux 1 : 2 lcd waveforms; icon mode.
2001 dec 19 21 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mge998 frame n + 1 frame n v op 2/3 v op 1/3 v op 0 - 1/3 v op - 2/3 v op - v op v op 2/3 v op 1/3 v op 0 - 1/3 v op - 2/3 v op - v op v op 2/3 v op 1/3 v op 0 - 1/3 v op - 2/3 v op - v op state 3 col 1 - row 1 to 16 state 2 col 2 - row 17 state 1 col 1 - row 17 state 3 (off) r17 r18 r1-16 v pixel state 1 (on) state 2 (off) fig.15 mux 1 : 2 lcd waveforms; icon mode. v on(rms) = 0.745v op v off(rms) = 0.333v op d v on v off ------------- 2.23 ==
2001 dec 19 22 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 7.16 reset function the pcf2113x automatically initializes (resets) when power is turned on. the chip executes a reset sequence, including a clear display, requiring 165 oscillator cycles. after the reset the chip has the state shown in table 3. table 3 state after reset step function control bit state conditions 1 clear display 2 entry mode set i/d = 1 +1 (increment) s = 0 no shift 3 display control d = 0 display off c = 0 cursor off b = 0 cursor character blink off 4 function set dl = 1 8-bit interface m = 0 1-line display h = 0 normal instruction set sl = 0 mux 1 : 18 mode 5 default address pointer to ddram; the busy flag (bf) indicates the busy state (bf = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see tables 17 and 18 6 icon control im = 0; ib = 0; dm = 0 icons, icon blink and direct mode disabled 7 display/screen con?guration l = 0; p = 0; q = 0 default con?gurations 8v lcd temperature coef?cient tc1 = 0; tc2 = 0 default temperature coef?cient 9 set v lcd v a = 0; v b =0 v lcd generator off 10 i 2 c-bus interface reset 11 set hvgen stages s1 = 1; s0 = 0 v lcd generator voltage multiplier set at factor 4
2001 dec 19 23 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 8 instructions only two pcf2113x registers, the instruction register (ir) and the data register (dr) can be directly controlled by the microcontroller. before internal operation, control information is stored temporarily in these registers, to allow interfacing to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ics. the instruction set for i 2 c-bus commands is given in table 4. the pcf2113x operation is controlled by the instructions shown in table 5 together with their execution time. details are explained in subsequent sections. instructions are of 4 types, those that: 1. designate pcf2113x functions such as display format, data length, etcetera. 2. set internal ram addresses 3. perform data transfer with internal ram 4. others. in normal use, category 3 instructions are used most frequently. however, automatic incrementing by 1 (or decrementing by 1) of internal ram addresses after each data write lessens the microcontroller program load. the display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. during internal operation, no instructions other than the read busy flag and read address instructions will be executed. because the busy flag is set to a logic 1 while an instruction is being executed, check to ensure it is a logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in table 5. an instruction sent while the busy flag is logic 1 will not be executed. table 4 instruction set for i 2 c-bus commands note 1. r/ w is set together with the slave address. control byte command byte i 2 c-bus commands cors000000db7db6db5db4db3db2db1db0 note 1
2001 dec 19 24 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 5 instruction set with parallel bus commands instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description require clock cycles h=0or1 nop 0000000000no operation 3 function set 00001dl0mslh sets interface data length (dl), number of display lines (m), single line/mux 1 : 9 (sl) and extended instruction set control (h) 3 read busy ?ag and address counter 0 1 bf a c reads the busy flag (bf) indicating internal operating is being performed and reads address counter (a c ) contents 0 read data 1 1 read data reads data from cgram or ddram 3 write data 1 0 write data writes data from cgram or ddram 3 h=0 clear display 0000000001 clears entire display and sets ddram address 0 in address counter 165 return home 0000000010 sets ddram address 0 in address counter; also returns shifted display to original position; ddram contents remain unchanged 3 entry mode set 00000001i/ds sets cursor move direction (i/d) and speci?es shift of display (s); these operations are performed during data write and read 3 display control 0000001dcb sets entire display on/off (d), cursor on/off (c) and blink of cursor position character (b); d = 0 (display off) puts chip into the power-down mode 3 cursor/display shift 000001s/cr/l00moves cursor or shifts display (s/c) to right or left (r/l) without changing ddram contents 3 set cgram address 0001 a cg sets cgram address; bit db6 is to be set by the command set ddram address; look at the description of the commands 3 set ddram address 001 a dd sets ddram address 3
2001 dec 19 25 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... h=1 reserved 0000000001do not use - screen con?guration 000000001l set screen con?guration (l) 3 display con?guration 00000001pq set display con?guration, columns (p) and rows (q) 3 icon control 0000001imibdm set icon mode (im), icon blink (ib), direct mode (dm) 3 temperature control 00000100tc1tc2 set temperature coef?cient (tcx) 3 set hvgen stages 00010000s1s0set internal v lcd generator voltage multiplier stages (s1 = 1 and s0 = 1 not allowed) 3 set v lcd 0 0 1 v voltage store v lcd in register v a or v b (v) 3 instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description require clock cycles
2001 dec 19 26 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x table 6 explanations of symbols used in tables 4 and 5. bit logic state 0 logic state 1 co last control byte; see table 4 another control byte follows after data/command dl 4 bits 8 bits m (no impact, if sl = 1) 1-line by 24 display 2-line by 12 display sl mux 1 : 18 (1 24 or 2 12 character display) mu x1:9 (1 12 character display) h use basic instruction set use extended instruction set i/d decrement increment s display freeze display shift d display off display on c cursor off cursor on b cursor character blink off; character at cursor position does not blink cursor character blink on; character at cursor position blinks s/c cursor move display shift r/l left shift right shift l (no impact, if m = 1 or sl = 1) left/right screen: standard connection left/right screen; mirrored connection 1st 12 characters of 24; columns are from 1 to 60 1st 12 characters of 24; columns are from 1 to 60 2nd 12 characters of 24; columns are from 1 to 60 2nd 12 characters of 24; columns are from 60 to 1 p column data: left to right; column data is displayed from 1 to 60 column data; right to left; column data is displayed from 60 to 1 q row data; top to bottom; row data is displayed from 1 to 16 and icon row data is in 17 and 18 row data; bottom to top; row data is displayed from 16 to 1 and icon row data is in 18 and 17 im character mode; full display icon mode; only icons displayed ib icon blink disabled icon blink enabled dm direct mode disabled direct mode enabled v set v a set v b 8.1 clear display clear display writes character code 20h into all ddram addresses (the character pattern for character code 20h must be a blank pattern), sets the ddram address counter to logic 0 and returns the display to its original position, if it was shifted. thus, the display disappears and the cursor or blink position goes to the left edge of the display. sets entry mode i/d = 1 (increment mode). s of entry mode does not change. the instruction clear display requires extra execution time. this may be allowed by checking the busy flag (bf) or by waiting until the 165 clock cycles have elapsed. the latter must be applied where no read-back options are foreseen, as in some chip-on-glass (cog) applications. 8.2 return home return home sets the ddram address counter to logic 0 and returns the display to its original position if it was shifted. ddram contents do not change. the cursor or blink position goes to the left of the first display line. i/d and s of entry mode do not change.
2001 dec 19 27 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 8.3 entry mode set 8.3.1 b it i/d when i/d = 1 (0) the ddram or cgram address increments (decrements) by 1 when data is written into or read from the ddram or cgram. the cursor or blink position moves to the right when incremented and to the left when decremented. the cursor underline and cursor character blink are inhibited when the cgram is accessed. 8.3.2 b it s when s = 1, the entire display shifts either to the right (i/d = 0) or to the left (i/d = 1) during a ddram write. thus it appears as if the cursor stands still and the display moves. the display does not shift when reading from the ddram, or when writing to or reading from the cgram. when s = 0, the display does not shift. 8.4 display control (and partial power-down mode) 8.4.1 b it d the display is on when d = 1 and off when d = 0. display data in the ddram is not affected and can be displayed immediately by setting d = 1. when the display is off (d = 0) the chip is in partial power-down mode: the lcd outputs are connected to v ss the lcd generator and bias generator are turned off. three oscillator cycles are required after sending the display off instruction to ensure all outputs are at v ss , afterwards the oscillator can be stopped. if the oscillator is running during partial power-down mode (display off) the chip can still execute instructions. even lower current consumption is obtained by inhibiting the oscillator (osc = v ss ). to ensure i dd <1 m a, the parallel bus pins db7 to db0 should be connected to v dd ; pins rs and r/ w to v dd or left open-circuit and pin pd to v dd . recovery from power-down mode: pd back to v ss , if necessary pin osc back to v dd and send a display control instruction with d=1. 8.4.2 b it c the cursor is displayed when c = 1 and inhibited when c = 0. even if the cursor disappears, the display functions i/d, etcetera, remain in operation during display data write. the cursor is displayed using 5 dots in the 8th line (see fig.6). 8.4.3 b it b the character indicated by the cursor blinks when b = 1. the cursor character blink is displayed by switching between display characters and all dots on with a period of approximately 1 second, with the cursor underline and the cursor character blink can be set to display simultaneously. 8.5 cursor or display shift cursor/display shift moves the cursor position or the display to the right or left without writing or reading display data. this function is used to correct a character or move the cursor through the display. in 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. when the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. the address counter (ac) content does not change if the only action performed is shift display, but increments or decrements with the cursor display shift. 8.6 function set 8.6.1 b it dl ( parallel mode only ) sets interface data width. data is sent or received in bytes (db7 to db0) when dl = 1 or in two nibbles (db7 to db4) when dl = 0. when 4-bit width is selected, data is transmitted in two cycles using the parallel bus. in a 4-bit application db3 to db0 should be left open-circuit (internal pull-ups). hence in the first function set instruction after power-on m, sl and h are set to logic 1. a second function set must then be sent (2 nibbles) to set m, sl and h to their required values. function set from the i 2 c-bus interface sets the dl bit to logic 1. 8.6.2 b it m selects either 1-line by 24 display (m = 0) or 2-line by 12 display (m = 1). 8.6.3 b it sl selects mu x 1 : 9, 1-line by 12 display (independent of m and l). only rows 1 to 8 and 17 are to be used. all other rows must be left open-circuit. the ddram map is the same as in the 2-line by 12 display mode, however, the second line cannot be displayed. f blink f osc 52 224 ---------------- - =
2001 dec 19 28 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 8.6.4 b it h when h = 0 the chip can be programmed via the standard 11 instruction codes used in the pcf2116 and other lcd controllers. when h = 1 the extended range of instructions will be used. these are mainly for controlling the display configuration and the icons. 8.7 set cgram address set cgram address sets bits db5 to 0 of the cgram address a cg into the address counter (binary a5 to a0). data can then be written to or read from the cgram. attention: the cgram address uses the same address register as the ddram address and consists of 7 bits (binary a6 to a0). with the set cgram address command, only bits db5 to db0 are set. bit db6 can be set using the set ddram address command first, or by using the auto-increment feature during cgram write. all bits db6 to db0 can be read using the read busy flag and read address command. when writing to the lower part of the cgram, ensure that bit db6 of the address is not set (e.g. by an earlier ddram write or read action). 8.8 set ddram address set ddram address sets the ddram address a dd into the address counter (binary a6 to a0). data can then be written to or read from the ddram. 8.9 read busy ?ag and read address read busy flag and address counter read the busy flag (bf) and address counter (ac). bf = 1 indicates that an internal operation is in progress. the next instruction will not be executed until bf = 0. it is recommended that the bf status is checked before the next write operation is executed. at the same time, the value of the address counter expressed in binary a6 to a0 is read out. the address counter is used by both cgram and ddram, and its value is determined by the previous instruction. 8.10 write data to cgram or ddram write data writes binary 8-bit data db7 to db0 to the cgram or the ddram. whether the cgram or ddram is to be written into is determined by the previous set cgram address or set ddram address command. after writing, the address automatically increments or decrements by 1, in accordance with the entry mode. only bits db4 to db0 of cgram data are valid, bits db7 to db5 are dont care. 8.11 read data from cgram or ddram read data reads binary 8-bit data db7 to db0 from the cgram or ddram. the most recent set address command determines whether the cgram or ddram is to be read. the read data instruction gates the content of the data register (dr) to the bus while pin e is high. after pin e goes low again, internal operation increments (or decrements) the ac and stores ram data corresponding to the new ac into the dr. there are only three instructions that update the data register: set cgram address set ddram address read data from cgram or ddram. other instructions (e.g. write data, cursor/display shift, clear display and return home) do not modify the data register content. 9 extended function set instructions and features 9.1 new instructions h = 1 sets the chip into alternate instruction set mode. 9.2 icon control the pcf2113x can drive up to 120 icons. see fig.16 for cgram to icon mapping.
2001 dec 19 29 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth col 1 to 5 12345 61 62 63 64 65 display: row 17 row 18 block of 5 columns col 6 to 10 678910 66 67 68 69 70 col 56 to 60 56 57 58 59 60 116 117 118 119 120 mge999 handbook, full pagewidth mgg001 116-120 odd (blink) 18/56-60 0 0 0 0 0 1 1 0 icon view 0 1 1 0 0 1 1 0 0 1 1 0 1-5 odd (blink) 17/1-5 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 116-120 even 18/56-60 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 61-65 even 18/1-5 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 56-60 even 17/56-60 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 11-15 even 17/11-15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 6-10 even 17/6-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1-5 even 17/1-5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 7 6 5 4 3 2 1 0 msb lsb lsb msb msb lsb 6 5 4 3 2 1 0 4 3 2 1 0 icon no. phase row/col character codes cgram address cgram data fig.16 cgram to icon mapping. cgram data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabl ed. data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
2001 dec 19 30 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 9.3 bit im when im = 0, the chip is in character mode. in the character mode characters and icons are driven (mux 1 : 18). the v lcd generator, if used, produces the v lcd voltage programmed in register v a . when im = 1, the chip is in icon mode. in the icon mode only the icons are driven (mux 1 : 2) and the v lcd generator, if used, produces the v lcd voltage as programmed in register v b . table 7 normal/icon mode operation 9.4 bit ib icon blink control is independent of the cursor/character blink function. when ib = 0, the icon blink is disabled. icon data is stored in cgram character 0 to 2 (3 8 5 = 120 bits for 120 icons). when ib = 1, the icon blink is enabled. in this case each icon is controlled by two bits. blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). icon states for the even phase are stored in cgram characters 0 to 2 (3 8 5 = 120 bits for 120 icons). these bits also define icon state when icon blink is not used (see table 9). icon states for the odd phase are stored in cgram character 4 to 6 (another 120 bits for the 120 icons). when icon blink is disabled cgram characters 4 to 6 may be used as normal cgram characters. 9.5 direct mode when dm = 0, the chip is not in the direct mode. either the internal v lcd generator or an external voltage may be used to achieve v lcd . when dm = 1, the chip is in direct mode. the internal v lcd generator is turned off and the v lcd2 output is directly connected to the v lcd generator supply voltage v dd2 . the direct mode can be used to reduce the current consumption when the required v lcd2 output voltage is close to the v dd2 supply voltage. this can be the case in icon mode or in mux 1:9 (depending on lcd liquid properties). 9.6 voltage multiplier control bits s1 and s0 a software configurable voltage multiplier is incorporated in the v lcd generator and can be set via the set hvgen stages command. the voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages, depending on the required v lcd output voltage (see table 8). table 8 s1 and s0 control of voltage multiplier 9.7 screen con?guration bit l l = 0: the two halves of a split screen are connected in a standard way i.e. column 1/61, 2/62 to 60/120; default. l = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120, 2/119 to 60/61. this allows single layer pcb or glass layout. im mode v lcd 0 character mode generates v a 1 icon mode generates v b s1 s0 description 0 0 set v lcd generator stages to 1 (2 x voltage multiplier) 0 1 set v lcd generator stages to 2 (3 x voltage multiplier) 1 0 set v lcd generator stages to 3 (4 x voltage multiplier) 1 1 do not use table 9 blink effect for icons and cursor character blink parameter even phase odd phase cursor character blink block (all on) normal (display character) icons state 1; cgram character 0 to 2 state 2; cgram character 4 to 6
2001 dec 19 31 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 9.8 display con?guration bit p p = 0: default. p = 1: mirrors the column data. bit q q = 0: default. q = 1: mirrors the row data. 9.9 temperature control default is tc1 = 0 and tc2 = 0. selects the default temperature coefficient for the internally generated v lcd (see table 10). the ranges for tc are given in chapter 13. table 10 tc1 and tc2 selection of v lcd temperature coef?cient 9.10 set v lcd the v lcd value is programmed by instruction. two on-chip registers, v a and v b hold v lcd values for the character mode and the icon mode respectively. the generated v lcd value is independent of v dd , allowing battery operation of the chip. v lcd programming: 1. send function set instruction with h = 1 2. send set v lcd instruction to write to voltage register: a) db7, db6 = 10: db5 to db0 are v lcd of character mode (v a ) b) db7, db6 = 11: db5 to db0 are v lcd of icon mode (v b ) c) db5 to db0 = 000000 switches v lcd generator off (when selected) d) during display off and power-down the v lcd generator is also disabled. 3. send function set instruction with h = 0 to resume normal programming. 9.11 reducing current consumption reducing current consumption can be achieved by one of the options given in table 11. when v lcd lies outside the v dd range and must be generated, it is usually more efficient to use the on-chip generator than an external regulator. table 11 reducing current consumption tc1 tc2 description 00v lcd temperature coef?cient 0 10v lcd temperature coef?cient 1 01v lcd temperature coef?cient 2 11v lcd temperature coef?cient 3 original mode alternative mode character mode icon mode (control bit im) display on display off (control bit d) v lcd generator operating direct mode any mode power-down (pd pin)
2001 dec 19 32 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 10 interfaces to microcontroller 10.1 parallel interface the pcf2113x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. in 8-bit mode data is transferred as 8-bit bytes using the 8 data lines db7 to db0. three further control lines e, rs and r/ w are required (see chapter 6). in 4-bit mode data is transferred in two cycles of 4 bits each using pins db7 to db4 for the transaction. the higher order bits (corresponding to db7 to db4 in 8-bit mode) are sent in the first cycle and the lower order bits (db3 to db0 in 8-bit mode) in the second cycle. data transfer is complete after two 4-bit data transfers. it should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction, see figs 17 to 19 for examples of bus protocol. in 4-bit mode, pins db3 to db0 must be left open-circuit. they are pulled up to v dd internally. 10.2 i 2 c-bus interface the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are the serial data line (sda) and the serial clock line (scl). both lines must be connected to a positive supply via pull-up resistors. data transfer may be initiated only when the bus is not busy. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). mga804 rs e db7 r/w db6 db5 db4 instruction write busy flag and address counter read data register read ir7 ir3 bf ac3 dr7 dr3 ir6 ir2 ac6 ac2 dr6 dr2 ir5 ir1 ac5 ac1 dr5 dr1 ir4 ir0 ac4 ac0 dr4 dr0 fig.17 4-bit transfer example.
2001 dec 19 33 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x mga805 rs e internal db7 r/w internal operation ir7 ir3 ac3 d7 d3 not busy ac3 busy instruction write busy flag check busy flag check instruction write fig.18 an example of 4-bit data transfer timing sequence. ir7, ir3: instruction 7th, 3rd bit. ac3: address counter 3rd bit. d7, d3: data 7th, 3rd bit. mga806 instruction write busy flag check busy flag check busy flag check instruction write internal operation rs e internal db7 r/w data busy busy not busy data fig.19 example of busy flag checking timing sequence.
2001 dec 19 34 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x a master receiver must signal an end of data to the transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. 10.2.1 i 2 c- bus protocol before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always carried out with the first byte transmitted after the start procedure. the i 2 c-bus configuration for the different pcf2113x read and write cycles is shown in figs 24 to 26. the slow down feature of the i 2 c-bus protocol (receiver holds scl low during internal operations) is not used in the pcf2113x. 10.2.2 d efinitions transmitter: the device which sends the data to the bus receiver: the device which receives the data from the bus master: the device which initiates a transfer generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronization: procedure to synchronize the clock signals of two or more devices. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.20 system configuration. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.21 bit transfer.
2001 dec 19 35 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.22 definition of start and stop conditions. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.23 acknowledgement on the i 2 c-bus.
2001 dec 19 36 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgg002 s a 0 s p 011101 0a slave address control byte a 1 co data byte a control byte a r/w 0 co update data pointer 1 byte n 3 0 bytes 2n 3 0 bytes data byte a acknowledgement from pcf2113x rs rs s a 0 011101 0 pcf2113x slave address r/w fig.24 master transmits to slave receiver; write mode.
2001 dec 19 37 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgg003 s a 0 s 011101 0 a slave address control byte a 1 co data byte a control byte a r/w 0 co co update data pointer update data pointer 1 byte n 3 0 bytes n bytes last byte 2n 0 bytes data byte (1) a acknowledgement s a 0 s 1a data byte a 1 p slave address data byte acknowledgement acknowledgement no acknowledgement r/w rs rs fig.25 master reads after setting word address; writes word address, set rs; read data. last data byte is a dummy byte (may be omitted).
2001 dec 19 38 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mgg004 co update data pointer update data pointer n bytes last byte s a 0 s 1a data byte a 1 p slave address data byte acknowledgement from pcf2113x acknowledgement from master no acknowledgement from master r/w fig.26 master reads slave immediately after first byte; read mode (rs previously defined). 11 limiting values in accordance with the absolute maximum rating system (iec 60134). 12 handling instructions inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter conditions min. max. unit v dd1 logic supply voltage - 0.5 +5.5 v v dd2 , v dd3 v lcd generator supply voltages - 0.5 +4 v v lcd lcd supply voltage - 0.5 +6.5 v v i/o(n) voltage on any v dd related input or output - 0.5 v dd + 0.5 v any v lcd related input or output - 0.5 v lcd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma i dd , i ss and i lcd v dd , v ss or v lcd supply current - 50 +50 ma p tot total power dissipation - 400 mw p o power dissipation per output - 100 mw v es electrostatic handling voltage human body model; c = 100 pf; r = 1.5 k w - 2000 v electrostatic handling voltage machine model; c = 200 pf; l = 0.75 m h - 150 v t stg storage temperature - 65 +150 c
2001 dec 19 39 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 13 dc characteristics v dd1 = 1.8 to 5.5 v; v dd2 =v dd3 = 2.2 to 4.0 v; v ss =0v;v lcd = 2.2 to 6.5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dd1 logic supply voltage note 1 1.8 - 5.5 v v dd2 ,v dd3 v lcd generator supply voltages internal v lcd generation (v dd2 and v dd3 2001 dec 19 40 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x notes 1. spikes on v dd1 or v ss1 which cause v dd1 - v ss1 1.6 v can cause a power-on reset. 2. resets all logic when v dd1 2v 3 -- ma v ol = 0.2 v dd1 ; v dd1 <2v 2 -- ma lcd outputs r o(row) row output resistance of pins r1 to r18 note 7 - 10 30 k w r o(col) column output resistance of pins c1 to c60 note 7 - 15 40 k w v bias(tol) bias voltage tolerance on pins r1 to r18 and c1 to c60 note 8 - 20 130 mv v lcd2(tol) v lcd voltage tolerance t amb =25 c; note 5 v lcd <3v -- 160 mv v lcd <4v -- 200 mv v lcd <5v -- 260 mv v lcd <6v -- 340 mv tc0 v lcd temperature coef?cient 0 -- 0.16 - %/k tc1 v lcd temperature coef?cient 1 -- 0.18 - %/k tc2 v lcd temperature coef?cient 2 -- 0.21 - %/k tc3 v lcd temperature coef?cient 3 -- 0.24 - %/k symbol parameter conditions min. typ. max. unit
2001 dec 19 41 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 14 ac characteristics v dd1 = 1.8 to 5.5 v; v dd2 =v dd3 = 2.2 to 4.0 v; v ss =0v;v lcd = 2.2 to 6.5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit f fr lcd frame frequency (internal clock) v dd = 5.0 v 45 95 147 hz f osc oscillator frequency (not available at any pin) 140 250 450 khz f osc(ext) external clock frequency 140 - 450 khz t osc(st) oscillator start-up time after power-down note 1 - 200 300 m s t w(pd) power-down high-level pulse width 1 --m s t sw(pd) tolerable spike width on pd pin note 1 -- 90 ns timing characteristics of parallel interface; note 2 w rite operation ( writing data from microcontroller to pcf2113 x ); see fig.27 t cy(en) enable cycle time 500 -- ns t w(en) enable pulse width 220 -- ns t su(a) address set-up time 50 -- ns t h(a) address hold time 25 -- ns t su(d) data set-up time 60 -- ns t h(d) data hold time 25 -- ns r ead operation ( reading data from pcf2113 x to microcontroller ); see fig.28 t cy(en) enable cycle time 500 -- ns t w(en) enable pulse width 220 -- ns t su(a) address set-up time 50 -- ns t h(a) address hold time 25 -- ns t d(d) data delay time v dd1 > 2.2 v -- 150 ns v dd1 > 1.5 v -- 250 ns t h(d) data hold time 5 - 100 ns timing characteristics of i 2 c-bus interface; see fig.29; note 2 f scl scl clock frequency -- 400 khz t low scl clock low period 1.3 --m s t high scl clock high period 0.6 --m s t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 -- ns t r scl and sda rise time note 1 and 3 15 + 0.1 c b - 300 ns t f scl and sda fall time note 1 and 3 15 + 0.1 c b - 300 ns c b capacitive bus line load -- 400 pf t su;sta set-up time for a repeated start condition 0.6 --m s t hd;sta start condition hold time 0.6 --m s
2001 dec 19 42 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x notes 1. tested on sample base. 2. all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . 3. c b = total capacitance of one bus line in pf. t su;sto set-up time for stop condition 0.6 --m s t sw tolerable spike width on bus -- 50 ns t buf bus free time between stop and start condition 1.3 --m s symbol parameter conditions min. typ. max. unit handbook, full pagewidth rs e db0 to db7 v v v v v v v v v v v v v t ih1 il1 ih1 il1 ih1 il1 il1 il1 ih1 il1 ih1 il1 v il1 v ih1 il1 cy(en) t su(d) h(d) t t w(en) t h(a) t h(a) t su(a) valid data mbk474 r/w fig.27 parallel bus write operation sequence; writing data from microcontroller to pcf2113x.
2001 dec 19 43 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth rs r/w e db0 to db7 v v v v v v v v v v ih1 il1 ih1 il1 ih1 il1 ih1 il1 v ol1 v oh1 il1 t cy(en) h(d) t t w(en) t h(a) t h(a) t su(a) ih1 v ol1 v oh1 t d(d) v ih1 mbk475 fig.28 parallel bus read operation sequence; writing data from pcf2113x to microcontroller. handbook, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat fig.29 i 2 c-bus timing diagram.
2001 dec 19 44 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 15 device protection circuits symbol pad internal circuit v dd1 1 v dd2 109 v dd3 110 v ss1 7 v ss2 8 v lcdsense 10 v lcd1 11 v lcd2 9 scl 96 sda 97 v ss1 v dd1 mgu200 v ss2 v ss1 v dd2 mgu201 v ss1 v dd3 mgu202 v ss1 v ss2 8 7 mgu203 v ss1 mgu196 v ss1 v dd1 mgu198
2001 dec 19 45 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x osc 2 pd 3 t1 5 t2 6 t3 4 e98 rs 99 r/w 100 db0 to db7 108 to 101 r1 to r8 94 to 87 r9 to r16 12 to 19 r17 95 r18 20 c1 to c2 86 to 85 c3 to 27 82 to 58 c28 to c52 55 to 31 c53 to c60 28 to 21 symbol pad internal circuit v ss1 mgu199 v dd1 v ss1 mgu197 v lcd2
2001 dec 19 46 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 16 application information handbook, full pagewidth pcf2113x mgg006 p80cl51 2 12 character lcd display plus 120 icons 16 4 c1 to c60 60 2 rs p10 p11 e p12 db7 to db4 p17 to p14 r17, r18 r1 to r16 r/w fig.30 direct connection to 8-bit microcontroller; 4-bit bus. handbook, full pagewidth pcf2113x mgg005 p80cl51 2 12 character lcd display plus 120 icons 16 8 c1 to c60 60 2 rs p20 p21 e p22 db7 to db0 p17 to p10 r17, r18 r1 to r16 r/w fig.31 direct connection to 8-bit microcontroller; 8-bit bus. handbook, full pagewidth mgg007 pcf2113x 2 12 character lcd display plus 120 icons 16 8 c1 to c60 60 2 osc rs db7 to db0 e 100 nf 100 nf r17, r18 r1 to r16 v dd v ss v dd v lcd v ss r/w fig.32 typical application using parallel interface.
2001 dec 19 47 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth v dd v dd scl sda master transmitter pcf84c81a; p80cl410 pcf2113x 2 12 character lcd display plus 120 icons 16 c1 to c60 60 2 osc scl sda db3/sao 100 nf 100 nf r17, r18 r1 to r16 v dd v dd v ss v dd v lcd v ss pcf2113x 1 24 character lcd display plus 120 icons 16 c1 to c60 60 2 osc scl sda db3/sao 470 nf 100 nf r17, r18 r1 to r16 v ss v dd v ss v dd v lcd v ss mgg008 fig.33 application using i 2 c-bus interface. 16.1 general application information the required minimum value for the external capacitors in an application with the pcf2113x are: c ext for v lcd /v ss = 100 nf min., for v dd /v ss = 470 nf. higher capacitor values are recommended for ripple reduction. for cog applications the recommended ito track resistance is to be minimized for the i/o and supply connections. optimized values for these tracks are below 50 w for the supply and below 100 w for the i/o connections. higher track resistance reduce performance and increase current consumption. to avoid accidental triggering of power-on reset (especially in cog applications), the supplies must be adequately decoupled. depending on power supply quality, v dd1 may have to be risen above the specified minimum.
2001 dec 19 48 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 16.2 4-bit operation, 1-line display using internal reset the program must set functions prior to a 4-bit operation (see table 12). when power is turned on, 8-bit operation is automatically selected and the pcf2113x attempts to perform the first write as an 8-bit operation. since nothing is connected to db0 to db3, a rewrite is then required. however, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see table 12 step 3). thus, db4 to db7 of the function set are written twice. 16.3 8-bit operation, 1-line display using internal reset tables 13 and 14 show an example of a 1-line display in 8-bit operation. the pcf2113x functions must be set by the function set instruction prior to display. since the ddram can store data for 80 characters, the ram can be used for advertising displays when combined with display shift operation. since the display shift operation changes display position only and the ddram contents remain unchanged, display data entered first can be displayed when the return home operation is performed. 16.4 8-bit operation, 2-line display for a 2-line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. thus, if there are only 8 characters in the first line, the ddram address must be set after the 8th character is completed (see table 15). it should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. 16.5 i 2 c-bus operation, 1-line display a control byte is required with most commands (see table 16). table 12 4-bit operation, 1-line display example using internal reset step instruction display operation 1 power supply on (pcf2113x is initialized by the internal reset) initialized; no display appears 2 function set rs r/ w db7 db6 db5 db4 sets to 4-bit operation; in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write 000010 3 function set 000010 sets to 4-bit operation, selects 1-line display and v lcd =v 0 ; 4-bit operation starts from this point and resetting is needed 000000 4 display control 000000 _ turns on display and cursor; entire display is blank after initialization 001110 5 entry mode set 000000 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the dd/cgram; display is not shifted 000110 6 write data to cgram/ddram 100101 p_ writes p; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 100000
2001 dec 19 49 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 13 8-bit operation, 1-line display example; using internal reset (character set a) step instruction display operation 1 power supply on (pcf2113x is initialized by the internal reset) initialized; no display appears 2 function set rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 sets to 8-bit operation, selects 1-line display and v lcd =v 0 0000110000 3 display control 0000001110 _ turns on display and cursor; entire display is blank after initialization 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the dd/cgram; display is not shifted 5 write data to cgram/ddram 1001010000 p_ writes p; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 6 write data to cgram/ddram 1001001000 ph_ writes h 7to10 | | writes ilip 11 write data to cgram/ddram 1001010011 philips_ writes s 12 entry mode set 0000000111 philips_ sets mode for display shift at the time of write 13 write data to cgram/ddram 1000100000 hilips _ writes space 14 write data to cgram/ddram 1001001101 ilips m_ writes m 15 to 19 | | writes icrok 20 write data to cgram/ddram 1001001111 microko_ writes o
2001 dec 19 50 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 21 cursor/display shift 0000010000 microk o shifts only the cursor position to the left 22 cursor/display shift 0000010000 micro ko shifts only the cursor position to the left 23 write data to cgram/ddram 1001000011 icroc o writes c correction; the display moves to the left 24 cursor/display shift 0000011100 microco shifts the display and cursor to the right 25 cursor/display shift 0000010100 microco_ shifts only the cursor to the right 26 write data to cgram/ddram 1001001101 icrocom_ writes m 27 return home 0000000010 philips m returns both display and cursor to the original position (address 0) step instruction display operation
2001 dec 19 51 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 14 8-bit operation, 1-line display and icon example; using internal reset (character set a) step instruction display operation 1 power supply on (pcf2113x is initialized by the internal reset) initialized; no display appears 2 function set rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 sets to 8-bit operation, selects 1-line display and v lcd =v 0 0000110000 3 display mode on/off control 0000001110 _ turns on display and cursor; entire display is blank after initialization 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the dd/cgram; display is not shifted 5 set cgram address 0001000000 _ sets the cgram address to position of character 0; the cgram is selected 6 write data to cgram/ddram 1000001010 _ writes data to cgram for icon even phase; icons appears 7| | 8 set cgram address 0001110000 _ sets the cgram address to position of character 4; the cgram is selected 9 write data to cgram/ddram 1000001010 _ writes data to cgram for icon odd phase 10 | | 11 function set 0000110001 _ sets h = 1 12 icon control 0000001010 _ icons blink 13 function set 0000110001 _ sets h = 0
2001 dec 19 52 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 14 set ddram address 0 0 1 0 0 0 0 0 0 0 sets the ddram address to the ?rst position; ddram is selected 15 write data to cgram/ddram 1001010000 p_ writes p; the cursor is incremented by 1 and shifted to the right 16 write data to cgram/ddram 1001001000 ph_ writes h 17 to 21 | | writes ilips 22 return home 0000000010 philips returns both display and cursor to the original position (address 0) step instruction display operation
2001 dec 19 53 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 15 8-bit operation, 2-line display example; using internal reset step instruction display operation 1 power supply on (pcf2113x is initialized by the internal reset) initialized; no display appears 2 function set rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 sets to 8-bit operation; selects 2-line display and v lcd generator off 0000110100 3 display on/off control 0000001110 _ turns on display and cursor; entire display is blank after initialization 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the cg/ddram; display is not shifted 5 write data to cgram/ddram 1001010000 p_ writes p; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 6 to 10 | | writes hilip 11 write data to cgram/ddram 1001010011 philips_ writes s 12 set ddram address 0011000000 philips _ sets ddram address to position the cursor at the head of the 2nd line 13 write data to cgram/ ddram 1001001101 philips m_ writes m 14 to 18 | | writes icroc 19 write data to cgram/ddram 1001001111 philips microco_ writes o
2001 dec 19 54 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 20 write data to cgram/ddram 0000000111 philips microco_ sets mode for display shift at the time of write 21 write data to cgram/ddram 1001001101 hilips icrocom_ writes m; display is shifted to the left; the ?rst and second lines shift together 23 return home 0000000010 philips microcom returns both display and cursor to the original position (address 0) step instruction display operation
2001 dec 19 55 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 16 example of i 2 c-bus operation; 1-line display (using internal reset, assuming sa0 = v ss ; note 1) step i 2 c-bus byte display operation 1i 2 c-bus start initialized; no display appears 2 slave address for write sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ w ack during the acknowledge cycle sda will be pulled-down by the pcf2113x 011101001 3 send a control byte for function set co rs 0 0 0 0 0 0 ack control byte sets rs for following data bytes 000000001 4 function set db7 db6 db5 db4 db3 db2 db1 db0 ack selects 1-line display and v lcd =v 0 ; scl pulse during acknowledge cycle starts execution of instruction 001x00001 5 display on/off control db7 db6 db5 db4 db3 db2 db1 db0 ack _ turns on display and cursor; entire display shows character 20h (blank in ascii-like character sets) 000011101 6 entry mode set db7 db6 db5 db4 db3 db2 db1 db0 ack _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the ddram or cgram; display is not shifted 000001101 7i 2 c-bus start _ for writing data to ddram, rs must be set to 1; therefore a control byte is needed 8 slave address for write sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ wack _ 011101001 9 send a control byte for write data co rs 0 0 0 0 0 0 ack _ 010000001 10 write data to ddram db7 db6 db5 db4 db3 db2 db1 db0 ack p_ writes p; the ddram has been selected at power-up; the cursor is incremented by 1 and shifted to the right 010100001 11 write data to ddram db7 db6 db5 db4 db3 db2 db1 db0 ack ph_ writes h 010010001
2001 dec 19 56 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 12 to 15 | | 16 write data to ddram db7 db6 db5 db4 db3 db2 db1 db0 ack philips_ writes s 010100111 17 (optional i 2 c-bus stop) i 2 c-bus start start + slave address for write (as step 8) philips_ 18 control byte co rs 0 0 0 0 0 0 ack philips_ 100000001 19 return home db7 db6 db5 db4 db3 db2 db1 db0 ack philips sets ddram address 0 in address counter (also returns shifted display to original position; ddram contents unchanged); this instruction does not update the data register (dr) 000000101 20 i 2 c-bus start philips 21 slave address for read sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ wack p hilips during the acknowledge cycle the content of the dr is loaded into the internal i 2 c-bus interface to be shifted out; in the previous instruction neither a set address nor a read data has been performed; therefore the content of the dr was unknown; the r/w has to be set to 1 while still in i 2 c-write mode 011101011 22 control byte for read co rs 0 0 0 0 0 0 ack philips ddram content will be read from following instructions 011000001 23 read data: 8 scl + master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack ph ilips 8 scl; content loaded into interface during previous acknowledge cycle is shifted out over sda; msb is db7; during master acknowledge content of ddram address 01 is loaded into the i 2 c-bus interface xxxxxxxx0 24 read data: 8 scl + master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack phi lips 8 scl; code of letter h is read ?rst; during master acknowledge code of i is loaded into the i 2 c-bus interface 010010000 step i 2 c-bus byte display operation
2001 dec 19 57 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... notes 1. x = dont care. 2. sda is left at high-impedance by the microcontroller during the read acknowledge. 25 read data: 8 scl + no master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack phi lips no master acknowledge; after the content of the i 2 c-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register, data register is not updated, address counter is not incremented and cursor is not shifted 010010011 26 i 2 c-bus stop phi lips step i 2 c-bus byte display operation
2001 dec 19 58 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 17 initialization by instruction, 8-bit interface (note 1) note 1. x = dont care. step description power-on or unknown state | wait 2 ms after internal reset has been applied | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction 0 0 0 0 1 1 x x x x function set (interface is 8 bits long) | wait 2 ms | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction 0 0 0 0 1 1 x x x x function set (interface is 8 bits long) | wait more than 40 m s | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction 0 0 0 0 1 1 x x x x function set (interface is 8 bits long) | | bf can be checked after the following instructions; when bf is not checked, the waiting time between instructions is the speci?ed instruction time (see table 3) rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 function set (interface is 8 bits long); specify the number of display lines 0000110m0h 0 0 0 0 0 0 1 0 0 0 display off 0 0 0 0 0 0 0 0 0 1 clear display 0 0 0 0 0 0 0 1 i/d s entry mode set | initialization ends
2001 dec 19 59 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 18 initialization by instruction, 4-bit interface; not applicable for i 2 c-bus operation step description power-on or unknown state | wait 2 ms after internal reset has been applied | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction 000011 function set (interface is 8 bits long) | wait 2 ms | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction 000011 function set (interface is 8 bits long) | wait 40 m s | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction 000011 function set (interface is 8 bits long) | bf can be checked after the following instructions; when bf is not checked, the waiting time between instructions is the speci?ed instruction time (see table 3) rs r/ w db7 db6 db5 db4 function set (set interface to 4 bits long) 000010 interface is 8 bits long 000010 function set (interface is 4 bits long) 0 0 0 m 0 h specify number of display lines 000000 001000 display off 000000 clear display 000001 000000 entry mode set 0 0 0 1 i/d s | initialization ends
2001 dec 19 60 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 17 bonding pad information symbol pad coordinates (1) xy v dd1 1 - 1345 - 1550 osc 2 - 1155 - 1550 pd 3 - 1 055 - 1550 t3 4 - 845 - 1550 t1 5 - 765 - 1550 t2 6 - 665 - 1550 v ss1 7 - 525 - 1550 v ss2 8 - 455 - 1550 v lcd2 9 - 295 - 1550 v lcdsense 10 - 145 - 1550 v lcd1 11 +15 - 1550 r9 12 +175 - 1550 r10 13 +245 - 1550 r11 14 +315 - 1550 r12 15 +385 - 1550 r13 16 +455 - 1550 r14 17 +525 - 1550 r15 18 +595 - 1550 r16 19 +665 - 1550 r18 20 +735 - 1550 c60 21 +805 - 1550 c59 22 +875 - 1550 c58 23 +995 - 1550 c57 24 +1065 - 1550 c56 25 +1135 - 1550 c55 26 +1205 - 1550 c54 27 +1275 - 1550 c53 28 +1345 - 1550 dummy pad 1 29 +1435 - 1550 dummy pad 2 30 +1630 - 1395 c52 31 +1630 - 1255 c51 32 +1630 - 1155 c50 33 +1630 - 1055 c49 34 +1630 - 955 c48 35 +1630 - 735 c47 36 +1630 - 635 c46 37 +1630 - 535 c45 38 +1630 - 435 c44 39 +1630 - 335 c43 40 +1630 - 235 c42 41 +1630 - 135 c41 42 +1630 - 35 c40 43 +1630 +65 c39 44 +1630 +165 c38 45 +1630 +265 c37 46 +1630 +365 c36 47 +1630 +465 c35 48 +1630 +565 c34 49 +1630 +665 c33 50 +1630 +765 c32 51 +1630 +865 c31 52 +1630 +965 c30 53 +1630 +1065 c29 54 +1630 +1165 c28 55 +1630 +1265 dummy pad 3 56 +1630 +1335 dummy pad 4 57 +1435 +1550 c27 58 +1335 +1550 c26 59 +1225 +1550 c25 60 +1115 +1550 c24 61 +1005 +1550 c23 62 +765 +1550 c22 63 +665 +1550 c21 64 +565 +1550 c20 65 +465 +1550 c19 66 +365 +1550 c18 67 +265 +1550 c17 68 +165 +1550 c16 69 +65 +1550 c15 70 - 35 +1550 c14 71 - 135 +1550 c13 72 - 235 +1550 c12 73 - 335 +1550 c11 74 - 435 +1550 c10 75 - 535 +1550 c9 76 - 635 +1550 c8 77 - 735 +1550 c7 78 - 835 +1550 c6 79 - 965 +1550 c5 80 - 1065 +1550 c4 81 - 1165 +1550 c3 82 - 1265 +1550 dummy pad 5 83 - 1465 +1550 dummy pad 6 84 - 1630 +1355 c2 85 - 1630 +1255 symbol pad coordinates (1) xy
2001 dec 19 61 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x note 1. all x and y coordinates are referenced to centre of chip and dimensions are in m m (see fig.34). c1 86 - 1630 +1185 r8 87 - 1630 +1115 r7 88 - 1630 +1045 r6 89 - 1630 +975 r5 90 - 1630 +905 r4 91 - 1630 +835 r3 92 - 1630 +765 r2 93 - 1630 +695 r1 94 - 1630 +625 r17 95 - 1630 +555 scl 96 - 1630 +375 sda 97 - 1630 +305 e98 - 1630 +85 rs 99 - 1630 - 15 r/w 100 - 1630 - 115 symbol pad coordinates (1) xy db7 101 - 1630 - 215 db6 102 - 1630 - 315 db5 103 - 1630 - 415 db4 104 - 1630 - 515 db3 105 - 1630 - 615 db2 106 - 1630 - 715 db1 107 - 1630 - 815 db0 108 - 1630 - 915 v dd2 109 - 1630 - 1015 v dd3 110 - 1630 - 1235 dummy pad 7 111 - 1630 - 1395 dummy pad 8 112 - 1465 - 1550 symbol pad coordinates (1) xy
2001 dec 19 62 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x handbook, full pagewidth mgu205 dummy pad 6 c2 10 9 10 8 10 7 10 6 10 5 10 4 10 3 10 2 101 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 61 110 111 112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 c1 r8 r7 r6 r5 r4 r3 r2 r1 r17 e rs rw db7 db6 db5 db4 db3 db2 db1 db0 dummy pad 8 v dd1 osc pd t3 t1 t2 r9 r10 r11 r12 r13 r14 r15 r16 r18 c60 c59 c58 c57 c56 c55 c54 c53 dummy pad 1 v ss1 v ss2 v lcd2 v lcd1 v lcdsense v dd2 v dd3 dummy pad 7 scl sda dummy pad 2 dummy pad 3 c52 c51 c50 c49 c48 c47 c46 c45 c44 c43 c42 c41 c40 c39 c38 c37 c36 c35 c34 c33 c32 c31 c30 c29 c28 dummy pad 4 c27 c26 c25 c24 c23 c22 c21 c20 c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 dummy pad 5 pc2113x x y 0 0 3.36 mm 3.52 mm fig.34 bonding pad locations.
2001 dec 19 63 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 18 tray information fig.35 tray details. handbook, full pagewidth mgu206 d c a x y f e b for dimensions see table 19. table 19 tray dimensions table 20 bump size handbook, halfpage mgu207 pc2113x fig.36 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. dimension description value a pocket pitch x direction 6.35 mm b pocket pitch y direction 5.59 mm c pocket width x direction 3.82 mm d pocket width y direction 3.66 mm e tray width x direction 50.8 mm f tray width y direction 50.8 mm x pockets in x direction 7 y pockets in y direction 8 parameter value unit type galvanic pure au - bump width 50 6 m m bump length 90 6 m m bump height 17.5 5 m m height difference in one die <2 m m convex deformation <5 m m pad size, aluminium 62 100 m m passivation opening cbb 36 76 m m wafer thickness 380 25 m m
2001 dec 19 64 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 19 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-01-19 00-02-01 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
2001 dec 19 65 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 20 soldering 20.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 20.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 20.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2001 dec 19 66 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 20.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2001 dec 19 67 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 21 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. 22 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 24 bare die disclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used.
2001 dec 19 68 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x 25 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2001 dec 19 69 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x notes
2001 dec 19 70 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x notes
2001 dec 19 71 philips semiconductors product speci?cation lcd controllers/drivers pcf2113x notes
? koninklijke philips electronics n.v. 2001 sca73 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 403502/03/pp 72 date of release: 2001 dec 19 document order number: 9397 750 06995

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