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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit m m m m pd444004l 4m-bit cmos fast sram 1m-word by 4-bit data sheet document no. m14427ej3v0ds00 (3rd edition) date published january 2001 ns cp(k) printed in japan the mark ? ? ? ? shows major revised points. description the m pd444004l is a high speed, low power, 4,194,304 bits (1,048,576 words by 4 bits) cmos static ram. operating supply voltage is 3.3 v 0.3 v. the m pd444004l is packaged in a 32-pin plastic soj and 32-pin plastic tsop (ii). features 1,048,576 words by 4 bits organization fast access time : 8, 10, 12 ns (max.) output enable input for easy application single +3.3 v power supply ordering information part number package access time supply current ma (max.) ns (max.) at operating at standby m pd444004lle-a8 32-pin plastic soj 8 180 5 m pd444004lle-a10 (10.16 mm (400)) 10 160 m pd444004lle-a12 12 150 m pd444004lg5-a8-7jd note 32-pin plastic tsop (ii) 8 180 m pd444004lg5-a10-7jd note (10.16 mm (400)) 10 160 m pd444004lg5-a12-7jd note (normal bent) 12 150 note under development ? ? ? ?
2 m m m m pd444004l data sheet m14427ej3v0ds pin configurations (marking side) / indicates active low signal. 32-pin plastic soj (10.16 mm (400)) [ m m m m pd444004lle ] 32-pin plastic tsop (ii) (10.16 mm (400)) (normal bent) [ m m m m pd444004lg5- -7jd ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a0 a1 a2 a3 a4 /cs i/o1 v cc gnd i/o2 /we a5 a6 a7 a8 a9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a19 a18 a17 a16 a15 /oe i/o4 gnd v cc i/o3 a14 a13 a12 a11 a10 nc a0 - a19 : address inputs i/o1 - i/o4 : data inputs / outputs /cs : chip select /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection remark refer to package drawings for the 1-pin index mark.
3 m m m m pd444004l data sheet m14427ej3v0ds block diagram a0 | a19 address buffer row decoder memory cell array 4,194,304 bits gnd v cc /we /oe /cs input data controller sense amplifier / switching circuit column decoder address buffer i/o1 | i/o4 output data controller truth table /cs /oe /we mode i/o supply current h not selected high impedance i sb l l h read d out i cc l lwrite d in l h h output disable high impedance remark : dont care
4 m m m m pd444004l data sheet m14427ej3v0ds electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc C0.5 note to +4.0 v input / output voltage v t C0.5 note to +4.0 v operating ambient temperature t a 0 to 70 c storage temperature t stg C55 to +125 c note C2.0 v (min.) (pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc +0.3 v low level input voltage v il C0.3 note +0.8 v operating ambient temperature t a 070 c note C2.0 v (min.) (pulse width : 2 ns) ? ?
5 m m m m pd444004l data sheet m14427ej3v0ds dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. typ. max. unit input leakage current i li v in = 0 v to v cc C2 +2 m a output leakage current i lo v i/o = 0 v to v cc ,C2+2 m a /cs = v ih or /oe = v ih or /we = v il operating supply current i cc /cs = v il , cycle time : 8 ns 180 ma i i/o = 0 ma, cycle time : 10 ns 160 minimum cycle time cycle time : 12 ns 150 standby supply current i sb /cs = v ih , v in = v ih or v il 40 ma i sb1 /cs 3 v cc C 0.2 v, 5 v in 0.2 v or v in 3 v cc C 0.2 v high level output voltage v oh i oh = C4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of package types. capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 6 pf input / output capacitance c i/o v i/o = 0 v 8 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are periodically sampled and not 100% tested.
6 m m m m pd444004l data sheet m14427ej3v0ds ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions input waveform (rise and fall time 3 ns) test points gnd 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load ac characteristics directed with the note should be measured with the output load shown in figure 1 or figure 2 . figure 1 figure 2 (t aa , t acs , t oe , t oh )(t clz , t olz , t chz , t ohz , t whz , t ow ) v tt = +1.5 v i/o (output) 50 w z o = 50 w 30 pf c l +3.3 v i/o (output) 317 w 5 pf c l 351 w remark c l includes capacitances of the probe and jig, and stray capacitances.
7 m m m m pd444004l data sheet m14427ej3v0ds read cycle parameter symbol m pd444004l-a8 m pd444004l-a10 m pd444004l-a12 unit notes min. max. min. max. min. max. read cycle time t rc 81012ns address access time t aa 81012ns1 /cs access time t acs 81012ns /oe access time t oe 456ns output hold from address change t oh 333ns /cs to output in low impedance t clz 333ns2, 3 /oe to output in low impedance t olz 000ns /cs to output in high impedance t chz 456ns /oe to output hold in high impedance t ohz 456ns notes 1. see the output load shown in figure 1 . 2. transition is measured at 200 mv from steady-state voltage with the output load shown in figure 2 . 3. these parameters are periodically sampled and not 100% tested. remark these ac characteristics are in common regardless of package types. read cycle timing chart 1 (address access) t oh t rc t aa address (input) i/o (output) previous data out data out remarks 1. in read cycle, /we should be fixed to high level. 2. /cs = /oe = v il
8 m m m m pd444004l data sheet m14427ej3v0ds read cycle timing chart 2 (/cs access) address (input) t rc t aa t olz /cs (input) i/o (output) data out t ohz high impedance t acs /oe (input) t oe t clz t chz high impedance caution address valid prior to or coincident with /cs low level input. remark in read cycle, /we should be fixed to high level.
9 m m m m pd444004l data sheet m14427ej3v0ds write cycle parameter symbol m pd444004l-a8 m pd444004l-a10 m pd444004l-a12 unit notes min. max. min. max. min. max. write cycle time t wc 81012ns /cs to end of write t cw 678ns address valid to end of write t aw 678ns write pulse width t wp 678ns data valid to end of write t dw 456ns data hold time t dh 000ns address setup time t as 000ns write recovery time t wr 000ns /we to output in high impedance t whz 456ns1, 2 output active from end of write t ow 333ns notes 1. transition is measured at 200 mv from steady-state voltage with the output load shown in figure 2 . 2. these parameters are periodically sampled and not 100% tested. remark these ac characteristics are in common regardless of package types. write cycle timing chart 1 (/we controlled) t wc t cw t wp t as t wr address (input) /cs (input) /we (input) i/o (input / output) t dh t whz t aw high impe- dance high impe- dance t ow indefinite data out data in indefinite data out t dw cautions 1. /cs or /we should be fixed to high level during address transition. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during the overlap time of a low level /cs and a low level /we. 2. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance. ?
10 m m m m pd444004l data sheet m14427ej3v0ds write cycle timing chart 2 (/cs controlled) t wc t as t cw t aw t wp t wr t dw t dh address (input) /cs (input) /we (input) i/o (input) high impedance data in high impedance cautions 1. /cs or /we should be fixed to high level during address transition. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /cs and a low level /we. ?
11 m m m m pd444004l data sheet m14427ej3v0ds package drawings item millimeters b c d e f g h i j k 21.26 0.2 11.18 0.2 3.5 0.2 2.545 0.2 0.8 min. 10.16 m n 9.4 0.20 0.12 1.27(t.p.) 2.6 0.40 0.10 p 1.005 0.1 0.74 p32le-400a-1 u 0.20 0.1 q t r0.85 + 0.10 - 0.05 note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. 32-pin plastic soj (10.16 mm (400)) 17 16 32 1 s n m q m g e f t u j i h k b cd p s
12 m m m m pd444004l data sheet m14427ej3v0ds note each lead centerline is located within 0.21 mm of its true position (t.p.) at maximum material condition. 32-pin plastic tsop ( ii ) (10.16mm (400)) item millimeters a b c e f g i 21.17 max. 1.27 (t.p.) 1.2 max. 0.97 1.075 max. m n 0.10 10.16 0.1 0.21 0.1 0.05 h 11.76 0.2 d 0.42 j 0.8 0.2 k 0.145 l 0.5 0.1 s32g5-50-7jd2-1 p3 + 7 - 3 + 0.025 - 0.015 + 0.08 - 0.07 m s dm c 32 1 17 16 n b k l j p e f detail of lead end g s a h i
13 m m m m pd444004l data sheet m14427ej3v0ds recommended soldering conditions please consult with our sales offices for soldering conditions of the m pd444004l. types of surface mount device m pd444004lle : 32-pin plastic soj (10.16 mm (400)) m pd444004lg5-7jd : 32-pin plastic tsop (ii) (10.16 mm (400)) (normal bent)
14 m m m m pd444004l data sheet m14427ej3v0ds [memo]
15 m m m m pd444004l data sheet m14427ej3v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd444004l m8e 00. 4 the information in this document is current as of january, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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