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profet ? bts 740 s2 semiconductor group page 1 of 16 2002-sep-30 smart high-side power switch two channels: 2 x 30m ? ? ? ? current sense product summary package operating voltage v bb(on) 5.0...34v active channels one two parallel on-state resistance r on 30m ? 15m ? nominal load current i l(nom) 5.5a 8.5a current limitation i l(scr) 24a 24a general description ? n channel vertical power mosfet with charge pump, ground referenced cmos compatible input, diagnostic feedback and proportional load current sense monolithically integrated in smart sipmos ? technology. ? fully protected by embedded protection functions applications ? c compatible high-side power switch with diagnostic feedback for 12v and 24v grounded loads ? all types of resistive, inductive and capacitve loads ? most suitable for loads with high inrush currents, so as lamps ? replaces electromechanical relays, fuses and discrete circuits basic functions ? cmos compatible input ? undervoltage and overvoltage shutdown with auto-restart and hysteresis ? fast demagnetization of inductive loads ? logic ground independent from load ground protection functions ? short circuit protection ? overload protection ? current limitation ? thermal shutdown ? overvoltage protection (including load dump) with external resistor ? reverse battery protection with external resistor ? loss of ground and loss of v bb protection ? electrostatic discharge protection (esd) diagnostic functions ? proportinal load current sense ? diagnostic feedback with open drain output ? open load detection in off-state with external resistor ? feedback of thermal shutdown in on-state p-dso-20-9 vbb logic channel 1 logic channel 2 in1 st1 is1 in2 st2 is2 gnd load 1 load 2 profet out 1 out 2
profet ? bts 740 s2 semiconductor group page 2 2002-sep-30 functional diagram pin definitions and functions pin symbol function 1,10, 11,12, 15,16, 19,20 v bb positive power supply voltage . design the wiring for the simultaneous max. short circuit currents from channel 1 to 2 and also for low thermal resistance 3in1 input 1,2 , activates channel 1,2 in case of 7 in2 logic high signal 17,18 out1 output 1,2 , protected high-side power output 13,14 out2 of channel 1,2. both pins of each output have to be connected in parallel for operation according ths spec (e.g. k ilis ). design the wiring for the max. short circuit current 4st1 diagnostic feedback 1,2 of channel 1,2, 8 st2 open drain, invers to input level 2 gnd1 ground 1 of chip 1 (channel 1) 6 gnd2 ground 2 of chip 2 (channel 2) 5is1 9is2 sense current output 1,2; proportional to the load current, zero in the case of current limitation of the load current pin configuration (top view) v bb 1 ? 20 v bb gnd1 2 19 v bb in1 3 18 out1 st1 4 17 out1 is1 5 16 v bb gnd2 6 15 v bb in2 7 14 out2 st2 8 13 out2 is2 9 12 v bb v bb 10 11 v bb out1 overvoltage p rotection logic internal volta g e su pp l y esd temperature sensor clamp for inductive load gate control + charge pump current limit open load detection st1 vbb load in1 profet gnd1 control and protection circuit of channel 2 in2 st2 out2 channel 1 current sense gnd2 is2 is1 r o1 gnd1
profet ? bts 740 s2 semiconductor group page 3 2002-sep-30 maximum ratings at t j = 25c unless otherwise specified parameter symbol values unit supply voltage (overvoltage protection see page 4) v bb 43 v supply voltage for full short circuit protection t j,start = -40 ...+150c v bb 34 v load current (short-circuit current, see page 6) i l self-limited a load dump protection 1 ) v loaddump = v a + v s , v a = 13.5 v r i 2 ) = 2 ? , t d = 200 ms; in = low or high, each channel loaded with r l = 7.0 ? , v load dump 3 ) 60 v operating temperature range storage temperature range t j t stg -40 ...+150 -55 ...+150 c power dissipation ( dc ) 4) t a = 25c: (all channels active) t a = 85c: p tot 3.8 2.0 w maximal switchable inductance, single pulse v bb = 12v, t j,start = 150c 4) , i l = 5.5 a, e as = 370 mj, 0 ? one channel: i l = 8.5 a, e as = 790 mj, 0 ? two parallel channels: see diagrams on page 11 z l 18 16 mh electrostatic dischar g e capabilit y ( esd ) in: ( human bod y model ) st, is: out to all other pins shorted: acc. mil-std883d, method 3015.7 and esd assn. std. s5.1-1993 r=1.5k ? ; c=100pf v esd 1.0 4.0 8.0 kv input voltage (dc) v in -10 ... +16 v current through input pin (dc) current through status pin (dc) current through current sense pin (dc) see internal circuit diagram page 10 i in i st i is 2.0 5.0 14 ma thermal characteristics parameter and conditions symbol values unit min typ max thermal resistance junction - soldering point 4),5) each channel: r thjs -- -- 12 k/w j unction - ambient 4) one channel active: all channels active: r thja -- -- 40 33 -- -- 1 ) supply voltages higher than v bb(az) require an external current limit for the gnd and status pins (a 150 ? resistor for the gnd connection is recommended. 2) r i = internal resistance of the load dump test pulse generator 3) v load dump is setup without the dut connected to the generator per iso 7637-1 and din 40839 4 ) device on 50mm*50mm*1.5mm epoxy pcb fr4 with 6cm 2 (one layer, 70 m thick) copper area for v bb connection. pcb is vertical without blown air. see page 16 5 ) soldering point: upper side of solder edge of device pin 15. see page 16
profet ? bts 740 s2 semiconductor group page 4 2002-sep-30 electrical characteristics parameter and conditions, each of the two channels symbol values unit at t j = -40...+150c, v bb = 12 v unless otherwise specified min typ max load switching capabilities and characteristics on-state resistance (v bb to out); i l = 5 a each channel, t j = 25c: t j = 150c: two parallel channels, t j = 25c: r on -- 27 54 14 30 60 15 m ? output voltage drop limitation at small load currents, see page 15 i l = 0.5 a t j =-40...+150c: v on(nl) -- 50 -- mv nominal load current one channel active: two parallel channels active: device on pcb 6 ) , t a = 85c, t j 150c i l(nom) 4.9 7.8 5.5 8.5 -- a output current while gnd disconnected or pulled up; v bb = 30 v, v in = 0, see diagram page 11; (not tested specified by design) i l(gndhigh) -- -- 8 ma turn-on time 7 ) in to 90% v out : turn-off time in to 10% v out : r l = 12 ? t on t off 25 25 70 80 150 200 s slew rate on 7) 10 to 30% v out , r l = 12 ? : d v /dt on 0.1 -- 1 v/ s slew rate off 7) 70 to 40% v out , r l = 12 ? : -d v /dt off 0.1 -- 1 v/ s operating parameters operating voltage 8 ) v bb(on) 5.0 -- 34 v undervoltage shutdown v bb(under) 3.2 -- 5.0 v undervolta g e restart t j =-40...+25c: t j =+150c: v bb(u rst) -- 4.5 5.5 6.0 v undervolta g e restart of char g e pump see dia g ram pa g e 14 t j =-40...+25c: t j =150c: v bb(ucp) -- -- 4.7 -- 6.5 7.0 v undervoltage hysteresis ? v bb(under) = v bb(u rst) - v bb(under) ? v bb(under) -- 0.5 -- v overvoltage shutdown v bb(over) 34 -- 43 v overvoltage restart v bb(o rst) 33 -- -- v 6 ) device on 50mm*50mm*1.5mm epoxy pcb fr4 with 6cm 2 (one layer, 70 m thick) copper area for v bb connection. pcb is vertical without blown air. see page 16 7 ) see timing diagram on page 12. 8) at supply voltage increase up to v bb = 4.7 v typ without charge pump, v out v bb - 2 v
profet ? bts 740 s2 parameter and conditions, each of the two channels symbol values unit at t j = -40...+150 c, v bb = 12 v unless otherwise specified min typ max semiconductor group page 5 2002-sep-30 overvoltage hysteresis ? v bb(over) -- 1 -- v overvolta g e protection 9 ) t j =-40: i bb =40 ma t j =+25...+150 c: v bb(az) 41 43 -- 47 -- 52 v standby current 10 ) t j =-40 c...25 c : v in = 0; see diagram page 10 t j =150 c: i bb(off) -- -- 8 24 30 50 a leakage output current (included in i bb(off) ) v in = 0 i l(off) -- -- 20 a operating current 11) , v in = 5v, i gnd = i gnd1 + i gnd2 , one channel on: two channels on: i gnd -- -- 1.2 2.4 3 6 ma protection functions 12) current limit, (see timing diagrams, page 13) t j =-40 c: t j =25 c: t j =+150 c: i l(lim) 48 40 31 56 50 37 65 58 45 a repetitive short circuit current limit, t j = t jt each channel two parallel channels (see timing diagrams, page 13) i l(scr) -- -- 24 24 -- -- a initial short circuit shutdown time t j,start =25 c: (see timing diagrams on page 13) t off(sc) -- 2.0 -- ms output clamp (inductive load switch off) 13) at v on(cl) = v bb - v out , i l = 40 ma t j =-40 c: t j =25 c...150 c: v on(cl) 41 43 -- 47 -- 52 v thermal overload trip temperature t jt 150 -- -- c thermal hysteresis ? t jt -- 10 -- k 9) supply voltages higher than v bb(az) require an external current limit for the gnd and status pins (a 150 ? resistor in the gnd connection is recommended). see also v on(cl) in table of protection functions and circuit diagram page 10. 10 ) measured with load; for the whole device; all channels off 11 ) add i st , if i st > 0 12 integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as "outside" normal operating range. protection functions are not designed for continuous repetitive operation. 13 ) if channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest v on(cl)
profet ? bts 740 s2 parameter and conditions, each of the two channels symbol values unit at t j = -40...+150 c, v bb = 12 v unless otherwise specified min typ max semiconductor group page 6 2002-sep-30 reverse battery reverse battery voltage 14 ) - v bb -- -- 32 v drain-source diode voltage (v out > v bb ) i l = - 4.0 a, t j = +150 c - v on -- 600 -- mv diagnostic characteristics current sense ratio 15) , static on-condition, v is = 0...5 v, v bb(on) = 6.5 16) ...27v, k ilis = i l / i is t j = -40 c, i l = 5 a: k ilis 4350 4800 5800 t j = -40 c, i l = 0.5 a: 3100 4800 7800 t j = 25...+150 c, i l = 5 a: t j = 25...+150 c, i l = 0.5 a: 4350 3800 4800 4800 5350 6300 current sense output voltage limitation t j = -40 ...+150 c i is = 0, i l = 5 a: v is(lim) 5.4 6.1 6.9 v current sense leakage/offset current t j = -40 ...+150 c v in =0, v is = 0, i l = 0: i is(ll) 0--1 a v in =5 v, v is = 0, i l = 0: i is(lh) 0--15 v in =5 v, v is = 0, v out = 0 (short circuit) ( i is(sh) not tested, specified by design) i is(sh) 0--10 current sense settling time to i is static 10% after positive input slope, i l = 0 5 a (not tested, specified by design) t son(is) -- -- 300 s current sense settling time to 10% of i is static after negative input slope, i l = 5 0 a (not tested, specified by design) t soff(is) -- 30 100 s current sense rise time (60% to 90%) after change of load current i l = 2.5 5 a (not tested, specified by design) t slc(is) -- 10 -- s open load detection voltage 17 ) (off-condition) v out(ol) 234v internal output pull down ( pin 17,18 to 2 resp. 13,14 to 6), v out =5 v r o 51540 k ? 14 ) requires a 150 ? resistor in gnd connection. the reverse load current through the intrinsic drain-source diode has to be limited by the connected load. power dissipation is higher compared to normal operating conditions due to the voltage drop across the drain-source diode. the temperature protection is not active during reverse current operation! input and status currents have to be limited (see max. ratings page 3 and circuit page 10). 15) this range for the current sense ratio refers to all devices. the accuracy of the k ilis can be raised at least by a factor of two by matching the value of k ilis for every single device. in the case of current limitation the sense current i is is zero and the diagnostic feedback potential v st is high. see figure 2c, page 13. 16) valid if v bb(u rst) was exceeded before. 17) external pull up resistor required for open load detection in off state.
profet ? bts 740 s2 parameter and conditions, each of the two channels symbol values unit at t j = -40...+150 c, v bb = 12 v unless otherwise specified min typ max semiconductor group page 7 2002-sep-30 input and status feedback 18 ) input resistance (see circuit page 10) r i 3.0 4.5 7.0 k ? input turn-on threshold voltage v in(t+) -- -- 3.5 v input turn-off threshold voltage v in(t-) 1.5 -- -- v input threshold hysteresis ? v in(t) -- 0.5 -- v off state input current v in = 0.4 v: i in(off) 1--50 a on state input current v in = 5 v: i in(on) 20 50 90 a delay time for status with open load after input neg. slope (see diagram page 14) t d(st ol3) -- 400 -- s status delay after positive input slope (not tested, specified by design) t don(st) -- 13 -- s status delay after negative input slope (not tested, specified by design) t doff(st) -- 1 -- s status output (open drain) zener limit voltage t j =-40...+150 c, i st = +1.6 ma: st low volta g e t j =-40...+25 c, i st = +1.6 ma: t j = +150 c, i st = +1.6 ma: v st(high) v st(low) 5.4 -- -- 6.1 -- -- 6.9 0.4 0.7 v status leakage current, v st = 5 v, t j =25 ... +150 c: i st(high) -- -- 2 a 18) if ground resistors r gnd are used, add the voltage drop across these resistors.
profet ? bts 740 s2 semiconductor group page 8 2002-sep-30 truth table input 1 output 1 status 1 current sense 1 input 2 output 2 status 2 current sense 2 level level level i is normal operation l h l h h l 0 nominal current- limitation l h l h h h 0 0 short circuit to gnd l h l l 19 ) h h 0 0 over- temperature l h l l h h 0 0 short circuit to v bb l h h h l 20 ) l 0 3v typ. under this condition the sense current i is is zero 20) an external short of output to v bb , in the off state, causes an internal current from output to ground. if r gnd is used, an offset voltage at the gnd and st pins will occur and the v st low signal may be errorious. 21 ) low ohmic short to v bb may reduce the output current i l and therefore also the sense current i is . 22 ) power transistor off, high impedance 23 ) with external resistor between v bb and out
profet ? bts 740 s2 semiconductor group page 9 2002-sep-30 terms profet v is1 st1 gnd1 bb v st1 v in1 i st1 i in1 v bb i bb i gnd1 17,18 2 leadframe 3 5 in1 v is1 i is1 v out1 v on1 i l1 out1 4 r gnd1 chip 1 profet v is2 st2 gnd2 bb v st2 v in2 i st2 i in2 i gnd2 13,14 6 leadframe 7 9 in2 v is2 i is2 v out2 v on2 out2 8 i l2 r gnd2 chip 2 leadframe (v bb ) is connected to pin 1,10,11,12,15,16,19,20 external r gnd optional; two resistors r gnd1 , r gnd2 = 150 ? or a single resistor r gnd = 75 ? for reverse battery protection up to the max. operating voltage.
profet ? bts 740 s2 semiconductor group page 10 2002-sep-30 input circuit (esd protection), in1 or in2 in gnd i r esd-zd i i i the use of esd zener diodes as voltage clamp at dc conditions is not recommended. status output, st1 or st2 st gnd esd- zd +5v r st(on) esd-zener diode: 6.1 v typ., max 5.0 ma; r st(on) < 375 ? at 1.6 ma. the use of esd zener diodes as voltage clamp at dc conditions is not recommended. current sense output is gnd is r is i esd-zd is v esd-zener diode: 6.1 v typ., max 14 ma; r is = 1 k ? nominal inductive and overvoltage output clamp, out1 or out2 +v bb out v z v on power gnd v on clamped to v on(cl) = 47 v typ. overvoltage and reverse batt. protection + v bb in is v r gnd gnd r signal gnd logic p ro fet v z2 i r v z1 load gnd load r out st r + 5v st is r v z1 = 6.1 v typ., v z2 = 47 v typ., r gnd = 150 ? , r st =15k ? , r i =4.5k ? typ., r is =1k ? , r v =15k ? , in case of reverse battery the current has to be limited by the load. temperature protection is not active open-load detection out1 or out2 off-state diagnostic condition: v out > 3 v typ.; in low logic st out v out signal gnd r ext r o off v bb
profet ? bts 740 s2 semiconductor group page 11 2002-sep-30 gnd disconnect profet v in st out gnd bb v bb v in v st v gnd any kind of load. in case of in = high is v out v in - v in(t+) . due to v gnd > 0, no v st = low signal available. gnd disconnect with gnd pull up profet v in st out gnd bb v bb v gnd v in v st any kind of load. if v gnd > v in - v in(t+) device stays off due to v gnd > 0, no v st = low signal available. v bb disconnect with energized inductive load profet v in st out gnd bb v bb high for inductive load currents up to the limits defined by z l (max. ratings and diagram on page 11) each switch is protected against loss of v bb . consider at your pcb layout that in the case of vbb dis- connection with energized inductive load all the load current flows through the gnd connection. inductive load switch-off energy dissipation profet v in st out gnd bb = e e e e as bb l r e load r l l { l z energy stored in load inductance: e l = 1 / 2 l i 2 l while demagnetizing load inductance, the energy dissipated in profet is e as = e bb + e l - e r = v on(cl) i l (t) dt, with an approximate solution for r l > 0 ? : e as = i l l 2 r l ( v bb + |v out(cl) |) ln (1+ i l r l |v out(cl) | ) maximum allowable load inductance for a single switch off (one channel) 4) l = f (i l ); t j,start = 150 c, v bb = 12 v, r l = 0 ? z l [mh] 1 10 100 1000 23456789101112 i l [a]
profet ? bts 740 s2 semiconductor group page 12 2002-sep-30 figure 1a: switching a resistive load, change of load current in on-condition: in st out l t v i i is t son(is) tt slc(is) slc(is) load 1 load 2 soff(is) t t don(st) t doff(st) t t on off the sense signal is not valid during settling time after turn or change of load current. figure 1b: v bb turn on: in2 v out1 t v bb st1 open drain in1 v out2 st2 open drain proper turn on under all conditions figure 2a: switching a resistive load, turn-on/off time and slew rate definition: in t v out i l t t on off 90% dv/dton dv/dtoff 10% figure 2b: switching a lamp: in st out l t v i timing diagrams both channels are symmetric and consequently the diagrams are valid for channel 1 and channel 2
profet ? bts 740 s2 semiconductor group page 13 2002-sep-30 figure 2c: switching a lamp with current limit: in st out l t v i i is figure 2d: switching an inductive load in st l t v i out i l(ol) *) if the time constant of load is too large, open-load-status may occur figure 3a: turn on into short circuit: shut down by overtemperature, restart by cooling other channel: normal operation i t st 1 in1 l1 l(scr) i i l(lim) t off(sc) is 1 = 0 heating up of the chip may require several milliseconds, depending on external conditions figure 3b: turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2) t s 1= is 2 = 0 in1/2 l1 l2 l(scr) i 2xi l(lim) i + i t off(sc) s t 1/2 st1 and st2 have to be configured as a 'wired or' function st1/2 with a single pull-up resistor.
profet ? bts 740 s2 semiconductor group page 14 2002-sep-30 figure 4a: overtemperature: reset if t j < t jt st j t t in i l i is figure 5a: open load: detection (with r ext ), turn on/off to open load in st out t v i open load l i is d(st ol3) t figure 6a: undervoltage: in v t bb st v v bb(under) bb(u cp) v i l i is bb(u rst) not defined figure 6b: undervoltage restart of charge pump bb(under) v v bb(u rst) v bb(over) v bb(o rst) v bb(u cp) off- state on-state v on(cl) v bb v on off- state charge pump starts at v bb(ucp) =4.7 v typ.
profet ? bts 740 s2 semiconductor group page 15 2002-sep-30 figure 7a: overvoltage: in v t bb st on(cl) v v bb(over) v bb(o rst) i l i is figure 8a: current sense versus load current 24 :: 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 0123456 i l [a] [ma] i is 24 this range for the current sense ratio refers to all devices. the accuracy of the k ilis can be raised at least by a factor of two by matching the value of k ilis for every single device. figure 8b: current sense ratio: 0 5000 10000 15000 012345678910111213 i l [a] k ilis figure 9a: output voltage drop versus load current: 0.0 0.1 0.2 012345678 i l [a] [v] v on on(nl) v on r
profet ? bts 740 s2 semiconductor group page 16 2002-sep-30 package and ordering code standard: p-dso-20-9 sales code bts 740 l2 ordering code q67060-s7012-a2 all dimensions in millimetres definition of soldering point with temperature t s : upper side of solder edge of device pin 15. p in 15 printed circuit board (fr4, 1.5mm thick, one layer 70 m, 6cm 2 active heatsink area) as a reference for max. power dissipation p tot , nominal load current i l(nom) and thermal resistance r thja published by siemens ag, bereich bauelemente, vertrieb, produkt-information, balanstra ? e 73, d-81541 m nchen siemens ag 2002. all rights reserved as far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for applications, processes and circuits implemented within components or assem- blies. the information describes a type of component and shall not be considered as warranted characteristics. the characteristics for which siemens grants a warranty will only be specified in the purchase contract. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the offices of semiconductor group in germany or the siemens companies and representatives woldwide (see address list). due to technical requirements components may contain dan- gerous substances. for information on the type in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing: please use the recycling operators known to you. we can also help you - get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is re- turned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorised for such purpose! critical components 25 ) of the semiconductor group of siemens ag, may only be used in life supporting devices or systems 26 ) with the express written approval of the semiconductor group of siemens ag. 25) a critical component is a component used in a life-support device or system whose failure can reas onably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 26) life support devices or systems are int ended (a) to be implanted in the human body or (b) support and/or maintain and sustain and/or protect human life. if they fail, it is reasonably to assume that the health of the user or other persons may be endangered.

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