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agilent hcpl-3180 2 amp output current, high speed igbt/mosfet gate drive optocoupler data sheet description this family of devices consists of a gaasp led. the led is optically coupled to an integrated circuit with a power stage. these optocouplers are ideally suited for high frequency driving of power igbt and mosfets used in plasma display panels, high performance dc/dc convertors and motor control invertor applications. ordering information specify part number followed by option number (if desired): example : hcpl-3180- xxx features ? 2 a minimum peak output current 250 khz maximum switching speed high speed response: 200 ns max propagation delay over temperature range 10 kv/us minimum common mode rejection (cmr) at v cm =1500 v under voltage lockout protection (uvlo) with hysteresis wide operating temperature range: -40 c to +100 c wide v cc operating range: 10 v to 20 v 20 ns typ pulse width distortion safety approvals: ul approval pending 3750 v rms for 1 minute. csa approval din en 60747-5-2 approval pending applications plasma display panel (pdp) distributed power architecture (dpa) switch mode rectifier (smr) high performance dc/dc convertor high performance switch mode power supply (smps) high performance uninterruptible power supply (ups) isolated igbt/power mosfet gate drive no option = standard dip package, 50 per tube. 300 = gull wing surface mount option, 50 per tube. 500 = tape and reel packaging option. 060 = din en 60747-5-2 option, viorm=630 vpeak (pending approval) n/c anode cathode n/c v cc v o v ee 1 6 3 4 27 8 5 v o functional diagram a 0.1 uf bypass capacitor must be connected between pins 5 and 8. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage an d/ or degradation which may be induced by esd.
2 hcpl-3180 standard dip package hcpl-3180 gull wing surface mount option 300
3 0 time (seconds) temperature (?c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160?c 140?c 150?c peak temp. 245?c peak temp. 240?c peak temp. 230?c soldering time 200?c preheating time 150?c, 90 + 30 sec. 2.5?c 0.5?c/sec. 3?c + 1?c/?0.5?c tight typical loose room temperature preheating rate 3?c + 1?c/?0.5?c/sec. reflow heating rate 2.5?c 0.5?c/sec. solder reflow temperature profile regulatory information the hcpl-3180 is pending approval by the following organizations: din en 60747-5-2 pending approval under din en-60747-5-2 with v iorm = 630 v peak ul approval under ul 1577, component recognition program up to v iso = 2500 v rms. pending 3750 v rms. csa approval under csa component.
4 din en 60747-5-2 insulation characteristics (hcpl-3180 option 060) * refer to the optocoupler section of the isolation and control components designer?s catalog, under product safety regulations section, (din) for a detailed description of method a and method b partial discharge test profiles. ** refer to the following figure for dependence of p s and i s on ambient temperature. description symbol hcpl-3180 unit installation classification per din en 0110 1997-04 for rated mains voltage 150 vrms i - iv for rated mains voltage 300 vrms i - iii for rated mains voltage 600 vrms i - ii climatic classification 55/100/21 pollution degree (din en 0110 1997 -04) 2 maximum working insulation voltage v iorm 630 vpeak input to output test voltage, method b* viorm x 1.875=vpr, 100% production test withtm=1 sec, partial discharge < 5 pc v pr 1181 vpeak input to output test voltage, method a* viorm x 1.5=vpr, type and sample test, tm=60 sec,partial discharge < 5 pc v pr 945 vpeak highest allowable overvoltage (transient overvoltage tini = 10 sec) v iotm 6000 vpeak safety-limiting values - maximum values allowed in the event of a failure. case temperature t s 175 c input current** i s, input 230 ma output power** p s, output 600 mw insulation resistance at ts, vio = 500 v r s >10 9 w output power ? p s , input current ? i s 0 0 t s ? case temperature ? ?c 200 600 400 25 800 50 75 100 200 150 175 p s (mw) 125 100 300 500 700 i s (ma)
5 insulation and safety related specifications absolute maximum ratings recommended operating conditions parameter symbol hcpl-3180 units conditions minimum external air gap (clearance) l(101) 7.1 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 7.4 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) parameter symbol min max units note storage temperature t s -55 +125 c junction temperature tj -40 +125 c average input current i f(avg) 25 ma 1 peak transient input current (<1s pulse width, 300 pps) i f(tran) 1.0 a reverse input voltage v r 5v "high" peak output current i oh(peak) 2.5 a 2 "low" peak output current i ol(peak) 2.5 a 2 supply voltage v cc - v ee -0.5 25 v output voltage v o(peak) 0v cc v output power dissipation p o 250 mw 3 total power dissipation p t 295 mw 4 lead solder temperature +260 c for 10 sec., 1.6 mm below seating plane solder reflow temperature profile see package outline drawings section parameter symbol min max units note power supply v cc - v ee 10 20 v input current (on) i f(on) 10 16 ma input voltage (off) v f(off) - 3.0 0.8 v operating temperature t a - 40 100 c
6 electrical specifications (dc) over recommended operating conditions unless otherwise specified. parameter symbol min typ max units test conditions fig note high level output current i oh 0.5 a v o = (v cc -4 v) 2, 3 5 2.0 a v o = (v cc -10 v) 17 2 low level output current i ol 0.5 a v o = (v ee +2.5 v) 5, 6 5 2.0 a v o = (v ee + 10 v) 18 2 high level output voltage v oh v cc - 4 v i o = -100 ma 1, 3 19 6, 7 low level output voltage v ol 0.5 v i o = 100 ma 4, 6 20 high level supply current i cch 3.0 6.0 ma output open i f = 10 to 16 ma 7, 8 low level supply current i ccl 3.0 6.0 ma output open vi f = -3.0 to 0.8 v 9, 15, 21 threshold input current low to high i flh 8.0 ma i o = 0 ma v o > 5 v threshold input voltage high to low v fhl 0.8 v i f - 10 ma 16 input forward voltage v f 1.2 1.5 1.8 v temperature coefficient of forward voltage d v f / t a -1.6 mv/c uvlo threshold v uvlo+ 7.9 v v o > 5 v i f = 10 ma 22, 34 v uvlo- 7.4 v uvlo hysteresis uvlo hyst 0.5 v input reverse breakdown voltage bv r 5vi r = 10 ua input capacitance c in 60 pf f = 1 mhz, v f = 0 v ?
7 switching specifications (ac) over recommended operating conditions unless otherwise specified. package characteristics notes: 1. derate linearly above +70 c free air temperature at a rate of 0.3 ma/c. 2. maximum pulse width = 10 us, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 2.0 a. see application section for additional details on limiting i ol peak. 3. derate linearly above +70 c, free air temperature at the rate of 4.8 mw/c. 4. derate linearly above +70 c, free air temperature at the rate of 5.4 mw/c. the maximum led junction temperature should not exceed +125 c. 5. maximum pulse width = 50 us, maximum duty cycle = 0.5%. 6. in this test, v oh is measured with a dc load current. when driving capacitive load v oh will approach v cc as i oh approaches zero amps. 7. maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage > 3000 v rms for 1 second (leakage detection current limit i i-o < 5 ua). 9. device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. t phl propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge o f the v o signal. t plh propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of t he v o signal 11. t psk is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions 12. pwd is defined as |t phl - t plh | for any given device. 13. pin 1 and 4 need to be connected to led common. parameter symbol min typ max units test conditions fig note propagation delay time to high output level t plh 50 150 200 ns i f = 10 ma r g = 10 w f = 250 khz duty cycle = 50% c g = 10 nf 10, 11, 12, 13, 14, 23 16 propagation delay time to low output level t phl 50 150 200 ns pulse width distortion pwd 20 65 ns 12 propagation delay difference between any two parts pdd (t phl - t plh ) -90 90 ms 35, 36 17 rise time t r 25 ns c l = 1 nf r g = 0 w 23 fall time t f 25 ns uvlo turn on delay t uvlo on 2.0 us 22 uvlo turn off delay t uvlo off 0.3 us output high level common mode transient immunity |cm h |10 kv/st a = +25 c i f = 10 to 16 ma v cm = 1.5 kv v cc = 20 v 24 13, 14 output low level common mode transient immunity |cm l |10 kv/st a = +25 c v f = 0 v v cm = 1.5 kv v cc = 20 v v cm = 1.5 kv 13, 15 parameter symbol min typ max units test conditions fig note input-output momentary withstand voltage v iso 2500 v rms t a = +25 c, rh < 50% 8, 9 input-output resistance r i-o 1011 w v i-o = 500 v 9 input-output capacitance c i-o 1pffreq = 1 mhz
8 figure 3. v oh vs i oh figure 4. v ol vs temperature 14. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse v cm to assure that the output will remain in the high state (i.e. v o > 10.0 v). 15. common mode transient immunity in a low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e. v o < 1.0 v). 16. t phl propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge o f the v o signal. t plh propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of t he v o signal 17. the difference between t phl and t plh between any two hcpl-3180 parts under same test conditions. figure 1. v oh vs temperature figure 2. i oh vs temperature -3 -2.5 -2 -1.5 -1 -0.5 0 -40-200 20406080100 t a (v oh -v cc ) - high output voltage drop - v i f =10 to 16ma i out =-100ma v cc =10 to 20v v ee = 0v 0 0.5 1 1.5 2 2.5 -40 10 60 t a i oh - output high current -a i f = 10 to 16ma v out =(v cc -4) v cc =10 to 20v v ee =0v -6 -5 -4 -3 -2 -1 01234 i oh - output high current - a (v oh -v cc ) - output high voltage drop - v 100 c -40 c 25 c i f =10ma to 16ma v cc =10 to 20 v v ee =0v 0 0.05 0.1 0.15 0.2 0.25 0.3 -40-20020406080100 t a - temperature - c v ol - output low voltage - v v f(off) = -3.0 to 0.8v i out = 100ma v cc = 10 to 20v v ee = 0
9 figure 5. i ol vs temperature figure 6. v ol vs i ol figure 7. i cc vs temperature figure 8. i cc vs v cc figure 9. iflh vs temperature figure 10. propagation delay vs v cc 0 0.5 1 1.5 2 2.5 3 -40-200 20406080100 t a i ol - output low current-a v f(off ) = -3.0 to 0.8v v out = 2.5v v cc = 10 to 20v v ee = 0 0 1 2 3 4 00.5 11.5 22.5 i ol - output low current - a v ol - output low voltage - v 25 c 0 c 100 c v f(off) = -3 to 0.8v v cc =10 to 20 v v ee =0v 0 0.5 1 1.5 2 2.5 3 3.5 4 -40-200 20406080100 t a - temperature - oc i cc - supply current - m a icch iccl v cc =20v v ee =0v i f =10ma for i cc h i f =0ma for i cc l 2.5 2.7 2.9 3.1 3.3 3.5 10 12 14 16 18 20 v cc - supply voltage - v i cc - supply current - m a iccl icch i f =10ma for i cc h i f =0ma for i cc l t a =25c v ee =0 v 0 1 2 3 4 5 -40-200 20406080100 t a - temperature - c i flh - low to high current threshold - ma v cc = 10 to 20v v ee = 0v output= open 50 100 150 200 250 10 15 20 25 v cc - supply voltage -v tp - propagation delay - ns tplh tphl i f =10ma t a =25c rg=10ohm cg=10nf duty cycle=50% f=2 50 khz
10 figure 11. propagation delay vs if figure 12. propagation delay vs temperature figure 13. propagation delay vs rg figure 14. propagation delay vs cg figure 15. transfer characteristics figure 16. input current vs forward voltage 50 100 150 200 250 6 8 10 12 14 16 i f - forward led current - ma tp - propagation delay - ns tplh tphl v cc =20v, v ee =0v rg=10 ohm, cg=10nf duty cycle = 50% f=250khz t a =25c 50 100 150 200 250 5 10152025 cg - load capacitance - nf tp - propagation delay -ns tplh tphl i f =10ma t a =25c rg=10ohm duty cycle=50% f=250khz 50 100 150 200 250 -40-200 20406080100 t a - temperature - c tp - propagation delay - ns tphl tplh i f =10ma v cc =20v, v ee =0v rg=10 ohm, cg=10nf duty cycle = 50% f=250khz 0 5 10 15 20 012345 i f - forward led current - ma v o - output voltage - v 50 100 150 200 250 10 20 30 40 50 rg - series load resistance - ohm tp propagation delay - ns tplh tphl i f =10ma t a =25c cg=10nf duty cycle=50% f=250khz i f ? forward current ? ma 1.10 0.001 v f ? forward voltage ? volts 1.60 10 1.0 0.1 1.20 1000 1.30 1.40 1.50 t a = 25?c i f v f + ? 0.01 100
11 figure 17. ioh test circuit figure 18. iol test circuit figure 19. voh test circuit 4v/10v 1 2 3 4 8 7 6 5 shield 0,1 f v cc =10 to 20v + - ioh + - i f =10ma to 16ma 2.5v/10v 1 2 3 4 8 7 6 5 shield 0,1 f v cc =10 to 20v + - iol + - 100ma 1 2 3 4 8 7 6 5 shield 0,1 f v cc =10 to 20v + - v oh i f =10ma to 16ma
12 figure 20. vol test circuit figure 21. iflh test circuit figure 22. uvlo test circuit 1 2 3 4 8 7 6 5 shield 0,1 f + - 100ma vol 1 2 3 4 8 7 6 5 shield 0,1 f v cc =10 to 20v + - v o > 5v if 1 2 3 4 8 7 6 5 shield 0,1 f v cc + - +- v o > 5v i f =10ma
13 figure 23. tplh, tphl, tr and tf test circuit and waveform figure 24. cmr test circuit and waveform 1 2 3 4 8 7 6 5 shield vcc=+20v + - 10 ? ? + - 10nf 250khz 50% duty cycle tr tf 90% 10% 50% tplh tphl vout 1 2 3 4 8 7 6 5 shield 0,1 f + - 500 gnd + - if= 10 to 16ma if 1 2 3 4 8 7 6 5 shield 0,1 f vcc =+20v + - + - 5v 0v vo if + - vcm =1500v vo vo vol voh dt switching at b if=0ma switching at a if=10ma dv/dt= vcm/dt 1 2 3 4 8 7 6 5 shield 0,1 f + - + - vo if + - vcm =1500v vo vo vol voh dt vcm switching at b if=0ma switching at a if=10ma dv/dt= vcm/dt
14 applications information eliminating negative igbt gate drive to keep the igbt firmly off, the hcpl-3180 has a very low maximum v ol specification of 0.4 v. the hcpl-3180 realizes the very low v ol by using a dmos transistor with 1 w (typical) on resistance in its pull down circuit. when the hcpl- 3180 is in the low state, the igbt gate is shorted to the emitter by rg + 1 w. minimizing rg and the lead inductance from the hcpl-3180 to the igbt gate and emitter (possibly by mounting hcpl-3180 on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applications as shown in figure 25. care should be taken with such a pc board design to avoid routing the igbt collector or emitter traces close to the hcpl-3180 input as this can result in unwanted coupling of transient signals into the input of hcpl-3180 and degrade performance. (if the igbt drain must be routed near the hcpl-3180 input, then the led should be reverse biased when in the off state, to prevent the transient signals coupled from the igbt drain from turning on the hcpl- 3180) selecting the gate resistor (r g ) for hcpl-3180 step 1: calculate r g minimum from the i ol peak specification. the igbt and r g in figure 25 can be analyzed as a simple rc circuit with a voltage supplied by the hcpl-3180. ? 5 8 . 2 3 20 i v v r olpeak ol cc g = ? = ? the v ol value of 3 v in the previous equation is the v ol at the peak current of 2 a. (see figure 6). step 2: check the hcpl-3180 power dissipation and increase r g if necessary. the hcpl-3180 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ). () () () f q ; r e v i f q ; r e v i p p p dutycycle v i p p p p g g sw cc cc g g sw cc cc g) o(switchin o(bias) o f f e o e t ? + ? = ? + ? = + = ? ? = + = for the circuit in figure 25 with the circuit in with i f (worst figure 25. recommended led drive and application circuit for hcpl-3180 case) = 16 ma, r g ~ 10 w, max duty cycle = 80%, q g = 100 nc, f = 200 khz and t amax = +75 c: () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = = ? + ? = = ? ? = ) / . * ( @ p mw mw 200khz j . v . p 23mw 0.8 1.8v 16ma p max o o e c mw c mw c ma 8 4 5 250 75 226 260 85 0 20 5 4 the value of 4.5 ma for i cc in the previous equation was obtained by derating the i cc max of 6 ma to i cc max at +75 c. since p o for this case is greater than the p o(max) , rg must be increased to reduce the hcpl- 3180 power dissipation. w khz mw mw mw mw bias max ax switchingm 68 0 200 136 136 90 226 . / f / p e ) ( p ) ( p ) ( p max) o(sitching sw(max) o 0 o = = = = ? = ? = for qg = 100 nc a value of esw = 0.68 uw gives a rg = 15 ohm 1 2 3 4 8 7 6 5 shield 0,1 f v cc =+15v + - rg 270 ? gnd gnd 74xxx open collector +5 v +hvdc - hvdc
15 ld = 442 ?c/w t je t jd lc = 467 ?c/w dc = 126 ?c/w ca = 83 ?c/w* t c t a thermal model (discussion applies to hcpl-3180) the steady state thermal model for the hcpl-3180 is shown in figure 28. the thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. as shown by the model, all heat generated flows through q ca which raises the case temperature t c accordingly. the value of q ca depends on the conditions of the board design and is, therefore, determined by the designer. the value of q ca = +83 c/w was obtained from thermal measurements using a 2.5 x 2.5 inch pc board, with small traces (no ground plane), a single hcpl- 3180 soldered into the center of the board and still air. the absolute maximum power dissipation derating specifications assume a q ca value of +83 c/w from the thermal mode in figure 28 the led and detector ic junction temperatures can be expressed as: a ca lc ld dc d ca ld dc lc dc lc e jd a ca ld dc lc dc lc d ca dc ld lc e je t p p t t p p t + + + + + + + = + + + + + + + = ) ) //( ( * ) * ( * ) * ( * ) //( ( * inserting the values for q lc and q dc shown in figure 28 gives: t je = pe(+256 c/w + q ca )+ pd(+57 c/w + q ca ) + t a t jd = pe(+57 c/w + q ca )+ pd(+111 c/w + q ca ) + t a for example, given p e = 45 mw, p o = 250 mw, t a = +70 c and qca= +83 c/w: t je = pe(+339 c/w + pd(+140 c/w + t a = 45 mw+339 c/w + 250 mw+140 c/w + +70 c = +120 c t jd = pe(+140 c/w + pd+194 c/w + t a = 45 mw+140 c/w + 250 mw+194 c/w + +70 c = +125 c t je and t jd should be limited to +125 c based on the board layout and part placement (qca) specific to the application. tje = led junction temperature tjd = detector ic junction temperature tc = case temperature measured at the center of the package bottom q lc = led-to-case thermal resistance q ld = led-to-detector thermal resistance q dc = detector-to-case thermal resistance q ca = case-to-ambient thermal resistance *q ca will depend on the board design and the placement of the part. figure 27. energy dissipated in the hcpl-3180 for each igbt figure 28. thermal model 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 1020304050 rg(ohm) esw(uj) qg = 100nc
16 led drive circuit considerations for ultra high cmr performance without a detector shield, the dominant cause of optocoupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 29. the hcpl- 3180 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and optocoupler pins 5-8 as shown in figure 30. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or off ) during common mode transients. for example, the recommended application circuit (figure 25), can achieve 10 kv/us cmr while minimizing component complexity. techniques to keep the led in the proper state are discussed in the next two sections. figure 29. optocoupler input to output capacitance model for unshielded optocouplers. vcc= 20v figure 31. equivalent circuit for figure 25 during common mode transient. figure 32. not recommended open collector drive circuit. figure 33. recommended led drive circuit for ultra-high cmr figure 30. optocoupler input to output capacitance model for shielded optocouplers.
17 cmr with the led on (cmr h ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by over-driving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. a minimum led current of 10 ma provides adequate margin over the maximum i flh of 8 ma to achieve 10 kv/us cmr. cmr with the led off (cmr l ) a high cmr led drive circuit must keep the led off (v f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 31, the current flowing through c ledp also flows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) the led will remain off and no common mode failure will occur. the open collector drive circuit, shown in figure 32, cannot keep the led off during a +dv cm /dt transient, since all the current flowing through c ledn must be supplied by the led, and it is not recommended for applications requiring ultra high cmr l performance. figure 33 is an alternative drive circuit, which like the recommended application circuit (figure 25), does achieve ultra high cmr performance by shunting the led in the off state. under voltage lockout feature the hcpl-3180 contains an under voltage lockout (uvlo) feature that is designed to protect the igbt under fault conditions which cause the hcpl-3180 supply voltage (equivalent to the fully charged igbt gate voltage) to drop below a level necessary to keep the igbt in a low resistance state. when the hcpl-3180 output is in the high state and the supply voltage drops below the hcpl- 3180 u vlo- threshold (typ 7.5 v) the optocoupler output will go into the low state. when the hcpl-3180 output is in the low state and the supply voltage rises above the hcpl-3180 v uvlo+ threshold (typ 8.5 v) the optocoupler output will go into the high state (assume led is on). figure 34. under voltage lock out figure 35. minimum led skew for zero dead time ipm dead time and propagation delay specifications the hcpl-3180 includes a propagation delay difference (pdd) specification intended to help designers minimize dead time in their power invertor designs. dead time is the time during which the high and low side power transistors are off. any overlap in q1 and q2 conduction will result in large currents flowing through the power devices from the high voltage to the low-voltage motor rails. 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 (v cc -v ee ) - supply voltage - v vo - output voltage - v
18 to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn off of led1) so that under worst-case conditions, transistor q1 has just turned off when transistor q2 turns on, as shown in figure 35. the amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, pdd max , which is specified to be 90 ns over the operating temperature range of -40 c to +100 c. delaying the led signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in figure 36. the maximum dead time for the hcpl-3180 is 180 ns (= 90 ns-(- 90 ns)) over the operating temperature range of C40 c to +100 c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts. figure 36. waveforms for dead time
www.agilent.com/ semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2003 agilent technologies, inc. august 11, 2003 5988-9921en

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