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sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 1 n patented simultaneous sampling of 2 channels (patent # 5,638,072) n 12 bit resolution n single +5volt supply n internal reference, 1.25v n unipolar 0 to +2.5 volt input range n fast, 7.75 m s conversion time both channels sp8530 s 2 adc? - simultaneous sampling analog to digital converter n fast power shutdown/turn-on mode n 3-wire synchronous serial high speed interface n true differential measurements n 2 m a shutdown mode (10 m w) n low power cmos 60mw typical description the sp8530 is a two channel simultaneous sampling, 12-bit serial out data acquisition system. the device contains a high speed 12-bit analog to digital converter, internal reference, and sample/hold circuitry for both channels. the 8530 is available in 16-pin pdip and soic packages, specified over commercial and industrial temperature ranges. ?-s 2 adc is a trademark of sipex corporation patent pending control logic counter sar dac latched comparator buffer status d out ref. cs sclk v in a v in b offset adjust pd gain adjust ref out rtrim ?
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 2 absolute maximum ratings (ta=+25?c unless otherwise noted) .............................................. vdd to dgnd ............................................................. -0.3v to +7v vda to agnd .............................................................. -0.3v to +7v vin to agnd .................................................... -0.3v to vda +0.3v digital input to vss ........................................... -0.3v to vdd+0.3v digital output to vss ........................................ -0.3v to vdd+0.3v operating temp. range commercial (j,k version) ............................... 0?c to 70?c industrial (a,b version) .............................. -40?c to +85?c storage temperature ............................................... -65?c to 150?c lead temperature(solder 10sec) ........................................ +300?c power dissipation to +70?c ................................................ 500mw derate above 70?c ......................................................... 10mw/ ?c specifications unless otherwise noted the following specifications apply for v dd = 5v with limits applicable for t a = 25 o c. parameter min. typ. max. unit conditions dc accuracy resolution 12 bits integral linearity j, a +0.6 +1 . 0 lsb k ,b +0.4 +0 . 75 lsb differential linearity error j, a +0.5 +1 . 0 lsb no missing codes k ,b +0.5 +1 . 0 lsb no missing codes gain error j, a +0.2 +1.0 %fsr externally trimmable to zero k,b +0.1 +0.5 %fsr externally trimmable to zero offset error j, a +4 +7 lsb externally trimmable to zero k,b +3 +5 lsb externally trimmable to zero gain match j, a +2 lsb k,b +2 lsb offset match j, a +1.0 lsb externally trimmable to zero k,b +0.5 lsb externally trimmable to zero analog input 0 to 2 . 5 volts conversion speed sample time 400 ns conversion time 7 . 75 m s complete cycle 8 . 25 simultaneous convert rate: 121 khz simultaneous pair clock speed 4 mhz data rate: 242 khz total data conversion rate
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 3 specifications (continued) unless otherwise noted the following specifications apply for v dd = 5v with limits applicable for t a = 25 o c. parameter min. typ. max. unit conditions reference output ref. out temp. coef. 1.25 volt.nom. j, a 15 ppm/?c k,b 10 ppm/?c ref.out error +2 +25 mv output current 1 ma digital inputs input low voltage , vil 0 . 8 volt max. vdd = 5v +5% input high voltage , vih 2 . 0 volt min. vdd = 5v +5% input current iin +1 m a input capacitance 3 pf max. digital outputs data format 12-bit serial see timing diagram data coding binary see timing diagram voh 4.0 volt. min. vdd=5v +5%, ioh=-0.4ma vol 0.4 volt max. vdd=5v +5%, iol=-1.6ma ac accuracy fin=47khz,vdd=5.0v @ 25?c, sclk=4mhz spurious free dynamic 83 db range (sfdr) total harmonic distortion (thd) -80 db signal to noise & distortion (sinad) 71 db signal to noise (snr) 72 db sampling dynamics acquisition time to 0.01% 200 ns for a +fs step change at input -3db small signal bw 13 mhz aperture delay 35 ns aperture jitter 150 ps rms aperture delay matching 400 ps power supplies vdd 4.75 5.25 volts
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 4 specifications (continued) unless otherwise noted the following specifications apply for v dd = 5v with limits applicable for t a = 25 o c. parameter min. typ. max. unit conditions power supplies cont. supply current operating mode 11.5 17 ma sd=0, vdd=+5.0v shutdown mode 0.01 2 m a sd=1 power dissipation operating mode 60 85 mw sd=0 shutdown mode .05 10 m w sd=1 power turn on 20 m s via shutdown control to 1 lsb settling error. temperature range commercial 0 to +70 ?c industrial -40 to +85 ?c storage -65 to +150 ?c
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 5 time, thus preserving the relevant temporal information of the applied signals, precisely. this unique feature permits the sp8530 to ideally fit applications where the information content is carried on dual carriers, such as in-phase and quadrature phase systems. further, s 2 adc? architecture permits the sampling of such signals without the necessity of demodulating or further conditioning of the carrier prior to conversion, potentially saving significant amounts of other support electronics. it is also suited to measure instantaneous transfer functions between input signals and their corresponding output signal. such measurements are commonly made in test equipment and pin electronics as well as in many other systems where instantaneous cause and effect relationships are monitored. the sp8530 permits the user to convert each channel and digitally subtract the result in external logic to produce a precise digital differential result. the sp8530 is fabricated in sipex' bipolar enhanced cmos process that permits state-of- the-art design using bipolar devices in the analog/linear section and extremely low power cmos in digital/logic section. circuit operation the operating circuit in figure 1 shows a simple circuit required to operate the sp8530 . the conversion is controlled by the user supplied signal chip select bar (cs) which selects and deselects the device, and a system clock (sclk). a high level applied to cs asynchronously clears the internal logic, puts the sample & hold (cdac) into sample mode and places the dout (data output) pin in a high impedance state. conversion is initiated by falling edge on cs in slave mode at which point the selected input voltages are held and a conversion is started. a delay of 90ns is required between the falling edge of cs and the first rising of sclk. features the sp8530 is a two channel simultaneous sampling, 12-bit serial out data acquisition system. the device contains a high speed 12-bit analog to digital converter, internal reference, and sample and hold circuitry for both channels. the patented, simultaneous sampling feature of this monolithic integrated circuit, permits the user to measure and convert the analog information on each of two channels at the same pin assignments pin 1-n.c.-no connection pin 2-vin b-analog input b pin 3-vin a- analog input a pin 4-agnd-analog ground pin 5-vss-digital ground pin 6-sclk-serial clock input pin 7-dout digital data output pin 8-status- high during conversion pin 9-cs-chip select bar input high deselects chip low selects chip pin 10-sd-shutdown input, logic low power up, logic high = powerdown pin 11-vdd digital +5v supply pin 12-vda analog +5v supply pin 13-offadj-a external offset adjust a pin 14-offadj-b external offset adjust b pin 15-refout-voltage reference output pin 16-gainadj-external gain adjustment 16 15 14 13 12 11 10 9 gain adjust ref out offset adj. b offset adj. a v da v dd pd cs 1 2 3 4 5 6 7 8 n.c. v in b v in a agnd v ss sclk d out status sp8530
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 6 the device responds to the shut down signal asynchronously so that a conversion in progress will be interrupted and the resulting data will be erroneous. a 20 m sec delay is required between the falling edge of power down and initiation of a conversion. layout considerations because of the high resolution and linearity of the sp8530 system design considerations such as ground path impedance and contact resistance become very important. to avoid introducing distortion when driving the analog inputs of these devices, the source resistance must be very low, or constant with signal level. note that in the operating circuit there is no connection made between vda (pin 12) and the system power supply. this is because the analog supply pin (vda) is connected internally to the digital supply pin (vdd) through a ten ohm resistor. this connection when combined with parallel combination of 6.8 m f tantalum and 0.1 m f ceramic capacitor between vda and analog ground, will provide some immunity to noise which resides on the system supply. to maintain maximum system accuracy, the supply connected to the vdd pin should be well isolated from digital supplies and wide load variations. to limit effects of digital switching elsewhere in a system, it often makes sense to run a separate +5v supply conductor from the supply regulator to any analog components requiring +5v including the sp8530 . noise on the power data format 32 bits of data are sent for each conversion. the first 16 bits are the conversion a result, which is shipped with 4 leading "0"s, and then 12 bits of data, msb first. the second 16 bits are the conversion b result, which are also shipped with 4 leading "0"s, and then 12 bits of data, msb first. data changes on the falling edge of sclk and is stable on the rising edge of sclk. continuous stand alone operation is obtained by holding cs low. in this mode an oscillator is connected directly to sclk pin. the sclk signal along with the status output signal are used to synchronize the host system with the converter's data. in this mode there is a single dead sclk cycle between the 32nd clock of one conversion and the first clock of the following conversion for the sp8530 . a clock frequency of 4 mhz the sp8530 provides a throughput rate of 121khz. in slave mode operation, cs is brought high on each conversion so that all conversions are initiated by falling edge on cs. figure 1. operating circuit 16 15 14 13 12 11 10 9 gain adjust ref out offset adj. b offset adj. a v da v dd shutdown cs 1 2 3 4 5 6 7 8 n.c. v in b v in a agnd v ss sclk d out status sp8530 v a +5v clock in data out status out chip select shutdown 0.1? 2kohms 5kohms 10kohms 2kohms 5kohms 0.01?* 6.8? 0.1? v b * optional filter capacitor is helpful in a noisy pc board application.
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 7 supply lines can degrade the converters performance, especially corrupting are noise and spikes from a switching power supply. the ground pins (agnd and vss) on the sp8530 are separated internally and should be connected to each other under the converter. applying the technique of using separate analog and digital ground planes is usually the best way to preserve dynamic performance and reduce noise coupling into sensitive converter circuits. where any compromise must be made the common return of the analog input signal should be referenced to the agnd pin of the converter. this prevents any voltage drops that might occur in the power supply's common return from appearing in series with the input signal. coupling between analog and digital lines should be minimized by careful layout. for instance, if analog and digital lines must cross they should do so at right angles. parallel analog and digital lines should be separated from each other by a trace connected to common. if external gain and offset potentiometers are used, the potentiometers and related resistors should be located as close to the sp8530 as possible. minimizing glitches coupling of external transients into an analog to digital converter can cause errors which are difficult to debug. in addition to the above discussions on layout considerations, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance from a system using the sp8530 converters. these potential system problem sources are particularly important to consider when developing a new system, and looking for causes of errors in breadboards. first, care should be taken to avoid transients during critical times in the sampling and conversion process. since the sp8530 has a internal sample/hold function, the signal that puts the device into hold state (cs going low) is critical, as it would be on any sample/hold amplifier. the cs falling edge should have a 5 to 10 ns transition time, low jitter, and have minimal ringing, especially during the first 20ns after it falls. layout considerations (cont.)
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 8 timing characteristics (typical @ 25 c with v dd = +5v, unless otherwise noted) parameter min. typ. max .unit cond. thoughput time (ttp=ta+tc) 8.25 m s acquisition time (ta) (2 sclk periods) 400 500 ns conversion time (tc) (31 sclk periods) 7.75 m s sclk low pulse width (tskl) 110 125 ns sclk high pulse width (tskh) 110 125 ns sclk period (tskt) 250 ns buss access time (tcba) 51 ns buss relinquish time (tbr) 45 ns setup time -sclk falling to csn falling (tcssu) 0 ns csn low before sclk rises (tcs) 90 ns sclk falling to data valid (tsd) 50 ns csn falling to status rising (tdcs) 69 ns sclk 33 falling to status rising free run (tdss) 70 ns sclk32 falling to status falling ( tdse) 45 ns delay sd low to initiate conversion (tpu) 5 m s aperture delay slave-mode (tapc) 30 ns aperture delay free-running mode (taps) 35 ns
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 9 timing diagrams slave mode free running mode sclk cs status data sd 31 32 tcssu x tcs b0 tbr acquire ta hi-z 1 2 3 45 tskl tskh tdcs tcba "0" tapc convert tc tsd a11 b1 b0 tdse hi-z acquire 31 32 x tpu tskt 1 23 45 a11 "0" "0" sclk cs status 32 33 tdse t aps 31 b0 aquire 32 33 31 1 tdss data tsd b1 b0 "0" convert ta tc acquire
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 10 d alternate end pins (both ends) d1 = 0.005" min. (0.127 min.) e package: plastic dual?n?ine (narrow) dimensions (inches) minimum/maximum (mm) a = 0.210" max. (5.334 max). e1 c l a2 a1 = 0.015" min. (0.381min.) b b1 e = 0.100 bsc (2.540 bsc) e a = 0.300 bsc (7.620 bsc) a2 b b1 c d e e1 l 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.735/0.775 (18.669/19.685) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.355/0.400 (9.017/10.160) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 22?in 8?in 14?in 16?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.145/1.155 (29.083/29.337) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.780/0.800 (19.812/20.320) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 18?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.880/0.920 (22.352/23.368) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 20?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.980/1.060 (24.892/26.924) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15?
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 11 d eh package: plastic small outline (soic) dimensions (inches) minimum/maximum (mm) 14?in a a1 l b e a a1 b d e e h l 16?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.398/0.413 (10.10/10.49) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8 (0?8? 18?in 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.447/0.463 (11.35/11.74) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8 (0?8? 20?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.496/0.512 (12.60/13.00) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc)) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8 (0?8? 24?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.599/0.614 (15.20/15.59) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8 (0?8? 28?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.697/0.713 (17.70/18.09) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8 (0?8? 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.348/0.363 (8.83/9.22) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8 (0?8?
sp8530ds/01 sp8530 s 2 adc tm - simultaneous sampling analog to digital converter ? copyright 2000 sipex corporation 12 ordering information model segment model ..................................................... inl linearity (lsb) ....... temperature range ............................................... package types sp8530jn ........................................................... 1.0 ........................... 0?c to +70?c .......................................... 16-pin, 0.3" plastic dip sp8530js ........................................................... 1.0 ........................... 0?c to +70?c .................................................... 16-pin, 0.3" soic sp8530kn ......................................................... 0.75 .......................... 0?c to +70?c .......................................... 16-pin, 0.3" plastic dip sp8530ks ......................................................... 0.75 .......................... 0?c to +70?c .................................................... 16-pin, 0.3" soic sp8530an .......................................................... 1.0 ......................... -40?c to +85?c ........................................ 16-pin, 0.3" plastic dip sp8530as .......................................................... 1.0 ......................... -40?c to +85?c .................................................. 16-pin, 0.3" soic sp8530bn ......................................................... 0.75 ........................ -40?c to +85?c ........................................ 16-pin, 0.3" plastic dip sp8530bs ......................................................... 0.75 ........................ -40?c to +85?c .................................................. 16-pin, 0.3" soic please consult the factory for pricing and availability on a tape-on-reel option. corporation signal processing excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. sipex corporation headquarters and sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600

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