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26 23 20 17 14 11 8 5 frequency (hz) 0.1m 1m 10m 100m 1g f ?db differential to single-ended frequency response gain (db) triple wideband, current-feedback operational amplifier with disable opa3681 features l wideband +5v operation: 225mhz (g = +2) l unity gain stable: 280mhz (g = 1) l high output current: 150ma l output voltage swing: 4.0v l high slew rate: 2100v/ m s l low supply current: 6ma/ch l low disabled current: 300 m a/ch l improved high frequency pinout applications l rgb amplifiers l wideband ina l broadband video buffers l high speed imaging channels l portable instruments l adc buffers l active filters l cable drivers description the opa3681 sets a new level of performance for broadband triple current-feedback op amps. operating on a very low 6ma/ch supply current, the opa3681 offers a slew rate and output power normally associated with a much higher supply current. a new output stage architecture delivers a high output current with minimal voltage headroom and crossover distor- tion. this gives exceptional single-supply operation. using a single +5v supply, the opa3681 can deliver a 1v to 4v output swing with over 100ma drive current and 150mhz bandwidth. this combination of features makes the opa3681 an ideal rgb line driver or single-supply adc input driver. the opa3681s low 6ma/ch supply current is precisely trimmed at 25 c. this trim, along with low drift over temperature, guarantees lower guaranteed maximum supply current than competing products. system power may be further reduced by using the optional disable control pin. leaving this disable pin open, or holding it high, gives normal operation. if pulled low, the opa3681 supply current drops to less than 300 m a/ch while the output goes into a high impedance state. this feature may be used for power savings or for video mux applications. ? 1999 burr-brown corporation pds-1452b printed in u.s.a. september, 1999 tm opa3681 related products singles duals triples voltage feedback opa680 opa2680 opa3680 current feedback opa681 opa2681 opa3681 fixed gain opa682 opa2682 opa3682 opa3681 opa3681 66.5 w high speed ina (>120mhz) 499 w 499 w 301 w 301 w 1/3 opa3681 1/3 opa3681 1/3 opa3681 v 1 10 (v 1 ?v 2 ) v 2 +5 ? +5 ? +5 ? 250 w 250 w international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 for most current data sheet and other product information, visit www.burr-brown.com sbos095
2 opa3681 specifications: v s = 5v r f = 499 w , r l = 100 w , and g = +2 , (figure 1 for ac performance only), unless otherwise noted. opa3681e, u typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c (2) 70 c (3) +85 c (3) units max level (1) ac performance (figure 1) small signal bandwidth (v o = 0.5vp-p) g = +1, r f = 549 w 280 mhz typ c g = +2, r f = 499 w 220 220 210 190 mhz min b g = +5, r f = 365 w 185 mhz typ c g = +10, r f = 182 w 125 mhz typ c bandwidth for 0.1db gain flatness g = +2, v o = 0.5vp-p 90 50 45 45 mhz min b peaking at a gain of +1 r f = 453, v o = 0.5vp-p 0.4 2 4 db max b large signal bandwidth g = +2, v o = 5vp-p 150 mhz typ c slew rate g = +2, 4v step 2100 1600 1600 1200 v/ m s min b rise/fall time g = +2, v o = 0.5v step 1.7 ns typ c g = +2, 5v step 2.0 ns typ c settling time to 0.02% g = +2, v o = 2v step 12 ns typ c 0.1% g = +2, v o = 2v step 8 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd harmonic r l = 100 w C75 dbc typ c r l 3 500 w C81 dbc typ c 3rd harmonic r l = 100 w C80 dbc typ c r l 3 500 w C95 dbc typ c input voltage noise f > 1mhz 2.2 3.0 3.4 3.6 nv/ ? hz max b non-inverting input current noise f > 1mhz 12 14 15 15 pa/ ? hz max b inverting input current noise f > 1mhz 15 18 18 19 pa/ ? hz max b differential gain g = +2, ntsc, v o = 1.4vp, r l = 150 w 0.001 % typ c r l = 37.5 w 0.005 % typ c differential phase g = +2, ntsc, v o = 1.4vp, r l = 150 w 0.01 deg typ c r l = 37.5 w 0.05 deg typ c crosstalk input referred, f = 5mhz, all hostile C55 dbc typ c dc performance (4) open-loop transimpedance gain (z ol ) v o = 0v, r l = 100 w 100 56 56 56 k w min a input offset voltage v cm = 0v 1.3 5 6.5 7.5 mv max a average offset voltage drift v cm = 0v +35 +40 m v/ c max b non-inverting input bias current v cm = 0v +30 +55 65 85 m a max a average non-inverting input bias current drift v cm = 0v C400 C450 na/ c max b inverting input bias current v cm = 0v 10 40 50 55 m a max a average inverting input bias current drift v cm = 0v C125 C150 na /c max b input common-mode input range (5) 3.5 3.4 3.3 3.2 v min a common-mode rejection (cmr) v cm = 0v 52 47 46 45 db min a non-inverting input impedance 100 || 2 k w || pf typ c inverting input resistance (r i ) open loop 42 w typ c output voltage output swing no load 4.0 3.8 3.7 3.6 v min a r l = 100 w 3.9 3.7 3.6 3.3 v min a current output, sourcing v o = 0 +190 +160 +140 +80 ma min a current output, sinking v o = 0 C150 C135 C130 C80 ma min a closed-loop output impedance g = +2, f = 100khz 0.03 w typ c disable (disabled low) power down supply current (+v s )v dis = 0, all channels C900 m a typ c disable time 100 ns typ c enable time 25 ns typ c off isolation g = +2, 5mhz 70 db typ c output capacitance in disable 4 pf typ c turn on glitch g = +2, r l = 150 w , v in = 0 50 mv typ c turn off glitch g = +2, r l = 150 w , v in = 0 20 mv typ c enable voltage 3.3 3.5 3.6 3.7 v min a disable voltage 1.8 1.7 1.6 1.5 v max a control pin input bias current (dis) v dis = 0, each channel 100 160 160 160 m a max a power supply specified operating voltage 5 v typ c maximum operating voltage range 6 6 6 v max a max quiescent current (3 channels) v s = 5v 18 19.2 19.5 19.8 ma max a min quiescent current (3 channels) v s = 5v 18 16.8 16.5 15.0 ma min a power supply rejection ratio (Cpsrr) input referred 58 52 50 49 db min a temperature range specification: e, u C40 to +85 c typ c thermal resistance, q ja e ssop-16 100 c/w typ c u so-16 100 c/w typ c notes: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (2) junction temperature = ambient for 25 c guaranteed specifications. (3) junction temperature = ambient at low temperature limit: junction temperature = ambient +23 c at high temperature limit for over temperature guaranteed specifications. (4) current is considered positive out of node. v cm is the input common-mode voltage. (5) tested < 3db below minimum specified cmr at cmir limits.
3 opa3681 specifications: v s = +5v r f = 499 w , r l = 100 w to v s /2, g = +2 , (figure 2 for ac performance only), unless otherwise noted. opa3681e, u typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c (2) 70 c (3) +85 c (3) units max level (1) ac performance (figure 2) small signal bandwidth (v o = 0.5vp-p) g = +1, r f = 549 w 250 mhz typ c g = +2, r f = 499 w 225 180 140 110 mhz min b g = +5, r f = 365 w 180 mhz typ c g = +10, r f = 182 w 165 mhz typ c bandwidth for 0.1db gain flatness g = +2, v o < 0.5vp-p 100 50 35 23 mhz min b peaking at a gain of +1 r f = 649 w , v o < 0.5vp-p 0.4 2 4 db max b large signal bandwidth g = +2, v o = 2vp-p 200 mhz typ c slew rate g = +2, 2v step 830 700 680 570 v/ m s min b rise/fall time g = +2, v o = 0.5v step 1.5 ns typ c g = +2, v o = 2v step 2.0 ns typ c settling time to 0.02% g = +2, v o = 2v step 14 ns typ c 0.1% g = +2, v o = 2v step 9 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd harmonic r l = 100 w to v s / 2 C75 dbc typ c r l 3 500 w to v s /2 C79 dbc typ c 3rd harmonic r l = 100 w to v s / 2 C68 dbc typ c r l 3 500 w to v s /2 C70 dbc typ c input voltage noise f > 1mhz 2.2 3 3.4 3.6 nv/ ? hz max b non-inverting input current noise f > 1mhz 12 14 14 15 pa/ ? hz max b inverting input current noise f > 1mhz 15 18 18 19 pa/ ? hz max b dc performance (4) open-loop transimpedance gain (z ol ) v o = v s /2, r l = 100 w to v s /2 100 60 53 51 k w min a input offset voltage v cm = 2.5v 1 5 6.0 7 mv max a average offset voltage drift v cm = 2.5v +15 +20 m v/ c max b non-inverting input bias current v cm = 2.5v +40 +65 +75 +95 m a max a average non-inverting input bias current drift v cm = 2.5v C300 C350 na/ c max b inverting input bias current v cm = 2.5v 5 20 25 35 m a max a average inverting input bias current drift v cm = 2.5v C125 C175 na / c max b input least positive input voltage (5) 1.5 1.6 1.7 1.8 v max a most positive input voltage (5) 3.5 3.4 3.3 3.2 v min a common-mode rejection (cmr) v cm = v s /2 51 45 44 44 db min a non-inverting input impedance 100 || 2 k w || pf typ c inverting input resistance (r i ) open loop 44 w typ c output most positive output voltage no load 4 3.8 3.7 3.5 v min a r l = 100 w , 2.5v 3.9 3.7 3.6 3.4 v min a least positive output voltage no load 1 1.2 1.3 1.5 v max a r l = 100 w , 2.5v 1.1 1.3 1.4 1.6 v max a current output, sourcing v o = v s /2 150 110 110 60 ma min a current output, sinking v o = v s /2 C110 C75 C70 C50 ma min a closed-loop output impedance g = +2, f = 100khz 0.03 w typ c disable (disable low) power down supply current (+v s )v dis = 0, all channels C750 m a typ c disable time 100 ns typ c enable time 25 ns typ c off isolation g = +2, 5mhz 65 db typ c output capacitance in disable 4 pf typ c turn on glitch g = +2, r l = 150 w , v in = v s /2 50 mv typ c turn off glitch g = +2, r l = 150 w , v in = v s /2 20 mv typ c enable voltage 3.3 3.5 3.6 3.7 v min a disable voltage 1.8 1.7 1.6 1.5 v max a control pin input bias current (dis) v dis = 0, each channel 100 m a typ c power supply specified single supply operating voltage 5 v typ c maximum single supply operating voltage 12 12 12 v max a max quiescent current (3 channels) v s = +5v 14.4 15.9 16.2 16.2 ma max a min quiescent current (3 channels) v s = +5v 14.4 12.3 11.1 10.8 ma min a power supply rejection ratio (+psrr) input referred 48 db typ c temperature range specification: e, u C40 to +85 c typ c thermal resistance, q ja e ssop-16 100 c/w typ c u so-16 100 c/w typ c notes: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (2) junction temperature = ambient for 25 c guaranteed specifications. (3) junction temperature = ambient at low temperature limit: junction temperature = ambient +23 c at high temperature limit for over temperature guaranteed specifications. (4) current is considered positive out of node. v cm is the input common-mode voltage. (5) tested < 3db below minimum specified cmr at cmir limits.
4 opa3681 power supply .............................................................................. 6.5vdc internal power dissipation (1) ............................ see thermal information differential input voltage .................................................................. 1.2v input voltage range ............................................................................ v s storage temperature range: e, u ................................ C40 c to +125 c lead temperature (soldering, 10s) .............................................. +300 c junction temperature (t j ) ........................................................... +175 c note:: (1) packages must be derated based on specified q ja . maximum t j must be observed. absolute maximum ratings electrostatic discharge sensitivity electrostatic discharge can cause damage ranging from perfor- mance degradation to complete device failure. burr-brown corpo- ration recommends that all integrated circuits be handled and stored using appropriate esd protection methods. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. pin configuration top view ssop-16 , so-16 package specified drawing temperature package ordering transport product package number (1) range marking number media opa3681e ssop-16 surface mount 322 C40 c to +85 c opa3681e opa3681e/250 tape and reel """"" opa3681e/2k5 tape and reel opa3681u so-16 surface mount 265 C40 c to +85 c opa3681u opa3681u rails """"" opa3681u/2k5 tape and reel notes: (1) for detailed drawing and dimension table, please see end of data sheet. (2) models with a slash (/) are available on ly in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 devices per reel). ordering 2500 pieces of opa3681e/2k5 will get a single 2500-piece tap e and reel. package/ordering information 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ?n a +in a dis b ?n b +in b dis c ?n c +in c dis a +v s out a ? s out b +v s out c ? s opa3681
5 opa3681 typical performance curves: v s = 5v g = +2, r f = 499 w , and r l = 100 w , unless otherwise noted (see figure 1). 2 1 0 ? ? ? ? ? ? ? ? frequency (25mhz/div) 0 250mhz 125mhz small-signal frequency response normalized gain (1db/div) g = +10, r f = 182 w g = +5, r f = 365 w g = +1, r f = 549 w v o = 0.5vp-p g = +2, r f = 499 w 8 7 6 5 4 3 2 1 0 ? ? frequency (25mhz/div) 0 250mhz 125mhz large-signal frequency response gain (1db/div) 2vp-p g = +2, r l = 100 w 1vp-p 4vp-p 7vp-p 400 300 200 100 0 ?00 ?00 ?00 ?00 small-signal pulse response time (5ns/div) output voltage (100mv/div) g = +2 v o = 0.5vp-p +4 +3 +2 +1 0 ? ? ? ? large-signal pulse response time (5ns/div) output voltage (1v/div) g = +2 v o = 5vp-p 5.0 4.0 2.0 0 2.0 1.6 1.2 0.8 0.4 0 large-signal disable/enable response time (50ns/div) output voltage (400mv/div) 6.0 4.0 2.0 0 v dis (2v/div) v dis output voltage g = +2 v in = +1v all hostile crosstalk ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 frequency (mhz) 0.3 10 100 1 300 crosstalk (db)
6 opa3681 typical performance curves: v s = 5v (cont.) g = +2, r f = 499 w , and r l = 100 w , unless otherwise noted (see figure 1). ?0 ?5 ?0 ?5 ?0 ?5 ?0 5mhz 2nd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 2nd harmonic distortion (dbc) r l = 200 w r l = 500 w r l = 100 w 5mhz 3rd harmonic distortion vs output voltage 3rd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 1 0.1 5 output voltage (vp-p) r l = 200 w r l = 500 w r l = 100 w 10mhz 2nd harmonic distortion vs output voltage 2nd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 1 0.1 5 output voltage (vp-p) r l = 200 w r l = 500 w r l = 100 w 10mhz 3rd harmonic distortion vs output voltage 3rd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 1 0.1 5 output voltage (vp-p) r l = 200 w r l = 500 w r l = 100 w 20mhz 2nd harmonic distortion vs output voltage 2nd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 1 0.1 5 output voltage (vp-p) r l = 200 w r l = 500 w r l = 100 w 20mhz 3rd harmonic distortion vs output voltage 3rd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 1 0.1 5 output voltage (vp-p) r l = 200 w r l = 500 w r l = 100 w
7 opa3681 typical performance curves: v s = 5v (cont.) g = +2, r f = 499 w , and r l = 100 w , unless otherwise noted (see figure 1). 100 10 1 input voltage and current noise density frequency (hz) 100 1k 10k 100k 1m 10m current noise (pa/ ? hz) voltage noise (nv/ ? hz) non-inverting input current noise inverting input current noise 12.2pa/ ? hz 15.1pa/ ? hz voltage noise 2.2nv/ ? hz ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 two-tone, 3rd-order intermodulation spurious single-tone load power (dbm) 86420246810 3rd-order spurious level (dbc) dbc = db below carriers 50mhz 20mhz 10mhz load power at matched 50 w load 60 50 40 30 20 10 0 recommended r s vs capacitive load capacitive load (pf) 1 10 100 r s ( w ) 15 12 9 6 3 0 ? ? ? ?2 ?5 frequency (30mhz/div) 0 300mhz 150mhz frequency response vs capacitive load gain to capacitive load (3db/div) r s v in v o c l 1k w 499 w 499 w 1k w is optional. c l = 22pf c l = 10pf c l = 47pf c l = 100pf 3rd harmonic distortion vs frequency 3rd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 10 1 0.1 20 frequency (mhz) v o = 2vp-p r l = 100 w g = +2, r f = 499 w g = +5, r f = 365 w g = +10, r f = 182 w ?0 ?0 ?0 ?0 ?0 ?0 frequency (mhz) 0.1 1 10 20 2nd harmonic distortion (dbc) v o = 2vp-p r l = 100 w g = +2, r f = 402 w g = +10, r f = 180 w g = +5, r f = 261 w 2nd harmonic distortion vs frequency
8 opa3681 typical performance curves: v s = 5v (cont.) g = +2, r f = 499 w , and r l = 100 w , unless otherwise noted (see figure 1). 70 65 60 55 50 45 40 35 30 25 20 frequency (hz) 10 2 10 3 10 4 10 5 10 6 10 7 10 8 cmr and psr vs frequency rejection ratio (db) +psr ?sr cmr 120 100 80 60 40 20 0 open-loop transimpedance gain/phase frequency (hz) 10 4 10 5 10 6 10 7 10 8 10 9 transimpedance gain (20db w /div) 0 ?0 ?0 ?20 ?60 ?00 ?40 transimpedance phase (40 /div) |z ol | e z ol 0.05 0.04 0.03 0.02 0.01 0 number of 150 w loads 1234 composite video dg/dp positive video negative sync dp dg dg/dp (%/ ) 5 4 3 2 1 0 ? ? ? ? ? typical dc drift over temperature ambient temperature ( c) ?0 ?0 v io 0 20 40 60 80 100 120 140 input offset voltage (mv) 50 40 30 20 10 0 ?0 ?0 ?0 ?0 ?0 input bias currents ( a) non-inverting input bias current inverting 5 4 3 2 1 0 ? ? ? ? ? output voltage and current limitations i o (ma) ?00 ?00 ?00 0 100 200 300 v o (volts) 100 w load line 50 w load line 25 w load line output current limited 1w internal power limit 1-channel only 1w internal power limit output current limit 10 7.5 5 2.5 0 200 150 100 50 0 supply and output current vs temperature ambient temperature ( c) ?0 ?0 0 20 40 60 80 100 120 140 supply current (ma) output current (ma) quiescent supply current sourcing output current sinking output current
9 opa3681 typical performance curves: v s = +5v g = +2, r f = 499 w , and r l = 100 w , unless otherwise noted (see figure 1). 2 1 0 ? ? ? ? ? ? ? ? frequency (25mhz/div) 0 250 125 small-signal frequency response normalized gain (1db/div) g = +2, r f = 499 w v o = 0.5vp-p g = +10, r f = 182 w g = +5, r f = 365 w g = +1, r f = 549 w 8 7 6 5 4 3 2 1 0 ? ? frequency (25mhz/div) 0 250 125 large-signal frequency response gain (1db/div) g = +2 r l = 100 w to 2.5v v o = 0.5vp-p v o = 1vp-p v o = 2vp-p 2.10 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 small-signal pulse response time (5ns/div) output voltage (100mv/div) g = +2 v o = 0.5vp-p 4.5 4.1 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 0.5 large-signal pulse response time (5ns/div) output voltage (400mv/div) g = +2 v o = 2vp-p 70 60 50 40 30 20 10 0 recommended r s vs capacitive load capacitive load (pf) 1 10 100 r s ( w ) 15 12 9 6 3 0 ? ? ? ?2 ?5 frequency response vs capacitive load frequency (20mhz/div) 0 200mhz 100mhz gain to capacitive load (3db/div) c l = 22pf c l = 10pf c l = 47pf c l = 100pf 499 w 499 w 57.6 w 806 w 806 w 1k w v i +5v 0.1 f v o r s c l 0.1 f 0.1 f
10 opa3681 typical performance curves: v s = +5v (cont.) g = +2, r f = 499 w , and r l = 100 w , unless otherwise noted (see figure 1). 10 1 0.1 0.01 closed-loop output impedance frequency (hz) 10k 100m 100k 1m 10m output impedance ( w ) 499 w +5 1/3 opa3681 ? 499 w 50 w z o ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 single-tone load power (dbm) ?4 ?2 ?0 ? ? ? ? 0 2 two-tone, 3rd-order spurious level 3rd-order spurious (dbc) 50mhz dbc = db below carrier load power at matched 50 w load 20mhz 10mhz 2nd harmonic distortion vs frequency 2nd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 10 1 0.1 20 frequency (mhz) v o = 2vp-p r l = 100 w g = +2, r f = 499 w g = +5, r f = 365 w g = +10, r f = 182 w 3rd harmonic distortion vs frequency 3rd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 10 1 0.1 20 frequency (mhz) v o = 2vp-p r l = 100 w g = +2, r f = 499 w g = +5, r f = 365 w g = +10, r f = 182 w 2nd harmonic distortion vs frequency 2nd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 10 1 0.1 20 frequency (mhz) v o = 2vp-p g = +2 r l = 200 w r l = 500 w r l = 100 w 3rd harmonic distortion vs frequency 3rd harmonic distortion (dbc) ?0 ?0 ?0 ?0 ?0 10 1 0.1 20 frequency (mhz) v o = 2vp-p g = +2 r l = 200 w r l = 500 w r l = 100 w
11 opa3681 applications information wideband current-feedback operation the opa3681 gives the exceptional ac performance of a wideband current-feedback op amp with a highly linear, high power output stage. requiring only 6ma/ch quiescent current, the opa3681 will swing to within 1v of either supply rail and deliver in excess of 135ma guaranteed at room temperature. this low output headroom requirement, along with supply voltage independent biasing, gives re- markable single (+5v) supply operation. the opa3681 will deliver greater than 200mhz bandwidth driving a 2vp-p output into 100 w on a single +5v supply. previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. the opa3681 achieves a comparable power gain with much better linearity. the primary advantage of a current- feedback op amp over a voltage-feedback op amp is that ac performance (bandwidth and distortion) is relatively inde- pendent of signal gain. figure 1 shows the dc-coupled, gain of +2, dual power supply circuit configuration used as the basis of the 5v specifications and typical performance curves. for test purposes, the input impedance is set to 50 w with a resistor to ground and the output impedance is set to 50 w with a series output resistor. voltage swings reported in the speci- fications are taken directly at the input and output pins while load powers (dbm) are defined at a matched 50 w load. for the circuit of figure 1, the total effective load will be 100 w || 998 w . the disable control line (dis) is typically left open to guarantee normal amplifier operation. one optional com- ponent is included in figure 1. in addition to the usual power supply de-coupling capacitors to ground, a 0.1 m f capacitor is included between the two power supply pins. in practical pc board layouts, this optionally added capacitor will typi- cally improve the 2nd harmonic distortion performance by 3db to 6db. figure 2 shows the ac-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5v specifica- tions and typical performance curves. though not a rail- to-rail design, the opa3681 requires minimal input and output voltage headroom compared to other very wideband current-feedback op amps. it will deliver a 3vp-p output swing on a single +5v supply with greater than 150mhz bandwidth. the key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. the circuit of figure 2 establishes an input midpoint bias using a simple resistive divider from the +5v supply (two 806 w resistors). the input signal is then ac-coupled into this midpoint voltage bias. the input voltage can swing to within 1.5v of either supply pin, giving a 2vp-p input signal range centered between the supply pins. the input impedance matching resistor (57.6 w ) used for testing is adjusted to give a 50 w input match when the parallel combination of the biasing divider network is included. the gain resistor (r g ) is ac-coupled, giving the circuit a dc gain of +1, which puts the input dc bias voltage (2.5v) on the output as well. again, on a single +5v supply, the output voltage can swing to within 1v of either supply pin while delivering more than 75ma output current. a demanding 100 w load to a midpoint bias is used in this characterization circuit. the new output stage used in the opa3681 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5v supply, 3rd harmonic distortion plots. 1/3 opa3681 +5v + dis ?v 50 w load 50 w 50 w v o v i 50 w source r g 499 w r f 499 w + 6.8 f 0.1 f 6.8 f 0.1 f 0.1 f +v s ? s figure 1. dc-coupled, g = +2, bipolar supply, specifi- cation and test circuit. figure 2. ac-coupled, g = +2, single supply, specifica- tion and test circuit. 1/3 opa3681 +5v +v s dis v s /2 806 w 100 w v o v i 57.6 w 806 w r f 499 w r g 499 w 0.1 f 0.1 f 6.8 f + 0.1 f
12 opa3681 triple adc buffer channel the opax681 family is ideally suited to single supply, wideband adc driving. a current feedback op amp is ideal where high gains with high bandwidths are required. the wide 3vp-p output swing with over 150mhz full power bandwidth on a single +5v supply is well suited to the 2vp-p input range commonly required from modern cmos pipelined adcs. three channels of very high speed digitizer channels are shown in figure 3 using the opa3681 driving three ads831s (8-bit, 80msps cmos converters). each input is ac-coupled into a 50 w gain resistor that also will act as a 50 w impedance match at high frequencies. the amplifiers inputs and outputs are centered on the adc common-mode input voltage by tying each converters v cm to the non-inverting inputs of the amplifier. this v cm acts as the swing midpoint for the input to the converter. since the ads831 can operate with differential inputs, driving into the in input will give a net non-inverting signal channel even with the amplifiers operating at an inverting gain of C6. the other input to the ads831 is tied to this v cm as well to give an input signal midpoint equal to v cm . the 300 w feedback resistor will be the output load in this configura- tion. harmonic distortion for the opa3681 will not degrade the converters sfdr performance in this application. wideband rgb multiplexer the opa3681 is ideally suited to implementing a simple, very wideband, 2x1 rgb multiplexer. this simple wired- or video multiplexer can be easily implemented using the circuit shown in figure 4. this circuit uses two opa3681s where each package ac- cepts the three rgb component video signals from one of two possible sources. each non-inverting input is terminated figure 3. adc driver. figure 4. wideband 2x1 rgb multiplexer. 1/3 opa3681 22 w 300 w 50 w 0.1 f 300 w 0.1 f 47pf v 1 ads831 8-bit 80msps in v cm in 1/3 opa3681 22 w 300 w 50 w 0.1 f 300 w 0.1 f 47pf v 1 ads831 8-bit 80msps in v cm in 1/3 opa3681 22 w 300 w 50 w 0.1 f 300 w 0.1 f 47pf v 1 ads831 8-bit 80msps in v cm in +5v power supply de-coupling not shown 1/3 opa3681 340 w 402 w 75 w 82.5 w v out red 75 w line r1 +5v +5v ?v 1/3 opa3681 340 w 402 w 75 w 82.5 w v out green 75 w line g1 1/3 opa3681 340 w 402 w 75 w 82.5 w v out blue 75 w line b1 1/3 opa3681 340 w 402 w 75 w 82.5 w r2 +5v ?v 1/3 opa3681 340 w 402 w 75 w 82.5 w g2 1/3 opa3681 340 w 402 w 75 w 82.5 w b2 v dis u1 u2 power supply de-coupling not shown
13 opa3681 in 75 w to match the typical video source impedance. the disable control is used to switch between channels by feed- ing a logic control line directly to all three v dis inputs on one package, and its complement to the three v dis inputs on the other. since the disable feature is intentionally make- before-break (to ensure that the output does not float in transition), each of the two possible outputs for the three rgb lines are combined through a limiting resistor. this 82.5 w resistor limits the current between the two outputs during switching. each output will have a disabled channel. the feedback and output network connected on the output slightly attenuates the signal going out onto the 75 w cable. the gain and output matching resistors (82.5 w ) have been slightly increased to get a signal gain of +1 to the matched load and provide a 75 w output impedance to the cable. the section on disable operation shows the turn-on and turn-off switching glitches, using a grounded input for the single channel, is typically less than 50mv. where two outputs are switched (shown in figure 4), the output line is always under the control of one amplifier or the other due to the make-before-break disable timing. in this case, the switch- ing glitches for 0v inputs drops to < 20mv. video dac reconstruction filter wideband current-feedback op amps make ideal elements for implementing high-speed active filters where the ampli- fier is used as fixed gain block inside a passive rc circuit network. their relatively constant bandwidth versus gain, provides low interaction between the actual filter poles and the required gain for the amplifier. figure 5 shows an example of a video dac reconstruction filter. the delay-equalized filter in figure 5 compensates for the dacs sin(x)/x response, and minimizes aliasing artifacts. it is designed for single +5v operation, with a 13.5msps dac sampling rate, and a 5.5mhz cutoff frequency. the first op amp buffers the video dac output and the first filter section from each other. this first filter section pro- vides group delay equalization. the second and third filter sections provide a 6th-order lowpass filter response that also compensates for the dacs sin(x)/x response. the filter response can be seen in figure 6. figure 5. filter schematic. figure 6. dac reconstruction filter response. high power xdsl line driver emerging broadband access technologies are making sig- nificant demands on the output stage drivers. some of the higher frequency versions, particularly in vdsl, require passive bandpass filters to spectrally isolate the upstream from downstream frequency bands. figure 7 shows one possible implementation of this using single-ended filters and giving differential push/pull drive into a transformer. the dac output from the analog front end (afe) typically requires isolation from the complex filter impedance. the first stage provides a tunable gain (using r g ) with a fixed 412 w 243 w 82.5 w 499 w 100pf 56pf 220pf +5v 402 w 237 w 97.6 w 499 w 1/3 opa3681 100pf 56pf 220pf +5v 75.5 w 1/3 opa3681 499 w 100 f 953 w +5v 1/3 opa3681 953 w 499 w 499 w 120pf 100 f v o video in +5v 20 10 0 ?0 ?0 ?0 ?0 ?0 0 1 10 100 frequency (mhz) (db) f ?db
14 opa3681 termination for the dac, r t . it is very useful from a distortion standpoint to scale the characteristic impedance up for the filter. this reduces the loading at the first stage amplifier output, typically improving 3rd-order terms di- rectly, as well as some improvement in 2nd-order terms. figure 7 assumes a 100 w characteristic impedance for the filter. the filter is driven from a 100 w source resistor into a 100 w load that is formed by the input gain resistor of the inverting amplifier channel. the other non-inverting input is isolated by a series 50 w resistorprincipally to isolate that input from the out-of-band source impedance of the filter. in this example, the output stage is set up for a differential gain of 8. the total gain from the output of the bandpass filter to the line will be 4 ? n, where n is the turns ratio used in the transformer. very broad bandwidths at high power levels are possible using the opa3681 in the circuit of figure 7. recognize also, that the output is in fact bandlimited by the filter. very high dynamic range is possible inside the filter bandwidth due to the significant performance margin pro- vided by the opa3681. wideband differential amplifier the differential amplifier (three amplifier instrumentation topology) on the front page of this data sheet shows a common application applied to this triple current feedback op amp. the two input stage amplifiers are configured for a relatively high differential gain of 10. lowering the feed- back resistor values in this input stage provides > 120mhz bandwidth, even at this high gain setting. the signal is applied to the high impedance, non-inverting inputs at the input stage. the differential gain is set by (1 + 2r f /r g ) = 10 using the values shown on the front page. the third amplifier performs the differential-to-single-ended conversion in a standard single op amp differential stage. this differential stage, built using the 3rd wideband current-feedback op amp, in the opa3681 will give lower cmrr at dc than using a voltage feedback part, but higher cmrr at higher frequencies. measured performance, with no resistor value tuning, gave approximately 75db at dc and > 55db cmrr (input referred) through 10mhz. to maintain good distor- tion performance for the input stage amplifiers, the loading at each output has been matched while achieving the gain of 1 and differential characteristic of the output stage. to improve dc cmrr, tune the resistor to ground at the non- inverting input of the output stage amplifier. wideband programmable gain by tying all three inputs together from a single source, and all three outputs together to drive a common load, a very wideband, programmable gain function may be implemented. figure 8 shows an example of this application where the three channels have been set up for gains of 2, 4, and 8 to their output pins. when driving a doubly-terminated 50 w load, this gives a user-selectable gain of 1, 2 and 4 to the matched load. the feedback resistor value has been opti- mized for maximum flat bandwidth in each channel. this will give an almost constant > 200mhz bandwidth at any of the three gain settings. the desired gain is selected by using the disable control lines to choose one of the three possible amplifiers as the active channel. an additional 10 w resistor was included inside the loop on each output stage to limit output stage currents if more than one output is on during gain select transition. this will reduce the maximum avail- able output voltage swing into the 100 w total load shown in figure 8 to approximately 3.2v, but will provide surge current protection during channel switching. the 20 w series resistors on each non-inverting input serves to isolate the input parasitic capacitance from the source. figure 7. single-to-differential xdsl line driver. 1/3 opa3681 50 w r s r s 1:n 1/3 opa3681 400 w 400 w 100 w bandpass filter 133 w 1/3 opa3681 100 w r g r t dsl afe 400 w +5v ?v supply de-coupling not shown
15 opa3681 operating suggestions setting resistor values to optimize bandwidth a current-feedback op amp like the opa3681 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values. this is shown in the typical performance curves; the small signal bandwidth decreases only slightly with increasing gain. these curves also show that the feedback resistor has been changed for each gain setting. the resistor values on the inverting side of the circuit for a current feedback op amp can be treated as frequency response compensation elements while their ratios set the signal gain. figure 9 shows the small-signal frequency response analysis circuit for the opa3681. the key elements of this current-feedback op amp model are: a ? buffer gain from the non-inverting input to the inverting input r i ? buffer output impedance i err ? feedback error current signal z(s) ? frequency dependent open loop transimpedance gain from i err to v o the buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. it will, however, set the cmrr for a single op amp differential amplifier configuration. for a buffer gain a < 1.0, the cmrr = C20 ? log (1C a ) db. r i , the buffer output impedance, is a critical portion of the bandwidth control equation. the opa3681 is typically 42 w . 1/3 opa3681 10 w 20 w 499 w 499 w g = +2 1/3 opa3681 10 w 20 w 140 w 422 w g = +4 1/3 opa3681 10 w 20 w 35.7 w 249 w g = +8 74hc238 50 w 50 w load ?v +5v power supply de-coupling not shown v in +5v d 1 d 2 y 0 y 1 y 2 50 w figure 9. current feedback transfer function analysis circuit. figure 8. wideband programmable gain. r f v o r g r i z (s) i err i err a v i
16 opa3681 a current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. the typical performance curves show this open-loop transimpedance response. this is analogous to the open-loop voltage gain curve for a voltage-feedback op amp. developing the transfer function for the circuit of figure 9 gives equation 1: this is written in a loop gain analysis format where the errors arising from a non-infinite open-loop gain are shown in the denominator. if z(s) were infinite over all frequencies, the denominator of equation 1 would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. the fraction in the denominator of equation 1 determines the frequency response. equation 2 shows this as the loop gain equation: if 20 ? log (r f + ng ? r i ) were drawn on top of the open- loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. eventually, z(s) rolls off to equal the denominator of equation 2 at which point the loop gain has reduced to 1 (and the curves have intersected). this point of equality is where the amplifiers closed-loop frequency response, given by equa- tion 1, will start to roll off and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage-feedback op amp. the difference here is that the total impedance in the denominator of equation 2 may be controlled somewhat separately from the desired signal gain (or ng). the opa3681 is internally compensated to give a maxi- mally flat frequency response for r f = 499 w at ng = 2 on 5v supplies. evaluating the denominator of equation 2 (which is the feedback transimpedance) gives an optimal target of 589 w . as the signal gain changes, the contribution of the ng ? r i term in the feedback transimpedance will change, but the total can be held constant by adjusting r f . equation 3 gives an approximate equation for optimum r f over signal gain: as the desired signal gain increases, this equation will eventually predict a negative r f . a somewhat subjective limit to this adjustment can also be set by holding r g to a minimum value of 20 w . lower values will load both the buffer stage at the input and the output stage if r f gets too lowactually decreasing the bandwidth. figure 10 shows the recommended r f vs ng for both 5v and a single +5v operation. the values shown in figure 10 give a good starting point for design where bandwidth optimization is desired. the total impedance going into the inverting input may be used to adjust the closed-loop signal bandwidth. inserting a series resistor between the inverting input and the summing junction will increase the feedback impedance (denominator of equation 2), decreasing the bandwidth. the internal buffer output impedance for the opa3681 is slightly influ- enced by the source impedance looking out of the non- inverting input terminal. high source resistors will have the effect of increasing r i , decreasing the bandwidth. for those single-supply applications which develop a midpoint bias at the non-inverting input through high valued resistors, the decoupling capacitor is essential for power supply ripple rejection, non-inverting input noise current shunting, and to minimize the high frequency value for r i in figure 9. inverting amplifier operation since the opa3681 is a general purpose, wideband current- feedback op amp, most of the familiar op amp application circuits are available to the designer. those triple op amp applications that require considerable flexibility in the feed- back element (e.g., integrators, transimpedance, some fil- ters) should consider the unity gain stable voltage-feedback opa2680, since the feedback resistor is the compensation element for a current feedback op amp. wideband inverting operation (especially summing) is particularly suited to the opa3681. figure 11 shows a typical inverting configuration where the i/o impedances and signal gain from figure 1 are retained in an inverting circuit configuration. 600 500 400 300 200 100 0 noise gain 020 10 15 5 feedback resistor vs noise gain feedback resistor ( w ) +5v 5v figure 10. recommended feedback resistor vs noise gain. v v r r rr r r z ng rrng z o i f g fi f g s fi s = + ? ? ? ? + ++ ? ? ? ? = + + a a 1 1 1 1 () () ng r r f g o+ ? ? ? ? ? ? 1 eq. 1 eq. 2 z rrng loop gain s fi () + = eq. 3 rngr fi = 589 w
17 opa3681 in the inverting configuration, two key design consider- ations must be noted. the first is that the gain resistor (r g ) becomes part of the signal channel input impedance. if input impedance matching is desired (which is beneficial when- ever the signal is coupled through a cable, twisted pair, long pc board trace or other transmission line conductor), it is normally necessary to add an additional matching resistor to ground. r g by itself is normally not set to the required input impedance since its value, along with the desired gain, will determine a r f which may be non-optimal from a frequency response standpoint. the total input impedance for the source becomes the parallel combination of r g and r m . the second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and will have slight effect on the bandwidth through equation 1. the values shown in figure 11 have accounted for this by slightly decreasing r f (from figure 1) to re-optimize the bandwidth for the noise gain of figure 11 (ng = 2.82) in the example of figure 11, the r m value combines in parallel with the external 50 w source impedance, yielding an effective driving impedance of 50 w || 64 w = 28.1 w . this impedance is added in series with r g for calculating the noise gainwhich gives ng = 2.82. this value, along with the r f of figure 10 and the inverting input impedance of 45 w , are inserted into equation 3 to get a feedback transimpedance nearly equal to the 589 w opti- mum value. note that the non-inverting input in this bipolar supply inverting application is connected directly to ground. it is often suggested that an additional resistor be connected to ground on the non-inverting input to achieve bias current error cancellation at the output. the input bias currents for a current feedback op amp are not generally matched in either magnitude or polarity. connecting a resistor to ground on the non-inverting input of the opa3681 in the circuit of figure 11 will actually provide additional gain for that inputs bias and noise currents, but will not decrease the output dc error since the input bias currents are not matched. output current and voltage the opa3681 provides output voltage and current capabili- ties that are unsurpassed in a low cost dual monolithic op amp. under no-load conditions at 25 c, the output voltage typically swings closer than 1v to either supply rail; the guaranteed swing limit is within 1.2v of either rail. into a 15 w load (the minimum tested load), it is guaranteed to deliver more than 135ma. the specifications described above, though familiar in the industry, consider voltage and current limits separately. in many applications, it is the voltage ? current, or v-i product, which is more relevant to circuit operation. refer to the output voltage and current limitations plot in the typi- cal performance curves. the x and y axes of this graph show the zero-voltage output current limit and the zero- current output voltage limit, respectively. the four quad- rants give a more detailed view of the opa3681s output drive capabilities, noting that the graph is bounded by a safe operating area of 1w maximum internal power dissipation. superimposing resistor load lines onto the plot shows that the opa3681 can drive 2.5v into 25 w or 3.5v into 50 w without exceeding the output capabilities or the 1w dissipation limit. a 100 w load line (the standard test circuit load) shows the full 3.9v output swing capability, as shown in the specifications table. the minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. only at cold startup will the output current and voltage decrease to the numbers shown in the guaranteed tables. as the output transistors deliver power, their junction temperatures will increase, decreasing their v be s (increasing the available output voltage swing) and increasing their current gains (increasing the available out- put current). in steady state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. to maintain maximum output stage linearity, no output short-circuit protection is provided. this will not normally be a problem since most applications include a series match- ing resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. however, shorting the output pin directly to the adjacent positive power supply pins will, in most cases, destroy the amplifier. if additional short-circuit protection is required, consider a small series resistor in the power supply leads. under heavy output loads, this will reduce the available output voltage swing. a 5 w series resistor in each power supply lead will limit the internal power dissipation to less than 1w for an output short circuit while decreasing the available output voltage swing only 0.5v for up to 100ma desired load currents. always place the 0.1 m f power supply decoupling capacitors after these supply current-limiting resistors directly on the supply pins. 1/3 opa3681 r f 464 w r g 226 w dis +5v ?v 50 w 50 w load v o power supply de-coupling not shown v i 50 w source r m 64.9 w figure 11. inverting gain of C2 with impedance matching.
18 opa3681 driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an a/d converterincluding additional external capacitance which may be recommended to improve a/d linearity. a high speed, high open-loop gain amplifier like the opa3681 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. when the amplifiers open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. several external solutions to this problem have been suggested. when the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the sim- plest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. this does not eliminate the pole from the loop re- sponse, but rather shifts it and adds a zero at a higher frequency. the additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. the typical performance curves show the recommended r s vs capacitive load and the resulting frequency response at the load. parasitic capacitive loads greater than 2pf can begin to degrade the performance of the opa3681. long pc board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. always consider this effect carefully, and add the recommended series resistor as close as possible to the opa3681 output pin (see board layout guidelines). distortion performance the opa3681 provides good distortion performance into a 100 w load on 5v supplies. relative to alternative solu- tions, it provides exceptional performance into lighter loads and/or operating on a single +5v supply. generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the distortion with a negligible 3rd harmonic component. focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. remember that the total load includes the feedback network; in the non-inverting configuration (figure 1), this is the sum of r f + r g , while in the inverting configuration it is just r f . also, providing an additional supply decoupling capacitor (0.1 m f) between the supply pins (for bipolar operation) improves the 2nd-order distor- tion slightly (3db to 6db). in most op amps, increasing the output voltage swing in- creases harmonic distortion directly. the typical performance curves show the 2nd harmonic increasing at a little less than the expected 2x rate while the 3rd harmonic increases at a little less than the expected 3x rate. where the test power doubles, the difference between it and the 2nd harmonic decreases less than the expected 6db while the difference between it and the 3rd decreases by less than the expected 12db. this also shows up in the 2-tone, 3rd-order intermodulation spurious (im3) response curves. the 3rd- order spurious levels are extremely low at low output power levels. the output stage continues to hold them low even as the fundamental power reaches very high levels. as the typical performance curves show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. as the fundamental power level increases, the dynamic range does not decrease signifi- cantly. for 2 tones centered at 20mhz, with 10dbm/tone into a matched 50 w load (i.e., 2vp-p for each tone at the load, which requires 8vp-p for the overall 2-tone envelope at the output pin), the typical performance curves show 62dbc difference between the test tone power and the 3rd-order intermodulation spurious levels. this exceptional perfor- mance improves further when operating at lower frequencies. noise performance wideband current feedback op amps generally have a higher output noise than comparable voltage-feedback op amps. the opa3681 offers an excellent balance between voltage and current noise terms to achieve low output noise. the inverting current noise (15pa/ ? hz) is significantly lower than earlier solutions while the input voltage noise (2.2nv/ ? hz) is lower than most unity gain stable, wideband, voltage feedback op amps. this low input voltage noise was achieved at the price of higher non-inverting input current noise (12pa/ ? hz). as long as the ac source impedance looking out of the non-inverting node is less than 100 w , this current noise will not contribute significantly to the total output noise. the op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. figure 12 shows the op amp noise analysis model with all the noise terms included. in this model, all noise terms are taken to be noise voltage or current density terms in either nv/ ? hz or pa/ ? hz. 4kt r g r g r f r s 1/3 opa3681 i bi e o i bn 4kt = 1.6e ?0j at 290 k e rs e ni 4ktr s ? 4ktr f ? figure 12. op amp noise analysis model.
19 opa3681 the total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. equation 4 shows the general form for the output noise voltage using the terms shown in figure 12. dividing this expression by the noise gain (ng = (1+r f /r g )) will give the equivalent input referred spot noise voltage at the non-inverting input as shown in equation 5. evaluating these two equations for the opa3681 circuit and component values shown in figure 1 will give a total output spot noise voltage of 8.4nv/ ? hz and a total equivalent input spot noise voltage of 4.2nv/ ? hz. this total input-referred spot noise voltage is higher than the 2.2nv/ ? hz specifica- tion for the op amp voltage noise alone. this reflects the noise added to the output by the inverting current noise times the feedback resistor. if the feedback resistor is reduced in high gain configurations (as suggested previously), the total input-referred voltage noise given by equation 5 will ap- proach just the 2.2nv/ ? hz of the op amp itself. for example, going to a gain of +10 using r f = 182 w will give a total input referred noise of 2.4nv/ ? hz. dc accuracy and offset control a current-feedback op amp like the opa3681 provides exceptional bandwidth in high gains, giving fast pulse set- tling but only moderate dc accuracy. the specifications table shows an input offset voltage comparable to high- speed, voltage-feedback amplifiers. however, the two input bias currents are somewhat higher and are unmatched. whereas bias current cancellation techniques are very effec- tive with most voltage-feedback op amps, they do not generally reduce the output dc offset for wideband current- feedback op amps. since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. evaluating the configuration of figure 1, using worst-case +25 c input offset voltage and the two input bias currents, gives a worst- case output offset range equal to: (ng ? v os(max) ) + (i bn ? r s /2 ? ng) (i bi ? r f ) where ng = non-inverting signal gain = (2 ? 5.0mv) + (55 m a ? 25 w ? 2) (499 w ? 40 m a) = 10mv + 2.75mv 20mv = C27.25mv ? +32.75mv in normal operation, base current to q1 is provided through the 110k w resistor while the emitter current through the 15k w resistor sets up a voltage drop that is inadequate to turn on the two diodes in q1s emitter. as v dis is pulled low, additional current is pulled through the 15k w resistor eventually turning on these two diodes ( ? 100 m a). at this point, any further current pulled out of v dis goes through those diodes holding the emitter-base voltage of q1 at approximately zero volts. this shuts off the collector current out of q1, turning the amplifier off. the supply current in the disable mode is that only required to operate the circuit of figure 13. additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). when disabled, the output and input nodes go to a high impedance state. if the opa3681 is operating in a gain of +1, this will show a very high impedance (4pf || 1m w ) at the output and exceptional signal isolation. if operating at a gain greater than +1, the total feedback network resistance (r f + r g ) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. if configured as an inverting ampli- fier, the input and output will be connected through the feedback network resistance (r f + r g ) giving relatively poor input to output isolation. one key parameter in disable operation is the output glitch when switching in and out of the disable mode. figure 14 shows these glitches for the circuit of figure 1 with the input signal set to zero volts. the glitch waveform at the output pin is plotted along with the dis pin voltage. 25k w 110k w 15k w i s control ? s +v s v dis q1 disable operation the opa3681 provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. if the dis control pin is left unconnected, the opa3681 will operate normally. to disable, the control pin must be asserted low. figure 13 shows a simplified internal circuit for the disable control feature. figure 13. simplified disable control circuit. e e i r ktr ng i r ktr ng onibns s bif f =+ () + () + () + 2 2 2 2 44 eq. 4 e e i r ktr ir ng ktr ng nnibns s bi f f =+ () ++ ? ? ? + 2 2 2 4 4 eq. 5
20 opa3681 the transition edge rate (dv/dt) of the dis control line will influence this glitch. for the plot of figure 14, the edge rate was reduced until no further reduction in glitch amplitude was observed. this approximately 1v/ns maximum slew rate may be achieved by adding a simple rc filter into the v dis pin from a higher speed logic line. if extremely fast transition logic is used, a 2k w series resistor between the logic gate and the v dis input pin will provide adequate bandlimiting using just the parasitic input capacitance on the v dis pin while still ensuring adequate logic level swing. thermal analysis due to the high output power capability of the opa3681, heatsinking or forced airflow may be required under extreme operating conditions. maximum desired junction tempera- ture will set the maximum allowed internal power dissipa- tion as described below. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d ? q ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipation in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). under this condition, p dl = v s 2 /(4 ? r l ) where r l includes feedback network loading. note that it is the power in the output stage and not into the load that determines internal power dissipation. as a worst-case example, compute the maximum t j using an opa3681 so-16 (in the circuit of figure 1), operating at the maximum specified ambient temperature of +85 c with all three outputs driving a grounded 20 w load to +2.5v: p d = 10v ? 19.2ma + 3 ? [5 2 /(4 ? (20 w || 998 w ))] = 1.15w maximum t j = +85 c + (1.15 ? 100 c/w) = 200 c this absolute worst-case condition exceeds specified maxi- mum junction temperature. normally this extreme case will not be encountered. careful attention to internal power dissipation is required and perhaps airflow considered under extreme conditions. board layout guidelines achieving optimum performance with a high frequency amplifier like the opa3681 requires careful attention to board layout parasitics and external component types. rec- ommendations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability: on the non- inverting input, it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted ca- pacitance, a window around the signal i/o pins should be opened in all of the ground and power planes around those pins. otherwise, ground and power planes should be unbro- ken elsewhere on the board. b) minimize the distance (< 0.25") from the power supply pins to high frequency 0.1 m f decoupling capacitors. at the device pins, the ground and power plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. the power supply connections (on pins 4 and 7) should always be decoupled with these capacitors. an optional supply de-coupling ca- pacitor across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. larger (2.2 m f to 6.8 m f) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board. c) careful selection and placement of external compo- nents will preserve the high frequency performance of the opa3681. resistors should be a very low reactance type. surface-mount resistors work best and allow a tighter overall layout. metal-film and carbon composition, axially leaded resistors can also provide good high frequency per- formance. again, keep their leads and pc board trace length as short as possible. never use wirewound type resistors in a high frequency application. since the output pin and inverting input pin are the most sensitive to parasitic capaci- tance, always position the feedback and series output resis- tor, if any, as close as possible to the output pin. other network components, such as non-inverting input termina- tion resistors, should also be placed close to the package. where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. the frequency response is primarily determined by the feedback resistor value as described previously. increasing its value will reduce the bandwidth, while decreasing it will give a more peaked frequency response. the 499 w feedback resistor used in the typical performance specifications at a gain of +2 on 5v supplies is a good starting point for design. note that a 549 w feedback resistor, rather than a direct short, is recommended for the unity gain follower application. a current feedback op amp requires a feedback resistor even in the unity gain follower configuration to control stability. 40 20 0 ?0 ?0 time (20ns/div) output voltage (20mv/div) output voltage (0v input) v dis 0.2v 4.8v figure 14. disable/enable glitch.
21 opa3681 d) connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the plot of recommended r s vs capacitive load. low parasitic capacitive loads (< 5pf) may not need an r s since the opa3681 is nominally compensated to operate with a 2pf parasitic load. if a long trace is required, and the 6db signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout tech- niques). a 50 w environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion vs load plots. with a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the opa3681 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. the high output voltage and current capa- bility of the opa3681 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. if the 6db attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of r s vs capacitive load. this will not preserve signal integrity as well as a doubly-terminated line. if the input impedance of the desti- nation device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) socketing a high speed part like the opa3681 is not recommended. the additional lead length and pin-to-pin capacitance introduced by the socket can create an ex- tremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa3681 onto the board. input and esd protection the opa3681 is built using a very high speed complemen- tary bipolar process. the internal junction breakdown volt- ages are relatively low for these very small geometry de- vices. these breakdowns are reflected in the absolute maxi- mum ratings table. all device pins have limited esd protection using internal diodes to the power supplies as shown in figure 15. these diodes provide moderate protection to input overdrive voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g., in systems with 15v supply parts driving into the opa3681), current limiting series resistors should be added into the two inputs. keep these resistor values as low as possible since high values degrade both noise performance and frequency response. design-in tools applications support the burr-brown applications department is available for design assistance at phone number 1-800-548-6132 (us/canada only). the burr-brown internet web page (http://www.burr-brown.com) has the latest data sheets and other design aids. demonstration boards a pc board will be available to assist in the initial evaluation of circuit performance of the opa3681. this is available as an unpopulated pcb with descriptive documentation. see the demonstration board literature for more information. the summary information for this board is shown below: check the burr-brown web site for availability of these boards. spice models computer simulation of circuit performance using spice is often useful when analyzing the performance of analog circuits and systems. this is particularly true for high speed active devices, like the opa3681, where parasitic capaci- tance and inductance can have a major effect on frequency response. spice models will be available through the burr-brown web page or on a disk (call our applications department). these models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. they do not do as well in predicting the har- monic distortion or differential gain and phase characteris- tics. these models do not distinguish between the ac performance of different package types. literature demonstration request product package board number opa3681e ssop-16 dem-opa368xe mkt-354 opa3681u so-16 dem-opa368xu mkt-364 figure 15. internal esd protection. external pin +v cc ? cc internal circuitry
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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