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wideband, current feedback operational amplifier with disable tm description the opa681 sets a new level of performance for broadband current feedback op amps. operating on a very low 6ma supply current, the opa681 offers a slew rate and output power normally associated with a much higher supply cur- rent. a new output stage architecture delivers a high output current with minimal voltage headroom and crossover distortion. this gives exceptional single-supply operation. using a single +5v supply, the opa681 can deliver a 1v to 4v output swing with over 100ma drive current and 150mhz bandwidth. this combination of features makes the opa681 an ideal rgb line driver or single-supply adc input driver. the opa681? low 6ma supply current is precisely trimmed at 25 c. this trim, along with low drift over temperature, opa681 features wideband +5v operation: 225mhz (g = +2) unity gain stable: 280mhz (g = 1) high output current: 150ma output voltage swing: 4.0v high slew rate: 2100v/ s low dg/d : .001% /.01 low supply current: 6ma low disabled current: 320 a applications xdsl line driver broadband video buffers high speed imaging channels portable instruments adc buffers active filters wideband inverting summing high sfdr if amplifier guarantees lower guaranteed maximum supply current than competing products. system power may be further reduced by using the optional disable control pin. leaving this disable pin open, or holding it high, gives normal operation. if pulled low, the opa681 supply current drops to less than 320 a while the output goes into a high impedance state. this feature may be used for either power savings or for video mux applications. opa681 related products singles duals triples voltage feedback opa680 opa2680 opa3680 current feedback opa681 opa2681 opa3681 fixed gain opa682 opa2682 opa3682 opa681 opa681 o p a 6 8 1 copyright ?1997, texas instruments incorporated sbos084a printed in u.s.a. february, 2001 100 ? 50 ? opa681 +5v dis C5v v o = C (v 1 + v 2 + v 3 + v 4 + v 5 ) 100mhz, C1db compression = 15dbm 50 ? v 2 50 ? v 3 50 ? v 4 50 ? v 1 50 ? rg-58 50 ? v 5 23.7 ? 200mhz rf summing amplifier www.ti.com
opa681 2 sbos084a specifications: v s = 5v r f = 402 ? , r l = 100 ? , and g = +2 , (figure 1 for ac performance only), unless otherwise noted. opa681p, u, n typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c (2) 70 c (3) +85 c (3) units max level (1) ac performance (figure 1) small-signal bandwidth (v o = 0.5vp-p) g = +1, r f = 453 ? 280 mhz typ c g = +2, r f = 402 ? 220 220 210 190 mhz min b g = +5, r f = 261 ? 185 mhz typ c g = +10, r f = 180 ? 180 mhz typ c bandwidth for 0.1db gain flatness g = +2, v o = 0.5vp-p 90 50 45 45 mhz min b peaking at a gain of +1 r f = 453, v o = 0.5vp-p 0.4 2 4 db max b large signal bandwidth g = +2, v o = 5vp-p 150 mhz typ c slew rate g = +2, 4v step 2100 1600 1600 1200 v/ s min b rise/fall time g = +2, v o = 0.5v step 1.7 ns typ c g = +2, 5v step 2.0 ns typ c settling time to 0.02% g = +2, v o = 2v step 12 ns typ c 0.1% g = +2, v o = 2v step 8 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd harmonic r l = 100 ? C 79 C 73 C 70 C 68 dbc max b r l 500 ? C 85 C 77 C 70 C 69 dbc max b 3rd harmonic r l = 100 ? C 74 C 71 C 71 C 68 dbc max b r l 500 ? C 77 C 75 C 74 C 72 dbc max b input voltage noise f > 1mhz 2.5 3.0 3.4 3.6 nv/ hz max b non-inverting input current noise f > 1mhz 12 14 15 15 pa/ hz max b inverting input current noise f > 1mhz 15 18 18 19 pa/ hz max b differential gain g = +2, ntsc, v o = 1.4vp, r l = 150 ? 0.001 % typ c r l = 37.5 ? 0.008 % typ c differential phase g = +2, ntsc, v o = 1.4vp, r l = 150 ? 0.01 deg typ c r l = 37.5 ? 0.05 deg typ c dc performance (4) open-loop transimpedance gain (z ol ) v o = 0v, r l = 100 ? 100 56 56 56 k ? min a input offset voltage v cm = 0v 1.3 5 6.5 7.5 mv max a average offset voltage drift v cm = 0v +35 +40 v/ c max b non-inverting input bias current v cm = 0v +30 +55 65 85 a max a average non-inverting input bias current drift v cm = 0v C 400 C 450 na/ c max b inverting input bias current v cm = 0v 10 40 50 55 a max a average inverting input bias current drift v cm = 0v C 125 C 150 na /c max b input common-mode input range (5) 3.5 3.4 3.3 3.2 v min a common-mode rejection v cm = 0v 52 47 46 45 db min a non-inverting input impedance 100 || 2 k ? || pf typ c inverting input resistance (r i ) open-loop 42 ? typ c output? voltage output swing no load 4.0 3.8 3.7 3.6 v min a 100 ? load 3.9 3.7 3.6 3.3 v min a current output, sourcing v o = 0 +190 +160 +140 +80 ma min a current output, sinking v o = 0 C 150 C135 C 130 C 80 ma min a closed-loop output impedance g = +2, f = 100khz 0.03 ? typ c disable (disabled low) power down supply current (+v s )v dis = 0 C 320 a typ c disable time 100 ns typ c enable time 25 ns typ c off isolation g = +2, 5mhz 70 db typ c output capacitance in disable 4 pf typ c turn on glitch g = +2, r l = 150 ? , v in = 0 50 mv typ c turn off glitch g = +2, r l = 150 ? , v in = 0 20 mv typ c enable voltage 3.3 3.5 3.6 3.7 v min a disable voltage 1.8 1.7 1.6 1.5 v max a control pin input bias current (dis) v dis = 0 100 160 160 160 a max a power supply specified operating voltage 5 v typ c maximum operating voltage range 6 6 6 v max a max quiescent current v s = 5v 6 6.4 6.5 6.6 ma max a min quiescent current v s = 5v 6 5.6 5.5 5.0 ma min a power supply rejection ratio ( C psrr) input referred 58 52 50 49 db min a temperature range specification: p, u, n C 40 to +85 c typ c thermal resistance, ja junction-to-ambient p 8-pin dip 100 c/w typ c u so-8 125 c/w typ c n sot23-6 150 c/w typ c notes: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (2) junction temperature = ambient for 25 c guaranteed specifications. (3) junction temperature = ambient at low temperature limit: junction temperature = ambient +23 c at high temperature limit for over temperature guaranteed specifications. (4) current is considered positive out-of-node. v cm is the input common-mode voltage. (5) tested < 3db below minimum specified cmr at cmir limits.
3 opa681 sbos084a specifications: v s = +5v r f = 499 ? , r l = 100 ? to v s /2, and g = +2 , (figure 2 for ac performance only), unless otherwise noted. opa681p, u, n typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c (2) 70 c (3) +85 c (3) units max level (1) ac performance (figure 2) small-signal bandwidth (v o = 0.5vp-p) g = +1, r f = 649 ? 250 mhz typ c g = +2, r f = 499 ? 225 180 140 110 mhz min b g = +5, r f = 360 ? 180 mhz typ c g = +10, r f = 200 ? 165 mhz typ c bandwidth for 0.1db gain flatness g = +2, v o < 0.5vp-p 100 50 35 23 mhz min b peaking at a gain of +1 r f = 649 ? , v o < 0.5vp-p 0.4 2 4 db max b large-signal bandwidth g = +2, v o = 2vp-p 200 mhz typ c slew rate g = +2, 2v step 830 700 680 570 v/ s min b rise/fall time g = +2, v o = 0.5v step 1.5 ns typ c g = +2, v o = 2v step 2.0 ns typ c settling time to 0.02% g = +2, v o = 2v step 14 ns typ c 0.1% g = +2, v o = 2v step 9 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd harmonic r l = 100 ? to v s /2 C 70 C 68 C 67 C 63 dbc max b r l 500 ? to v s /2 C 72 C 70 C 70 C 68 dbc max b 3rd harmonic r l = 100 ? to v s /2 C 72 C 65 C 65 C 62 dbc max b r l 500 ? to v s /2 C 73 C 68 C 67 C 67 dbc max b input voltage noise f > 1mhz 2.2 3 3.4 3.6 nv/ hz max b non-inverting input current noise f > 1mhz 12 14 14 15 pa/ hz max b inverting input current noise f > 1mhz 15 18 18 19 pa/ hz max b dc performance (4) open-loop transimpedance gain (z ol ) v o = v s /2, r l = 100 ? to v s /2 100 60 53 51 k ? min a input offset voltage v cm = 2.5v 1 5 6.0 7 mv max a average offset voltage drift v cm = 2.5v +15 +20 v/ c max b non-inverting input bias current v cm = 2.5v +40 +65 +75 +95 a max a average non-inverting input bias current drift v cm = 2.5v C 300 C 350 na/ c max b inverting input bias current v cm = 2.5v 5 20 25 35 a max a average inverting input bias current drift v cm = 2.5v C 125 C 175 na / c max b input least positive input voltage (5) 1.5 1.6 1.7 1.8 v max a most positive input voltage (5) 3.5 3.4 3.3 3.2 v min a common-mode rejection ratio (cmrr) v cm = v s /2 51 45 44 44 db min a non-inverting input impedance 100 || 2 k ? || pf typ c min inverting input resistance (r i ) open-loop 46 38 36 35 ? min a max inverting input resistance (r i ) open-loop 46 53 55 60 ? max a output most positive output voltage no load 4 3.8 3.7 3.5 v min a r l = 100 ? to v s /2 3.9 3.7 3.6 3.4 v min a least positive output voltage no load 1 1.2 1.3 1.5 v max a r l = 100 ? to v s /2 1.1 1.3 1.4 1.6 v max a current output, sourcing v o = v s /2 150 110 110 60 ma min a current output, sinking v o = v s /2 C 110 C75 C 70 C 50 ma min a closed-loop output impedance g = +2, f = 100khz 0.03 ? typ c disable (disable low) power down supply current (+v s )v dis = 0 C 270 a typ c disable time 100 ns typ c enable time 25 ns typ c off isolation g = +2, 5mhz 65 db typ c output capacitance in disable 4 pf typ c turn on glitch g = +2, r l = 150 ? , v in = v s /2 50 mv typ c turn off glitch g = +2, r l = 150 ? , v in = v s /2 20 mv typ c enable voltage 3.3 3.5 3.6 3.7 v min a disable voltage 1.8 1.7 1.6 1.5 v max a control pin input bias current (dis) v dis = 0 100 a typ c power supply specified single-supply operating voltage 5 v typ c max single-supply operating voltage 12 12 12 v max a max quiescent current v s = +5v 5.3 5.4 5.5 5.5 ma max a min quiescent current v s = +5v 5.3 4.1 3.7 3.6 ma min a power supply rejection ratio ( C psrr) input referred 48 db typ c temperature range specification: p, u, n C 40 to +85 c typ c thermal resistance, ja junction-to-ambient p 8-pin dip 100 c/w typ c u so-8 125 c/w typ c n sot23-6 150 c/w typ c notes: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (2) junction temperature = ambient for 25 c guaranteed specifications. (3) junction temperature = ambient at low temperature limit: junction temperature = ambient +23 c at high temperature limit for over temperature guaranteed specifications. (4) current is considered positive out-of-node. v cm is the input common-mode voltage. (5) tested < 3db below minimum specified cmr at cmir limits.
opa681 4 sbos084a absolute maximum ratings power supply .............................................................................. 6.5vdc internal power dissipation (1) ............................ see thermal information differential input voltage .................................................................. 1.2v input voltage range ............................................................................ v s storage temperature range: p, u, n ........................... C 40 c to +125 c lead temperature (soldering, 10s) .............................................. +300 c junction temperature (t j ) ........................................................... +175 c note:: (1) packages must be derated based on specified ja . maximum t j must be observed. package specified drawing temperature package ordering transport product package number (1) range marking number (2) media opa681p 8-pin plastic dip 006 C 40 c to +85 c opa681p opa681p rails opa681u so-8 surface mount 182 C 40 c to +85 c opa681u opa681u rails " " " " " opa681u/2k5 tape and reel opa681n 6-lead sot23-6 332 C 40 c to +85 c a81 opa681n/250 tape and reel " " " " " opa681n/3k tape and reel notes: (1) for detailed drawing and dimension table, please see end of data sheet. (2) models with a slash (/) are available on ly as tape and reel in the quantity indicated after the slash (e.g. /2k5 indicates 2500 devices per reel). ordering 3000 pieces of the opa681n/3k will get a single 3000-piece tape and reel. package/ordering information electrostatic discharge sensitivity electrostatic discharge can cause damage ranging from perfor- mance degradation to complete device failure. burr-brown corpo- ration recommends that all integrated circuits be handled and stored using appropriate esd protection methods. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. 1 2 3 6 5 4 output C v s non-inverting input +v s dis inverting input 123 654 a81 pin orientation/package marking pin configuration top view dip/so-8 top view sot23-6 1 2 3 4 8 7 6 5 nc inverting input non-inverting input C v s dis +v s output nc nc = no connection
5 opa681 sbos084a typical performance curves: v s = 5v g = +2, r f = 402 ? , and r l = 100 ? , unless otherwise noted (see figure 1). +4 +3 +2 +1 0 C 1 C 2 C 3 C 4 large-signal pulse response time (5ns/div) output voltage (1v/div) g = +2 v o = 5vp-p 400 300 200 100 0 C 100 C 200 C 300 C 400 small-signal pulse response time (5ns/div) output voltage (100mv/div) g = +2 v o = 0.5vp-p disabled feedthrough vs frequency C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 C 95 frequency (mhz) 1 10 100 feedthrough (5db/div) forward v dis = 0 reverse 8 7 6 5 4 3 2 1 0 C 1 C 2 frequency (25mhz/div) 0 250mhz 125mhz large-signal frequency response gain (1db/div) 2vp-p g = +2, r l = 100 ? 1vp-p 4vp-p 7vp-p 2.0 1.6 1.2 0.8 0.4 0 large-signal disable/enable response time (50ns/div) output voltage (400mv/div) 6.0 4.0 2.0 0 v dis (2v/div) v dis output voltage g = +2 v in = +1v 2 1 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 frequency (25mhz/div) 0 250mhz 125mhz small-signal frequency response normalized gain (1db/div) g = +10, r f = 180 ? g = +5, r f = 261 ? g = +1, r f = 453 ? g = +2, r f = 402 ?
opa681 6 sbos084a typical performance curves: v s = 5v (cont.) g = +2, r f = 402 ? , and r l = 100 ? , unless otherwise noted (see figure 1). C 60 C 65 C 70 C 75 C 80 C 85 C 90 5mhz 2nd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 2nd harmonic distortion (dbc) r l = 200 ? r l = 500 ? r l = 100 ? C 60 C 65 C 70 C 75 C 80 C 85 C 90 5mhz 3rd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 3rd harmonic distortion (dbc) r l = 200 ? r l = 100 ? r l = 500 ? C 60 C 65 C 70 C 75 C 80 C 85 C 90 10mhz 2nd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 2nd harmonic distortion (dbc) r l = 500 ? r l = 100 ? r l = 200 ? C 60 C 65 C 70 C 75 C 80 C 85 C 90 10mhz 3rd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 3rd harmonic distortion (dbc) r l = 500 ? r l = 100 ? r l = 200 ? C 50 C 55 C 60 C 65 C 70 C 75 C 80 20mhz 2nd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 2nd harmonic distortion (dbc) r l = 500 ? r l = 100 ? r l = 200 ? C 50 C 55 C 60 C 65 C 70 C 75 C 80 20mhz 3rd harmonic distortion vs output voltage output voltage swing (vp-p) 0.1 1 10 3rd harmonic distortion (dbc) r l = 500 ? r l = 100 ? r l = 200 ?
7 opa681 sbos084a typical performance curves: v s = 5v (cont.) g = +2, r f = 402 ? , and r l = 100 ? , unless otherwise noted (see figure 1). C 40 C 50 C 60 C 70 C 80 C 90 2nd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 2nd harmonic distortion (dbc) v o = 2vp-p r l = 100 ? g = +2, r f = 402 ? g = +10, r f = 180 ? g = +5, r f = 261 ? C 40 C 50 C 60 C 70 C 80 C 90 3rd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 3rd harmonic distortion (dbc) v o = 2vp-p r l = 100 ? g = +2, r f = 402 ? g = +10, r f = 180 ? g = +5, r f = 261 ? C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 two-tone, 3rd-order intermodulation spurious single-tone load power (dbm) C 8 C 6 C 4 C 20246810 3rd-order spurious level (dbc) dbc = db below carriers 50mhz 20mhz 10mhz load power at matched 50 ? load 60 50 40 30 20 10 0 recommended r s vs capacitive load capacitive load (pf) 1 10 100 r s ( ? ) 15 12 9 6 3 0 C 3 C 6 C 9 C 12 C 15 frequency (30mhz/div) 0 300mhz 150mhz frequency response vs capacitive load gain to capacitive load (3db/div) opa681 r s v in v o c l 1k ? 402 ? 402 ? 1k ? is optional. c l = 22pf c l = 10pf c l = 47pf c l = 100pf 100 10 1 input voltage and current noise density frequency (hz) 100 1k 10k 100k 1m 10m current noise (pa/ hz) voltage noise (nv/ hz) non-inverting input current noise inverting input current noise 12.2pa/ hz 15.1pa/ hz voltage noise 2.2nv/ hz
opa681 8 sbos084a typical performance curves: v s = 5v (cont.) g = +2, r f = 402 ? , and r l = 100 ? , unless otherwise noted (see figure 1). 5 4 3 2 1 0 C 1 C 2 C 3 C 4 C 5 output voltage and current limitations i o (ma) C 300 C 200 C 100 0 100 200 300 v o (volts) 100 ? load line 50 ? load line 25 ? load line output current limited 1w internal power limit 1w internal power limit output current limit 10 7.5 5 2.5 0 200 150 100 50 0 supply and output current vs temperature ambient temperature ( c) C 40 C 20 0 20 40 60 80 100 120 140 supply current (2.5ma/div) output current (ma) quiescent supply current sourcing output current sinking output current 120 100 80 60 40 20 0 open-loop transimpedance gain/phase frequency (hz) 10 4 10 5 10 6 10 7 10 8 10 9 transimpedance gain (20db ? /div) 0 C 40 C 80 C 120 C 160 C 200 C 240 transimpedance phase (40 /div) |z ol | z ol 0.05 0.04 0.03 0.02 0.01 0 number of 150 ? loads 1234 composite video dg/d positive video negative sync d dg dg/d (%/ ) 5 4 3 2 1 0 C 1 C 2 C 3 C 4 C 5 typical dc drift over temperature ambient temperature ( c) C 40 C 20 v io 0 20 40 60 80 100 120 140 input offset voltage (mv) 50 40 30 20 10 0 C 10 C 20 C 30 C 40 C 50 input bias currents ( a) non-inverting input bias current inverting input bias current 70 65 60 55 50 45 40 35 30 25 20 frequency (hz) 10 2 10 3 10 4 10 5 10 6 10 7 10 8 cmrr and psrr vs frequency rejection ratio (db) +psrr C psrr cmrr
9 opa681 sbos084a typical performance curves: v s = +5v g = +2, r f = 499 ? , and r l = 100 ? to +2.5v, unless otherwise noted (see figure 2). 2.10 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 small-signal pulse response time (5ns/div) output voltage (100mv/div) g = +2 v o = 0.5vp-p 2 1 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 frequency (25mhz/div) 0 250 125 small-signal frequency response normalized gain (1db/div) g = +2, r f = 499 ? g = +10, r f = 200 ? g = +5, r f = 360 ? g = +1, r f = 649 ? 70 60 50 40 30 20 10 0 recommended r s vs capacitive load capacitive load (pf) 1 10 100 r s ( ? ) 8 7 6 5 4 3 2 1 0 C 1 C 2 frequency (25mhz/div) 0 250 125 large-signal frequency response gain (1db/div) g = +2 r l = 100 ? to 2.5v v o = 0.5vp-p v o = 1vp-p v o = 2vp-p 4.5 4.1 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 0.5 large-signal pulse response time (5ns/div) output voltage (400mv/div) g = +2 v o = 2vp-p 15 12 9 6 3 0 C 3 C 6 C 9 C 12 C 15 frequency response vs capacitive load frequency (20mhz/div) 0 200mhz 100mhz gain to capacitive load (3db/div) c l = 22pf c l = 10pf c l = 47pf c l = 100pf opa681 499 ? 499 ? 57.6 ? 806 ? 806 ? 1k ? v i +5v 0.1 f v o r s c l 0.1 f 1k ? is optional.
opa681 10 sbos084a typical performance curves: v s = +5v (cont.) g = +2, r f = 499 ? , and r l = 100 ? to +2.5v, unless otherwise noted (see figure 2). 10 1 0.1 0.01 closed-loop output impedance frequency (hz) 10k 100m 100k 1m 10m output impedance ( ? ) opa681 402 ? +5 C 5 402 ? 50 ? z o C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 single-tone load power (dbm) C 14 C 12 C 10 C 8 C 6 C 4 C 20 2 two-tone, 3rd order spurious level 3rd order spurious (dbc) 50mhz dbc = db below carriers 20mhz 10mhz load power at matched 50 ? load C 40 C 50 C 60 C 70 C 80 2nd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 2nd harmonic distortion (dbc) v o = 2vp-p r l = 100 ? to 2.5v g = +2, r f = 499 ? g = +10, r f = 200 ? g = +5, r f = 360 ? 3rd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 3rd harmonic distortion (dbc) C 40 C 50 C 60 C 70 C 80 v o = 2vp-p r l = 100 ? to 2.5v g = +10, r f = 200 ? g = +5, r f = 360 ? g = +2, r f = 499 ? 2nd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 2nd harmonic distortion (dbc) r l = 200 ? r l = 100 ? C 50 C 60 C 70 C 80 C 90 v o = 2vp-p g = +2 loads to 2.5v r l = 500 ? 3rd harmonic distortion vs frequency frequency (mhz) 0.1 1 10 20 3rd harmonic distortion (dbc) C 50 C 60 C 70 C 80 C 90 v o = 2vp-p g = +2 r l = 100 ? r l = 500 ? r l = 200 ? loads to 2.5v
11 opa681 sbos084a applications information wideband current feedback operation the opa681 gives the exceptional ac performance of a wideband current feedback op amp with a highly linear, high power output stage. requiring only 6ma quiescent current, the opa681 will swing to within 1v of either supply rail and deliver in excess of 135ma guaranteed at room temperature. this low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5v) supply operation. the opa681 will deliver greater than 200mhz bandwidth driving a 2vp-p output into 100 ? on a single +5v supply. previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. the opa681 achieves a comparable power gain with much better linear- ity. the primary advantage of a current feedback op amp over a voltage feedback op amp is that ac performance (bandwidth and distortion) is relatively independent of sig- nal gain. for similar ac performance at low gain, with improved dc accuracy, consider the high slew rate, unity gain stable, voltage feedback opa680. figure 1 shows the dc coupled, gain of +2, dual power supply circuit configuration used as the basis of the 5v specifications and typical performance curves. for test purposes, the input impedance is set to 50 ? with a resistor to ground and the output impedance is set to 50 ? with a series output resistor. voltage swings reported in the speci- fications are taken directly at the input and output pins while load powers (dbm) are defined at a matched 50 ? load. for the circuit of figure 1, the total effective load will be 100 ? || 804 ? = 89 ? . the disable control line (dis) is typically left open to guarantee normal amplifier operation. one optional component is included in figure 1. in addition to the usual power supply de-coupling capacitors to ground, a 0.1 f capacitor is included between the two power supply pins. in practical pc board layouts, this optional added capacitor will typically improve the 2nd harmonic distortion perfor- mance by 3db to 6db. figure 2 shows the ac-coupled, gain of +2, single supply circuit configuration used as the basis of the +5v specifica- tions and typical performance curves. though not a ?ail- to-rail?design, the opa681 requires minimal input and output voltage headroom compared to other very wideband current feedback op amps. it will deliver a 3vp-p output swing on a single +5v supply with greater than 150mhz bandwidth. the key requirement of broadband single supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. the circuit of figure 2 establishes an input midpoint bias using a simple resistive divider from the +5v supply (two 806 ? resistors). the input signal is then ac coupled into this midpoint voltage bias. the input voltage can swing to within 1.5v of either supply pin, giving a 2vp-p input signal range centered between the supply pins. the input impedance matching resistor (57.6 ? ) used for testing is adjusted to give a 50 ? input match when the parallel combination of the biasing divider network is included. the gain resistor (r g ) is ac-coupled, giving the circuit a dc gain of +1?hich puts the input dc bias voltage (2.5v) on the output as well. the feedback resistor value has been adjusted from the bipolar supply condition to re-optimize for a flat frequency response in +5v, gain of +2, operation (see setting resistor values to optimize bandwidth). again, on a single +5v supply, the output voltage can swing to within 1v of either supply pin while delivering more than 80ma output current. a demanding 100 ? load to a midpoint bias is used in this characterization circuit. the new output stage used in the opa681 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5v supply, 3rd harmonic distortion plots. figure 1. dc-coupled, g = +2, bipolar supply, specifi- cation and test circuit. figure 2. ac-coupled, g = +2, single supply specifica- tion and test circuit. opa681 +5v + dis C 5v C v s +v s 50 ? load 50 ? 50 ? v o v i 50 ? source r g 402 ? r f 402 ? + 6.8f 0.1f 6.8f 0.1f 0.1f opa681 +5v dis v s /2 806 ? 100 ? v o v i +v s 57.6 ? 806 ? r f 499 ? r g 499 ? 0.1f 0.1f 6.8f + 0.1f
opa681 12 sbos084a single-supply a/d converter interface most modern, high performance a/d converters (such as the texas instruments ads8xx and ads9xx series) operate on a single +5v (or lower) power supply. it has been a consid- erable challenge for single-supply op amps to deliver a low distortion input signal at the adc input for signal frequen- cies exceeding 5mhz. the high slew rate, exceptional out- put swing and high linearity of the opa681 make it an ideal single-supply adc driver. figure 3 shows an example input interface to a very high performance 10-bit, 60msps cmos converter. the opa681 in the circuit of figure 3 provides > 180mhz bandwidth operating at a signal gain of +4 with a 2vp-p output swing. one of the primary advantages of the current feedback internal architecture used in the opa681 is that high bandwidth can be maintained as the signal gain is increased. the non-inverting input bias voltage is referenced to the mid-point of the adc signal range by dividing off the top and bottom of the internal adc reference ladder. with the gain resistor (r g ) ac-coupled, this bias voltage has a gain of +1 to the output, centering the output voltage swing as well. tested performance at a 20mhz analog input frequency and a 60msps clock rate on the converter gives > 58dbc sfdr. wideband inverting summing amplifier since the signal bandwidth for a current feedback op amp may be controlled independently of the noise gain (ng, which is normally the same as the non-inverting signal gain), very broadband inverting summing stages may be imple- mented using the opa681. the circuit on the front page of this data sheet shows an example inverting summing ampli- fier where the resistor values have been adjusted to maintain both maximum bandwidth and input impedance matching. if each rf signal is assumed to be driven from a 50 ? source, the ng for this circuit will be (1 + 100 ? /(100 ? /5)) = 6. the total feedback impedance (from v o to the inverting error current) is the sum of r f + (r i x ng) where r i is the impedance looking into the inverting input from the sum- ming junction (see setting resistor values to optimize performance section). using 100 ? feedback (to get a signal gain of ? from each input to the output pin) requires an additional 20 ? in series with the inverting input to increase the feedback impedance. with this resistor added to the typical internal r i = 41 ? , the total feedback impedance is 100 ? + (65 ? x 6) = 490 ? , which is equal to the required value to get a maximum bandwidth flat frequency response for ng = 6. tested performance shows more than 200mhz small signal bandwidth and a ?dbm compression of 15dbm at the matched 50 ? load through 100mhz. wideband video multiplexing one common application for video speed amplifiers which include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. this simple ?ired-or video multiplexer?can be easily implemented using the opa681 as shown in figure 4. typically, channel switching is performed either on sync or retrace time in the video signal. the two inputs are approxi- mately equal at this time. the ?ake-before-break?disable characteristic of the opa681 ensures that there is always one amplifier controlling the line when using a wired-or circuit like that shown in figure 4. since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5 ? in this case). when one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. the gain and output matching resistor have been slightly increased to get a signal gain of +1 at the matched load and provide a 75 ? output impedance to the cable. the video multiplexer connection (figure 4) also insures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated 1.2v maximum for standard video signal levels. figure 3. wideband, ac-coupled, single-supply a/d driver. opa681 360 ? +2.5v dc bias ads823 10-bit 60msps 50 ? 2vp-p dis 22pf input 120 ? refb reft cm input 0.1 f 0.1 f 0.5vp-p 2k ? 0.1 f +3.5v 2k ? 0.1 f +1.5v +5v clock +5v r g r f
13 opa681 sbos084a figure 4. two-channel video multiplexer. the section on disable operation shows the turn-on and turn-off switching glitches using a grounded input for a single channel is typically less than 50mv. where two outputs are switched (as shown in figure 6), the output line is always under the control of one amplifier or the other due to the ?ake-before-break?disable timing. in this case, the switching glitches for two 0v inputs drop to <20mv. single-supply if amplifier the high bandwidth provided by the opa681 while operat- ing on a single +5v supply lends itself well to if amplifier applications. one of the advantages of using an op amp like the opa681 as an if amplifier is that precise signal gain is achieved along with much lower 3rd-order intermodulation versus quiescent power dissipation. in addition, the opa681 in the sot23-6 package offers a very small package with a power shutdown feature for portable applications. one con- cern with using op amps for an if amplifier is their relatively high noise figures. it is sometimes suggested that an opti- mum source resistance can be used to minimize op amp noise figure. adding a resistor to reach this optimum value may improve noise figure, but will actually decrease the signal-to-noise ratio. a more effective way to move towards an optimum source impedance is to bring the signal in through an input transformer. figure 5 shows an example that is particularly useful for the opa681. figure 5. low noise, single supply, if amplifier. r f 600 ? v o = 3v/v (9.54db) v i r g 200 ? opa681 +5v dis power supply de-coupling not shown v i v o 50 ? load 50 ? 50 ? source 1:2 5k ? 5k ? 1f 0.1f bringing the signal in through a step up transformer to the inverting input gain resistor has several advantages for the opa681. first, the decoupling capacitor on the non-invert- ing input eliminates the contribution of the non-inverting input current noise to the output noise. secondly, the non- inverting input noise voltage of the op amp is actually opa681 2k ? 82.5 ? 75 ? cable rg-59 82.5 ? 75 ? 402 ? 340 ? video 1 +5v +5v C 5v opa681 2k ? 75 ? 402 ? 340 ? video 2 C 5v +5v v dis dis dis
opa681 14 sbos084a attenuated if reflected to the input side of r g . using the 1:2 (turns ratio) step-up transformer reflects the 50 ? source imped- ance at the primary through to the secondary as a 200 ? source impedance (and the 200 ? r g resistor is reflected through to the transformer primary as a 50 ? input matching impedance). the noise gain (ng) to the amplifier output is then 1+ 600/400 = 2.5v/v. taking the op amp? 2.2nv/ hz input voltage noise times this noise gain to the output, then reflecting this noise term to the input side of the r g resistor, divides it by 3. this gives a net gain of 0.833 for the non-inverting input voltage noise when reflected to the input point for the op amp circuit. this is further reduced when referred back to the transformer primary. the relatively low gain if amplifier circuit of figure 5 gives a 12db noise figure at the input of the transformer. increasing the r f resistor to 600 ? (once r g is set to 200 ? for input impedance matching) will slightly reduce the bandwidth. measured results show 150mhz small-signal bandwidth for the circuit of figure 5 with exceptional flatness through 30mhz. although the opa681 does not show an intercept characteristic for the 2-tone, 3rd-order intermodulation distortion, it does hold a very high spurious free dynamic range through high output powers and frequencies. the maximum single-tone power at the match- ed load for the single-supply circuit of figure 5 is 1dbm (this requires a 2.8vp-p swing at the output pin of the opa681 for the 2-tone envelope). measured 2-tone sfdr at this maximum load power for the circuit of figure 5 exceeds 55dbc for frequencies to 30mhz. design-in tools demonstration boards several pc boards are available to assist in the initial evaluation of circuit performance using the opa681 in its three package styles. all of these are available free as an unpopulated pc board delivered with descriptive documen- tation. the summary information for these boards is shown in the table below. ti applications department (1-800-548-6132). the appli- cations department is also available for design assistance at this number. these models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. they do not do as well in predicting the harmonic distortion or dg/d characteristics. these models do not attempt to distinguish between the package types in their small-signal ac performance. operating suggestions setting resistor values to optimize bandwidth a current feedback op amp like the opa681 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values. this is shown in the typical performance curves; the small-signal bandwidth de- creases only slightly with increasing gain. those curves also show that the feedback resistor has been changed for each gain setting. the resistor ?alues?on the inverting side of the circuit for a current feedback op amp can be treated as frequency response compensation elements while their ?atios?set the signal gain. figure 6 shows the small-signal frequency response analysis circuit for the opa681. figure 6. current feedback transfer function analysis circuit. r f v o r g r i z (s) i err i err v i board literature part request product package number number opa681p 8-pin dip dem-opa68xp mkt-350 opa681u 8-pin so-8 dem-opa68xu mkt-351 opa681n 6-lead sot23-6 dem-opa68xn mkt-348 contact the ti applications support line to request any of these boards. macromodels and applications support computer simulation of circuit performance using spice is often useful when analyzing the performance of analog circuits and systems. this is particularly true for video and rf amplifier circuits where parasitic capacitance and induc- tance can have a major effect on circuit performance. a spice model for the opa681 is available through either the ti web site (www.ti.com) or as one model on a disk from the the key elements of this current feedback op amp model are: buffer gain from the non-inverting input to the inverting input r i buffer output impedance i err feedback error current signal z(s) frequency dependent open loop transimpedance gain from i err to v o the buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. it will, however, set the cmrr for a single op amp differential amplifier configuration. for a buffer gain < 1.0, the cmrr = ?0 x log (1 ) db. r i , the buffer output impedance, is a critical portion of the bandwidth control equation. the opa681 is typically about 41 ? .
15 opa681 sbos084a a current feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. the typical performance curves show this open-loop transimpedance response. this is analogous to the open-loop voltage gain curve for a voltage feedback op amp. developing the transfer function for the circuit of figure 6 gives equation 1: this is written in a loop gain analysis format where the errors arising from a non-infinite open-loop gain are shown in the denominator. if z(s) were infinite over all frequencies, the denominator of equation 1 would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. the fraction in the denominator of equation 1 determines the frequency response. equation 2 shows this as the loop gain equation: if 20 x log (r f + ng x r i ) were drawn on top of the open- loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. eventually, z(s) rolls off to equal the denominator of equation 2 at which point the loop gain has reduced to 1 (and the curves have intersected). this point of equality is where the amplifier? closed-loop frequency response given by equa- tion 1 will start to roll off, and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage feedback op amp. the difference here is that the total impedance in the denominator of equation 2 may be controlled somewhat separately from the desired signal gain (or ng). the opa681 is internally compensated to give a maximally flat frequency response for r f = 402 ? at ng = 2 on 5v supplies. evaluating the denominator of equation 2 (which is the feedback transimpedance) gives an optimal target of 484 ? . as the signal gain changes, the contribution of the ng x r i term in the feedback transimpedance will change, but the total can be held constant by adjusting r f . equation 3 gives an approximate equation for optimum r f over signal gain: eq. 3 as the desired signal gain increases, this equation will eventually predict a negative r f . a somewhat subjective limit to this adjustment can also be set by holding r g to a minimum value of 20 ? . lower values will load both the buffer stage at the input and the output stage if r f gets too low?ctually decreasing the bandwidth. figure 7 shows the recommended r f vs ng for both 5v and a single +5v operation. the values for r f versus gain shown here are approximately equal to the values used to generate the typical performance curves. they differ in that the opti- mized values used in the typical performance curves are also correcting for board parasitics not considered in the simplified analysis leading to equation 3. the values shown in figure 7 give a good starting point for design where bandwidth optimization is desired. z (s) r f + r i ng = loop gain eq. 2 v o v i = 1 + r f r g ? ? ? ? ? ? 1 + r f + r i 1 + r f r g ? ? ? ? ? ? z (s) = ng 1 + r f + r i ng z (s) eq. 1 ng = 1 + r f r g ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 7. recommended feedback resistor vs noise gain. 600 500 400 300 200 100 0 noise gain 020 10 15 5 feedback resistor vs noise gain feedback resistor ( ? ) +5v 5v the total impedance going into the inverting input may be used to adjust the closed-loop signal bandwidth. inserting a series resistor between the inverting input and the summing junction will increase the feedback impedance (denominator of equation 2), decreasing the bandwidth. this approach to bandwidth control is used for the inverting summing circuit on the front page. the internal buffer output impedance for the opa681 is slightly influenced by the source impedance looking out of the non-inverting input terminal. high source resistors will have the effect of increasing r i , decreasing the bandwidth. for those single-supply applications which de- velop a midpoint bias at the non-inverting input through high valued resistors, the decoupling capacitor is essential for power supply noise rejection, non-inverting input noise current shunting, and to minimize the high frequency value for r i in figure 6. inverting amplifier operation since the opa681 is a general purpose, wideband current feedback op amp, most of the familiar op amp application circuits are available to the designer. those applications that require considerable flexibility in the feedback element (e.g., integrators, transimpedance, some filters) should con- rngr fi = 484 ?
opa681 16 sbos084a sider the unity gain stable voltage feedback opa680, since the feedback resistor is the compensation element for a current feedback op amp. wideband inverting operation (and especially summing) is particularly suited to the opa681. figure 8 shows a typical inverting configuration where the i/o impedances and signal gain from figure 1 are retained in an inverting circuit configuration. ground on the non-inverting input to achieve bias current error cancellation at the output. the input bias currents for a current feedback op amp are not generally matched in either magnitude or polarity. connecting a resistor to ground on the non-inverting input of the opa681 in the circuit of figure 8 will actually provide additional gain for that input? bias and noise currents, but will not decrease the output dc error since the input bias currents are not matched. output current and voltage the opa681 provides output voltage and current capabili- ties that are unsurpassed in a low cost monolithic op amp. under no-load conditions at 25 c, the output voltage typi- cally swings closer than 1v to either supply rail; the guaran- teed swing limit is within 1.2v of either rail. into a 15 ? load (the minimum tested load), it is guaranteed to deliver more than 135ma. the specifications described above, though familiar in the industry, consider voltage and current limits separately. in many applications, it is the voltage x current, or v-i product, which is more relevant to circuit operation. refer to the ?utput voltage and current limitations?plot in the typi- cal performance curves. the x and y axes of this graph show the zero-voltage output current limit and the zero- current output voltage limit, respectively. the four quad- rants give a more detailed view of the opa681? output drive capabilities, noting that the graph is bounded by a ?afe operating area?of 1w maximum internal power dissipation. superimposing resistor load lines onto the plot shows that the opa681 can drive 2.5v into 25 ? or 3.5v into 50 ? without exceeding the output capabilities or the 1w dissipation limit. a 100 ? load line (the standard test circuit load) shows the full 3.9v output swing capability, as shown in the typical specifications. the minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. only at cold startup will the output current and voltage decrease to the numbers shown in the guaranteed tables. as the output transistors deliver power, their junction temperatures will increase, decreasing their v be ? (increasing the available output voltage swing) and increasing their current gains (increasing the available out- put current). in steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. to maintain maximum output stage linearity, no output short-circuit protection is provided. this will not normally be a problem since most applications include a series match- ing resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. however, shorting the output pin directly to the adjacent positive power supply pin (8-pin packages) will, in most cases, destroy the amplifier. if additional short-circuit protection is required, consider a small series resistor in the power supply leads. this will, under heavy output loads, figure 8. inverting gain of ? with impedance matching. opa681 r f 365 ? r g 182 ? dis +5v C 5v 50 ? 50 ? load v o power supply de-coupling not shown v i 50 ? source r m 68.1 ? in the inverting configuration, two key design consider- ations must be noted. the first is that the gain resistor (r g ) becomes part of the signal channel input impedance. if input impedance matching is desired (which is beneficial when- ever the signal is coupled through a cable, twisted pair, long pc board trace or other transmission line conductor), it is normally necessary to add an additional matching resistor to ground. r g by itself is normally not set to the required input impedance since its value, along with the desired gain, will determine an r f which may be non-optimal from a fre- quency response standpoint. the total input impedance for the source becomes the parallel combination of r g and r m . the second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and will have slight effect on the bandwidth through equation 1. the values shown in figure 8 have accounted for this by slightly decreasing r f (from figure 1) to re-optimize the bandwidth for the noise gain of figure 8 (ng = 2.74) in the example of figure 8, the r m value combines in parallel with the external 50 ? source impedance, yielding an effective driving impedance of 50 ? || 68 ? = 28.8 ? . this impedance is added in series with r g for calculating the noise gain?hich gives ng = 2.74. this value, along with the r f of figure 8 and the inverting input impedance of 41 ? , are inserted into equation 3 to get a feedback transimpedance nearly equal to the 484 ? opti- mum value. note that the non-inverting input in this bipolar supply inverting application is connected directly to ground. it is often suggested that an additional resistor be connected to
17 opa681 sbos084a reduce the available output voltage swing. a 5 ? series resistor in each power supply lead will limit the internal power dissipation to less than 1w for an output short circuit while decreasing the available output voltage swing only 0.5v for up to 100ma desired load currents. always place the 0.1 f power supply decoupling capacitors after these supply current limiting resistors directly on the supply pins. driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an a/d converter?ncluding additional external capacitance which may be recommended to improve a/d linearity. a high speed, high open-loop gain amplifier like the opa681 can be very susceptible to de- creased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. when the amplifier? open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. several external solutions to this problem have been suggested. when the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the sim- plest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. this does not eliminate the pole from the loop re- sponse, but rather shifts it and adds a zero at a higher frequency. the additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. the typical performance curves show the recommended r s vs capacitive load and the resulting frequency response at the load. parasitic capacitive loads greater than 2pf can begin to degrade the performance of the opa681. long pc board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. always consider this effect carefully, and add the recommended series resistor as close as possible to the opa681 output pin (see board layout guidelines). distortion performance the opa681 provides good distortion performance into a 100 ? load on 5v supplies. relative to alternative solu- tions, it provides exceptional performance into lighter loads and/or operating on a single +5v supply. generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the distortion with a negligible 3rd harmonic component. focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. remember that the total load includes the feedback network?n the non-inverting configuration (fig- ure 1) this is the sum of r f + r g , while in the inverting configuration it is just r f . also, providing an additional supply de-coupling capacitor (0.1 f) between the supply pins (for bipolar operation) improves the 2nd-order distor- tion slightly (3db to 6db). in most op amps, increasing the output voltage swing in- creases harmonic distortion directly. the typical perfor- mance curves show the 2nd harmonic increasing at a little less than the expected 2x rate while the 3rd harmonic increases at a little less than the expected 3x rate. where the test power doubles, the difference between it and the 2nd harmonic decreases less than the expected 6db while the difference between it and the 3rd decreases by less than the expected 12db. this also shows up in the 2-tone, 3rd-order intermodulation spurious (im3) response curves. the 3rd- order spurious levels are extremely low at low output power levels. the output stage continues to hold them low even as the fundamental power reaches very high levels. as the typical performance curves show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. as the fundamental power level increases, the dynamic range does not decrease significantly. for two tones centered at 20mhz, with 10dbm/tone into a matched 50 ? load (i.e., 2vp-p for each tone at the load, which requires 8vp-p for the overall 2-tone envelope at the output pin), the typical performance curves show 62dbc difference between the test-tone power and the 3rd-order intermodulation spurious levels. this exceptional perfor- mance improves further when operating at lower frequen- cies. noise performance wideband current feedback op amps generally have a higher output noise than comparable voltage feedback op amps. the opa681 offers an excellent balance between voltage and current noise terms to achieve low output noise. the inverting current noise (15pa/ hz) is significantly lower than earlier solutions while the input voltage noise (2.2nv/ hz) is lower than most unity gain stable, wideband, voltage feedback op amps. this low input voltage noise was achieved at the price of higher non-inverting input current noise (12pa/ hz). as long as the ac source impedance looking out of the non-inverting node is less than 100 ? , this current noise will not contribute significantly to the total output noise. the op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. figure 9 shows the op amp noise analysis model with all the noise terms figure 9. op amp noise analysis model. 4kt r g r g r f r s opa681 i bi e o i bn 4kt = 1.6e C 20j at 290 k e rs e ni 4ktr s 4ktr f
opa681 18 sbos084a included. in this model, all noise terms are taken to be noise voltage or current density terms in either nv/ hz or pa/ hz. the total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. equation 4 shows the general form for the output noise voltage using the terms shown in figure 9. dividing this expression by the noise gain (ng = (1+r f /r g )) will give the equivalent input-referred spot noise voltage at the non-inverting input as shown in equation 5. evaluating these two equations for the opa681 circuit and component values shown in figure 1 will give a total output spot noise voltage of 8.4nv/ hz and a total equivalent input spot noise voltage of 4.2nv/ hz. this total input-referred spot noise voltage is higher than the 2.2nv/ hz specifica- tion for the op amp voltage noise alone. this reflects the noise added to the output by the inverting current noise times the feedback resistor. if the feedback resistor is reduced in high gain configurations (as suggested previously), the total input-referred voltage noise given by equation 5 will ap- proach just the 2.2nv/ hz of the op amp itself. for example, going to a gain of +10 using r f = 180 ? will give a total input-referred noise of 2.4nv/ hz . dc accuracy and offset control a current feedback op amp like the opa681 provides exceptional bandwidth in high gains, giving fast pulse set- tling but only moderate dc accuracy. the typical specifi- cations show an input offset voltage comparable to high speed voltage feedback amplifiers. however, the two input bias currents are somewhat higher and are unmatched. whereas bias current cancellation techniques are very effec- tive with most voltage feedback op amps, they do not generally reduce the output dc offset for wideband current feedback op amps. since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. evaluating the configuration of figure 1, using worst-case +25 c input offset voltage and the two input bias currents, gives a worst- case output offset range equal to: (ng x v os(max) ) + (i bn x r s /2 x ng) (i bi x r f ) where ng = non-inverting signal gain = (2 x 5.0mv) + (55 a x 25 ? x 2) (402 ? x 40 a) = 10mv + 2.75mv 16mv = ?3.25mv +28.25mv a fine-scale, output offset null, or dc operating point adjustment, is sometimes required. numerous techniques are available for introducing dc offset control into an op amp circuit. most simple adjustment techniques do not correct for temperature drift. it is possible to combine a lower speed, precision op amp with the opa681 to get the dc accuracy of the precision op amp along with the signal bandwidth of the opa681. figure 10 shows a non-inverting g = +10 circuit that holds an output offset voltage less than 7.5mv over temperature with > 150mhz signal band- width. this dc-coupled circuit provides very high signal band- width using the opa681. at lower frequencies, the output voltage is attenuated by the signal gain and compared to the original input voltage at the inputs of the opa237 (this is a low cost, precision voltage feedback op amp with 1.5mhz gain bandwidth product). if these two don? agree (due to dc offsets introduced by the opa681), the opa237 sums in a correction current through the 2.86k ? inverting sum- ming path. several design considerations will allow this circuit to be optimized. first, the feedback to the opa237? non-inverting input must be precisely matched to the high speed signal gain. making the 2k ? resistor to ground an adjustable resistor would allow the low and high frequency gains to be precisely matched. secondly, the crossover frequency region where the opa237 passes control to the opa681 must occur with exceptional phase linearity. these two issues reduce to designing for pole/zero cancellation in the overall transfer function. using the 2.86k ? resistor will nominally satisfy this requirement for the circuit in figure 10. perfect cancellation over process and temperature is not possible. however, this initial resistor setting and precise gain matching will minimize long term pulse settling tails. disable operation the opa681 provides an optional disable feature that may be used either to reduce system power or to implement a opa681 180 ? 2.86k ? 20 ? dis +5v C 5v v o power supply de-coupling not shown opa237 C 5v +5v v i 18k ? 2k ? 1.8k ? figure 10. wideband, precision, g = +10 composite amplifier. eq. 5 e n = e ni 2 + i bn r s () 2 + 4ktr s + i bi r f ng ? ? ? ? 2 + 4ktr f ng eq. 4 e o = e ni 2 + i bn r s () 2 + 4ktr s () ng 2 + i bi r f () 2 + 4ktr f ng
19 opa681 sbos084a simple channel multiplexing operation. if the dis control pin is left unconnected, the opa681 will operate normally. to disable, the control pin must be asserted low. figure 11 shows a simplified internal circuit for the disable control feature. in normal operation, base current to q1 is provided through the 110k ? resistor while the emitter current through the 15k ? resistor sets up a voltage drop that is inadequate to turn on the two diodes in q1? emitter. as v dis is pulled low, additional current is pulled through the 15k ? resistor eventually turning on these two diodes ( 100 a). at this point, any further current pulled out of v dis goes through those diodes holding the emitter-base voltage of q1 at approximately zero volts. this shuts off the collector current out of q1, turning the amplifier off. the supply current in the disable mode are only those required to operate the circuit of figure 11. additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). when disabled, the output and input nodes go to a high impedance state. if the opa681 is operating in a gain of +1, this will show a very high impedance (4pf || 1m ? ) at the output and exceptional signal isolation. if operating at a gain greater than +1, the total feedback network resistance (r f + r g ) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. if configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (r f + r g ) giving relatively poor input to output isolation. one key parameter in disable operation is the output glitch when switching in and out of the disabled mode. figure 12 shows these glitches for the circuit of figure 1 with the input signal set to zero volts. the glitch waveform at the output pin is plotted along with the dis pin voltage. the transition edge rate (dv/dt) of the dis control line will influence this glitch. for the plot of figure 12, the edge rate was reduced until no further reduction in glitch amplitude was observed. this approximately 1v/ns maximum slew rate may be achieved by adding a simple rc filter into the v dis pin from a higher speed logic line. if extremely fast transition logic is used, a 2k ? series resistor between the logic gate and the dis input pin will provide adequate bandlimiting using just the parasitic input capacitance on the dis pin while still ensuring an adequate logic level swing. 25k ? 110k ? 15k ? i s control C v s +v s v dis q1 figure 11. simplified disable control circuit. 40 20 0 C 20 C 40 time (20ns/div) output voltage (20mv/div) output voltage (0v input) v dis 0.2v 4.8v figure 12. disable/enable glitch. thermal analysis due to the high output power capability of the opa681, heatsinking or forced airflow may be required under extreme operating conditions. maximum desired junction tempera- ture will set the maximum allowed internal power dissipa- tion as described below. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d x ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). under this condition p dl = v s 2 /(4 x r l ) where r l includes feedback network loading. note that it is the power in the output stage and not in the load that determines internal power dissipation. as a worst-case example, compute the maximum t j using an opa681n (sot23-6 package) in the circuit of figure 1 operating at the maximum specified ambient temperature of +85 c and driving a grounded 20 ? load to +2.5v dc: p d = 10v x 7.2ma + 5 2 / (4 x (20 ? || 804 ? )) = 392mw maximum t j = +85 c + (0.39w (150 c/w) = 144 c although this is still well below the specified maximum junction temperature, system reliability considerations may require lower guaranteed junction temperatures. remember, this is a worst-case internal power dissipation?se your actual signal and load to compute p dl . the highest possible
opa681 20 sbos084a internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. this puts a high current through a large internal voltage drop in the output transistors. the output voltage and current limitations plot shown in the typical performance curves include a boundary for 1w maximum internal power dissi- pation under these conditions. board layout guidelines achieving optimum performance with a high frequency amplifier like the opa681 requires careful attention to board layout parasitics and external component types. rec- ommendations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability: on the non- inverting input, it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted ca- pacitance, a window around the signal i/o pins should be opened in all of the ground and power planes around those pins. otherwise, ground and power planes should be unbro- ken elsewhere on the board. b) minimize the distance (< 0.25") from the power supply pins to high frequency 0.1 f decoupling capacitors. at the device pins, the ground and power plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. the power supply connections (on pins 4 and 7) should always be decoupled with these capacitors. an optional supply decoupling ca- pacitor across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. larger (2.2 f to 6.8 f) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board. c) careful selection and placement of external compo- nents will preserve the high frequency performance of the opa681. resistors should be a very low reactance type. surface-mount resistors work best and allow a tighter over- all layout. metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. again, keep their leads and pc board trace length as short as possible. never use wirewound type resistors in a high frequency application. since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. other network components, such as non-inverting input termination resis- tors, should also be placed close to the package. where double-side component mounting is allowed, place the feed- back resistor directly under the package on the other side of the board between the output and inverting input pins. the frequency response is primarily determined by the feedback resistor value as described previously. increasing its value will reduce the bandwidth, while decreasing it will give a more peaked frequency response. the 402 ? feedback resis- tor used in the typical performance specifications at a gain of +2 on 5v supplies is a good starting point for design. note that a 453 ? feedback resistor, rather than a direct short, is recommended for the unity gain follower application. a current feedback op amp requires a feedback resistor even in the unity gain follower configuration to control stability. d) connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the plot of recommended r s versus capacitive load. low parasitic capacitive loads (< 5pf) may not need an r s since the opa681 is nominally compensated to operate with a 2pf parasitic load. if a long trace is required, and the 6db signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout tech- niques). a 50 ? environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion vs load plots. with a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the opa681 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. the high output voltage and current capa- bility of the opa681 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. if the 6db attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of r s vs capacitive load. this will not preserve signal integrity as well as a doubly-terminated line. if the input impedance of the desti- nation device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) socketing a high speed part like the opa681 is not recommended. the additional lead length and pin-to-pin capacitance introduced by the socket can create an ex- tremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa681 onto the board. if socketing for the dip package is desired, high frequency flush-mount pins (e.g., mckenzie technol- ogy #710c) can give good results.
21 opa681 sbos084a input and esd protection the opa681 is built using a very high speed complemen- tary bipolar process. the internal junction breakdown volt- ages are relatively low for these very small geometry de- vices. these breakdowns are reflected in the absolute maxi- mum ratings table. all device pins have limited esd protection using internal diodes to the power supplies as shown in figure 13. these diodes provide moderate protection to input overdrive voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g., in systems with 15v supply parts driving into the opa681), current-limiting series resis- tors should be added into the two inputs. keep these resistor values as low as possible since high values degrade both noise performance and frequency response. external pin +v cc C v cc internal circuitry figure 13. internal esd protection.
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