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publication number S29NS-N_00 revision a amendment 12 issue date june 13, 2006 S29NS-N mirrorbit? flash family S29NS-N mirrorbit? flash family cover sheet s29ns256n, s29n s128n, s29ns064n 256/128/64 megabit (16/8/4m x 16-bit), cmos 1.8 volt-only simultaneous read/write, multiplexed, burst mode flash memory data sheet (advance information) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
ii S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 notice on data sheet designations spansion llc issues data sheets with advance information or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion llc therefore places the following conditions upon advance information content: ?this document contains information on one or mo re products under development at spansion llc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion llc reserves t he right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or inco rrect specification. spansion llc applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document des ignations may be directed to your local amd or fujitsu sales office.
this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice. publication number S29NS-N_00 revision a amendment 12 issue date june 13, 2006 distinctive characteristics ? single 1.8v read, program and erase (1.70v to 1.95v) ? versatileio? feature ? device generates data output voltages and tolerates data input voltages as determined by the voltage on the v ccq pin ? 1.8v compatible i/o signals ? multiplexed data and address for reduced i/o count ? a15?a0 multiplexed as dq15?dq0 ? addresses are latched by avd# control input when ce# low ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in other bank ? zero latency between read and write operations ? read access times at 80/66 mhz ? burst access times of 9/11 ns at industrial temperature range ? asynchronous random access times of 80 ns ? synchronous random access times of 80 ns ? burst length ? continuous linear burst ? 8/16/32 word linear burst with wrap around ? 8/16/32 word linear burst without wrap around ? secured silicon sector region ? 256 words accessible through a command sequence ? 128 words for the factory secured silicon sector ? 128 words for the customer secured silicon sector ? power dissipation (typical values: 8 bits switching, c l = 30 pf) @ 80 mhz ? continuous burst mode read: 28 ma (at 66mhz) ? simultaneous operation: 50 ma ? program/erase: 19 ma ? standby mode: 20 a ? sector architecture ? four 16 k word sectors (s29ns256n and s29ns128n) and four 8k word sectors (s29ns064n) in upper-most address range ? two-hundred-fifty-five 64-kword sectors (s29ns256n), one- hundred-twenty-seven 64-kword sectors (s29ns128n) and one hundred twenty-seven 32kword sectors (s29ns064n) ? sixteen banks (s29ns128n and s29ns256n) and eight banks (s29ns064n) ? high performance ? typical word programming time of 40 s ? typical effective word programming time of 9.4 s utilizing a 32-word write buffer at v cc level ? typical effective word programming time of 6 s utilizing a 32-word write buffer at acc level ? typical sector erase time of 150 ms for 16 kword sectors and 800 ms sector erase time for 64 kword sectors security features ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector using a user-defined 64-bit password ? hardware sector protection ? wp# protects the two highest sectors ? all sectors locked when acc = v il ? handshaking feature ? provides host system with minimum possible latency by monitoring rdy ? supports common flash memory interface (cfi) ? software command set compatible with jedec 42.4 standards ? backwards compatible with am29f and am29lv families ? manufactured on 110 nm mirrorbit tm process technology ? cycling endurance: 100,000 cycles per sector typical ? data retention: 20 years typical ? data# polling and toggle bits ? provides a software method of detecting program and erase operation completion ? erase suspend/resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? program suspend/resume ? suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ? packages ? 48-ball very thin fbga (s29ns256n) ? 44-ball very thin fbga (s29ns128n, s29ns064n) S29NS-N mirrorbit? flash family s29ns256n, s29n s128n, s29ns064n 256/128/64 megabit (16/8/4m x 16-bit), cmos 1.8 volt-only simultaneous read/write, multiplexed, burst mode flash memory data sheet (advance information)
2 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 1. general description the s29ns256n, s29ns128n and s29ns064n are 256 mb, 128 mb and 64mb (respectively), 1.8 volt-only, simultaneous read/write, burst mode flash memory devices, organized as 16, 777,216, 8,388,608, and 4,194,304 words of 16 bits each. these devices use a single v cc of 1.70 to 1.95 v to read, program, and erase the memory array. a 9.0-volt acc, may be us ed for faster program performance if desired. these devices can also be programmed in standard eprom programmers. the devices are offered at the following speeds: the devices operate within the temperature range of ?25 c to +85 c, and are offered in very thin fbga packages. 1.1 simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into sixteen banks. the device allows a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero lat ency. this releases the system from waiting for the completion of program or erase operations. the device s are structured as shown in the following tables: the versatileio? (v io ) control allows the host system to set the vo ltage levels that the device generates at its data outputs and the voltages tolera ted at its data inputs to the same vo ltage level that is asserted on the v ccq pin. the devices use chip enable (ce#), write enable (we# ), address valid (avd#) and output enable (oe#) to control asynchronous read and write operations. for bur st operations, the devices additionally require ready (rdy) and clock (clk). this implementation allo ws easy interface with minimal glue logic to microprocessors/microcontrollers for high performance read operations. the devices offer complete compatibility with the jedec 42.4 single-power-s upply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device are similar to reading from other flash or eprom devices. clock speed burst access (ns) synch. initial access (ns) asynch. initial access (ns) output loading 80 mhz 9 80 80 30 pf 66 mhz 11.0 80 80 s29ns256n bank 0-14 sectors bank 15 sectors quantity size quantity size 240 64 kwords 4 16 kwords 15 64 kwords 240 mb total 16 mb total s29ns128n bank 0-14 sectors bank 15 sectors quantity size quantity size 120 64 kwords 4 16 kwords 7 64 kwords 120 mb total 8 mb total s29ns064n bank 0-6 sectors bank 7 sectors quantity size quantity size 112 32 kwords 4 8 kwords 15 32 kwords 56 mbits 8 mbits
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 3 data sheet (advance information) the host system can detect whether a program or erase operation is complete by using the device status bit dq7 (data# polling) and dq 6/dq2 (toggle bits). afte r a program or erase cycle has been comp leted, the device automatically returns to reading array data. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the devices ar e fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the devices also offer thre e types of data protection at the sector level. persistent sector protection provides in-system, command-enabled protecti on of any combination of sectors using a single power supply at v cc . password sector protection prevents unauthorized wr ite and erase operations in any combination of sectors through a user-defined 64-bit password. when at v il , wp# locks the highest two sectors. finally, when acc is at v il , all sectors are locked. the devices offer two power-saving features. when add resses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm - an internal algorithm that automatic ally times the program pulse widths and verifies proper cell margin. the unlock bypass mode facilitates faster program times by requiring only two write cycles to program data inst ead of four. additionally, write buffer programming is available on this family of devices. this feature provides superior programmi ng performance by grouping locations being programmed. device erasure occurs by executing the er ase command sequence. this initiates the embedded erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already fully programmed) before executing the erase operation. duri ng erase, the device autom atically times the erase pulse widths and verifies proper cell margin. the program suspend/ program resume feature enables the user to put program on hold to read data from any sector that is not selected for programming. if a read is needed from the pe rsistent protection area, dynamic protection area, or the cfi area, after an program suspend, t hen the user must use the proper command sequence to enter and exit this region. the pr ogram suspend/resume functionality is also available when programming in erase suspend (1 level depth only). the erase suspend/erase resume feature enables the user to put erase on hold to read data from, or program data to, any sector that is not selected for erasure. true background eras e can thus be achieved. if a read is needed from the persistent protection area, dynamic protection area, or the cfi area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitr y. a system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the flash memory device. the host system can detect wh ether a memory array program or erase operation is comple te by using the device status bit dq7 (data# polli ng), dq6/dq2 (toggle bits), dq5 (exc eeded timing limit), dq3 (sector erase start timeout state indicator), and dq1 (write to bu ffer abort). after a program or erase cycle has been completed, the device automatical ly returns to reading array data. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory . hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the device also offers two type s of data protection at the sector level. when at v il , wp# locks the two outermost boot sectors at the top of memory. when the acc pin = v il , the entire flash memory array is protected. spansion llc flash technology combines years of fl ash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective ness. the device electrically erases all bits within a sector. the data is programmed using hot electron injection.
4 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 simultaneous read/write operations with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. block diagram of simu ltaneous operation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5. connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 s29ns256n ? 48-ball very thin fbga connection diagr am. . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 s29ns128n ? 48-ball very thin fbga connection diagr am. . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 s29ns064n ? 44-ball very thin fbga connection diagr am. . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 special package handling instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8. device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 versatileio? (v io ) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2 requirements for asynchronous read operation (non-burs t) . . . . . . . . . . . . . . . . . . . . . . . 14 8.3 requirements for synchronous (burst) read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.4 programmable wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.5 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.6 handshaking feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.7 simultaneous read/write operations with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.8 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.9 accelerated program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.10 write buffer programming operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.11 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.12 advanced sector protection and unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.13 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.14 persistent sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.15 persistent sector protection mode lock bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.16 password sector protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.17 64-bit password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.18 password mode lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.19 persistent protection bit lock (ppb lock bit) in password sector protection mode . . . . . . 23 8.20 hardware data protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.21 wp# boot sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.22 low vcc write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.23 write pulse ?glitch? protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.24 logical inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.25 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.26 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.27 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.28 reset#: hardware reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 8.29 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.30 secured silicon sector sectorflash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9. common flash memory interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 set configuration register command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.3 read configuration register command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 5 data sheet (advance information) 11. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.3 enter/exit secured silicon sector command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.4 program command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.5 accelerated program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.6 write buffer programming command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.7 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.8 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.9 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.10 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.11 lock register command set definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.12 password protection command set definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.13 non-volatile sector protection comm and set definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.14 global volatile sector pr otection freeze command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.15 volatile sector protection command set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.2 rdy: ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.4 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.5 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.6 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.7 dq3: sector erase start timeout state indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.8 dq1: write to buffer abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 15. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 15.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17. key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 18. switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 19. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19.1 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19.2 synchronous/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 19.3 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19.4 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 19.5 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 20. erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 21. bga ball capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 22. physical dimensions (s29ns256n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 22.1 vdc048?48-ball very thin fine-pitch ball gr id array (fbga) 11 x 10 mm package. . . . . 77 23. physical dimensions (s29ns128n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 23.1 vdd044?44-ball very thin fine-pitch ball grid array (fbga) 9.2 x 8 mm package . . . . . 78 23.2 vde044?44-ball very thin fine-pitch ball grid array (fbga) 7.7 x 6.2mm package . . . . 79 24. revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 24.1 revision a (april 16, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 24.2 revision a1 (june 28, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 24.3 revision a2 (september 9, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 24.4 revision a3 (november 16, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 24.5 revision a3a (april 5, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 24.6 revision a4 (april 12, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 24.7 revision a5 (august 15, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 24.8 revision a6 (august 24, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 24.9 revision a7 (september 16, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 24.10 revision a8 (september 23, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 24.11 revision a9 (november 15, 2005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 24.12 revision a10 (march 23, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 24.13 revision a11 (april 20, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 24.14 revision a12 (june 13, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 7 data sheet (advance information) 2. product selector guide 3. block diagram note a max indicates the highest order address bit. a max equals a23 for ns256n, and a22 for ns128n and a21 for s29ns064n. description s29ns256n, s29ns128n, s29ns064n burst frequency 80 mhz 66 mhz max initial synchronous access time, ns (t iacc )8080 max burst access time, ns (t bacc ) 9 11.0 max asynchronous access time, ns (t acc ) 80 80 max ce# access time, ns (t ce ) max oe# access time, ns (t oe ) 9 11.0 inp u t/o u tp u t b u ffer s x-decoder y-decoder chip en ab le o u tp u t en ab le logic er as e volt a ge gener a tor pgm volt a ge gener a tor timer v cc detector s t a te control comm a nd regi s ter v ccq v cc v ss we# re s et# acc ce# oe# a/dq15?a/dq0 d a t a l a tch y-g a ting cell m a trix addre ss l a tch a/dq15?a/dq0 rdy b u ffer rdy b u r s t s t a te control b u r s t addre ss co u nter avd# clk a m a x ?a0 wp# a m a x ?a16
8 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 4. block diagram of simultaneous operation circuit notes 1. a15?a0 are multiplexed with dq15?dq0. 2. amax indicates the highest order address bit. a23 (ns256n), a22 (ns128n), and a21 (ns064n). 3. n = 15 for ns256n and ns128n, n = 7 for ns064n. v cc v ss v ssq bank address reset# we# ce# avd# dq15?dq0 clk state control & command register bank 1 x-decoder y-decoder latches and control logic bank 0 x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15? dq0 bank n-1 y-decoder x-decoder latches and control logic bank n y-decoder x-decoder latches and control logic oe# oe# oe# oe# status control a max ?a0 a max ?a0 a max ?a0 a max ?a0 a max ?a0 bank address bank address bank address rdy v ccq acc ( note 4 ) wp#
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 9 data sheet (advance information) 5. connection diagram 5.1 s29ns256n ? 48-ball very thin fbga connection diagram a1 rdy a2 a21 a3 v ss a4 clk a5 v cc a6 we# a7 acc a8 a19 a9 a17 a10 a22 b1 v ccq b2 a16 b3 a20 b4 avd# b5 a23 b6 reset# b7 wp# b8 a18 b9 ce# b10 v ssq c1 v ss c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 v ssq d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v ccq d9 a/dq1 d10 a/dq0 nc nc nc nc nc nc nc nc s29ns256n 48-ball very thin fbga top view, balls facing down
10 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 5.2 s29ns128n ? 48-ball very thin fbga connection diagram a1 rdy a2 a21 a3 v ss a4 clk a5 v cc a6 we# a7 acc a8 a19 a9 a17 a10 a22 b1 v ccq b2 a16 b3 a20 b4 avd# b5 nc b6 reset# b7 wp# b8 a18 b9 ce# b10 v ssq v ss c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 v ssq d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v ccq d9 a/dq1 d10 a/dq0 nc nc nc nc c1 s29ns128n 44-ball very thin fbga top view, balls facing down
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 11 data sheet (advance information) 5.3 s29ns064n ? 44-ball very thin fbga connection diagram 5.4 special package handling instructions special handling is required for flash memory products in fbga packages.the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 rdy a2 a21 a3 v ss a4 clk a5 v cc a6 we# a7 acc a8 a19 a9 a17 a10 nc b1 v ccq b2 a16 b3 a20 b4 avd# b5 nc b6 reset# b7 wp# b8 a18 b9 ce# b10 v ssq v ss c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 v ssq d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v ccq d9 a/dq1 d10 a/dq0 nc nc nc nc c1 s29ns064n 44-ball very thin fbga top view, balls facing down
12 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 6. input/output descriptions a23?a16 = address inputs, s29ns256n a22?a16 = address inputs, s29ns128n a21-a16 = address inputs, s29ns064n a/dq15?a/dq0 = multiplexed address/data input/output ce# = chip enable input. asynchronous relative to clk for the burst mode oe# = output enable input. asynchronous relative to clk for the burst mode we# = write enable input v cc = device power supply (1.70v?1.95v) v ccq = input/output power supply (1.70v?1.95v) v ss = ground v ssq = input/output ground nc = no connect; not connected internally rdy = ready output; indicates the status of the burst read. v ol = data invalid. v oh = data valid clk = the first rising edge of clk in conjunction with avd# low latches address input and activates burst mode operation. after the initial word is output, subsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access avd# = address valid input. indicates to device that the valid address is present on the address inputs (address bits a15?a0 are multiplexed, address bits amax?a16 are address only) v il = for asynchronous mode, indicates vali d address; for burst mode, causes starting address to be latched on rising edge of clk. v ih = device ignores address inputs reset# = hardware reset input. v il = device resets and returns to reading array data wp# = hardware write protect input. v il = disables writes to sa257?258 (s29ns256n), sa129?130 (s29ns128n) or sa129-130 (s29ns064n). should be at v ih for all other conditions acc = at 9v, accelerates programming; automati cally places device in unlock bypass mode. at v il , disables program and erase functions. should be at v ih for all other conditions 6.1 logic symbol 5 to 8 a/dq15? a/dq0 a m a x - a16 ce# oe# we# re s et# clk rdy avd# wp# acc a m a x indic a te s the highe s t order a ddre ss b it. 16
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 13 data sheet (advance information) 7. ordering information the order number (valid combination) is formed by the following: 7.1 valid combinations consult the local sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. s29ns 256 n 0s bj w 00 0 packing type 0 = tray 2 = 7? tape and reel 3 = 13? tape and reel model number (dyb protect after power-up) 00 = dyb protect after power-up temperature range w = wireless (?25 c to +85 c) package type bj = very thin fine-pitch bga lead (pb)-free lf35 package speed option (burst frequency) 0s = 80 mhz 0p = 66 mhz process technology n = 110 nm mirrorbit tm te c h n o l o gy flash density 256 = 256 mb 128 = 128 mb 064 = 64 mb device family s29ns = 1.8 volt-only, simultaneous read/write, burst mode flash memory with multiplexed i/o interface s29nsxxxn valid combinations package marking speed options (mhz) package type base ordering part number package & temperature model number packing type (note 1 , 2 ) s29ns256n bjw 00 0, 2, 3 (note 1) ns256n0sbjw00 80 48-ball fbga 10mm x 11mm vcd048 ns256n0pbjw00 66 s29ns128n bjw 00 0, 2, 3 (note 1) ns128n0sbjw00 80 44-ball fbga 9.2mm x 8.0mm vdd044 ns128n0pbjw00 66 s29ns064n bjw 00 0, 2, 3 (note 1) ns064n0sbjw00 80 44-ball fbga 7.7mm x 6.2mm vde044 ns064n0pbjw00 66
14 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 8. device bus operations this section describes the requiremen ts and use of the device bus operati ons, which are initiated through the internal command register. the command register itse lf does not occupy any add ressable memory location. the register is composed of latc hes that store the commands, along with the address and data information needed to execute the command. the cont ents of the register serve as inputs to the internal state machine. the state machine output s dictate the function of the device. table 8.1 lists the device bus operations, the inputs and control levels they require, and the resu lting output. the following subsections describe each of these operations in further detail. legend l = logic 0, h = logic 1, x = don?t care. note terminating the current burst cycle is determined by the falling edge of avd#, while starting a new burst read cycle is determi ned by the rising edge of avd#. 8.1 versatileio? (v io ) control the versatileio (v io ) control allows the host system to set the vo ltage levels that the device generates at its data outputs and the voltages tolerated at its data inpu ts to the same voltage level that is asserted on the v ccq pin. 8.2 requirements for asynchronous read operation (non-burst) to read data from the memory array, t he system must assert a valid address on a max ?a16 and a/dq15?a/ dq0 while avd# and ce# are at v il . we# should remain at v ih . note that clk must remain at v il during asynchronous read operations. the rising edge of av d# latches the address, af ter which the system can drive oe# to v il . the data will appear on a/dq15?a/dq0. (see figure 19.4 on page 67 .) since the memory array is divided into banks, each bank remains enabled for read access until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and st able ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memo ry content occurs during the power transition. table 8.1 device bus operations operation ce# oe# we# a max ?16 a/dq15?0 reset# clk avd# asynchronous read l l h addr in i/o h l write l h l addr in i/o h h/l standby (ce#) h x x x high z h h/l x hardware reset x x x x high z l x x burst read operations load starting burst address l h h addr in addr in h advance burst to next address with appropriate data presented on the data bus llh x burst data out hh terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle lhh x i/o h
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 15 data sheet (advance information) 8.3 requirements for synchronous (burst) read operation the device is capable of seven different burst read m odes: continuous burst read; 8-, 16-, and 32-word linear burst reads with wrap around; and 8-, 16-, and 32- word linear burst reads without wrap around. 8.3.1 continuous burst when the device first powers up, it is enabled for asyn chronous read operation. the device is automatically enabled for burst mode and addresses are latched on the fi rst rising edge of clk input, while avd# is held low for one clock cycle. prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (t iacc ) of each burst session. the system would t hen write the set conf iguration register command sequence. the initial word is output t iacc after the rising edge of the first cl k cycle. subsequent words are output t bacc after the rising edge of each successive clock cycle, which automatically increments the internal address counter. note that the device has a fixed internal ad dress boundary that occurs every 128 words, starting at address 00007fh. the transition from the highest address 7fffff h to 000000h is also a boundary crossing . during a boundary crossing, there is a no add itional latency between the valid read at address 00007f and the valid read at address 000080 (or between addresses offset from these values by the same multiple of 128 words) for frequencies equal to or lower than 66 mhz. for frequencies higher than 66 mhz, there is a latency of 1 cycle. during the time the device is output ting data with the starting burst addre ss not divisible by four, additional waits are required. the rdy output indicates this condition to the system by deasserting. table 8.2 through table 8.5 shows the address latency as a function of variable wait states. table 8.2 address latency for 7, 6, and 5 wait states word 0 7, 6, and 5 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 table 8.3 address latency for 4 wait states word 0 4 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8d9 2 d2 d3 1 ws d4 d5 d6 d7 d8 d9 3 d3 1 ws 1 ws d4 d5 d6 d7 d8 d9 table 8.4 address latency for 3 wait states word 0 3 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8 d9 2 d2d3d4d5d6d7d8d9 d10 3 d3 1 ws d4 d5 d6 d7 d8 d9 d10
16 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) table 8.6 through table 8.8 show the address/boundary crossing late ncy for variable wait state if a boundary crossing occurs during initial access the device will continue to output continuous, s equential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location , until the system asserts ce# high, reset# low, or avd# low in conjunction with a new address. see table 8.1 on page 14 . the reset command does not terminate the burst read operation. if the host system crosses a 128 word line boundary while reading in burst mode, and the device is not programming or erasing, no additional latency will o ccur as described above. if the host system crosses the bank boundary while the device is programming or erasing, the device will provide asynchronous read status information. the clock will be ignored. after the host has completed status reads, or the device has completed the program or erase operation, t he host can restart a burst operation using a new address and avd# pulse. table 8.5 address latency for 2 wait states word 0 2 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8 d9 2 d2d3d4d5d6d7d8d9 d10 3 d3d4d5d6d7d8d9d10d11 table 8.6 address/boundary crossing latency for 7, 6, and 5 wait states word 0 7, 6, and 5 ws d0 d1 d2 d3 1 ws d4 d5 d6 d7 1 d1 d2 d3 1 ws 1 ws d4 d5 d6 d7 2 d2 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 3 d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 d7 table 8.7 address/boundary crossing latency for 4 wait states word 0 4 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 figure 8.1 address/boundary crossing latency for 3 wait states word 0 3 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2 d3 d4d5d6d7d8 d9 2 d2 d3 1 ws d4 d5 d6 d7 d8 d9 3 d3 1 ws 1 ws d4 d5 d6 d7 d8 d9 table 8.8 address/boundary crossing latency for 2 wait states word 0 2 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3d4d5d6d7d8 d9 2 d2 d3 d4d5d6d7d8d9 d10 3 d3 1 ws d4 d5 d6 d7 d8 d9 d10
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 17 data sheet (advance information) 8.3.2 8-, 16-, and 32-word li near burst with wrap around these three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burs t addresses read are determined by the group within which the starting address falls. the groups are sized acco rding to the number of words read in a single burst sequence for a given mode (see table 8.9 .) as an example: if the starting address in the 8-word mode is 3ah, and the burst sequence would be 3a-3b- 3c-3d-3e-3f-38-39h. the burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address written to the device, and then wraps back to the first address in the selected address group and terminates the burst read. note that in these three burst read modes the address pointer does not cross the boundary that occurs every 128 words; thus, no wait states are inserted (exc ept during the initial access). 8.3.3 8-, 16-, and 32-word linear burst without wrap around in these modes, a fixed number of words (predefined as 8, 16, or 32 words) are read from consecutive addresses starting with the initial word, which is written to the device. when the address is at the end of the group address range (see burst address groups table) , the burst read operation stops and the rdy output goes low. there is no group limit ation and is different from th e linear burst with wrap around. as an example, for 8-word length bu rst read, if the starting address writ ten to the device is 3a, the burst sequence would be 3a-3b-3c-3d-3e-3f-40-41h, and th e read operation will be terminated after all eight words. the 16-word and 32-word modes would operate in a similar fashion and continuously read to the predefined 16 or 32 words accordingly. note: in this burst read mode, the address pointer may cross the boundary that occurs every 128 words. 8.4 programmable wait state the programmable wait state feature in dicates to the device the number of additional clock cycles that must elapse after avd# is driven active before data will be available. upon power up, the device defaults to the maximum of seven tota l cycles. the total number of wait states is programmable from two to seven cycles. for further details, see set configuration register command sequence on page 37 . 8.5 configuration register the device uses a configuration register to set the va rious burst parameters: num ber of wait states, burst read mode, burst length, rdy configuration, and synchronous mode active. 8.6 handshaking feature the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial word of burst data is ready to be read. the host system should use the configuration register to set the number of wait states for optimal burst mode oper ation. the initial word of burst data is indicated by the rising edge of rdy after oe# goes low. table 8.9 burst address groups mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h, 18-1fh... 16-word 16 words 0-fh, 10-1fh, 20-2fh, 30-3fh... 32-word 32 words 00-1fh, 20-3fh, 40-5fh, 60-7fh...
18 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 8.7 simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in one of the other banks of memory. an erase operation may also be suspended to read from or program to another location within the same bank (e xcept the sector being erased). figure 19.13 on page 75 shows how read and write cycles may be initiated for simultaneous op eration with zero latency. refer to the table dc characteristics on page 62 for read-while-program and read-while-erase current specifications. 8.8 writing commands/command sequences the device has inputs/outputs that accept both addr ess and data information. to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih . when writing commands or data. the device features an unlock bypass mode to facilitate faster programm ing. once the device enters the unlock bypass mode, only two wr ite cycles are required to progr am a word, instead of four. an erase operation can erase one sector, multiple sect ors, or the entire device. table 14-17 indicates the address space that each sector occupies. the device address space is divided into multiple banks. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. refer to the dc characteristics table for writ e mode current specifications. the section ac characteristics on page 64 contains timing specification tables and timing diagrams for write operations. 8.9 accelerated program and erase operations the device offers accelerated program and erase oper ation through the acc func tion. acc is primarily intended to allow faster manufacturing throughput at the factory and not to be used in system operations. if the system asserts v hh on this input, the device automatica lly enters the aforementioned unlock bypass mode and uses the higher voltage on the input to redu ce the time required for program and erase operations. the system can then use the abb reviated embedded programming command and write buffer load command sequence provided by the unlock bypass mode. note that if a ?write-to-buffer-abort reset? is required while in unlock bypass mode, the full 3-cycle reset command sequ ence must be used to reset the device . removing v hh from the acc input, upon completion of the embedded program or erase operation, returns the device to normal operation. note that sectors must be unlocked prior to raising acc to v hh . note that the acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. in addition, the acc pin must not be left floating or unconnected; inconsistent behavior of the device may result . when at v il , acc locks all sectors. acc should be at v ih for all other conditions. 8.10 write buffer programming operation write buffer programming allows the system to write a maximum of 32 words in one programming operation. this results in a faster effective word programming time than the standard ?word? programming algorithms. the write buffer progra mming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the wr ite buffer load command wri tten at the sector address in which programming will occur. at this point, the system writes the number of ? word locations minus 1 ? that will be loaded into the page buffer at the sector address in which programming will occur. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the ?program buffer to flash? confirm command. the number of locati ons to program cannot exceed the size of the write buffer or the operation will abort. (note: the number lo aded = the number of locations to program minus 1. for example, if the system will program 6 address lo cations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starti ng address is the first address/data pair to be programmed, and selects the ?write-buffe r-page? address. all subs equent address/data pairs must fall within the ?selected-wr ite-buffer-page?, and be loaded in sequential order. the ?write-buffer-page? is selected by using the addresses a max -a5 where a max is a23 for s29ns256n, a22 for s29ns128n and a21 for s29ns064n.
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 19 data sheet (advance information) the ?write-buffer-page? addresses must be the same for all address/ data pairs loaded into the write buffer . (this means write buffer programming cannot be performed across multip le ?write-buffer-pages?. this also means that wr ite buffer programming cannot be performed across multip le sectors. if the system attempts to load programming data outside of the selected ?write-buffer-page?, the operation will abort.) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. write buffer locations must be loaded in sequential order. note that if a write buffer address location is loaded multiple times, the ?address/data pair? counter will be decremented for every data load operation . also, the last data loaded at a location before the ?program buffer to flash? confirm command will be programmed into the device. it is the software?s responsibility to comprehend ramifications of loading a write-buffer location more than once. the counter decrements for each data load operation , not for each unique writ e-buffer-address location . once the specified number of writ e buffer locations have been load ed, the system must then write the ?program buffer to flash? command at the sector address. any other address/data write combinations will abort the write buffer programmi ng operation. the device will then ?go busy?. the data bar polling techniques should be used while monitoring the last address location lo aded into the write buffer . this eliminates the need to store an address in memory beca use the system can load the last address location, issue the program confirm command at the last loaded add ress location, and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be mo nitored to determine the de vice status during write buffer programming. the write-buffer ?embedded? progra mming operation can be suspended using the standard suspend/resume commands. upon successful completion of the write buffer programming operation, the device will return to read mode. the write buffer programming sequence can be abo rted under any of the following conditions: ? load a value that is greater than the page buffer size during the ?number of locations to program? step. ? write to an address in a sector different than the one specified during the ?write-buffer-load? command. ? write an address/data pair to a different write-buffe r-page than the one selected by the ?starting address? during the ?write buffer data loading? stage of the operation. ? write data other than the ?confirm command? after the specified number of ?data load? cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the ?last address location loaded?), dq6 = toggle, dq5 = 0. this indicates that the write bu ffer programming operation was aborted. a ?write-to- buffer-abort reset? command sequence is required when using the write-buffer-programming features in unlock bypass mode. note: the secured silicon se ctor, autoselect, and cfi functions are unavailable when a program operation is in progress . use of the write buffer is strongly recommended for programming when multiple words are to be programmed . write buffer programming is allowed in any sequence of memory (or address) locations. these flash devices are capable of handling mu ltiple write buffer programming oper ations on the same write buffer address range without intervening erases. however, pr ogramming the same word address multiple times without intervening erases requires a modified progra mming method. please contact your local spansion tm representative for details. 8.11 autoselect mode the autoselect mode provides manufa cturer and device identification, an d sector protection verification, through identifier codes out put from the internal register (which is separate from the memory array) on dq15? dq0. this mode is primarily intended for programmi ng equipment to automatically match a device to be programmed with its corresponding programming algori thm. the autoselect codes can also be accessed in- system. when verifying sector protection, the sector address must appear on the appropria te highest order address bits. the remaining address bits are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0. the autoselect codes can also be accessed in-system through the co mmand register. the command sequence is illustrated in table 11.4, command definitions on page 52 . note that if a bank address (ba) on address bits a23, a22, a21, and a20 for the ns256n, a22, a21, a20, a19 fo r the ns128n and a21, a20, and a19 for the ns064n, is asserted during the third write cycle of the autos elect command, the host system can read autos elect data that bank and then immediately read array data fr om the other bank, without exiting the autoselect mode.
20 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) to access the autoselect codes, the host system must issue the autoselect command via the command register, as shown in table 11.4, command definitions on page 52 . 8.12 advanced sector protection and unprotection this advanced security feature provides an additional level of protection to all sectors against inadvertent program or erase operations. the advanced sector protec tion feature disables both programming an d erase operations in any sector while the advanced sector unprotection feature re-enable s both program and erase operations in previously protected sectors. sector protecti on/unprotection can be implemented using either of the two methods ? hardware method ? software method persistent/password sector pr otection is achieved by using the softwa re method while the sector protection with wp# pin is achieved by using the hardware method. all parts default to operate in the pe rsistent sector protection mode. t he customer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non- volatile bits that define which se ctor protection method will be used. ? persistent mode lock bit ? password mode lock bit if the customer decides to continue using the persis tent sector protection method, they must set the persistent mode lock bit . this will permanently set the part to operate only using persistent sector protection. however, if t he customer decides to use the password se ctor protection method, they must set the password mode lock bit . this will permanently set the part to operate only using password sector protection. it is important to remember that setting either the persistent mode lock bit or the password mode lock bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit has been set. it is important that one mode is explici tly selected when the device is first programmed, rather than relying on the default mode alone. if both are selected to be set at the same time, the operation will abort. this is done so that it is not possible fo r a system program or virus to later set the password mode locking bit, which would cause an un expected shift from the default persistent sector protection mode into the passw ord sector protection mode. the device is shipped with all sectors unprotected. sp ansion offers the option of programming and protecting sectors at the factory prior to shipping the device through spansion programming services. contact an spansion representative for details. 8.13 sector protection the device features several levels of sector protection, which can di sable both the program and erase operations in certain sectors. ? persistent sector protection a software enabled command sector protection method that replaces the old 12 v controlled protection method. ? password sector protection a highly sophisticated software enabled protection method that requires a password before changes to certain sectors or sector groups are permitted ? wp# hardware protection a write protect pin (wp#) can prevent program or er ase operations in the outermost sectors.the wp# hardware protection feature is always available, i ndependent of the software managed protection method chosen.
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 21 data sheet (advance information) 8.14 persistent sector protection the persistent sector protection me thod replaces the old 12 v controll ed protection method while at the same time enhancing flexibility by providing three different sector protection states: ? persistently locked ?a sector is protected and cannot be changed. ? dynamically locked ?the sector is protected and can be changed by a simple command ? unlocked ?the sector is unprotected and can be changed by a simple command in order to achieve these states, three types of ?b its? namely persistent pr otection bit (ppb), dynamic protection bit (dyb), and pers istent protection bit lock (ppb lock) ar e used to achieve the desired sector protection scheme: 8.14.1 persistent pr otection bit (ppb) ppb is used to as an advanced secu rity feature to protec t individual sectors from being programmed or erased thereby providing additional level of protection. every sector is assigned a persistent protection bit. each ppb is individually programmed through the ppb program command . however all ppbs are erased in parallel through the all ppb erase command . prior to erasing, these bits don?t have to be pre programmed. the embedded erase algorithm automatically preprograms and verifies prior to an electrical erase. the system is not required to provide any controls or timings during these operations. the ppbs retain their st ate across power cycles because they ar e non-volatile. the ppbs has the same endurance as the flash memory. 8.14.2 persistent protection bit lock (ppb lock bit) in pe rsistent sector protection mode ppb lock bit is a global volatile bit and provides an add itional level of protection to the sectors. when programmed (set to ?0?) , all the ppbs are locked and hence none of them can be changed. when erased (cleared to ?1?) , the ppbs are changeable. there is only one ppb lock bit in every device. only a hardware reset or a power-up clears the ppb lock bit. it is to be noted that there is no software solution, i.e. command sequence to unlock the ppb lock bit. once all ppbs are configured to the desired settings, the ppb lock bit ma y be set (programmed to ?0?). the ppb lock bit is set by issuing th e ppb lock bit set command. programmi ng or setting the ppb lock bit disables program and eras e commands to all the ppbs. in effect, t he ppb lock bit locks t he ppbs into their current state. the only way to clear the ppb lock bit is to go through a hardware or power-up reset. system boot code can determine if any changes to the ppb are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can disable the ppb lock bit to prevent any further changes to the ppbs during system operation. 8.14.3 dynamic protection bit (dyb) dyb is a security feature used to protect individual sect ors from being programmed or erased inadvertently. it is a volatile protection bit and is assigned to each sect or. upon power-up, the contents of all dybs are set (programmed to ?0?). each dyb can be individually modified through the dyb set command or the dyb clear command. the protection status for a particular sector is determ ined by the status of the ppb and the dyb relative to that sector. for the sector s that have the ppbs cleared (erased to ?1 ?), the dybs control whether or not the sector is protected or unprotected. by issuing the dyb set or clear command sequences, the dybs will be set (programmed to ?0?) or cleared (e rased to ?1?), thus placing each sect or in the protected or unprotected state respectively. these states are the so-called dynam ic locked or unlocked states due to the fact that they can switch back and forth betwe en the protected and unprot ected states. this feature allows software to easily protect sectors against inadvertent changes ye t does not prevent the easy removal of protection when changes are needed. the dybs maybe set (programmed to ?0?) or cleared (erase d to ?1?) as often as needed. when the parts are first shipped, the ppbs are cleared (e rased to ?1?) and upon power up or reset, the dybs are set (programmed to ?0?). the ppb lock bit defaults to the cleared stat e (erased to ?1?) after power up and the ppbs retain their previous state as they are non-volatile.
22 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) note: dynamic protection bits revert back to their defa ult values after programming device?s ?lock register.? it is possible to have sectors that hav e been persistently locked, and sectors th at are left in the dynamic state. the sectors in the dynamic state are al l unprotected. if there is a need to protect some of them, a simple dyb set command sequence is all that is necessary. the dyb set or clear command for the dynamic sectors signify protected or unprotected stat e of the sectors respectively. however, if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a powe r-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. note: to achieve the best protection, it?s recommen ded to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . note that the ppb and dyb bits have the same function when acc = v hh as they do when acc = v ih . table 8.10 contains all possible combinatio ns of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set (progra mmed to ?0?), and the ppb lo ck is set (programmed to ?0?), the sector is protected and the prot ection can not be removed unti l the next power cycle clears (erase to ?1?) the ppb lock bit. once the ppb lock bit is clear ed (erased to ?1?), the sector can be persistently lock ed or unlocked. likewise, if both ppb lock bit or ppb is cleared (erased to ?1?) the sect or can then be dynamically locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector , the device ignores the command and returns to read mode. a program or erase command to a protec ted sector enables status polling and returns to read mode without having modified the c ontents of the protected sector. the programming of the dyb, ppb, a nd ppb lock for a given sector can be verified by writing individual status read commands dyb status, ppb status, and ppb lock status to the device. 8.15 persistent sector protection mode lock bit a persistent mode lock bit exists to guarantee that the device remain in software sector protection. once programmed (set to ?0?), the persistent mode lock bi t prevents programming of the password mode lock bit. this guarantees that now, a hacker cannot plac e the device in password sector protection mode. 8.16 password sector protection the password sector protection mode method allows an even higher level of securi ty than the persistent sector protection mode. there are two main differenc es between the persistent sector protection mode and the password sector protection mode: ? when the device is first powered up, or comes out of a reset cycle, the ppb lock bit is set to the locked state , rather than cleared to the unlocked state. ? the only means to clear the ppb lo ck bit is by writing a unique 64-bit password to the device. the password sector protection meth od is otherwise identical to the persistent sector protection method. a 64-bit password is the only additi onal tool utilized in this method. table 8.10 sector protection schemes dyb ppb ppb lock sector state 1 1 1 sector unprotected 0 1 1 sector protected through dyb 1 0 1 sector protected through ppb 0 0 1 sector protected through ppb and dyb 1 1 0 sector unprotected 0 1 0 sector protected through dyb 1 0 0 sector protected through ppb 0 0 0 sector protected through ppb and dyb
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 23 data sheet (advance information) the password is stored in a one-time programmable (otp) region of the flash memory. once the password mode lock bit is set, the password is permanently se t with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally co mpares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 1 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 8.17 64-bit password the 64-bit password is located in a non-erasable region of the flash and is accessible through the use of the password program and verify commands (see password protection command set definitions on page 48 ). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify command from reading the cont ents of the password on the pins of the device. 8.18 password mode lock bit in order to select the password se ctor protection scheme, the customer must first program the password. spansion llc recommends that the password be so mehow correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. whil e programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the cust omer must then set the password mode locking bit. this operation achieves two objectives: ? it permanently sets the device to operate using the pa ssword sector protection mode. it is not possible to reverse this function. ? it also disables all further commands to the password region. all program and read operations are ignored. both of these objectives are important, and if not care fully considered, may lead to unrecoverable errors. the user must be sure that the password sector protecti on method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode lock bit, there will be no way to clear the ppb lock bit. the password mode lock bit, once set, prevents read ing the 64-bit password on the dq bus and further password programming. the password mode lock bit is not erasable. once password mode lock bit is programmed, the persistent mode lock bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 8.19 persistent protection bit lock (ppb lock bit) in password sector protection mode the persistent protection bit lock (ppb lock bit) is a volatile bit that reflects the state of the password mode lock bit after power-up reset. if the password mode lock bit is also set, after a hard ware reset (reset# asserted) or a power-up reset, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock co mmand. successful execution of t he password unlock command to enter the entire password clears the ppb lock bit, allowing for sector ppbs modificati ons. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1?. if the password mode lock bit is not set (device is oper ating in the default persiste nt protection mode). the password unlock command is ignored in persistent sector protection mode.
24 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 8.20 hardware data protection mode the device offers two types of data protection at the sector level: 1. when wp# is at v il , the two outermost sectors at the top are locked (device specific). 1. when acc is at v il , all sectors are locked. sa257 and sa258 are locked (s29ns256n) sa129 and sa130 are locked (s29ns128n) sa129 and sa130 are locked (s29ns064n) the write protect pin (wp#) adds a final level of hardwa re program and erase protec tion to the boot sectors. the boot sectors are the two sectors containing the hi ghest set of addresses in these top-boot-configured devices. for the none boot option, the wp # hardware feature is not available. when this pin is low it is not possible to change the cont ents of these top sectors. these sectors generally hold system boot code. so, the wp# pin can prevent any changes to the boot co de that could override the choices made while setting up sector protection duri ng system initialization. the following hardware data protection measures prev ent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. 8.20.1 write protect (wp#) the write protect feature provides a hardware method of protecting the tw o outermost sectors. this function is provided by the wp# pin and overrides the previous ly discussed sector protection/unprotection method. if the system asserts v il on the wp# pin, the device disables program and erase functions in the ?top? boot sectors. if the system asserts v ih on the wp# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector pr otection or unprotection for these sectors depends on whether they were last protected or unprotected. 8.21 wp# boot sector protection the wp# signal will be latched at a specific time in the embedded program or erase sequence. to prevent a write to the top two sectors, wp# must be asserted (wp#=v il ) on the last write cycle of the embedded sequence (i.e., 4th write cycle in embedded program, 6th write cycle in embedded erase). if selecting multiple sectors for eras ure: the wp# protection status is latc hed only on the 6th write cycle of the embedded sector erase command sequence when the firs t sector is selected. if additional sectors are selected for erasure, they are subject to the wp# st atus that was latched on the 6th write cycle of the command sequence. note that the wp# pin must not be left floating or unconnected; inconsistent behavior of the device may result. 8.22 low vcc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when vcc is greater than vlko. 8.23 write pulse ?glitch? protection noise pulses of less than t wep on we# do not initiate a write cycle. 8.24 logical inhibit write cycles are inhi bited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one.
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 25 data sheet (advance information) 8.24.1 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device d oes not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up 8.25 lock register the lock register consists of 3 bits. each of thes e bits are non-volatile and read-only. dq15-dq3 are reserved and are undefined. note when the device lock register is programmed (ppb mode lock bit is programmed, password mode lock bit programmed, or the secured silicon lock bit is programmed) all dybs revert to the power-on default state. 8.26 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when t he ce# and reset# inputs are both held at v cc . the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. 8.27 automatic sleep mode the automatic sleep mode minimizes flash device energ y consumption. the device automatically enters this mode when addresses and clock remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad dress access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. 8.28 reset#: hardware reset input the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, and ignores all read/write commands for th e duration of the reset# pulse. the device also resets the internal state machine to reading arra y data. the operation that was interrupted should be reinitiated once the device is ready to accept a nother command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss , the standby current will be greater. reset# may be tied to the system reset circuitry. a syst em reset would thus also reset the flash memory, enabling the system to read the boot -up firmware from the flash memory. refer to the ac characteristics tables for reset# parameters and to figure 19.5 on page 68 for the timing diagram. 8.28.1 v cc power-up and power-down sequencing the device imposes no restrictions on v cc power-up or power-down sequencing. asserting reset# to v il is required during the entire v cc power sequence until the respective s upplies reach their operating voltages. once v cc attains its operating voltage, de-assertion of reset# to v ih is permitted. table 8.11 lock register dq15-dq3 dq2 dq1 dq0 undefined password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit
26 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 8.29 output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. 8.30 secured silicon sector sector flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 words in length. all reads outside of the 256 word address range will return non-valid data. the factory indicator bit (dq7) is used to indicate whether or not the factory secured si licon sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secured silicon sector is locked when shipped from the factory. the factory secu red silicon bits are permanently set at the factory and cannot be changed, which prevents cloning of a fact ory locked part. this ensures the security of the esn and customer code once the product is shipped to the field. spansion offers the device with a factory secured sili con sector that is locked and a customer secured silicon sector that is either locked or is lockable. the factory secured silicon sector is always protected when shipped from the factory, and has the factory indicator bit (dq7) permanently set to a ?1?. the customer secured silicon sector is shipped unprotecte d, allowing customers to utilize that sector in any manner they choose. once the customer secured silic on sector area is protected, the customer indicator bit will be permanently set to ?1.? the system accesses the secured silicon sector through a command sequence (see enter/exit secured silicon sector command sequence on page 40 ). after the system has writt en the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 of the memory array. this mo de of operation continues until the system issues the exit secured silicon sector command sequence, or unt il power is removed from the device. while secured silicon sector access is enabled, memory array read acce ss, program operations, and erase operations to all sectors other than sa0 are also available. on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. 8.30.1 factory locked: factor secured sili con sector programm ed and protected at the factory in a factory sector locked device, the factory secured s ilicon sector is protected when the device is shipped from the factory. the factory secured silicon sector cannot be modified in any way. the device is pre programmed with both a random number and a secure esn. the factory secured silicon sector is located at addresses 000000h?00007fh. the device is available pre programmed with one of the following: ? a random, secure esn only within the factor secured silicon sector ? customer code within the customer secure d silicon sector through the spansion tm programming services ? both a random, secure esn and customer code through the spansion tm programming services. customers may opt to have their code pr ogrammed by spansion through the spansion tm programming services. spansion programs the customer?s code, with or without the random esn. the devices are then shipped from spansion?s factory with the factory secu red silicon sector and customer secured silicon sector permanently locked. contact an spansion representative for detai ls on using spansion?s spansion tm programming services. table 8.12 secured silicon sector secure sector addresses sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 27 data sheet (advance information) 8.30.2 customer s ecured silicon sector if the security feature is not required, the custom er secured silicon sector secure sector can be treated as an additional flash memory space. the customer secure d silicon sector can be read any number of times, but can be programmed and locked only once. note t hat the accelerated programming (acc) and unlock bypass functions are not available when programming the customer secur ed silicon sector, but reading the first bank through the last bank is available. the cu stomer secured silicon sector is located at addresses 000080h?0000ffh. the customer secured silicon sector area can be protected by writing the secured s ilicon sector protection bit lock command sequence. once the customer secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing sa0 in the memory array. the customer secured silicon sector lock must be us ed with caution since, once locked, there is no procedure available for unlocking the customer secure d silicon sector area and none of the bits in the customer secured silicon sector memory space can be modified in any way. 9. common flash memory interface (cfi) the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device -independent, jedec id-independent, and forward- and backward-compatible for the specifie d flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h any time the device is ready to read array data. the system can re ad cfi information at the addresses given in tables 9.1 ? 9.5 . to terminate reading cfi data, the system must write the reset command. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi . alternatively, contact the local sales representative for copies of these documents. table 9.1 cfi query identification string addresses data description s29ns256n s29ns128n s29ns064n 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
28 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) table 9.2 system interface string addresses data description s29ns256n s29ns128n s29ns064n 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h acc min. voltage (00h = no acc pin present) refer to 4dh 1eh 0000h acc max. voltage (00h = no acc pin present) refer to 4eh 1fh 0006h typical timeout per single byte/word write 2 n s 20h 0009h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0003h max. timeout for byte/word write 2 n times typical 24h 0001h max. timeout for buffer write 2 n times typical 25h 0002h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 9.3 device geometry definition addresses data description s29ns256n s29ns128n s29ns064n 27h 0019h 0018h 0017h device size = 2n byte 28h 0001h flash device interface description (refer to cfi publication 100) 29h 0000h 2ah 0006h max. number of bytes in multi-byte write = 2n (00h = not supported) 2bh 0000h 2ch 0002h number of erase block regions within device 2dh 00feh 007eh 007eh erase block region 1 information (refer to the cfi specification or cfi publication 100) 2eh 0000h 0000h 0000h 2fh 0000h 0000h 0000h 30h 0002h 0002h 0001h 31h 0003h 0007h erase block region 2 information 32h 0000h 0000h 33h 0080h 0020h 34h 0000h 0000h 35h 0000h erase block region 3 information 36h 0000h 37h 0000h 38h 0000h 39h 0000h erase block region 4 information 3ah 0000h 3bh 0000h 3ch 0000h
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 29 data sheet (advance information) table 9.4 primary vendor-specific extended query addresses data description s29ns256n s29ns128n s29ns064n 40h 0050h query-unique ascii string ?pri? 41h 0052h 42h 0049h 43h 0031h major version number, ascii 44h 0034h minor version number, ascii 45h 0010h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2= to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 08 = advanced sector protection 4ah 00f0h 0078h 0070h simultaneous operation number of sectors in all banks except boot bank 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode 00 = not supported, 01 = supported 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3- d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3- d0: 100 mv 4fh 0003h top/bottom boot sector flag 0001h = top/middle boot device, 0002h = bottom boot device, 03h = top boot device 50h 0001h program suspend. 00h = not supported 51h 0001h unlock bypass 00 = not supported, 01 = supported 52h 0008h secured silicon sector (customer otp area) size 2n bytes 53h 0008h hardware reset low time-out during an embedded algorithm to read more mode maximum 2n ns 54h 0008h hardware reset low time-out during an embedded algorithm to read more mode maximum 2n ns 55h 0005h erase suspend time-out maximum 2n ns 56h 0005h program suspend time-out maximum 2n ns 57h 0010h 0010h 0008h bank organization: x = number of banks 58h 0010h 0008h 0010h bank 0 region information. x = number of sectors in banks 59h 0010h 0008h 0010h bank 1 region information. x = number of sectors in banks 5ah 0010h 0008h 0010h bank 2 region information. x = number of sectors in banks 5bh 0010h 0008h 0010h bank 3 region information. x = number of sectors in banks 5ch 0010h 0008h 0010h bank 4 region information. x = number of sectors in banks 5dh 0010h 0008h 0010h bank 5 region information. x = number of sectors in banks 5eh 0010h 0008h 0010h bank 6 region information. x = number of sectors in banks 5fh 0010h 0008h 0013h bank 7 region information. x = number of sectors in banks 60h 0010h 0008h 0000h bank 8 region information. x = number of sectors in banks 61h 0010h 0008h 0000h bank 9 region information. x = number of sectors in banks 62h 0010h 0008h 0000h bank 10 region information. x = number of sectors in banks 63h 0010h 0008h 0000h bank 11 region information. x = number of sectors in banks 64h 0010h 0008h 0000h bank 12 region information. x = number of sectors in banks 65h 0010h 0008h 0000h bank 13 region information. x = number of sectors in banks 66h 0010h 0008h 0000h bank 14 region information. x = number of sectors in banks 67h 0013h 000bh 0000h bank 15 region information. x = number of sectors in banks 68h 0002h process technology. 00h = 230nm, 01h = 170nm, 02h = 130nm/110nm
30 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) table 9.5 sector address table, s29ns256n (sheet 1 of 3) bank sector sector size address range bank sector sector size address range bank 0 sa0 64 kwords 000000h?00ffffh bank 2 sa32 64 kwords 200000h?20ffffh sa1 64 kwords 010000h?01ffffh sa33 64 kwords 210000h?21ffffh sa2 64 kwords 020000h?02ffffh sa34 64 kwords 220000h?22ffffh sa3 64 kwords 030000h?03ffffh sa35 64 kwords 230000h?23ffffh sa4 64 kwords 040000h?04ffffh sa36 64 kwords 240000h?24ffffh sa5 64 kwords 050000h?05ffffh sa37 64 kwords 250000h?25ffffh sa6 64 kwords 060000h?06ffffh sa38 64 kwords 260000h?26ffffh sa7 64 kwords 070000h?07ffffh sa39 64 kwords 270000h?27ffffh sa8 64 kwords 080000h?08ffffh sa40 64 kwords 280000h?28ffffh sa9 64 kwords 090000h?09ffffh sa41 64 kwords 290000h?29ffffh sa10 64 kwords 0a0000h?0affffh sa42 64 kwords 2a0000h?2affffh sa11 64 kwords 0b0000h?0bffffh sa43 64 kwords 2b0000h?2bffffh sa12 64 kwords 0c0000h?0cffffh sa44 64 kwords 2c0000h?2cffffh sa13 64 kwords 0d0000h?0dffffh sa45 64 kwords 2d0000h?2dffffh sa14 64 kwords 0e0000h?0effffh sa46 64 kwords 2e0000h?2effffh sa15 64 kwords 0f0000h?0fffffh sa47 64 kwords 2f0000h?2fffffh bank 1 sa16 64 kwords 100000h?10ffffh bank 3 sa48 64 kwords 300000h?30ffffh sa17 64 kwords 110000h?11ffffh sa49 64 kwords 310000h?31ffffh sa18 64 kwords 120000h?12ffffh sa50 64 kwords 320000h?32ffffh sa19 64 kwords 130000h?13ffffh sa51 64 kwords 330000h?33ffffh sa20 64 kwords 140000h?14ffffh sa52 64 kwords 340000h?34ffffh sa21 64 kwords 150000h?15ffffh sa53 64 kwords 350000h?35ffffh sa22 64 kwords 160000h?16ffffh sa54 64 kwords 360000h?36ffffh sa23 64 kwords 170000h?17ffffh sa55 64 kwords 370000h?37ffffh sa24 64 kwords 180000h?18ffffh sa56 64 kwords 380000h?38ffffh sa25 64 kwords 190000h?19ffffh sa57 64 kwords 390000h?39ffffh sa26 64 kwords 1a0000h?1affffh sa58 64 kwords 3a0000h?3affffh sa27 64 kwords 1b0000h?1bffffh sa59 64 kwords 3b0000h?3bffffh sa28 64 kwords 1c0000h?1cffffh sa60 64 kwords 3c0000h?3cffffh sa29 64 kwords 1d0000h?1dffffh sa61 64 kwords 3d0000h?3dffffh sa30 64 kwords 1e0000h?1effffh sa62 64 kwords 3e0000h?3effffh sa31 64 kwords 1f0000h?1fffffh sa63 64 kwords 3f0000h?3fffffh bank 4 sa64 64 kwords 400000h?40ffffh bank 6 sa96 64 k words 600000h?60ffffh sa65 64 kwords 410000h?41ffffh sa97 64 k words 610000h?61ffffh sa66 64 kwords 420000h?42ffffh sa98 64 k words 620000h?62ffffh sa67 64 kwords 430000h?43ffffh sa99 64 k words 630000h?63ffffh sa68 64 kwords 440000h?44ffffh sa100 64 k words 640000h?64ffffh sa69 64 kwords 450000h?45ffffh sa101 64 k words 650000h?65ffffh sa70 64 kwords 460000h?46ffffh sa102 64 k words 660000h?66ffffh sa71 64 kwords 470000h?47ffffh sa103 64 k words 670000h?67ffffh sa72 64 kwords 480000h?48ffffh sa104 64 k words 680000h?68ffffh sa73 64 kwords 490000h?49ffffh sa105 64 k words 690000h?69ffffh sa74 64 kwords 4a0000h?4affffh sa106 64 k words 6a0000h?6affffh sa75 64 kwords 4b0000h?4bffffh sa107 64 k words 6b0000h?6bffffh sa76 64 kwords 4c0000h?4cffffh sa108 64 k words 6c0000h?6cffffh sa77 64 kwords 4d0000h?4dffffh sa109 64 k words 6d0000h?6dffffh sa78 64 kwords 4e0000h?4effffh sa110 64 k words 6e0000h?6effffh sa79 64 kwords 4f0000h?4fffffh sa111 64 k words 6f0000h?6fffffh
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 31 data sheet (advance information) bank 5 sa80 64 kwords 500000h?50ffffh bank 7 sa112 64 k words 700000h?70ffffh sa81 64 kwords 510000h?51ffffh sa113 64 k words 710000h?71ffffh sa82 64 kwords 520000h?52ffffh sa114 64 k words 720000h?72ffffh sa83 64 kwords 530000h?53ffffh sa115 64 k words 730000h?73ffffh sa84 64 kwords 540000h?54ffffh sa116 64 k words 740000h?74ffffh sa85 64 kwords 550000h?55ffffh sa117 64 k words 750000h?75ffffh sa86 64 kwords 560000h?56ffffh sa118 64 k words 760000h?76ffffh sa87 64 kwords 570000h?57ffffh sa119 64 k words 770000h?77ffffh sa88 64 kwords 580000h?58ffffh sa120 64 k words 780000h?78ffffh sa89 64 kwords 590000h?59ffffh sa121 64 k words 790000h?79ffffh sa90 64 kwords 5a0000h?5affffh sa122 64 k words 7a0000h?7affffh sa91 64 kwords 5b0000h?5bffffh sa123 64 k words 7b0000h?7bffffh sa92 64 kwords 5c0000h?5cffffh sa124 64 k words 7c0000h?7cffffh sa93 64 kwords 5d0000h?5dffffh sa125 64 k words 7d0000h?7dffffh sa94 64 kwords 5e0000h?5effffh sa126 64 k words 7e0000h?7effffh sa95 64 kwords 5f0000h?5fffffh sa127 64 k words 7f0000h?7fffffh bank 8 sa128 64 kwords 800000h?80ffffh bank 10 sa160 64 kwords a00000h?a0ffffh sa129 64 kwords 810000h?81ffffh sa161 64 kwords a10000h?a1ffffh sa130 64 kwords 820000h?82ffffh sa162 64 kwords a20000h?a2ffffh sa131 64 kwords 830000h?83ffffh sa163 64 kwords a30000h?a3ffffh sa132 64 kwords 840000h?84ffffh sa164 64 kwords a40000h?a4ffffh sa133 64 kwords 850000h?85ffffh sa165 64 kwords a50000h?a5ffffh sa134 64 kwords 860000h?86ffffh sa166 64 kwords a60000h?a6ffffh sa135 64 kwords 870000h?87ffffh sa167 64 kwords a70000h?a7ffffh sa136 64 kwords 880000h?88ffffh sa168 64 kwords a80000h?a8ffffh sa137 64 kwords 890000h?89ffffh sa169 64 kwords a90000h?a9ffffh sa138 64 kwords 8a0000h?8affffh sa170 64 kwords aa0000h?aaffffh sa139 64 kwords 8b0000h?8bffffh sa171 64 kwords ab0000h?abffffh sa140 64 kwords 8c0000h?8cffffh sa172 64 kwords ac0000h?acffffh sa141 64 kwords 8d0000h?8dffffh sa173 64 kwords ad0000h?adffffh sa142 64 kwords 8e0000h?8effffh sa174 64 kwords ae0000h?aeffffh sa143 64 kwords 8f0000h?8fffffh sa175 64 kwords af0000h?afffffh bank 9 sa144 64 kwords 900000h?90ffffh bank 11 sa176 64 kwords b00000h?b0ffffh sa145 64 kwords 910000h?91ffffh sa177 64 kwords b10000h?b1ffffh sa146 64 kwords 920000h?92ffffh sa178 64 kwords b20000h?b2ffffh sa147 64 kwords 930000h?93ffffh sa179 64 kwords b30000h?b3ffffh sa148 64 kwords 940000h?94ffffh sa180 64 kwords b40000h?b4ffffh sa149 64 kwords 950000h?95ffffh sa181 64 kwords b50000h?b5ffffh sa150 64 kwords 960000h?96ffffh sa182 64 kwords b60000h?b6ffffh sa151 64 kwords 970000h?97ffffh sa183 64 kwords b70000h?b7ffffh sa152 64 kwords 980000h?98ffffh sa184 64 kwords b80000h?b8ffffh sa153 64 kwords 990000h?99ffffh sa185 64 kwords b90000h?b9ffffh sa154 64 kwords 9a0000h?9affffh sa186 64 kwords ba0000h?baffffh sa155 64 kwords 9b0000h?9bffffh sa187 64 kwords bb0000h?bbffffh sa156 64 kwords 9c0000h?9cffffh sa188 64 kwords bc0000h?bcffffh sa157 64 kwords 9d0000h?9dffffh sa189 64 kwords bd0000h?bdffffh sa158 64 kwords 9e0000h?9effffh sa190 64 kwords be0000h?beffffh sa159 64 kwords 9f0000h?9fffffh sa191 64 kwords bf0000h?bfffffh table 9.5 sector address table, s29ns256n (sheet 2 of 3) bank sector sector size address range bank sector sector size address range
32 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) bank 12 sa192 64 kwords c00000h?c0ffffh bank 14 sa224 64 k words e00000h?e0ffffh sa193 64 kwords c10000h?c1ffffh sa225 64 k words e10000h?e1ffffh sa194 64 kwords c20000h?c2ffffh sa226 64 k words e20000h?e2ffffh sa195 64 kwords c30000h?c3ffffh sa227 64 k words e30000h?e3ffffh sa196 64 kwords c40000h?c4ffffh sa228 64 k words e40000h?e4ffffh sa197 64 kwords c50000h?c5ffffh sa229 64 k words e50000h?e5ffffh sa198 64 kwords c60000h?c6ffffh sa230 64 k words e60000h?e6ffffh sa199 64 kwords c70000h?c7ffffh sa231 64 k words e70000h?e7ffffh sa200 64 kwords c80000h?c8ffffh sa232 64 k words e80000h?e8ffffh sa201 64 kwords c90000h?c9ffffh sa233 64 k words e90000h?e9ffffh sa202 64 kwords ca0000h?caffffh sa234 64 k words ea0000h?eaffffh sa203 64 kwords cb0000h?cbffffh sa235 64 k words eb0000h?ebffffh sa204 64 kwords cc0000h?ccffffh sa236 64 k words ec0000h?ecffffh sa205 64 kwords cd0000h?cdffffh sa237 64 k words ed0000h?edffffh sa206 64 kwords ce0000h?ceffffh sa238 64 k words ee0000h?eeffffh sa207 64 kwords cf0000h?cfffffh sa239 64 k words ef0000h?efffffh bank 13 sa208 64 kwords d00000h?d0ffffh bank 15 sa240 64 k words f00000h?f0ffffh sa209 64 kwords d10000h?d1ffffh sa241 64 k words f10000h?f1ffffh sa210 64 kwords d20000h?d2ffffh sa242 64 k words f20000h?f2ffffh sa211 64 kwords d30000h?d3ffffh sa243 64 k words f30000h?f3ffffh sa212 64 kwords d40000h?d4ffffh sa244 64 k words f40000h?f4ffffh sa213 64 kwords d50000h?d5ffffh sa245 64 k words f50000h?f5ffffh sa214 64 kwords d60000h?d6ffffh sa246 64 k words f60000h?f6ffffh sa215 64 kwords d70000h?d7ffffh sa247 64 k words f70000h?f7ffffh sa216 64 kwords d80000h?d8ffffh sa248 64 k words f80000h?f8ffffh sa217 64 kwords d90000h?d9ffffh sa249 64 k words f90000h?f9ffffh sa218 64 kwords da0000h?daffffh sa250 64 k words fa0000h?faffffh sa219 64 kwords db0000h?dbffffh sa251 64 k words fb0000h?fbffffh sa220 64 kwords dc0000h?dcffffh sa252 64 k words fc0000h?fcffffh sa221 64 kwords dd0000h?ddffffh sa253 64 k words fd0000h?fdffffh sa222 64 kwords de0000h?deffffh sa254 64 k words fe0000h?feffffh sa223 64 kwords df0000h?dfffffh sa255 16 k words ff0000h?ff3fffh sa256 16 k words ff4000h?ff7fffh sa257 16 k words ff8000h?ffbfffh sa258 16 k words ffc000h?ffffffh table 9.5 sector address table, s29ns256n (sheet 3 of 3) bank sector sector size address range bank sector sector size address range
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 33 data sheet (advance information) table 9.6 sector address table, s29ns128n (sheet 1 of 2) bank sector sector size address range bank sector sector size address range bank 0 sa0 64 kwords 000000h?00ffffh bank 4 sa32 64 kwords 200000h?20ffffh sa1 64 kwords 010000h?01ffffh sa33 64 kwords 210000h?21ffffh sa2 64 kwords 020000h?02ffffh sa34 64 kwords 220000h?22ffffh sa3 64 kwords 030000h?03ffffh sa35 64 kwords 230000h?23ffffh sa4 64 kwords 040000h?04ffffh sa36 64 kwords 240000h?24ffffh sa5 64 kwords 050000h?05ffffh sa37 64 kwords 250000h?25ffffh sa6 64 kwords 060000h?06ffffh sa38 64 kwords 260000h?26ffffh sa7 64 kwords 070000h?07ffffh sa39 64 kwords 270000h?27ffffh bank 1 sa8 64 kwords 080000h?08ffffh bank 5 sa40 64 kwords 280000h?28ffffh sa9 64 kwords 090000h?09ffffh sa41 64 kwords 290000h?29ffffh sa10 64 kwords 0a0000h?0affffh sa42 64 kwords 2a0000h?2affffh sa11 64 kwords 0b0000h?0bffffh sa43 64 kwords 2b0000h?2bffffh sa12 64 kwords 0c0000h?0cffffh sa44 64 kwords 2c0000h?2cffffh sa13 64 kwords 0d0000h?0dffffh sa45 64 kwords 2d0000h?2dffffh sa14 64 kwords 0e0000h?0effffh sa46 64 kwords 2e0000h?2effffh sa15 64 kwords 0f0000h?0fffffh sa47 64 kwords 2f0000h?2fffffh bank 2 sa16 64 kwords 100000h?10ffffh bank 6 sa48 64 kwords 300000h?30ffffh sa17 64 kwords 110000h?11ffffh sa49 64 kwords 310000h?31ffffh sa18 64 kwords 120000h?12ffffh sa50 64 kwords 320000h?32ffffh sa19 64 kwords 130000h?13ffffh sa51 64 kwords 330000h?33ffffh sa20 64 kwords 140000h?14ffffh sa52 64 kwords 340000h?34ffffh sa21 64 kwords 150000h?15ffffh sa53 64 kwords 350000h?35ffffh sa22 64 kwords 160000h?16ffffh sa54 64 kwords 360000h?36ffffh sa23 64 kwords 170000h?17ffffh sa55 64 kwords 370000h?37ffffh bank 3 sa24 64 kwords 180000h?18ffffh bank 7 sa56 64 kwords 380000h?38ffffh sa25 64 kwords 190000h?19ffffh sa57 64 kwords 390000h?39ffffh sa26 64 kwords 1a0000h?1affffh sa58 64 kwords 3a0000h?3affffh sa27 64 kwords 1b0000h?1bffffh sa59 64 kwords 3b0000h?3bffffh sa28 64 kwords 1c0000h?1cffffh sa60 64 kwords 3c0000h?3cffffh sa29 64 kwords 1d0000h?1dffffh sa61 64 kwords 3d0000h?3dffffh sa30 64 kwords 1e0000h?1effffh sa62 64 kwords 3e0000h?3effffh sa31 64 kwords 1f0000h?1fffffh sa63 64 kwords 3f0000h?3fffffh bank 8 sa64 64 kwords 400000h?40ffffh bank 12 sa96 64 k words 600000h?60ffffh sa65 64 kwords 410000h?41ffffh sa97 64 k words 610000h?61ffffh sa66 64 kwords 420000h?42ffffh sa98 64 k words 620000h?62ffffh sa67 64 kwords 430000h?43ffffh sa99 64 k words 630000h?63ffffh sa68 64 kwords 440000h?44ffffh sa100 64 k words 640000h?64ffffh sa69 64 kwords 450000h?45ffffh sa101 64 k words 650000h?65ffffh sa70 64 kwords 460000h?46ffffh sa102 64 k words 660000h?66ffffh sa71 64 kwords 470000h?47ffffh sa103 64 k words 670000h?67ffffh bank 9 sa72 64 kwords 480000h?48ffffh bank 13 sa104 64 k words 680000h?68ffffh sa73 64 kwords 490000h?49ffffh sa105 64 k words 690000h?69ffffh sa74 64 kwords 4a0000h?4affffh sa106 64 k words 6a0000h?6affffh sa75 64 kwords 4b0000h?4bffffh sa107 64 k words 6b0000h?6bffffh sa76 64 kwords 4c0000h?4cffffh sa108 64 k words 6c0000h?6cffffh sa77 64 kwords 4d0000h?4dffffh sa109 64 k words 6d0000h?6dffffh sa78 64 kwords 4e0000h?4effffh sa110 64 k words 6e0000h?6effffh sa79 64 kwords 4f0000h?4fffffh sa111 64 k words 6f0000h?6fffffh
34 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) bank 10 sa80 64 kwords 500000h?50ffffh bank 14 sa112 64 k words 700000h?70ffffh sa81 64 kwords 510000h?51ffffh sa113 64 k words 710000h?71ffffh sa82 64 kwords 520000h?52ffffh sa114 64 k words 720000h?72ffffh sa83 64 kwords 530000h?53ffffh sa115 64 k words 730000h?73ffffh sa84 64 kwords 540000h?54ffffh sa116 64 k words 740000h?74ffffh sa85 64 kwords 550000h?55ffffh sa117 64 k words 750000h?75ffffh sa86 64 kwords 560000h?56ffffh sa118 64 k words 760000h?76ffffh sa87 64 kwords 570000h?57ffffh sa119 64 k words 770000h?77ffffh bank 11 sa88 64 kwords 580000h?58ffffh bank 15 sa120 64 k words 780000h?78ffffh sa89 64 kwords 590000h?59ffffh sa121 64 k words 790000h?79ffffh sa90 64 kwords 5a0000h?5affffh sa122 64 k words 7a0000h?7affffh sa91 64 kwords 5b0000h?5bffffh sa123 64 k words 7b0000h?7bffffh sa92 64 kwords 5c0000h?5cffffh sa124 64 k words 7c0000h?7cffffh sa93 64 kwords 5d0000h?5dffffh sa125 64 k words 7d0000h?7dffffh sa94 64 kwords 5e0000h?5effffh sa126 64 k words 7e0000h?7effffh sa95 64 kwords 5f0000h?5fffffh sa127 16 k words 7f0000h?7f3fffh sa128 16 k words 7f4000h?7f7fffh sa129 16 k words 7f8000h?7fbfffh sa130 16 k words 7fc000h?7fffffh table 9.7 sector address table, s29ns064n (sheet 1 of 3) bank sector sector size address range bank sector sector size address range bank 0 sa0 32 kwords 000000h-007fffh bank 2 sa32 32 kwords 100000h-107fffh sa1 32 kwords 008000h-00ffffh sa33 32 kwords 108000h-10ffffh sa2 32 kwords 010000h-017fffh sa34 32 kwords 110000h-117fffh sa3 32 kwords 018000h-01ffffh sa35 32 kwords 118000h-11ffffh sa4 32 kwords 020000h-027fffh sa36 32 kwords 120000h-127fffh sa5 32 kwords 028000h-02ffffh sa37 32 kwords 128000h-12ffffh sa6 32 kwords 030000h-037fffh sa38 32 kwords 130000h-137fffh sa7 32 kwords 038000h-03ffffh sa39 32 kwords 138000h-13ffffh sa8 32 kwords 040000h-047fffh sa40 32 kwords 140000h-147fffh sa9 32 kwords 048000h-04ffffh sa41 32 kwords 148000h-14ffffh sa10 32 kwords 050000h-057fffh sa42 32 kwords 150000h-157fffh sa11 32 kwords 058000h-05ffffh sa43 32 kwords 158000h-15ffffh sa12 32 kwords 060000h-067fffh sa44 32 kwords 160000h-167fffh sa13 32 kwords 068000h-06ffffh sa45 32 kwords 168000h-16ffffh sa14 32 kwords 070000h-077fffh sa46 32 kwords 170000h-177fffh sa15 32 kwords 078000h-0f7fffh sa47 32 kwords 178000h-17ffffh table 9.6 sector address table, s29ns128n (sheet 2 of 2) bank sector sector size address range bank sector sector size address range
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 35 data sheet (advance information) bank 1 sa16 32 kwords 080000h-087fffh bank 3 sa48 32 kwords 180000h-187fffh sa17 32 kwords 088000h-08ffffh sa49 32 kwords 188000h-18ffffh sa18 32 kwords 090000h-097fffh sa50 32 kwords 190000h-197fffh sa19 32 kwords 098000h-09ffffh sa51 32 kwords 198000h-19ffffh sa20 32 kwords 0a0000h-0a7fffh sa52 32 kwords 1a0000h-1a7fffh sa21 32 kwords 0a8000h-0affffh sa53 32 kwords 1a8000h-1affffh sa22 32 kwords 0b0000h-0b7fffh sa54 32 kwords 1b0000h-1b7fffh sa23 32 kwords 0b8000h-0bffffh sa55 32 kwords 1b8000h-1bffffh sa24 32 kwords 0c0000h-0c7fffh sa56 32 kwords 1c0000h-1c7fffh sa25 32 kwords 0c8000h-0cffffh sa57 32 kwords 1c8000h-1cffffh sa26 32 kwords 0d0000h-0d7fffh sa58 32 kwords 1d0000h-1d7fffh sa27 32 kwords 0d8000h-0dffffh sa59 32 kwords 1d8000h-1dffffh sa28 32 kwords 0e0000h-0e7fffh sa60 32 kwords 1e0000h-1e7fffh sa29 32 kwords 0e8000h-0effffh sa61 32 kwords 1e8000h-1effffh sa30 32 kwords 0f0000h-0f7fffh sa62 32 kwords 1f0000h-1f7fffh sa31 32 kwords 0f8000h-0fffffh sa63 32 kwords 1f8000h-1fffffh bank 4 sa64 32 kwords 200000h-207fffh bank 6 sa96 32 kwords 300000h-307fffh sa65 32 kwords 208000h-20ffffh sa97 32 kwords 308000h-30ffffh sa66 32 kwords 210000h-217fffh sa98 32 kwords 310000h-317fffh sa67 32 kwords 218000h-21ffffh sa99 32 kwords 318000h-31ffffh sa68 32 kwords 220000h-227fffh sa100 32 kwords 320000h-327fffh sa69 32 kwords 228000h-22ffffh sa101 32 kwords 328000h-32ffffh sa70 32 kwords 230000h-237fffh sa102 32 kwords 330000h-337fffh sa71 32 kwords 238000h-23ffffh sa103 32 kwords 338000h-33ffffh sa72 32 kwords 240000h-247fffh sa104 32 kwords 340000h-347fffh sa73 32 kwords 248000h-24ffffh sa105 32 kwords 348000h-34ffffh sa74 32 kwords 250000h-257fffh sa106 32 kwords 350000h-357fffh sa75 32 kwords 258000h-25ffffh sa107 32 kwords 358000h-35ffffh sa76 32 kwords 260000h-267fffh sa108 32 kwords 360000h-367fffh sa77 32 kwords 268000h-26ffffh sa109 32 kwords 368000h-36ffffh sa78 32 kwords 270000h-277fffh sa110 32 kwords 370000h-377fffh sa79 32 kwords 278000h-2f7fffh sa111 32 kwords 378000h-37ffffh table 9.7 sector address table, s29ns064n (sheet 2 of 3) bank sector sector size address range bank sector sector size address range
36 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 10. command definitions writing specific address and data co mmands or sequences into the co mmand register initiates device operations. table 11.4 on page 52 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the rising edge of avd#. all data is latched on the rising edge of we#. refer to the ac characteristics section for timing diagrams. 10.1 reading array data the device is automatically set to reading array data af ter device power-up. no commands are required to retrieve data in asynchronous mode. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend- read mode, after which the system can read data fr om any non-erase-suspended sector. after completing a programming operation in the erase suspend mode, th e system may once again read array data with the same exception. see erase suspend/erase resume commands on page 46 for more information. after the device accepts a program suspend comm and, the corresponding bank enters the program- suspend-read mode, after which t he system can read data from any no n-program-suspended sector within the same bank. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operatio n, or if the bank is in the autoselect mode. see also versatileio? (vio) control on page 14 and requirements for synchronous (burst) read operation on page 15 in the device bus operations section for more information. the asynchronous bank 5 sa80 32 kwords 280000h-287fffh bank 7 sa112 32 kwords 380000h-387fffh sa81 32 kwords 288000h-28ffffh sa113 32 kwords 388000h-38ffffh sa82 32 kwords 290000h-297fffh sa114 32 kwords 390000h-397fffh sa83 32 kwords 298000h-29ffffh sa115 32 kwords 398000h-39ffffh sa84 32 kwords 2a0000h-2a7fffh sa116 32 kwords 3a0000h-3a7fffh sa85 32 kwords 2a8000h-2affffh sa117 32 kwords 3a8000h-3affffh sa86 32 kwords 2b0000h-2b7fffh sa118 32 kwords 3b0000h-3b7fffh sa87 32 kwords 2b8000h-2bffffh sa119 32 kwords 3b8000h-3bffffh sa88 32 kwords 2c0000h-2c7fffh sa120 32 kwords 3c0000h-3c7fffh sa89 32 kwords 2c8000h-2cffffh sa121 32 kwords 3c8000h-3cffffh sa90 32 kwords 2d0000h-2d7fffh sa122 32 kwords 3d0000h-3d7fffh sa91 32 kwords 2d8000h-2dffffh sa123 32 kwords 3d8000h-3dffffh sa92 32 kwords 2e0000h-2e7fffh sa124 32 kwords 3e0000h-3e7fffh sa93 32 kwords 2e8000h-2effffh sa125 32 kwords 3e8000h-3effffh sa94 32 kwords 2f0000h-2f7fffh sa126 32 kwords 3f0000h-3f7fffh sa95 32 kwords 2f8000h-2fffffh sa127 8 kwords 3f8000h-3f9fffh sa128 8 kwords 3fa000h-3fbfffh sa129 8 kwords 3fc000h-3fdfffh sa130 8 kwords 3fe000h-3fffffh table 9.7 sector address table, s29ns064n (sheet 3 of 3) bank sector sector size address range bank sector sector size address range
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 37 data sheet (advance information) read and synchronous/burst read tables provide the read parameters, and figure 19.3 on page 66 and figure 19.4 on page 67 show the timings. 10.2 set configuration re gister command sequence the device uses a configuration register to set the va rious burst parameters: num ber of wait states, burst read mode, rdy configuration, and synchronous mode acti ve. the configuration regist er must be set before the device will enter burst mode. the configuration register is loaded with a four-cycl e command sequence. the first two cycles are standard unlock sequences. on the third cycle, the data should be d0h and address bits should be 555h. during the fourth cycle, the configuration code should be entered onto the data bus with the address bus set to address 000h. once the data has been programmed into the co nfiguration register, a software reset command is required to set the device into the correct state. the device will power up or after a hardware reset with the default setting, which is in asynchronous mode. the register must be set before the device can enter synchronous mode. the configuration register can not be changed during device operations (program, erase, or sector lock). 10.3 read configuration re gister command sequence the configuration register can be read with a fo ur-cycle command sequence. the first two cycles are standard unlock sequences. on the third cycle, the da ta should be c6h and address bits should be 555h. during the fourth cycle, the configur ation code should be read out of the data bus with the a ddress bus set to address 000h. once the data has been read from the c onfiguration register, a software reset command is required to set the device into the correct set mode. 10.3.1 read mode setting on power-up or hardware reset, the de vice is set to be in asynchronous read mode. this setting allows the system to enable or disable bur st mode during sy stem operations. 10.3.2 programmable wait state configuration the programmable wait state f eature informs the device of the number of clock cycles that must elapse after avd# is driven active before data will be available. th is value is determined by the input frequency of the device. configuration bit cr13?cr11 determine the setting (see table 10.1 ). the wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that shou ld be programmed into the device is directly related to the clock frequency. notes 1. upon power-up or hardware reset, the default setting is seven wait states. 2. rdy will default to being active with data when the wait state setting is set to a total initial access cycle of 2. it is recommended that the wait state command sequenc e be written, even if the de fault wait state value is desired, to ensure the device is set as expected. a ha rdware reset will set the wait state to the default setting. table 10.1 programmable wait state settings cr13 cr12 cr11 total initial access cycles 000 2 001 3 010 4 011 5 100 6 1 0 1 7 (default) 110 reserved 111 reserved
38 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 10.3.3 programmable wait state the host system should set cr13-cr11 to 101/100/011 for a clock frequency of 80/66 mhz for the system/ device to execute at maximum speed. table 10.2 describes the typical number of clock cycl es (wait states) for various conditions. 10.3.4 handshaking for optimal burst mode perfo rmance, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. the autoselect function allows t he host system to determine whether the flash device is enabled for handshaking. 10.3.5 burst length configuration the device supports four di fferent read modes: continuous mode, an d 8, 16, and 32 word linear with or without wrap around modes. a continuous sequence (def ault) begins at the starting address and advances the address pointer until the burst operation is complete. if the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. for example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. the address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the star ting location. the sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. table 10.3 shows the cr2-cr0 and settings for the four read modes. notes 1. upon power-up or hardware reset the default setting is continuous. 2. all other conditions are reserved. 10.3.6 burst wrap around by default, the device will perform burst wrap around with cr3 set to a ?1?. changing the cr3 to a ?0? disables burst wrap around. 10.3.7 rdy configuration by default, the device is set so that the rdy pin will output v oh whenever there is valid data on the outputs. the device can be set so that rdy goes active one data cycle befo re active data. cr8 determines this setting; ?1? for rdy active (default) with data, ?0? for rdy active one clock cycle before valid data. table 10.2 wait states for handshaking conditions at address typical no. of clock cycles after avd# low 80 mhz 66 mhz initial address (v ccq = 1.8 v) 7 6 table 10.3 burst length configuration burst modes address bits cr2 cr1 cr0 continuous 0 0 0 8-word linear 0 1 0 16-word linear 0 1 1 32-word linear 1 0 0
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 39 data sheet (advance information) 10.3.8 rdy polarity by default, the rdy pin will always indicate that th e device is ready to handle a new transaction with cr10 set to a ?1?. in this case, the rdy pin is active high. changing the cr10 to a ?0? sets the rdy pin to be active low. in this case, the rdy pin will always indicate that the device is ready to handle a new transaction when low. 11. configuration register table 11.1 shows the address bits that determine the conf iguration register settings for various device functions. notes 1. device will be in the default state upon power-up or hardware reset. 2. cr3 will always equal to 1 (wrap around mode) when cr0,cr1,cr2 = 000 (continuous burst mode). 3. a software reset command is required after a read or write command. 11.1 reset command writing the reset command resets the banks to the read or erase-suspend-read mode . address bits are don?t cares for this command. the reset command may be written between the s equence cycles in an erase command sequence before erasing begins. this resets the bank to wh ich the system was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete . the reset command may be writt en between the s equence cycles in a progra m command sequence before programming begins. this resets the bank to which t he system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to t he erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete . table 11.1 configuration register cr bit function settings (binary) cr15 reserved 0 = default cr14 reserved 0 = default cr13 programmable wait state 000 = data is valid on the 2nd active clk edge after avd# transition to v ih 001 = data is valid on the 3rd active clk edge after avd# transition to v ih 010 = data is valid on the 4th active clk edge after avd# transition to v ih 011 = data is valid on the 5th active clk edge after avd# transition to v ih 100 = data is valid on the 6th active clk edge after avd# transition to v ih 101 = data is valid on the 7th active clk edge after avd# transition to v ih (default) 110 = reserved 111 = reserved cr12 cr11 cr10 rdy polarity 0 = rdy signal is active low 1 = rdy signal is active high (default) cr9 reserved 1 = default cr8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) cr7 reserved 1 = default cr6 reserved 1 = default cr5 reserved 0 = default cr4 reserved 0 = default cr3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr2 burst length 000 = continuous (default) 010 = 8-word linear burst 011 = 16-word linear burst 100 = 32-word linear burst (all other bit settings are reserved) cr1 cr0
40 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) the reset command may be written between the sequ ence cycles in an autose lect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase susp end mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). note: if dq1 goes high during a write buffer programmi ng operation, the system must write the ?write to buffer abort reset? command sequence to reset th e device to reading array data. the standard reset command will not work. see table 11.4 on page 52 for details on this command sequence. 11.2 autoselect command sequence the autoselect command sequence allows the host sys tem to access the manufacturer and device codes, and determine whether or not a sector is protected. table 11.4 on page 52 shows the address and data requirements. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode . the autoselect command may not be written while the device is actively programming or erasing in the other bank. au toselect does not support simultaneous operations or burst mode. the autoselect command sequence is in itiated by first writing two unlock c ycles. this is followed by a third write cycle that contains the bank address and the autos elect command. the bank then enters the autoselect mode. the system may read at any address within the same bank any number of times without initiating another autoselect command sequence. the following table describes the address requirements for the various autoselect functions, and the resulting data. ba represents the bank address. the device id is read in three cycles. during this time, other banks are stil l available to read the data from the memory. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). 11.3 enter/exit secured silic on sector command sequence the secured silicon sector region provides a secured data area containing a random, eight word electronic serial number (esn). the system can access the secured silicon sector region by issu ing the three-cycle enter secured silicon sector command sequence. t he device continues to a ccess the secured silicon sector region until the system issues the four-cycle exit secured silicon sector co mmand sequence. the exit secured silicon sector command sequence returns t he device to normal operation. the secured silicon sector is not accessible when the device is executing an embedded pr ogram or embedded erase algorithm. table 11.4 on page 52 shows the address and data requi rements for both command sequences. table 11.2 device id description address read data 256n 128n 064n manufacturer id (ba) + 00h 0001h 0001h 0001h device id, word 1 (ba) + 01h 2d7e 2c7eh 2b7eh device id, word 2 (ba) + 0eh 2d2f 2c35h 2b33h device id, word 3 (ba) + 0fh 2d00 2c00h 2b00h revision id (ba) + 03h tbd sector block lock/unlock (sa) = 02h 0001 - locked 0000 - unlocked indicator bits (ba) + 07h dq15 - dq8 = reserved dq7 - factory lock bit 1 = locked, 0 = not locked dq6 - customer lock bit 1 = locked, 0 = not locked dq5 handshake bit 1 = reserved 0 = standard handshake dq4 & dq3 - wp# protections boot code 01 = wp# protects only the top boot sectors dq2-dq0 = reserved
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 41 data sheet (advance information) 11.3.1 unlock bypa ss command sequence the unlock bypass feature allows the system to program faster t han the standard program command sequence. the unlock bypass command sequence is init iated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock by pass command, 20h. that bank then enters the unlock bypass mode. during the unlock bypass mode only the command is valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequenc e. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. 11.4 program command sequence 11.4.1 program command sequence programming is a four-bus-cycle o peration. the program co mmand sequence is initiated by writing two unlock write cycles, followed by th e program set-up command. the pr ogram address and data are written next, which in turn initia te the embed ded program algorit hm. the system is not required to provide further controls or timings. the device autom atically provides internally generated program pulses and verifies the programmed cell margin. table 11.4 on page 52 shows the address and data r equirements for the program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer la tched. the system can determine the status of the program ope ration by monitoring dq7 or dq6/dq2. refer to the write operation status on page 55 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operat ion. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may causes that bank to set dq5 = 1 (change-up condition). however, a succeeding read will show that the data is still ?0 .? only erase operations can convert a ?0? to a ?1.? 11.4.2 program command s equence (unlock bypass mode) once the device enters the unlo ck bypass mode, then a two-cycle unlock bypass program command sequence is all that is requi red to program in this mode. the first cycle in this s equence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, result ing in faster total programming time. table 11.4 on page 52 shows the requirements for the unlock bypass command sequences. 11.5 accelerated program the device offers accelerated prog ram operations through the acc input. w hen the system asserts acc on this input, the device automatically enters the unlock bypa ss mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the acc input to accelerate the operation. figure 11.1 illustrates the algorithm for the program operation. refer to table 19.5, erase/program operations on page 69 and figure 19.6 on page 70 for timing diagrams.
42 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 11.1 program operation note see table 11.4 on page 52 for program. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 43 data sheet (advance information) 11.6 write buffer programming command sequence write buffer programming sequence allows for faster programming as compared to the standard program command sequence. see table 11.3 on page 43 for the program command sequence. note write buffer addresses must be loaded in sequential order. table 11.3 write buffer command sequence sequence address data comment unlock command 1 555 00aa not required in the unlock bypass mode unlock command 2 2aa 0055 same as above write buffer load starting address 0025h specify the number of program locations starting address word count number of locations to program minus 1 load 1st data word starting address program data all addresses must be within write-buffer-page boundaries, but do not have to be loaded in any order load next data word write buffer location program data same as above ... ... ... same as above load last data word write buffer location program data same as above write buffer program confirm sector address 0029h this command must follow the last write buffer location loaded, or the operation will abort device goes busy status monitoring through dq pins (perform data bar polling on the last loaded address )
44 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 11.2 write buffer programming operation 11.7 chip erase command sequence 11.7.1 chip erase command sequence chip erase is a six bus cycle operatio n. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the emb edded erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings du ring these operations. table 11.4 on page 52 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system ca n determine the status of the erase operation by usi ng dq7 or dq6/dq2. refer to write operation status on page 55 for information on these status bits. any commands written during the chip erase op eration are ignored. however, note that a hardware reset immediately terminates the erase operation. if that o ccurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pa s s read dq15 - dq0 at last loaded address read dq15 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode.
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 45 data sheet (advance information) 11.8 sector erase command sequence 11.8.1 sector erase command sequence sector erase in normal mode is a six bus cycle operati on. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 11.4 on page 52 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea , sector erase accept, occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than t sea . any sector erase address and command following the exceeded time-out may or may not be accepted. any command other than sector erase or erase suspen d during the time-out period resets that bank to the read mode. the system can monitor dq3 to determ ine if the sector erase timer has timed out (see the section on dq3: sector erase start timeout state indica tor.). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing banks. the system can determine t he status of the erase ope ration by reading dq7 or dq6/ dq2 in the erasing bank. refer to write operation status on page 55 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operat ion. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. 11.8.2 accelerated sector erase the device offers accelerated sector erase operation through the acc function. this method of erasing sectors is faster than the standar d sector erase command sequence. the accelerated sector erase function must not be used mo re than 100 times per sector. in addition, accelerated sector erase should be performed at room temperature (30 c +-10 c). the following procedure is used to perform accelerated sector erase: 1. sectors to be erased must be ppb and dyb cleared. all sectors that remain locked will not be erased. 2. apply 9v to the acc input. this voltage must be applied at least 1 s before executing step 3 3. issue the standard chip erase command. 4. monitor status bits dq2/dq6 or dq7 to determ ine when erasure is complete, just as in the standard erase operation. see write operation status on page 55 for further details. 5. lower acc from 9v to v cc .
46 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 11.3 erase operation note see the section on dq3 for information on the sector erase start timeout state indicator. 11.9 erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector eras e operation and then read data from, program data to, any sector not select ed for erasure. the system may also lock or unlock any sector while the erase operation is suspended. the system must not write the sector lock/unlock command to sectors selected for erasure. the bank address is required wh en writing this command. this command is valid only during the sector erase operation, including the minimum t sea time-out period during the sector erase command sequence. the erase susp end command is ignored if written during the chip erase operation or em bedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of t esl , erase suspend latency, to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the ba nk enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) the system may also lock or unlock any sector while in the erase-suspend-read mode. reading at any address within erase-suspend ed sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq 2 together, to determine if a sector is actively erasing or is erase- suspended. refer to write operation status on page 55 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq 7 or dq6 status bits, just as in the standard program operation. refer to write operation status on page 55 for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect functions and autoselect command sequence sections for details. to resume the sector erase operation, the syst em must write the erase resume command. the bank address of the erase-suspended bank is required when wr iting this command. furthe r writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. note: while an erase operation can be suspended and resumed multiple times, a minimum delay of t ers (erase resume to erase suspend) is required from resume to the next suspend. s ta rt write er as e comm a nd s e qu ence d a t a poll from s y s tem d a t a = ffh? no ye s er asu re completed em b edded er as e a lgorithm in progre ss
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 47 data sheet (advance information) 11.10 program suspend/program resume commands the program suspend command allows the system to interrupt a embedded programming operation or a ?write to buffer? programming operation so that data can read from any non-suspended sector. when the program suspend command is written during a progra mming process, the device halts the programming operation within t psl , program suspend latency, and updates the status bits. addresses are defined when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non- suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area (one time program area), then user must use the proper command sequ ences to enter and exit this region. the system may also write the autoselect comm and sequence when the device is in program suspend mode. the device allows reading autoselect codes in t he suspended sectors, since the codes are not stored in the memory array. when the devic e exits the autoselect mode, the device reverts to program suspend mode, and is ready for another valid operation. s ee ?autoselect command sequence? for more information. after the program resume command is written, th e device reverts to prog ramming. the system can determine the status of the program operation using the dq7 or dq6 stat us bits, just as in the standard program operation. see ?write oper ation status? for more information. the system must write the program resume command (address bits are ?don?t ca re?) to exit the program suspend mode and continue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resume programming. note: while a program operation can be suspended and resumed multiple times, a minimum delay of t prs (program resume to program suspend) is re quired from resume to the next suspend. 11.11 lock register command set definitions the lock register command set perm its the user to one-tim e program the persistent protection mode lock bit or password protection mode lock bit. the lo ck command set also allows for the reading of the persistent protection mode lock bit or password protection mode lock bit. the lock register command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the lock register command set entry command disables reads and writes for bank 0. reads from other banks excluding bank 0 are allowed. ? lock register program command ? lock register read command ? lock register exit command the lock register command set exit command must be issued after the execution of the commands to reset the device to read mode, and re-enables reads and writes for bank 0. for the device to be permanently set to the persistent protection mode or the password protection mode, the sequence of a lock register command set exit command, must be initiated after issuing the persistent protection mode lock bit program and the password protection mode lock bit program commands. note that if the persistent protection mode lock bit and the password protection mode lock bit are programmed at the same time, neither will be programmed.
48 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 11.12 password protectio n command set definitions the password protection command set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later un lock the device by issuing the valid 64-bit password. the password protection command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the password pr otection command set entry command di sables reads and writes for bank 0. reads for other banks excluding bank 0 are allowed. however writes to any bank are not allowed. ? password program command ? password read command ? password unlock command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. there is no special addressing order required for programming the password. once the password is written and verified, the passw ord mode locking bit must be set in order to prevent verification. the password program co mmand is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time- out by the embedded program algorithm with the cell remaining as a ?0?. the password is all 1?s when shipp ed from the factory. all 64-bit password combinations are valid as a password. the password verify command is used to verify the password. the password is verifiable only when the password mode lock bit is not programmed. if the password mode lock bit is programmed and the user attempts to verify the passwor d, the device will always drive all 1?s onto the dq data bus. the lower two address bits (a1?a0) are valid during the password read, password program, and password unlock. the password unlock command is used to clear th e ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become a ccessible for modification. the exact password must be entered in order for the unlocking function to occur. th is command cannot be issued any faster than 1 s at a time to prevent a hacker from running through the all 64- bit combinations in an attempt to correctly match a password. if the command is issued before the 1 s execution window for each portion of the unlock, the command will be ignored. the password unlock function is accomplished by writ ing password unlock command and data to the device to perform the clearing of the ppb lock bit. the password is 64 bits long. a1 and a0 are used for matching. writing the password unlock command does not need to be address order specific. an example sequence is starting with the lower address a1?a0= 00, followed by a1?a0= 01, a1?a0= 10, and a1?a0= 11. approximately 1 s is required for unlocking the device af ter the valid 64-bit password is given to the device. it is the responsibility of the microprocessor to keep track of the entering the portions of the 64-bit password with the password unlock command, the order, and w hen to read the ppb lock bit to confirm successful password unlock. in order to re-lock the device in to the password mode, the ppb lock bit set command can be re-issued. the password protection command set exit command must be issued af ter the execution of the commands listed previously to reset the device to read mode, otherwise the devi ce will hang. note that issuing the password protection command set exit command re-enables reads and writes for bank 0.
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 49 data sheet (advance information) 11.13 non-volatile sector prot ection command set definitions the non-volatile sector protection command set permits the user to program the pe rsistent protection bits (ppbs), erase all of the persistent prot ection bits (ppbs), and read the logi c state of the pers istent protection bits (ppbs). the non-volatile sector protection command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the non-volatile sector protection command set entry command disables reads and writes for active bank . reads from other banks excluding active bank are allowed. ? ppb program command ? all ppb erase command ? ppb status read command the ppb program command is used to program, or set, a given ppb. ea ch ppb is individually programmed (but is bulk erased with the other ppbs). the spec ific sector addresses (a max ?a14) are written at the same time as the program command. if the ppb lock bit is set, the ppb program command will not execute and the command will ti me-out without pr ogramming the ppb. the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually erasing a specific ppb. unlike the ppb progra m, no specific sector address is r equired. however, when the ppb erase command is written, all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the command will time-out without erasing the ppbs. the device will preprogram a ll ppbs prior to erasing when issuing the all ppb erase command. also note that the total number of ppb program/erase cycles has the same endurance as the flash memory array. the programming st ate of the ppb for a given sect or can be verified by writ ing a ppb status read command to the device. see table 11.4 on page 50 for the ppb program/erase algorithm. note: ppb reads data on ly asynchronously.
50 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 11.4 ppb program/erase algorithm note the bank entered during entry is the active bank. take for exampl e the active bank is ba0. any reads in ba0 will result in stat us reads of the ppb bit. if the user wants to set (programmed to ?0?) in a diff erent bank other than the active bank, say for example ba5, then the active bank switches from ba0 to ba5. reading in ba5 will result in status read of the bit whereas reading in ba0 will result in true data. read byte twice. addr = sa0 enter ppb command set. addr = ba program ppb bit. addr = sa read byte. addr = sa0 dq5 = 1? yes yes yes no no no yes dq6 = toggle? dq6 = toggle? read byte. addr = sa0 read byte. addr = sa pass fail issue reset command exit ppb command set dq0 = '1' (erase) '0' (pgm.)?
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 51 data sheet (advance information) the non-volatile sector pr otection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the non-volatile sector protection command set exit command re-enables reads and writes for active bank. after entering the ppb mode ? the ppb status read (ba) is the mode entry (ba) ? if ppb program command is given, the new ppb status read (ba) will be the same (ba) as given in the ppb program. ? if ppb erase command is given, the new ppb status re ad (ba) is the same (ba) as given in the ppb program or ppb set entry, whichever was last. ? during ppb program or erase operation, ppb status read is not available. only po lling data is available in bank0 and no other bank. reading from all other banks will give core data. 11.14 global volatile sector pr otection freeze command set the global volatile sector protec tion freeze command set permits t he user to set the ppb lock bit and reading the logic state of the ppb lock bit. the volatile sector protection freeze comma nd set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. reads from all banks excluding mode entry bank are allowed. ? ppb lock bit set command ? ppb lock bit status read command the ppb lock bit set command is used to set the ppb lock bit if it is cleared ei ther at reset or if the password unlock command was successful ly executed. there is no ppb lo ck bit clear command. once the ppb lock bit is set, it cannot be cl eared unless the device is taken thro ugh a power-on clear (for persistent sector protection mode) or the password unlock comm and is executed (for password sector protection mode). if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycle. the programming state of the ppb lock bit can be ve rified by executing a p pb lock bit status read command to the device. the global volatile sector prot ection freeze command set exit command must be issued after the execution of the commands listed previous ly to reset the device to read mode. 11.15 volatile sector protection command set the volatile sector protection command set permits th e user to set the dynamic protection bit (dyb), clear the dynamic protection bit (dyb), and read the lo gic state of the dynamic protection bit (dyb). the volatile sector protect ion command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the volatile sector protect ion command set entry command disables reads and writes for the bank selected with the command. reads for ot her banks excluding the selected bank are allowed. ? dyb set command ? dyb clear command ? dyb status read command the dyb set/clear command is used to set or clear a dyb for a given sector. the high order address bits (a23?a14 for the ns256n, a22?a14 for the ns128n and a21-a14 for the ns064n) are issued at the same time as the code 00h or 01h on dq7-dq0. all other dq data bus pins are ignored du ring the data write cycle. the dybs are modifiable at any time , regardless of the state of the p pb or ppb lock bit. the dybs are set at power-up or hardware reset. the programming state of the dyb for a given sector can be verified by writing a dyb status read command to the device. note that dyb reads data only asynchronously.
52 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) note: the bank entered during entry is the active bank. take for example the active bank is ba0. any reads in ba0 will result in status reads of the dyb bit. if the user wants to set (programmed to ?0?) in a different bank other than the active bank, say for example ba5, then the active bank switches from ba0 to ba5. reading in ba5 will result in status read of the bit wher eas reading in ba0 will result in true data. the volatile sector protec tion command set exit command must be issued af ter the execution of the commands listed previously to reset the device to read mode. note that issuing the volatile sector protection command set exit command re-enables reads and writes for the bank selected. table 11.4 command definitions (sheet 1 of 3) command sequence (notes) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data asynchronous read ( 7 ) 1 ra rd reset ( 8 )1xxxf0 autoselect ( 9 ) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 0001 device id 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 (note 10) (ba) x0e (note 10) (ba) x0f (note 10) indicator bits (11) 4 555 aa 2aa 55 (ba) 555 90 (ba) x0d (note 11) revision id 4 555 aa 2aa 55 (ba) 555 90 (ba) x03 unlock bypass mode entry 3 555 aa 2aa 55 555 20 program ( 12 )2xxxa0papd reset ( 13 ) 2 ba 90 xxx 00 cfi 1 55 98 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer ( 17 ) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( 20 ) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend / program suspend ( 14 ) 1ba b0 erase resume / program resume ( 15 ) 1ba 30 set config. register (28) 4 555 aa 2aa 55 555 d0 x00 cr read configuration register 4 555 aa 2aa 55 555 c6 x00 cr
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 53 data sheet (advance information) lock register command set definitions lock lock register command set entry 3 555 aa 2aa 55 555 40 lock register bits program ( 23 ) 2 xx a0 00 data lock register bits read 1 (ba0) 00 data lock register command set exit ( 24 ) 2xx 90 xx 00 password protection command set definitions pass-word password protection command set entry 3 555 aa 2aa 55 555 60 password program ( 24 , 26 )2 xx a0 00/ 01/ 02/ 03 pwd0 / pwd1 / pwd2 / pwd3 password read ( 27 ) 4 00pwd 001pwd102pwd203pwd3 password unlock ( 26 ) 7 00 25 00 03 00pwd001pwd102pwd203pwd300 29 password protection command set exit 2xx 90 xx 00 non-volatile sector protection command set definitions ppb non-volatile sector protection command set entry 3 555 aa 2aa 55 (ba) 555 c0 ppb program ( 29 )2xxa0 (ba) sa 00 all ppb erase ( 19 , 29 )2xx80sa030 ppb status read 1 (ba) sa rd (0) non-volatile sector protection command set exit 2xx 90 xx 00 global volatile sector protection command set definitions ppb lock bit global volatile sector protection freeze command set entry 3 555 aa 2aa 55 (ba) 555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 (ba)x x rd (0) global volatile sector protection freeze command set exit 2xx 90 xx 00 table 11.4 command definitions (sheet 2 of 3) command sequence (notes) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
54 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) legend x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever ha ppens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. pd(0) = secured silicon sector lock bit. pd(0), or bit[0]. pd(1) = persistent protection mode lock bit. pd(1), or bit[1], must be set to ?0? for protection while pd(2), bit[2] must be le ft as ?1?. pd(2) = password protection mode lock bit. pd(2), or bit[2], must be set to ?0? for protection while pd(1), bit[1] must be left as ?1?. pd(3) = protection mode otp bit. pd(3) or bit[3]. sa = address of the sector to be verified (in autose lect mode) or erased. sa includes ba. address bits a max ?a14 uniquely select any sector (ns256n and ns128n), and address bits a max - a13 uniquely select any sector (ns064n). ba = address of the bank (a23?a20 for s29ns256n, a22?a19 for s29ns 128n), and a21-a19 for s29ns064n, that is being switched to a utoselect mode, is in bypass mode, or is being erased. cr = configuration register set by data bits d15-d0. pwd3?pwd0 = password data. pd3?pd0 present four 16 bit combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0) = dq0 protection indicator bit. if protected, dq0 = 0, if unprotected, dq0 = 1. rd(1) = dq1 protection indicator bit. if protected, dq1 = 0, if unprotected, dq1 = 1. rd(2) = dq2 protection indicator bit. if protected, dq2 = 0, if unprotected, dq2 = 1. rd(4) = dq4 protection indicator bit. if protected, dq4 = 0, if unprotected, dq4 = 1. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see table 8.1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a max ?a12 are don?t cares. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. secured silicon sector command definitions secured silicon sector secured silicon sector entry ( 21 ) 3 555 aa 2aa 55 555 88 secured silicon sector program 2 xx a0 00 data secured silicon sector read 100 data secured silicon sector exit ( 24 ) 4 555 aa 2aa 55 555 90 xx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry ( 21 ) 3 555 aa 2aa 55 (ba) 555 e0 dyb set 2 xx a0 (ba) sa 00 dyb clear 2 xx a0 (ba) sa 01 dyb status read 1 (ba) sa rd(0) volatile sector protection command set exit ( 24 ) 2xx 90 xx 00 table 11.4 command definitions (sheet 3 of 3) command sequence (notes) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 55 data sheet (advance information) 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspe nd) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). 9. the fourth cycle of the autoselect command sequence is a read c ycle. the system must read device ids across the 4th, 5th, and 6th cycles, the system must provide the bank address. see the autoselect command sequence section for more information. 10. see table 11.2 on page 40 for description of bus operations. 11. see the autoselect command sequence on page 40 . 12. the unlock bypass command sequence is required prior to this command sequence. 13. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. command is valid when device is ready to read array data or when device is in autoselect mode. 17. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the max imum number of cycles in the command sequence is 37. 18. the entire four bus-cycle sequence must be entered for which portion of the password. 19. the all ppb erase command will pre-program all ppbs before erasure to prevent over-erasure of ppbs. 20. command sequence resets device for next command after write-to-buffer operation. 21. entry commands are needed to enter a specific mode to enable instructions only available within that mode. 22. write buffer programming can be initiated after unlock bypass entry. 23. if both the persistent protection mode locking bit and the pa ssword protection mode locking bit are set a the same time, the command operation will abort and return the device to the default persistent sector protection mode. 24. the exit command must be issued to reset the device into read mode. otherwise the device will hang. 25. note: autoselect, cfi, otp, unlock bypass mode and all asp modes cannot be nested with each other. 26. only a7 - a0 (lower address bits) are used 27. a max ?a0 (all address bits) are used. 28. requires the reset# command to configure the configuration register. 29. see figure 11.4 on page 50 for details. 12. write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 12.2 on page 60 and the following subsections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase operation is complete or in progress. 12.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. note that the data# polling is valid only for the last word being programmed in the write-buffer- page during write buffer programming. reading data# polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq 7 is active for approximately t psp , then that bank returns to the read mode. during the embedded erase algorithm, data# poll ing produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the eras e suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read m ode. if not all selected sectors are protected, the embedded eras e algorithm erases the unpr otected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address withi n a protected sector, the status may not be valid.
56 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6?dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6?dq0 may be still invali d. valid data on dq7?dq0 will appear on successive read cycles. table 12.2 on page 60 shows the outputs for data# polling on dq7. figure 12.1 on page 56 shows the data# polling algorithm. figure 19.9 on page 72 in the ac characteristics section shows the data# polling timing diagram. figure 12.1 data# polling algorithm notes 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 57 data sheet (advance information) 12.2 rdy: ready the rdy pin is a dedicated status ou tput that indicates valid output data on a/dq15?a/dq0 during burst (synchronous) reads. when rdy is asserted (rdy = v oh ), the output data is valid and can be read. when rdy is de-asserted (rdy = v ol ), the system should wait until rdy is re-asserted before expecting the next word of data. in synchronous (burst) mode with ce# = oe# = v il , rdy is de-asserted under the following conditions: during the initial access; after crossing the internal boundary between addresses 7eh and 7fh (and addresses offset from these by a multiple of 64). the rdy pin will also switch during status reads when a clock signal drives the clk input. in addition, rdy = v oh when ce# = v il and oe# = v ih , and rdy is hi-z when ce# = v ih . in asynchronous (non-burst) mode, the rdy pin does not i ndicate valid or invalid output data. instead, rdy = v oh when ce# = v il , and rdy is hi-z when ce# = v ih . 12.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and du ring the sector erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. note that oe# must be low during toggle bit status reads. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately t asp , all sectors protected toggle time, then return s to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see the subsection on dq7: data# polling on page 55 ). if a program address falls within a protec ted sector, dq6 toggles for approximately t psp after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: (toggle bit flowchart), dq6: toggle bit i on page 57 (description), figure 19.10 on page 73 (toggle bit timing diagram), and table 12.1 on page 59 (compares dq2 and dq6). 12.4 dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have be en selected for erasure. note that oe# must be low during toggle bit status re ads. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whet her the device is actively erasing, or is in erase suspend, but cannot distinguish which se ctors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 12.2 on page 60 to compare outputs for dq2 and dq6. see the following for additional information: (toggle bit flowchart), dq6: toggle bit i on page 57 (description), figure 19.10 on page 73 (toggle bit timing diagram), and table 12.1 on page 59 (compares dq2 and dq6).
58 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 12.2 toggle bit algorithm note the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information. start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte dq7-dq0 address = va dq6 = toggle? read byte twice dq7-dq0 adrdess = va read byte dq7-dq0 address = va fail pass
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 59 data sheet (advance information) 12.5 reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, th e system would note and store the value of the toggle bit after the first read. after the second read, th e system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the de vice has completed the program or erase operation. the system can read array data on dq7?dq0 on the fo llowing read cycle. however, if after the initial two re ad cycles, the system determi nes that the toggle bit is still to ggling, the system also should note whet her the value of dq5 is high (see the section on dq5) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successf ully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. 12.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timi ng limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ ously in the erase-suspend-program mode). 12.7 dq3: sector erase star t timeout state indicator after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure has begun. (the sector erase ti mer does not apply to the chip eras e command.) if additional sectors are selected for erasure, the entire time-out also ap plies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0 ? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (e xcept erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? th e device will accept additional sector erase commands. table 12.1 dq6 and dq2 indications if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
60 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) to ensure the command has been accepted, the system so ftware should check the stat us of dq3 prior to and following each subsequent sector erase command. if dq 3 is high on the second status check, the last command might not have been accepted. table 12.2 on page 60 shows the status of dq3 relati ve to the other status bits. 12.8 dq1: write to buffer abort dq1 indicates whether a write to buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write to buffer abort rese t command sequence to return the device to reading array data. see write buffer programming operation on page 18 for more details. notes 1. dq5 switches to ?1? when an embedded program or embedded erase o peration has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer programming operations. note that dq7# during write buffer programming indicates the data-bar for dq7 data for the last loaded write-buffer address location . table 12.2 write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle n/a program suspend mode (note 3) reading within program suspended sector valid data for all address except the address being programed, which will return invalid data reading within non-program suspended sector data erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data data data data data data erase-suspend-program dq7# toggle 0 n/a n/a n/a write to buffer (note 5) busy state dq7# toggle 0 n/a n/a 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 abort state dq7# toggle 0 n/a n/a 1
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 61 data sheet (advance information) 13. absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65c to +125c voltage with respect to ground, all inputs and i/os except acc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc + 0.5 v v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v acc (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to + 9. 5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma notes 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, input at i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 13.1 on page 61 . maximum dc voltage on input and i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 13.2 on page 61 . 2. minimum dc input voltage on acc is ?0.5 v. during voltage transitions, acc may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 13.1 on page 61 . maximum dc input voltage on acc is +9.5 v which may overshoot to +10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 14. operating ranges ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?25c to +85c ambient temperature (t a ) during accelerated sector erase . . . . . . . . . . . . . . .+20c to +40c v cc supply voltages v cc min. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 v v cc max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 .95 v operating ranges define those limits between whic h the functionality of th e device is guaranteed. figure 13.1 maximum negative overshoot waveform figure 13.2 maximum positive overshoot waveform 20 n s 20 n s +0. 8 v ?2.0 v 20 n s ?0.5 v 20 n s 20 n s v cc +2.0 v 20 n s 1.0 v v cc +0.5 v
62 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 15. dc characteristics 15.1 cmos compatible notes 1. maximum i cc specifications are tested with v cc = v cc max . 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. i cc active while embedded erase or embedded program is in progress. 4. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 5. specifications assume 8 i/os switching. 6. not 100% tested. acc is not a power supply pin. 7. while measuring output leakage current, ce# should be at v ih . 8. v ih = v cc -0.2 v and v il > -0.1v. 9. clock frequency 66 mhz and in continuous mode. parameter description test conditions (note 1) min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current (note 5) ce# = v il , oe# = v il , burst length = 8 80 mhz 26 36 ma 66 mhz 24 33 ce# = v il , oe# = v il , burst length = 16 80 mhz 26 38 ma 66 mhz 24 35 ce# = v il , oe# = v il , burst length = 32 80 mhz 28 40 ma 66 mhz 26 37 ce# = v il , oe# = v il , burst length = continuous 80 mhz 30 42 ma 66 mhz 28 39 i cc1 v cc active asynchronous read current (note 2) ce# = v il , oe# = v ih 5 mhz 15 18 ma 1 mhz 3 4 ma i cc2 v cc active write current (note 3) ce# = v il , oe# = v ih , acc = v ih 19 52.5 ma i cc3 v cc standby current (note 4) ce# = v ih , reset# = v ih (note 8) 20 70 a i cc4 v cc reset current reset# = v il, clk = v il (note 8) 80 150 a i cc5 v cc active current (read while write) ce# = v il , oe# = v il (note 8) (note 9) 50 60 ma i cc6 v cc sleep current ce# = v il , oe# = v ih 20 70 a i ppw accelerated program current (note 6) acc = 9 v 20 30 ma i ppe accelerated erase current (note 6) acc = 9 v 20 30 ma v il input low voltage ?0.5 0.4 v v ih input high voltage v ccq ? 0.4 v ccq + 0.2 v v ol output low voltage i ol = 100 a, v cc = v cc min 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min v ccq ? 0.1 v v id voltage for accelerated program 8.5 9.5 v v lko low v cc lock-out voltage 1.0 1.4 v
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 63 data sheet (advance information) 16. test conditions figure 16.1 test setup 17. key to switching waveforms 18. switching waveforms figure 18.1 input waveforms and measurement levels table 16.1 test specifications test condition all speeds unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 2.5 @ 80 mhz, 3 @ 66 mhz ns input pulse levels 0.0?v cc v input timing measurement reference levels v ccq /2 v output timing measurement reference levels v ccq /2 v c l device under tes t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 0.0 v output measurement level input v ccq /2 v ccq /2 v ccq
64 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 19. ac characteristics 19.1 v cc power-up notes 1. v cc >+ v ccq - 100 mv 2. v cc ramp rate is >1 v/100 s figure 19.1 v cc power-up diagram clk characterization notes 1. clock jitter of +/- 5% permitted. 2. not 100% tested. figure 19.2 clk characterization parameter description test setup speed unit t vcs v cc setup time min 1 ms parameter description (80 mhz) (66 mhz) unit f clk clk frequency max 80 66 mhz t clk clk period min 12.5 15.0 ns t ch clk high time min 5 6.1 ns t cl clk low time t cr (note) clk rise time max 2.5 3 ns t cf (note) clk fall time v cc reset# t vcs v ccq t clk t cl t ch t cr t cf clk
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 65 data sheet (advance information) 19.2 synchronous/burst read note not 100% tested. parameter description (80 mhz) (66 mhz) unit jedec standard t iacc initial access time max 80 ns t bacc burst access time valid clock to output delay max 9 11.0 ns t avds avd# setup time to clk min 4 4 ns t avdh avd# hold time from clk min 6 6 ns t avdo avd# high to oe# low min 0 ns t acs address setup time to clk min 4 4 ns t ach address hold time from clk min 6 6 ns t bdh data hold time from next clock cycle min 3 3 ns t oe output enable to data, or rdy valid max 9 11.0 ns t cez chip enable to high z (note) max 8 10 ns t oez output enable to high z (note) max 8 10 ns t ces ce# setup time to clk min 4 ns t rdys rdy setup time to clk min 3.5 4 ns t racc ready access time from clk max 9 11.0 ns
66 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 19.3 burst mode read notes 1. figure shows total number of clock set to five. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address +3?, additional clock delays are inserted, and are i ndicated by rdy. da da + 1 da + n oe# a/dq15- a/dq0 (n) amax-a16 aa avd# rdy (n) clk ce# t ces t acs t avds t avdh t ach t oe t racc t oez t cez t iacc t bdh 5 cycles for initial access shown. 15.2 ns typ. (66 mhz) 12.5 ns typ. (80 mhz) hi-z hi-z hi-z 12 3456 7 t rdys t bacc da + 3 da + 2 da da + 1 da + n a/dq15- a/dq0 (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da + 2 da da + 1 da + n a/dq15- a/dq0 (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da + 1 da da da + n a/dq15- a/dq0 (n + 3) rdy (n + 3) hi-z hi-z hi-z da da t cr aa t avdo
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 67 data sheet (advance information) 19.3 asynchronous read note not 100% tested. figure 19.4 asynchronous mode read note ra = read address, rd = read data. parameter description (80 mhz) (66 mhz) unit jedec standard t ce access time from ce# low max 80 ns t acc asynchronous access time max 80 ns t avdp avd# low time min 8 ns t aavds address setup time to rising edge of avd min 4 4 ns t aavdh address hold time from rising edge of avd min 3.7 3.7 ns t oe output enable to output valid max 9 11.0 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 10 ns t oez output enable to high z (see note) max 10 ns t ce we# amax ? a16 ce# oe# valid rd t acc t oeh t oe a/dq15 ? a/dq0 t oez t aavdh t avdp t aavds avd# ra ra
68 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 19.4 hardware reset (reset#) note not 100% tested figure 19.5 reset timings parameter description all speed options unit jedec std t rp reset# pulse width min 200 ns t rh reset high time before read min 10 s reset# t rp ce#, oe# t rh
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 69 data sheet (advance information) 19.5 erase/program operations notes 1. not 100% tested. 2. see the erase and programming performance section for more information. 3. does not include the preprogramming time. parameter description (80 mhz) (66 mhz) unit jedec standard t avav t wc write cycle time (note 1) min 45 45 ns t avwl t as address setup time min 4 4 ns t wlax t ah address hold time min 6 6 ns t avdp avd# low time min 8 ns t dvwh t ds data setup time min 20 25 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write typ 0 ns t elwl t cs ce# setup time to we# typ 8 8 ns t wheh t ch ce# hold time typ 0 ns t wlwh t wp /t wrl write pulse width typ 30 ns t whwl t wph write pulse width high typ 20 ns t sr/w latency between read and write operations min 0 ns t acc acc rise and fall time min 500 ns t vps acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t sea sector erase accept time-out max 50 s t esl erase suspend latency max 35 s t psl program suspend latency max 35 s t ers erase resume to erase suspend min 30 s t prs program resume to program suspend min 30 s t psp toggle time during programming within a protected sector typ 1 s t asp toggle time during sector protection typ 100 s t wep noise pulse margin on we# max 3 ns
70 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 19.6 program operation timings notes 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a max ?a16 are don?t care during command sequence unlock cycles. oe# ce# a/dq15 ? a/dq0 amax ? a16 avd we# clk v cc 555h a0h pd t as t wp t ah t wc t wph pa pa t vcs t cs t dh t ch in progress t whwh1 va va complete va va program command sequence (last two cycles) read status data t ds v ih v il t avdp
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 71 data sheet (advance information) figure 19.7 chip/sector erase operations notes 1. sa is the sector address for sector erase. 2. address bits a max ?a16 are don?t cares during unlock cycles in the command sequence. oe# ce# a/dq15 ? a/dq0 amax ? a16 avd we# clk v cc 2aah 55h 30h t as t wp t ah t wc t wph sa sa t vcs t cs t dh t ch in progress t whwh2 va va complete va va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp
72 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 19.8 accelerated unlock by pass programming timing notes 1. acc can be left high for subsequent programming pulses. 2. use setup and hold times from conventional program operation. figure 19.9 data# polling timings (during embedded algorithm) notes 1. all status reads are asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. ce# avd# we# amax ? a16 a/dq15 ? a/dq0 ce# acc don't care don't care a0h pa pa pd v id v il or v ih t acc t vps we# ce# oe# high z t oe high z a max ? a16 a/dq15 ? a/dq0 avd# t oeh t ce t ch t oez t cez status data status data t acc va va va va
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 73 data sheet (advance information) figure 19.10 toggle bit timings (during embedded algorithm) notes 1. all status reads are asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. figure 19.11 8-, 16-, and 32-word linear burst address wrap around note 8-word linear burst mode shown. 16- and 32-word linear burst read modes behave similarly. d0 represents the first word of the l inear burst. we# ce# oe# high z t oe high z a max ? a16 a/dq15 ? a/dq0 avd# t oeh t ce t ch t oez t cez status data status data t acc va va va va clk address (hex) d0 d1 d2 a/dq15 ? a/dq0 oe# address wraps back to beginning of address group. 39 39 3a 3b 3c 3d 3e 3f 38 initial access v il v ih avd# v il v ih d3 d4 d5 d6 d7 (stays low) ce# v il (stays low)
74 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) figure 19.12 latency with boundary crossing notes 1. cxx indicates the clock that triggers data dxx on the outputs; for example, c60 triggers d60. 2. at frequencies less than or equal to 66 mhz, there is no latency. clk address (hex) c124 c125 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(2) latency t racc t racc t racc t racc
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 75 data sheet (advance information) figure 19.13 back-to-back read/write cycle timings note breakpoints in waveforms indicate that system may alternately read array data from the ?non-busy bank? while checking the statu s of the program or erase operation in the ?busy? bank. the system should read status twice to ensure valid information. oe# ce# we# t oeh a/dq15 ? a/dq0 amax ? a16 avd# pd/30h pa/sa aah 555h ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra ra ra rd t wph
76 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 20. erase and programming performance notes 1. typical program and erase times assume the following conditions: 25 c, 1.8 v v cc , 10,000 cycles typical. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.70 v, 100,000 cycles. 3. effective write buffer specification is based upon a 32-word write buffer operation. 4. the typical chip programming time is considerably less than t he maximum chip programming time listed, since most words progra m faster than the maximum program times listed. 5. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 6. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 11.4 on page 52 for further information on command definitions. 21. bga ball capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 64 kword v cc 0.8 3.5 s excludes 00h programming prior to erasure (note 5) 32 kword v cc 0.6 3 16 kword v cc 0.15 2 8 kword v cc 0.12 2 chip erase time v cc 154 (ns256n) 308 (ns256n) 77 (ns128n) 154 (ns128n) 58 (ns064n) 116 (ns064n) acc 131 (ns256n) 262 (ns256n) 66 (ns128n) 132 (ns128n) 50 (ns064n) 100 (ns064n) single word programming time v cc 40 400 us acc 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 acc 6 60 total 32-word buffer programming time v cc 300 3000 acc 192 1920 chip programming time (note 4) v cc 157.3 (ns256n) 314.6 (ns256n) s excludes system level overhead (note 6) 78.6 (ns128n) 157.3 (ns128n) 39.3 (ns064n) 78.6 (ns064n) acc 101 (ns256n) 202 (ns256n) 51 (ns128n) 102 (ns128n) 26 (ns064n) 52 (ns064n) parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4.2 5.0 pf c out output capacitance v out = 0 5.4 6.5 pf c in2 control pin capacitance v in = 0 3.9 4.7 pf
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 77 data sheet (advance information) 22. physical dimensions (s29ns256n) 22.1 vdc048?48-ball very thin fine-pitch ball grid array (f bga) 11 x 10 mm package *for reference only. bsc is an ansi standard for basic space centering package vdc 048 jedec n/a 9.95 mm x 10.95 mm nom package symbol min nom max note a 0.86 --- 1.00 overall thickness a1 0.20 --- --- ball height a2 0.66 0.71 0.76 body thickness d 9.85 9.95 10.05 body size e 10.85 10.95 11.05 body size d1 4.50 ball footprint e1 1.50 ball footprint md 10 row matrix size d direction me 4 row matrix size e direction n 48 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 ball pitch sd / se 0.25 solder ball placement ? 3241 \ 16-038.9h.aa01 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in ? the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. index mark a1 corner nf4 nf1 nf8 1 2 43 5 6 8 97 nf2 nf3 a b nf7 nf5 c d 10 nf6 d a 10 e a1 corner se 7 e1 d1 e 1.00 1.00 7 sd b 6 b c m c m 0.05 0.15 a 1.00 1.00 c 0.10 c 0.08 a b c a2 seating plane a1
78 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 23. physical dimensions (s29ns128n) 23.1 vdd044?44-ball very thin fine-pitch ball grid array (fbga) 9.2 x 8 mm package package vdd 044 jedec n/a 8.00 mm x 9.20 mm nom package symbol min nom max note a 0.86 --- 1.00 overall thickness a1 0.20 --- --- ball height a2 0.66 0.71 0.76 body thickness d 7.90 8.00 8.10 body size e 9.10 9.20 9.30 body size d1 4.50 ball footprint e1 1.50 ball footprint md 10 row matrix size d direction me 4 row matrix size e direction n 44 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 ball pitch sd / se 0.25 solder ball placement 3239 \ 16-038.9h.aa01 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. index mark a1 corner side view top view bottom view nf1 nf3 2 1 3 4 5 6 987 10 a nf2 c d nf4 b d a 10 d1 sd b e1 se 1.00 e a2 a1 e seating plane a m m c c 0.15 0.05 b a1 corner 7 7 6 c 0.10 c b a c 0.08 1.00
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 79 data sheet (advance information) 23.2 vde044?44-ball very thin fine-pitch ball grid array (fbga) 7.7 x 6.2mm package package vde 044 jedec n/a 7.60 mm x 6.10 mm nom package symbol min nom max note a 0.86 --- 1.00 overall thickness a1 0.20 --- --- ball height a2 0.66 0.71 0.76 body thickness d 7.50 7.60 7.70 body size e 6.00 6.10 6.20 body size d1 4.50 ball footprint e1 1.50 ball footprint md 10 row matrix size d direction me 4 row matrix size e direction n 44 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 bsc. ball pitch sd / se 0.25 bsc. solder ball placement depopulated solder balls 3308 \ 16-038.9l notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. index mark a1 corner side view top view d a 10 a2 a1 e seating plane c 0.10 c b a c 0.08 bottom view nf1 nf3 2 1 3 4 5 6 987 10 a nf2 c d nf4 b d1 sd b e1 se 1.00 e a m m c c 0.05 0.15 b a1 corner 7 7 6 1.00
80 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) 24. revision summary 24.1 revision a (april 16, 2004) initial release. 24.2 revision a1 (june 28, 2004) general description corrected the effective temperature range to -25c to +85c. connection diagram corrected pin b5 on the s29ns256n to a23. corrected pin b1 on the s29ns256n to v cc . corrected pin b1 on the s29ns128n to v cc . corrected pin b1 on the s29ns064n to v cc . created separate illustrations for s29ns128n and s29ns064n. ordering information corrected the package type offerings. valid combinations table included package type description for s29ns064n device. completely revised format and layout. 8-, 16-, and 32-word linear burst without wrap around corrected information in this section. lock register section and table were substantially revised. programmable wait state corrected information in this section. handshaking feature corrected information in this section. autoselect command sequence corrected information in this section. physical dimensions corrected the drawing for the s29ns064n device. write buffer command sequence corrected the address for the write buffer load sequence. 24.3 revision a2 (september 9, 2004) connection diagrams updated pin labels. ordering information completely updated the opn table. valid combinations table updated this table.
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 81 data sheet (advance information) continuous burst added information to this section. lock register updated the lock register table. configuration register updated the settings for cr15. device id table updated the indicator bits information. figure 7 updated the waveform. figure 21 updated the waveform. 24.4 revision a3 (november 16, 2004) table ?primary vendor-specific extended query? updated the data values for addresses 45h, 53h, and 54h. global updated the synchronous and asynchronous access times. programmable wait state updated this section. write buffer programming command sequence added a note to the table. 24.5 revision a3a (april 5, 2005) global updated reference links. distinctive characteristics added note to acc is represented as v pp in older documentation. general description added note regarding acc and v pp . block diagram added same note regarding acc and v pp . added wp# term and arrow to state control and command register block. block diagram of simultan eous operation circuit changed v pp to v ssq. added wp# term and arrow to state control and command register block. added acc term and arrow to state control and command register block. added note to acc is represented as v pp in older documentation. input/output description added v pp term adjacent to acc term.
82 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) tables 2, 3, 4, 5, 6, 7, 8, and 9 change wait state titles and columns in these tables. table 24 changed function column and settings to represent reserved cr bits. table 27 removed several bold lines between columns. dc characteristics reduced typ and max values for i ccb . added note for clock frequency in continuous mode. erase & programming performance table corrected sector erase time typ. value for 64 kw ord from 0.6 to 0.8 in erase and programming performance table physical dimensions (s29ns046n) replaced vde044 with new package drawing. device history updated device history table 24.6 revision a4 (april 12, 2005) global changes removed 64mb density. removed 54mhz speed option. changed acc to v pp. read access times removed burst access for 54mhz. defined asynchronous random access and synchronous random access to 80 ns for all speed options. dc characteristics cmos compatible table. updated i cc3 and i cc6 values from 40 a to 70 a. 24.7 revision a5 (august 15, 2005) added s29ns064n with new sector and bank architecture. added vde044 package type for s29ns064n erase/program operations table updated description and values for t cs . device history updated table with latest revision information. 24.8 revision a6 (august 24, 2005) ac characteristics updated the notes for the v cc power-up table erase and programming performance operations
S29NS-N_00_a12 june 13, 2006 S29NS-N mirrorbit? flash family 83 data sheet (advance information) updated max value for 8 kword sector erase time updated typical and max values for chip programming time 24.9 revision a7 (september 16, 2005) ordering information updated the package type options valid combinations table updated entire table to show new options 24.10 revision a8 (september 23, 2005) dynamic protection bit (dyb) added note: dynamic protection bits revert back to their default values after programming the device ?lock register.? lock register table added note: when the device lock register is progr ammed (ppb mode lock bit is programmed, password mode lock bit programmed, or the secured silicon lock bit is programmed) all dybs revert to the power-on default state. 24.11 revision a9 (november 15, 2005) write buffer programming operation updated the flowchart 24.12 revision a10 (march 23, 2006) asynchronous read ac characteristics table updated the minimum specifications of t aavdh for both speed bins. global change changed v pp to acc 24.13 revision a11 (april 20, 2006) global change changed layout and font absolute maximum ratings updated figure 13.1 and 13.2 24.14 revision a12 (june 13, 2006) global change publication identification number was incorrectly set to S29NS-N_01 for revision 11 instead of S29NS-N_00. it is corrected in this revision. the documen t file name was not affected by this error. added a note to table 8.1 device bus operations added a note to table 11.1 configuration register added a note to section 11.9 erase suspend/erase resume commands
84 S29NS-N mirrorbit? flash family S29NS-N_00_a12 june 13, 2006 data sheet (advance information) added a note to section 11.10 program suspend/program resume commands added a note to section 11.13 non-volatile sector protection command set definitions added a note to section 11.15 volatile sector protection command set modified the ?all ppb erase? row of table 11.4 command definitions (sheet 2 of 3) changed v i/o to v ccq in section 15.1 cmos compatible changed v i/o to v ccq in table 16.1 test specifications changed v i/o to v ccq in figure 18.1 input waveforms and measurement levels added parameters t ers and t prs in section 19.5 eras e/program operations colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 - 2006 spansion llc. all rights reserved. spansi on, the spansion logo, mirrorbi t, ornand, hd-sim, and combinat ions thereof are trademarks of spansion llc. other names are for informational purposes only and may be trademarks of their respecti ve owners.

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