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rev. 1.0 12/02 copyright ? 2002 by silicon laboratori es si5017-evb-ds10 si5017-evb e valuation b oard for si5017 siphy? sonet/sdh c lock and d ata r ecovery ic description the si5017 evaluation board provides a platform for testing and characte rizing silicon la boratories? si5017 siphy? sonet/sdh clock an d data recovery ic. the si5017 cdr supports oc-48, stm-16, and 2.7 gbps fec rates. all high-speed i/os are ac coupled to ease interfacing to industry standard test equipment. features ? single 3.3 v power supply ? differential i/os ac coupled ? simple jumper configuration functional block diagram refclk + ? z c = 50 ? z c = 50 ? z c = 50 ? z c = 50 ? datain + ? clkout + ? dataout + ? z c = 50 ? z c = 50 ? z c = 50 ? z c = 50 ? pulse generator pattern generator jitter analyzer scope pattern analyzer si5017 los ltr si5017-evb dsqlch reset/cal clkdsbl jumpers rext 10 k ? test points lol ber_alm los_lvl slice_lvl ber_lvl ? vdd 210 ? 348
si5017-evb 2 rev. 1.0 functional description the evaluation board simplifies characterization of the si5017 clock and data recovery (cdr) device by providing access to all of the si5017 i/os. device performance can be evaluated by following the ?test configuration? se ction. specific performance metrics include input sensitiv ity, jitter toleranc e, jitter generation, and jitter transfer. power supply the evaluation board requires one 3.3 v supply. supply filtering is placed on the bo ard to filter typical system noise components; however, initial performance testing should use a linear supply capable of supplying the nominal voltage 5% dc. caution : the evaluation board is designed so that the body of the sma jacks and gnd are shorted. care must be taken when powering the pcb at potentials other than gnd at 0.0 v and vdd at 3.3 v relative to chassis gnd. device powerdown the cdr can be powered down via the reset/cal signal. when asserted, the evaluation board draws minimal current. reset/cal is controlled via one jumper located in the lowe r left-hand corner of the evaluation board. reset/cal is wired to the signal post adjacent to the vdd post. for a valid reset to occur when using external reference clock mode, a proper external reference clock frequency must be applied as specified in table 1. clkout, dataout, datain clkout, dataout, and datain (all high-speed i/os) are wired to the board perimeter on 30 mil (0.030 inch) 50 ? microstrip lines to th e end-launch sma jacks as labeled on the pcb. these i/os are ac coupled to simplify direct connection to a wide array of standard test hardware. because each of these signals are differential, both the positive (+) and negative (?) terminals must be terminated to 50 ? . terminating only one side will adversely degra de the performance of the cdr. the inputs are terminated on the die with 50 ? resistors. note: the 50 ? termination is for each terminal/side of a dif- ferential signal, thus the differential termination is actu- ally 50 ? +50 ? =100 ? . refclk refclk is optional for clock and data recovery within the si5017 device. if refclk is not used, jumper both jp15 and jp16. these jumpers pull the refclk+ input to vdd and refclk? input to gnd, which configures the device to operate without an external reference. when applied, refclk is us ed to center the frequency of the dspll? so the device can lock to the data. ideally, the refclk frequency should be 1/128th, 1/32nd, or 1/16th the vco frequency and must have a frequency accuracy of 100 ppm. internally, the cdr automatically recognizes the refclk frequency within one of these three frequency ranges. typical refclk frequencies are given in table 1. refclk is ac coupled to the sma jacks located on the top side of the evaluation board. loss-of-lock (lol ) loss-of-lock (lol ) is an indicator of the relative frequency between the data and the refclk. lol asserts when the frequency difference is greater than 600 ppm. to prevent lol from de-asserting prematurely, there is hysterisis in returning from the out- of-lock condition. lol will be de-asserted when the frequency difference is less than 300 ppm. lol is wired to a test point which is located on the upper right-hand side of the evaluation board. loss-of-signal alarm threshold control the loss-of-signal alarm (los ) is used to signal low incoming data amplitude levels. the programmable threshold control is set by applying a dc voltage level from a low noise voltage source to the los_lvl pin. the los_lvl is controllable through the bnc jack j10. the mapping of the los_lvl voltage to input signal alarm threshold level is shown in figure 1. the los threshold to los level is mapped as follows: if this function is not used, install jumper to jp1 header. table 1. typical refclk frequencies sonet/sdh sonet/sdh with 15/14 fec ratio of vco to refclk 19.44 mhz 20.83 mhz 128 77.76 mhz 83.31 mhz 32 155.52 mhz 166.63 mhz 16 v los v los_lvl 1.5 ? 25 --------------------------------------- =
si5017-evb rev. 1.0 3 figure 1. los_lvl mapping extended los hysteresis option an optional los hysteresis extension circuit is included on the si5017-evb to prov ide a convenient means of increasing the amount of los alarm hysteresis when testing and evaluating the si5017 los functionality. this simple networ k will extend the los hysteresis to approximately 6 db, thereby preventing unnecessary switching on los for low level datain signals in the range of 20 mv ppd . hysteresis is defined as the ratio of the los deassert level (losd) and the los assert level (losa). the hysteresis in decibels is calculated as 20log(losd/losa). this circuit is constructed with one cmos inverter (u2) and two resistors (r12, r13) mounted on the underside of the pcb. if desired, this circuit can be enabled by installing a jumper on jp17 (hyst enable) located near the power entry block. data slicing level the slicing level allows opti mization of the input cross- over point for systems where the slicing level is not at the amplitude average. the data slicing level can be adjusted from the nominal cross-over point of the data by applying a voltage to the slice_lvl pin. slice_lvl is controllable through the bnc jack j11. the slice_lvl to the data slicing level is mapped as follows: if this function is not used, jumper jp6. bit-error-rate alarm threshold the bit-error-rate of the incoming data can be monitored by the ber_alm pin. when the bit-error-rate exceeds an externally set threshold level, ber_alm is asserted. ber_alm is brought to a test point located in the upper right-hand corner of the board. the ber_alm threshold level is set by applying a dc voltage to the ber_lvl pin. ber_lvl is controllable through the bnc jack j12. jumper jp7 to disable the ber alarm. refer to the ?ber detection? section of the si5016/si5017 data sheet for threshold level programming. test configuration the three critical jitter test s typically performed on a cdr device are jitter transfer, jitter tolerance, and jitter generation. by connecting the si5017 evaluation board as shown in figure 2, all three measurements can be easily made. when applied, refclk should be within 100 ppm of the frequency selected fr om table 1 and reset/cal must be unjumpered. jitter tolerance : referring to figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, a pattern analyzer, and a pulse generator (all unconnected high-speed outp uts must be terminated to 50 ? ). during this test, the jitter analyzer directs the modulation source to apply prescribed amounts of jitter to the synthesizer source. this ?jitters? the pattern generator timebase which drives the datain ports of the cdr. the bit-error-rate (ber) is monitored on the pattern analyzer. the modulation (jitter) frequency and amplitude is recorded when the ber approaches a specified threshold. the si 5017 limiting amplifier can also be examined during this test. simply lower the amplitude of the incoming data to the minimum value typically expected at t he limiting amplifier inputs (typically 10 mv pp for the si5017 device). jitter generation : referring to figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ? ). during this test, there is no modulation of the data clock, so the data that is sent to the cdr is jitter free. the jitter analyzer measures the rms and peak-to-peak ji tter on the cdr clkout. thus, any jitter measured is jitter generated by the cdr. jitter transfer : referring to figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ? ). during this test, the jitter analyzer modulates the data pattern and data clock reference. the modulated data clock reference is compared with the clkout of the cdr. jitter on clkout relative to the jitter on the data clock reference is plotted versus modulation frequency at predefined jitter amplitudes. 40 mv/v 0 mv 0 v los_lvl (v) los threshold (mv pp ) 30 mv 2.25 v 1.50 v 1.00 v 15 mv los disabled los undefined 1.875 v 40 mv 2.5 v v slice v slice_lvl 1.5 ? 50 -------------------------------------------- =
si5017-evb 4 rev. 1.0 figure 2. test configuration for jitter tolerance, transfer, and generation jitter analyzer pattern analyzer pulse generator pattern generator modulation source synthesizer signal source 3.3 v refclk (optional) datain clkout dataout scope si5017-evb refclk+ datain+ dataout+ clkout+ gpib dataout? clock data clock+ fm gpib gpib clkout? refclk? datain? gpib ? + + ? + ? + ? + ? data clock-
si5017-evb rev. 1.0 5 ltr dsqlch reset/cal clkdsbl lol los ber_alm slice_lvl los_lvl ber_lvl din+ din- refclk+ refclk- dout- dout+ clkout- clkout+ ber_mon reference less operation (jumper both jp15 and jp16) ------- ------- ------- ---------------- no load no load hysteresis enable los_n los_n vdd vdd vdd vdd 3.3v j5 amp 449692 r11 0603 0 c1 0603 0.1uf j6 amp 449692 c14 0603 100pf c2 0603 0.1uf c3 0603 0.1uf jp14 c15 0603 100pf c4 0603 0.1uf c13 0603 100pf c5 0603 0.1uf c6 0603 0.1uf c7 0603 0.1uf c8 0603 0.1uf r12 0603 806 c12 tantalum 10uf c17 0603 0.1uf j1 amp 449692 j2 amp 449692 c16 0603 100pf jp2 r1 0603 10k (1%) r7 0603 4.99k j10 bnc jp3 j11 bnc nc7sz04 u2 2 3 4 5 j12 bnc jp5 jp1 jp9 jp8 jp6 r10 0603 0 jp7 jp10 l1 jp4 r8 0603 100 si5017 u1 si5017 7 16 17 22 23 24 12 13 5 6 20 11 14 18 21 8 10 15 19 9 27 3 4 25 28 26 2 1 lol dout- dout+ clkout- clkout+ clkdsbl din+ din- refclk+ refclk- rext vdda vddb vddc vddd ltr dsqlch tdi reset/cal los ber_alm los_lvl slice_lvl vdde ber_mon ber_lvl res/vddg res/vddf c18 0603 0.1uf c19 0603 0.1uf c20 0603 0.1uf jp15 jp16 r13 0603 10k r9 0603 0 jp11 jp12 r5 0603 348 jp13 j7 amp 449692 jp17 j8 amp 449692 j13 mkdsn 2,5/3-5,08 1 2 pos1 pos2 r6 0603 210 j3 amp 449692 j4 amp 449692 figure 3. si5017 schematic
si5017-evb 6 rev. 1.0 bill of materials si5017evb assy rev b-01 bom 2/8/2002 reference description manufacturer's # manufacturer c1,c2,c3,c4,c5,c6, cap,sm,0.1uf, 16v,20%,x7r,0603 c0603x7r160-104kne venkel c7,c8,c17,c18,c19, c20 c12 cap,sm,10uf,10v,10%,tantalum,3216 ta010tcm106kar venkel c13,c14,c15,c16 cap,sm,100pf,50v, 10%,c0g,0603 c0603c0g500-101kne venkel jp1,jp6,jp7,jp11, conn,header,2x1 2340-6111tn or 2380-6121tn 3m jp12,jp13,jp14, jp15,jp16,jp17 jp2,jp3,jp5,jp8, conn,header,3x1 2340-6111tn or 2380-6121tn 3m j1,j2,j3,j4,j5,j6, conn,sma side mount 901-10003 amphenol j7,j8 j10,j11,j12 conn,bnc,vert 161-9317 mouser j13 conn,power,2 position 1729018 phoenix contact l1 ferrite,sm,600,1206 blm31a601s murata r1,r13 res,sm,10k,1%,0603 cr0603-16w-1002ft venkel r5 res,sm,348,1%,0603 cr0603-16w-3480ft venkel r6 res,sm,210,1%,0603 cr0603-16w-2100ft venkel r7 res,sm,4.99k,1%,0603 cr0603-16w-4991ft venkel r8 res,sm,100,1%,0603 cr0603-16w-1000ft venkel r10,r11 res,sm,0,0603 cr0603-16w-000t venkel r12 res,sm,806,1%,0603 cr0603-16w-8060ft venkel u1 si5017 rev b device SI5017-BM rev b silicon laboratories u2 ic,sm,7sz04,single gate inverter,5 pin sot23 nc7sz04m5x fairchild pcb printed circuit board si5017-evb pcb rev c silicon laboratories no load r9 res,sm,0,0603 cr0603-16w-000t venkel jp4,jp9,jp10 conn,header,3x1 2340-6111tn or 2380-6121tn 3m
si5017-evb rev. 1.0 7 figure 4. si5017 top view
si5017-evb 8 rev. 1.0 figure 5. si5017 component side
si5017-evb rev. 1.0 9 figure 6. si5017 solder side
si5017-evb 10 rev. 1.0 document change list revision 0.23 to revision 1.0 ? ?preliminary? language removed. evaluation board assem bly revision history assembly level pcb rev. si5017 rev. assembly notes b-01 rev. c rev. b assemble per bom rev b-01
si5017-evb rev. 1.0 11 notes:
si5017-evb 12 rev. 1.0 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and siphy are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

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