july 2003 the following document refers to spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this document as a result of offering the device as a spansion product. any changes that have been made are the result of normal documentation impr ovements and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use on ly the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. 1.8 volt-only flash memory technology technology background publication number 21628 revision a amendment 0 issue date december 1, 1997
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2 1.8 volt-only flash memory technology background ,qwurgxfwlrq amds flash technology leadership and innovation have produced a new generation of single- power-supply flash memory devices. the am29sl800b is the first of a new family of s uper l ow voltage flash memory devices from amd. this device performs read, program, and erase operations using only a single power supply down to 1.8 volts , while maintaining performance comparable to 5.0 volt-only technology. the device offers all the features of amds industry-standard 2.7 volt-only am29lv800b device at substantially reduced power consumption, making it the ideal choice for low-power, battery-operated portable applications such as cellular phones, pdas, and pagers. the following is an abbreviated list of the am29sl800b distinctive characteristics: o 1.8 v to 2.2 v device v cc operating range o 1 ma typical active read current at 1 mhz (5 ma at 5 mhz) o 10 ma typical active program/erase current o 0.2 m a typical standby current o automatic sleep mode (no turn-on penalty) o minimum 1,000,000 program/erase cycle guarantee per sector for a complete list of features, operational description and specifications see publication number 21545 (the am29sl800b data sheet). the remainder of this document will focus on the fundamentals of flash technology at 1.8 volts. :kdw0dnhv2shudwlqjdw9rowvvr'liilfxow" flash memory technology is a very complex science, as exemplified by the small number of volume manufacturers present today in the world. performing this science from a single 1.8 volt source, while maintaining performance and reliability with minimal die size impact, was a significant engineering achievement. the development of this product resulted in several patents specific to low voltage operation. there are three major operations that a flash memory device performs: program, erase and read. the following is an examination of each of these processes. 7kh)odvk5hdg2shudwlrq amds flash memory cell is composed of a single stacked gate transistor. the gate structure of this transistor consists of a polysilicon control gate located directly above a polysilicon floating gate, separated by a dielectric (see figure 1). the amount of charge present on the floating gate affects the turn-on threshold (v t ) of the transistor. imagine the charge on the
1.8 volt-only flash memory technology background 3 floating gate as a voltage source in series with the control gate. charge is moved on and off the floating gate by the program and erase operations respectively. if the voltage on the control gate exceeds the resultant v t , the transistor begins to conduct, and a current (i ds ) proportional to this voltage begins to flow from the drain to the source. the proportionality factor is the transconductance of the transistor (g m ). the current i ds flows in the bit line through an active load. it is the voltage developed across the load that is compared to a preset reference (v ref ) to determine the state of the cell (see figure 2). figure 1. amd flash memory cell word line floating gate (poly) source n+ drain n+ p substrate control gate (poly) tunnel oxide inter-poly dielectric bit line
4 1.8 volt-only flash memory technology background figure 2. flash cell sensing at this point a few observations can be made. the operation of the flash memory cells and sensing circuits is analog in nature with transistors operating in their active (linear) regions. reliable operation of these circuits in the presence of external noise requires margin in the design. cycle endurance of the device is dependent on cell v t ; that is, the difference in v t between the programmed state and the erased state. finally, the performance of these circuits is a function of the voltages applied. reducing the external supply voltage would appear to comparator v px v ref v bl bit line i ds note: address decodes to only one word line. word line (0) v wl 0 word line (1) v wl 1 word line (n) v wl n cell transistors active load
1.8 volt-only flash memory technology background 5 have severe negative impact on the read operation of the device in terms of reliability and performance. to achieve robust read operation, an approach similar to that used in the 2.7 volt-only devices is taken. these devices utilize a dynamic circuit design approach. there are many advantages to this approach, including high performance and reduced power consumption. for this discussion, however, the main advantage is the limited time that elevated currents are required to complete the read access. this allows use of very silicon-efficient booster circuits on the wordline to provide the required control gate voltage. this enables the super low voltage family to use the same proven, highly reliable memory cell structure as in the 5 volt-only and 2.7 volt-only device families. operating at the same v t levels results in the same guaranteed high endurance (1,000,000 cycles minimum). an additional benefit to the booster circuit is the noise isolation it provides. the booster circuit essentially decouples the word line allowing line levels to be tightly controlled during the access. to achieve performance at 1.8 volts, a new thin gate oxide transistor is used in the peripheral circuits. reducing the gate oxide thickness from 150 ? down to 100 ? increases the transconductance (gain) of these transistors while reducing their threshold voltage. the net effect is to bring circuit operating currents up to a level consistent with the desired level of performance and active power consumption. the proven amd flash memory cell structure and the innovative techniques discussed above combine to deliver a highly reliable, high performance device capable of operating from a single 1.8 volt supply. 7kh)odvk3urjudpplqj2shudwlrq the program operation deposits electrons (charge) on the cells floating gate. in amd devices, channel hot electron injection (che) is the mechanism utilized. che depends on imparting more kinetic energy to the channel electrons than can be transferred to the silicon lattice, thus making them hot. in order for these electrons to make it onto the floating gate, they need to become hot enough (gain enough energy) to overcome the tunnel oxide potential barrier. creating the environment for che requires a high bias on the control gate (8 v) and elevated drain voltage (5 v). reducing the external supply voltage presents an obvious challenge. a charge pump approach is utilized to support the che programming environment. generating the voltage levels required isnt trivial, but the real issue is in managing the current. silicon efficient implementation demands maintaining a strict power budget. this is
6 1.8 volt-only flash memory technology background accomplished through a unique bit sensing circuit in conjunction with a proprietary, intelligent programming algorithm. together they exploit the fact that at the location selected for programming, only the bits to be programmed with a logic 0 require programming current (the other bits are already at logic 1 from a previous erase operation). managing the current makes this approach silicon efficient, while maintaining overall programming performance. 7kh)odvk(udvh2shudwlrq the erase operation removes electrons (charge) from the cells floating gate. in amd devices fowler-nordheim tunneling (fn) is the mechanism employed. fn tunneling is a quantum mechanical process whose explanation is beyond the scope of this paper. understanding the constraints this mechanism places on the design is our interest here. fn tunneling requires an electric field across the tunneling oxide. the strength of this field for a given oxide thickness determines the erase performance. again, reducing the external supply voltage while maintaining performance presents yet another challenge. amd pioneered its patented negative gate erase (nge) technique several years ago as a solution to the problem of maintaining erase performance without requiring multiple external voltage sources. the nge technique has proven to be a key enabler of amds ability to offer first 5 volt-only followed by 2.7 volt-only, 2.2 volt-only, and now 1.8 volt-only devices. nge takes advantage of the superposition principle of electric fields. applying a negative bias to the control gate and a small positive bias to the source generates the resultant field intensity required for fn tunneling (see figure 3). the key here is the current reduction as a result of reducing the source voltage. keeping the source voltage low suppresses avalanche-dominated conduction between the source and the substrate, reducing overall internal power generating requirements. nge therefore allows a charge pump approach to be utilized with negligible impact on die size, while maintaining erase performance.
1.8 volt-only flash memory technology background 7 figure 3. amd negative gate erase 6xppdu\ technology leadership, experience and creativity of amds engineering resources have once again lead the arrival of the next generation of low voltage flash memory devices. these super low voltage high performance devices operate from a single 1.8 volt supply, reducing active read current to just 1.0 ma (at 1.0 mhz). the reduced power consumption, silicon efficient design, and industry-leading guaranteed minimum endurance of 1,000,000 cycles combine to make this device family an ideal choice for cost-sensitive, battery-powered applications. bit line array ground (+5.0v) word line (C8.5v) (floating) flash cell transistor s g d 13.5v
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