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1 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter ace1202t data encryption standard (des) transmitter ACE1202TEM8 device pin-out preliminary august 2001 ?2001 fairchild semiconductor corporation general description the ace1202t is a customizable transmitter implementing the des algorithm to encrypt a pulse-width-modulated (pwm) signal transmitted through a radio frequency (rf) module. the ace1202t together with the ace1202r 1 form an encoder/decoder chip-set used in high-security applications. remote keyless entry (rke) burglar alarms / garage door openers individualized recognition / transmission systems. game protection the ace1202t is a member of the ace1202 (arithmetic control- ler engine) family of microcontrollers. the ace1202 product family is a dedicated programmable monolithic integrated circuit for applications requiring high performance, low power, and small size. it is a fully static part fabricated using cmos technology. for additional information regarding the ace1202 family of microcontrollers please see fairchild semiconductor? web site at www.fairchildsemi.com. features 32-bit des encoder rf or wired interface up to 4 pushbutton keys programming interface low power single supply operation (2.2 ?5.5v) low power halt mode (100na @ 3.3v) integrated power-on reset low battery voltage detection brown-out reset integrated rc oscillator integrated eeprom - 64 bytes of data eeprom for data storage and options - 2k bytes of code eeprom - 40-year data retention - 1,000,000 data writes 8-pin soic package 1 see the ace1202r datasheet at www.fairchildsemi.com for details. 2 pin 8 must be de-coupled with a 10nf ceramic capacitor to gnd. v cc gnd k4 k1 k2 led k3/rxd 1 2 3 4 8 2 7 6 5 txd
2 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 2.0 pin description 2.1 k1 C pin 1 transmitter key 1 (k1) is an active low input with an internal weak pull-up. pressing k1 sets bit 7 of the data field to 1 keeping track of the active key (see figure 7.) once pressed, the ace1202t exits the low-power halt mode and sends a normal frame. the normal frame will be transmitted continuously as long as k1 is low or until the transmission timeout expires. 2.2 k2 C pin 2 transmitter key 2 (k2) is an active low input with an internal weak pull-up. pressing k2 sets bit 6 of the data field to 1 keeping track of the active key (see figure 7.) once pressed, the ace1202t exits the low-power halt mode and sends a normal frame. the normal frame will be transmitted continuously as long as k2 is low or until the transmission timeout expires. 2.3 k3/rxd C pin 4 transmitter key 3 (k3) is an active low input with an internal weak pull-up. pressing k3 sets bit 5 of the data field to 1 keeping track of the active key (see figure 7.) once pressed, the ace1202t exits the low-power halt mode and sends a normal frame. the normal frame will be transmitted continuously as long as k3 is low or until the transmission timeout expires. if the k3 is pressed after a power-on reset and flag enaksync in the option register is set, a sync_des_key frame is transmit- ted transferring the internal des key into the ace1202r eeprom memory. this special frame will only be sent one time authorizing the transmission of only the normal frames. (see section 5.0) in nrz mode, k3 is used to receive serial information from an external programmer or from ace1202r. 2.4 k4 C pin 5 transmitter key 4 (k4) is an active low input with an internal weak pull-up. pressing k4 sets bit 4 of the data field to 1 keeping track of the active key (see figure 7.) once pressed, the ace1202t exits the low-power halt mode and sends a normal frame. the normal frame will be transmitted continuously as long as k4 is low or until the transmission timeout expires. if the k4 is pressed after a power-on reset and flag enacsync in the option register is set, a sync_des_cnt frame is transmit- ted transferring the internal des counter into the ace1202r eeprom memory. this special frame will only be sent one time authorizing the transmission of only the normal frames. (see section 5.0) 2.5 led C pin 3 the led output is driven in sink mode and is activate during the interframe time (with a pause between frames.) this output is also used to indicate a low battery condition (see section 10.0) by turning on the led once in a consecutive series of frames. 2.6 txd C pin 6 txd is the transmitter output and is used in both the pwm and nrz communication modes. in pwm mode, txd is used to send encoded information to an external rf transmitter stage using the pwm coding scheme (1/3 or 2/3). in nrz mode, txd is used to transmit serial information to an external programmer or the ace1202r. 2.7 v cc and gnd C pins 8 and 7 v cc and gnd are the power supply lines. the ace1202t is designed to work with a standard 3.0v lithium battery. it can also work with a 5.0v supply voltage; however, the low-battery thresh- old is calibrated for only a 3.0v operation. figure 2. transmitter block diagram key1 key2 key3 key4 1 2 3 4 8 7 6 5 v cc gnd 3v lithium battery stage rf txd k4 k1 k2 led k3/rxd ace1202t
3 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 3.0 electrical characteristics absolute maximum ratings ambient storage temperature -65 c to +150 c input voltage -0.3v to v cc +0.3v lead temperature (10s max) +300 c electrostatic discharge on all pins 2000v operating conditions ambient operating temperatures: ACE1202TEM8 -40 c to +85 c operating supply voltage: from -40 c to +85 c 2.2v to 5.5v relative humidity (non-condensing) 95% eeprom write limits see dc electrical characteristics preliminary ACE1202TEM8 dc electrical characteristics for v cc = 2.2 to 5.5v all measurements are valid for ambient operating temperature range unless otherwise stated. symbol parameter conditions min typ max unit i cc 3 supply current - no 2.2v 0.4 1.0 ma data eeprom write 2.7v 0.7 1.2 ma in progress 3.3v 1.2 2.0 ma 5.5v 3.7 5.5 ma i cch halt mode current 3.3v @ -40 c to 25 c 10 100 na 5.5v @ -40 c to 25 c 60 1000 na 3.3v @ +85 c 75 1000 na 5.5 @ +85 c 400 2500 na v ccw eeprom write voltage data eeprom in 2.4 5.5 v operating mode s vcc power supply slope 1 s/v 10ms/v v il k1, k2, k3/rxd, k4 with v cc = 2.2 - 5.5v 0.2v cc v schmitt trigger buffer v ih k1, k2, k3/rxd, k4 with v cc = 2..2 - 5.5v 0.8v cc v schmitt trigger buffer i ip input pull-up current v cc = 5.5v, v in = 0v 30 65 350 a i tl tri-state leakage v cc = 5.5v 2 200 na v ol output low voltage: v cc = 2.2v - 3.3v txd 3.0 ma sink 0.2v cc v led 5.0 ma sink 0.2v cc v output low voltage: v cc = 3.3 - 5.5v txd 5.0 ma sink 0.2v cc v led 10.0 ma sink 0.2v cc v v oh output high voltage: v cc = 2.2v - 3.3v txd 0.4 ma source 0.8v cc v led 0.8 ma source 0.8v cc v output high voltage: v cc = 3.3 - 5.5v txd 0.4 ma source 0.8v cc v led 1.0 ma source 0.8v cc v 3 see figure 5 for or i cc active data with eeprom writes.
4 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter preliminary ACE1202TEM8 ac electrical characteristics for v cc = 2.2 to 5.5v all measurements are valid for ambient operating temperature range unless otherwise stated. parameter conditions min typ max unit instruction cycle time from internal 5.0v at + 25 c 0.9 1.0 1.1 s clock - setpoint internal cycle voltage-dependent 3.0v to 5.5v, constant 5% frequency variation temperature internal clock temperature-dependent 3.0v to 5.5v, full 10 % frequency variation temperature range internal clock frequency deviation for 3.0v to 4.5v, constant 2% 0.5v drop temperature eeprom write time 310ms internal clock start up time (note 5) 2 ms oscillator start up time (note 5) 2400 cycles preliminary ACE1202TEM8 low battery detect (lbd) characteristics, v cc = 2.2 to 5.5v parameter conditions min typ max unit lowbattlev addr. 0x67 -40 c 2.45 v eewritelev addr. 0x68 -40 c 2.2 v lowbattlev addr. 0x67 0 c 2.63 v eewritelev addr. 0x68 0 c 2.3 v lowbattlev addr. 0x67 +25 c 2.67 v eewritelev addr. 0x68 +25 c 2.44 v lowbattlev addr. 0x67 +85 c 2.87 v eewritelev addr. 0x68 +85 c 2.55 v preliminary ACE1202TEM8 brown-out reset (bor) characteristics, v cc = 2.2 to 5.5v parameter conditions min typ max unit bor trigger threshold -40 c 1.98 v 0 c 2.06 v +25 c 2.12 v +85 c 2.27 v
5 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 3.1 preliminary ac & dc electrical characteristic graphs figure 3. internal oscillator frequency figure 4. power supply rise time t s min t s actual t s max time v cc v batt 1v name parameter unit v cc supply voltage [v] v batt battery voltage (nominal operating voltage) [v] t s min minimum time for v cc to rise by 1v [ms] t s actual actual time for v cc to rise by 1v [ms] t s max maximum time for v cc to rise by 1v [ms] s vcc power supply slope [ms/v] internal osc. frequency vs. temperature 1.60 1.70 1.80 1.90 2.00 2.10 2.20 -40 0 25 85 125 temperature (c) frequency (mhz) 2.2v 2.7v 3.3v 5.5v
6 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter figure 5. i cc active icc active (no data eeprom writes) vs. temperature 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 -40 0 25 85 125 temperature (c) icc active (ma) 2.2v 2.7v 3.3v 5.5v icc active (data eeprom writes) vs. temperature 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 -40 0 25 85 125 temperature (c) icc active (ma) 2.7v 3.3v 5.5v
7 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter figure 6. halt current halt current vs. temperature 0 200 400 600 800 1000 1200 1400 1600 -40 0 25 85 125 temperature (c) icc halt (na) 3.3v 5.5v
8 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 4.0 general characteristics the ace1202t is intended for use with the ace1202r product. this chip-set forms a secure and inexpensive system for a variety of applications that require a high level of security such as remote keyless entry or software protection. the basic function of the ace1202t is to transmit a des coded frame containing a fixed identifier (24-bit), data field (8-bit), des code (32-bit), a sequential counter (16-bit), and a parity field. this frame is received in a pwm coded format suitable for a rf system or a nrz format used in a direct wire connection. 4 this frame will be compared with previously stored information in order to match the fixed and dynamic part of the code message. 4.1 mode of operations the ace1202t can be programmed to work in three different modes as indicated in table 5 and as described in later sections. table 5 ace1202t operating modes operating modes description pwm mode indicated to work with a rf module nrz mode indicated to work with wired connection programming mode to select and program the user- defined area 4 pwm coding is typically used for a rf transmission, but nrz coding can also be used. however, the bit rate tolerance is a cri tical aspect to consider for extracting the correct information. we suggest adopting nrz mode for wired direct connection.
9 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 5.0 des message description the des coded message is 12-bytes wide and is divided into fields transmitted in the following order: preamble sent only once as a continuous series of frames used to wake the receiver from halt mode. sync field 8 coded bits for the synchronization of the incoming data stream. data field contains information about the channel selected and special transmitting modes: des_key and des_counter. it is 8 bits wide. fixed field a unique 24-bit code that identifies the transmitter. des field the 32-bit des generated code. counter field the lower 16 bits of the des counter. parity field byte-wise exclusive-or from sync field to des field. the frame type selection bits of the data field configures the des field for one of three configurations. the three des frame configu- rations are the normal frame, the sync_des_key frame, and the sync_des_cnt frame. (see figure 7) 5.1 sync field the sync field is 8-bits wide and identifies the start of the des frame. 5.2 fixed field the fixed field is three bytes (24-bits) long and is used to identify the individual transmitter. if the fixed field is not found in the ace1202r memory, the frame will be rejected. the ace1202r must learn the fixed field while in a special operating mode. 5 5.3 data field the data field contains the current configuration of the transmission. bits 7 to 4 decode the binary transmitter key configuration. the least significant nibble selects the frame type. see table 6 for details. table 6 data field bit definition bit value description bit 7 1 key1 has been pressed bit 6 1 key2 has been pressed bit 5 1 key3 has been pressed bit 4 1 key4 has been pressed bit 3-0 frame type selection: 0000 normal 0010 des key sync 0011 des counter sync 1111 low battery 5.4 des code field the des code field is the 32 most significant bits of the calculated des algorithm using the known des key and counter. (see section 6.0) this field is compared with the des code calculated internally by the receiver. this field is only sent in the normal frame. 5.5 counter field the counter field is the 16 least significant bits of the internal 64- bit des counter. the counter is used to synchronize the des operation on the receiver side. this field is transmitted only in the normal frame. this information helps track the current des progression held in the linear des counter. normally, only one calculation is needed to determine the current des code. 5.6 parity field the parity field is present in all the frames and contains the checksum for the frame transmitted. the checksum is the exclu- sive-or of all bytes received in the frames starting from sync field. 5.7 des key field the des key field is the security des key used in the algorithm to calculate the current des code. the four least significant bits in the data field indicate to the receiver that a sync_des_key frame (0x02) will be received. the receiver will store the des key in the internal register for future normal frame decoding. the true length of the des key is 56-bits wide. the des key field is 48 bits wide (addr. 0x45 to 0x4a duplicated in addr. 0x75 to 0x7a) and the remaining 8 bits of the des key is a user defined value, stored in memory (addr. 0x4b, duplicated in addr. 0x7b) during factory programming, otherwise it is defaulted to 0x00. if pin 1 of the ace1202r is set to logic 0 , the receiver will ignore any sync frame requests. 5.8 des counter field the des counter field is the 48-bit des counter used in the algorithm to calculate the current des code. the four least significant bits in the data field indicate to the receiver that a sync_des_cnt frame (0x03) will be received. the des counter will be stored in the internal registers for future normal frame decoding. the true length of the des counter is 64-bits long. the des counter field is 48-bits and the remaining 16 least significant bits are set to 0 every time a sync_des_cnt frame is transmit- ted. if pin 1 of ace1202r is set to logic 0 , the receiver will ignore any sync frame request. 5 see section 7.1 of the ace1202r datasheet at www.fairchildsemi.com for details. sync field 8 bit fixed field 24 bit data field xxxx0000 des code 32 bit counter 16 bit parity 8 bit normal frame sync field 8 bit fixed field 24 bit data field xx1x0010 des key 48 bit parity 8 bit sync_des_key frame sync field 8 bit fixed field 24 bit data field xxx10011 des counter 48 bit parity 8 bit sync_des_cnt frame figure 7. normal and sync frames
10 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 6.0 des algorithm with the help of the national security agency the national bureau of standards certified the data encryption standard (des) in 1977 to be used in electronic devices for the protection of coded data during transmission and storage in a computer system or network. the des algorithm is different from other cryptographic algo- rithms in that it is not kept in secret like the others. the des algorithm is public and the system security is based on a secret key (des key) of 56-bits plus 8-bits of parity known only by the transmitter and receiver. the des key must be transmitted or directly stored in the transmitter / receiver memory. the implementation of the des algorithm used in the ace1202r and ace1202t chip-set does not use the initial and final permu- tations normally used in des, as there is no benefit in implement- ing these permutations where des is used for authentication. figure 8 shows how the des algorithm encodes a 64-bit counter using a 56-bit des key to obtain the 64-bit des code. 64-bit des code 32 lsb bits of des code 16 lsb bits of des counter des algorithm sync field 8 bit fixed field 24 bit data field xxxx0000 des code 32 bit counter 16 bit parity 8 bit 56-bit des key 64-bit counter figure 8. des algorithm data flow
11 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 7.0 user area: it is possible to read, write, or protect the user-defined area using a two-wire programming interface. the programming interface operates as a half duplex asynchronous protocol with txd (pin 6) and rxd (pin 4) dedicated lines with communications using the nrz format. the nrz format operates at a baud rate of 4800bps and a data frame format of 8 data bits, 1 start bit, and 1 stop bit. in order to enter programming, mode pins 4 and 6 must be at logic 1 level during power-up. after 500ms the part is ready to accept command from an external programmer. the first message must be a character corresponding to the hex value 0x55 needed to calibrate the internal baud-rate register. upon reception of the baud adjustment message, ace1202t will respond with an acknowledge message to inform the external programmer to be ready to receive new messages. the message structure is variable in length and follows the form: a) [0x55]: sent only to ace1202t b) nbytes : the number of bytes to send 1 c) opcode : op-code field d) data : variable field from 1 to 15 bytes depending on op- code e) checksum : logical byte-wise exclusive-or of the previous fields b) to c) characters are spaced by a delay of 5ms. possible messages are: eeprom read (progr. to ace1202t) 0x55 + nbytes + read_usr_area + addr. + checksum (to read any location in user area) nbytes = 3 read_usr_area = 0x38 this message is valid only if the rd_protect bit is zero in options address (0x60). if the operation is executed correctly, the ace1202r will return the message: nbytes + read_usr_area + addr. + read_value + checksum , otherwise the message unknown will be returned. eeprom write (progr. to ace1202t) 0x55 + nbytes + write usr_area + addr.+ value + checksum (to write any location in user 0x55 + area) nbytes = 4 write_usr_area = 0x93 this message is valid only if the wr_protect bit is zero in options address (0x60). if the operation is executed correctly, the ace1202r will return the message: nbytes + write_usr_area + addr. + programmed_value + checksum , otherwise the message unknown will be returned. des frame (ace1202r to ace1202t)/des valid (ace1202t to ace1202r) [0x55 +] nbytes + des_frame + fixedhigh + fixedmid + fixedlow + data + cnt0 + cnt1 + des3 + des2 + des1 + des0 + checksum (represent the des frame to be checked by the internal algorithm see section 12.0 for more details) nbytes = 12 des_frame = des_valid = 0x5a if the message has the correct checksum and valid des code, it will answer with the next des code generated by incrementing the des counter. if the message contains an invalid des code ace1202t will re-send the same message back to ace1202r (see section 12.0). the 0x55 preamble is sent only from ace1202r to ace1202t (des_frame). des key and counter info (ace1202r to ace1202t) 0x55 + nbytes + des_par + syncfield + fixedhigh + fixedmid + fixedlow + des_key0 + des_key1 + des_key2 + des_key3 + des_key4 + des_key5 + des_key6 + des_cnt0 + des_cnt1 + des_cnt2 + des_cnt3 + des_cnt4 + des_cnt5 + des_cnt6 + des_cnt7 + checksum (see figure 14a). nbytes = 18 des_par = 0x44 this frame is sent when the ace1202t is not in programmed state (blanked) and it is used to store the des parameters, des key, des counter and fix code into ace1202t user area. status request (ace1202r or progr. to ace1202t) 0x55 + nbytes + tx_stat_req + ace-t_state + sw_revision + checksum (this message is only sent after pc connection following the inquire (0x55) parameter.) nbytes = 4 tx_stat_req = 0x80 ace-t_state = 0x6d-> tx has no des information stored in memory ace-t_state = 0xe2 -> tx has des information stored in memory sw_revision: bit0 to 3 = data eeprom revision bit4 to 7 = code revision exit 0x55 + nbytes + exit + checksum (to exit from programming mode ) nbytes = 2 exit = 0x2b
12 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 7.1 message table table 7. nrz messages message byte sent 1 op-code meaning read_usr_area 3 0x38 progr to ace1202t - read one location at specified address write_usr_area 4 0x93 progr to ace1202t write data at specified address des_frame 12 0x5a ace1202r to ace1202t send current des code des_param 21 0x5a ace1202t to ace1202r next calculated des code rx_stat 3 0x80 ace1202t to progr. actual ace1202t status exit 2 0x2b progr to ace1202t exit from progr connection unknown 2 0x55 ace1202t response to invalid messages des_valid 12 0x44 ace1202r to ace1202t send des key and counter 7.2 programming recommendations: ace1202t and ace1202r are delivered from the factory with default values loaded into user area allowing the designer to perform a test on the parts without data initialization.the program- ming interface is designed to allow easy in-circuit programming using the 4-wires interface. it is the responsibility of the user to load the appropriate value in the user area. it is recommended always to set the read and write protection bits prior to terminat- ing the programming process. if further programming is needed, the read protection bit should be enabled to avoid external reading of des information which need to remain secret to avoid system intrusion.
13 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 7.3 user area table table 8 user area registers addr. label description note 6 0x40 free 0x41-0x71 sync field 8 bit synchronization field read/write 0x42-0x72 fixhigh 24 bit fixed code high part read/write 0x43-0x73 fixmid 24 bit fixed code mid part read/write 0x44-0x74 fixlow 24 bit fixed code low part read/write 0x45-0x75 des_key0 56 bit des key byte 0 read/write 0x46-0x76 des_key1 56 bit des key byte 1 read/write 0x47-0x77 des_key2 56 bit des key byte 2 read/write 0x48-0x78 des_key3 56 bit des key byte 3 read/write 0x49-0x79 des_key4 56 bit des key byte 4 read/write 0x4a-0x7a des_key5 56 bit des key byte 5 read/write 0x4b-0x7b des_key6 56 bit des key byte 6 user defined. read/write 0x4c-0x7c des_key_check des _k+ fixed checksum value read/write 0x4d des_cnt0_a 64 bit des counter byte 0 bank 0 - read/write 0x4e des_cnt1_a 64 bit des counter byte 1 bank 0 - read/write 0x4f des_cnt2_a 64 bit des counter byte 2 bank 0 - read/write 0x50 des_cnt3_a 64 bit des counter byte 3 bank 0 - read/write 0x51 des_cnt4_a 64 bit des counter byte 4 bank 0 - read/write 0x52 des_cnt5_a 64 bit des counter byte 5 bank 0 - read/write 0x53 des_cnt6_a 64 bit des counter byte 6 bank 0 - read/write 0x54 des_cnt7_a 64 bit des counter byte 7 bank 0 - read/write 0x55 des_cnta_check counter a checksum bank 0 - read/write 0x56 des_cnt0_b 64 bit des counter byte 0 bank 1 - read/write 0x57 des_cnt1_b 64 bit des counter byte 1 bank 1 - read/write 0x58 des_cnt2_b 64 bit des counter byte 2 bank 1 - read/write 0x59 des_cnt3_b 64 bit des counter byte 3 bank 1 - read/write 0x5a des_cnt4_b 64 bit des counter byte 4 bank 1 - read/write 0x5b des_cnt5_b 64 bit des counter byte 5 bank 1 - read/write 0x5c des_cnt6_b 64 bit des counter byte 6 bank 1 - read/write 0x5d des_cnt7_b 64 bit des counter byte 7 bank 1 - read/write 0x5e des_cntb_check counter b checksum bank 1 - read/write 0x5f eepntr des counter pointer (cnt_a or cnt_b) read 0x60 options operation options read/write 0x61 tx_preamble delay between preamble field and sync read/write step 1ms 0x62 tx_interframe pause between frames read/write step 1ms 0x63 tx_timeout continuous transmission timeout read/write step 1s 0x64 lowbattcntr no. of consecutive low battery samples read/write 0x65 baud_adj adjusted baud-rate value read 0x66 acetx_state functional transmitter state read/write 0x67 lowbattlev low battery threshold level read 7 0x68 eewritelev min. writing voltage read 7 0x69 lowbattled led duration in low battery state read/write 0x6a maxlbattact no. of possible tx activation in low battery read/write 0x6b pwm_time change pwm timing from 256 to 512 s read/write. step 1 s 0x6c datacode data field sent in nrz mode red/write 0x6d factory data1 free read/write 0x6e factory data2 free read/write 0x6f data revision data eeprom revision read 0x70 numpreamble number of pwm bit sent in preamble read/write 6 though some location are indicated as read only it is still possible to change its contents, however, we recommend to not modi fy these values unless agreed with fairchild. 7 these locations are factory calibrated and must not be changed to avoid incorrect low-battery detection.
14 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 7.4 options register (addr. 0x60) bit 0 C enaksync if set to '1,' the des key synchronization frame will never be sent. the ace1202r must be factory-coupled with the ace1202t or programmed with a wire connection. if set to '0,' the des key is sent only one time after a power-up condition (pressing k3). bit 1 C enacsync if set to '1,' the des counter synchronization frame will never be sent. the ace1202r must be factory-coupled with the ace1202t or programmed with a wire connection. if set to '0,' the des counter is sent only one time after a power-up condition (pressing k4). bit 2 C distimeout if set to '1,' no timeout condition exists when a key is continuously pressed. tranmission will stop as soon as no key is pressed. if set to '0,' the timeout is determined by tx_timout in seconds. bit 3 C setpwmtime if set to '1,' the pwm clock timing is defined by the pwm_time register (0x6b) and can vary from 256 to 512 s. if set to '0,' the pwm timing is fixed to 500 s. bit 4 C forcenrz when this bit is set to '1,' the ace1202t enters the nrz mode regardless the port level on txd and rxd after a power-on reset. this option can be used when the only mode requested is nrz and save external pull-ups on rxd and txd pins. bit 5 C unused bit 6 C rd_protect if set to '1,' reads to the user area registers are no longer possible. once this bit set to '1,' this register cannot be written to again. bit 7 C wr_protect if set to '1,' writes to the user area registers are no longer possible. when the write protection option is disabled and read protection is enabled, an external write operation will force a read of the same location for verification. figure 9. options register bit definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wr_protect rd_protect x forcenrz setpwmtime distimeout enacsync enaksync
15 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 7.5 register tx_preamble (addr. 0x61) tx_preamble determines the pause between the preamble field and the sync field. it must be defined according to receiver's characteristics (wakeup time, rf sensitivity). the preamble is sent during the first frame only, with a correction step of 1ms. 7.6 register tx_interframe (addr. 0x62) tc_interframe determines the pause between consecutive frames. during this time the led is switched on with a correction step of 1ms. 7.7 register tx_timeout (addr. 0x63) tx_timeout defines the maximum transmission time when a key is pressed continuously. if the distimeout bit in the option register is set, the timeout in infinite (as long as the key is pressed). 7.8 register lowbattcntr (addr. 0x64) lowbattcntr defines the number of low battery consecutive samples, minus one, before entering the 'low battery' state. the counter is reset every time the battery voltage is above the low battery threshold (defined in lowbattlev register). (refer to the low battery detect s electrical specification.) 7.9 register baud_adj (addr. 0x65) the baud_adj register contains the auto-adjusted baud rate value. this value is automatically written after a connection with an external programmer; therefore re-writing this register is not recom- mended. 7.10 register acetx_state (addr. 0x66) acetx_state represents the transmitter's actual state. it con- tains the value 0x6d if no des parameters are stored in the user area (blank from factory). once the des information is transferred into the user area, the external programmer must take care to write the value 0xe2 into this location. if during a normal operation the des fix blocks (0x40 - 0x4c and 0x71 - 0x7c) are invalid, the transmitter will write 0x6d in acetx_state while waiting for an external programmer con- nection. 7.11 register lowbattlev (addr. 0x67) lowbattlev determines the voltage threshold where the battery in use is considered low. the value is chosen to match 3.0v lithium battery characteristics in order to guarantee as many writing operations as defined in register lowbattcntr before entering the disable state . (refer to the low battery detect s electrical specifi- cation.) 7.12 register eewritelev (addr. 0x68) eewritelev determines the lowest voltage level that data eeprom writes can occur. when the battery voltage is above this limit, a write operation into the data eeprom is possible, otherwise the writes are skipped. (refer to the low battery detect s electrical specification.) 7.13 register lowbattled (addr. 0x69) lowbattled determines the duration of the led flashes when the ace1202t is in the low battery state (the correction step is 1ms). during this state, the led will flash only once in a continuous series of frames. 7.14 register maxlbattact (addr. 0x6a) once ace1202t is in the low battery state, maxlbattact detemines the number of new transmissions, minus one, before entering the disabled state (no transmission) while waiting for the battery to be replaced. (refer to the low battery detect s electrical specification.) 7.15 register pwm_time (addr. 0x6b) when bit setpwmtime in the options register is set, pwm_time determines the pwm clock timing used to send the frames. the formula to obtain the pwm clock is 10 6 / (256 + pwm_time) in hertz. (see section 8.0) 7.16 factory data1 to 3 (0x6d to 0x6f) these unused locations could be programmed to hold user factory information such as production date to track lot and testing information. 7.17 software revision (0x6f) contains the eeprom data version (0 to 0xf) and can be read through an external programmer by asserting an inquire com- mand (0x55). only bits 0 to 3 are used, always keep the remaining bits to '0.' 7.18 numpreamble (0x70) numpreamble determines the number of pwm coded zeros sent in the preamble field. this allows for the adaptation of the ace1202r wakeup time when the receiver switched mode 9 supply is used. 9 see section 10.0 of the ace1202r datasheet at www.fairchildsemi.com for details.
16 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 8.0 pwm mode the pulse width modulation (pwm) mode works in those applica- tions where the tolerance of the coded signal must be large, such as in rf transmission. the bit coding is defined as 1/3 or 2/3 duty to distinguish between a coded '0' and a coded '1' respectively (see figure 10). if the set pwmtime bit in the options register is '0,' each coded bit is created in three phases for a total of 1.5ms (pwm clock = 2khz). if it is set to '1,' the pwm clock is 10 6 / (256 + pwm_time). the ace1202t, after a power-on reset, samples the k3/rxd and txd lines. if one or both lines are low the device enters the pwm mode. the device then loads the des counters from the user area into working memory. if both des counters are invalid, the device stops waiting for external programming connection. the address 0x66 will then be loaded with the value 0x6d to inform the external programmer (or ace1202r) that the transmitter is not programmed. (the same process is applied to the des key fix parameter.) when valid des key and counter are found in the user area, the ace1202t will start the normal pwm operation waiting for a key depression to send the appropriate frame. as long as the electronic keys are not pressed, the ace1202t will remain in halt mode. after power-on reset, it is also possible to send synchronization frames if bits enaksync and enacsync in the options register are both set to '0.' this allows the ace1202r to receive and store the needed des parameter in order to decode incoming normal frames. the ace1202t can send only a series of synchronization frames by depressing k3 to send the des key message (datafield = 0x23) or k4 to send the des counter message (datafield = 0x12). a new transmission, using the same key, will send nor- mal frames encoding the key depressed information in the data field. to send a new sync frame it is necessary to remove the battery, assuring that the internal capacitors are discharged, to issue a new power-on reset to the ace1202t. once the key is pressed, the ace1202t will exit from halt mode, increment the des counter, and send the normal frames. the preamble is the first field sent and is a series of pwm coded zeros. the number of preamble bits is defined in the numpreamble register (0x70). after the ace1202t transmits the preamble, a pause (no carrier) is followed. the length of the pause is defined by the tx_preamble register. the preamble is sent only during the first frame. the transmission frame start with 8-bit syncfield used by the receiver to recognize the arrival of a new frame in order to synchronize the bit shift in to the receiving buffer. the next field sent is the fixed code used to identify a unique transmitter. the fixed code is 24-bits long transmitted from msb to lsb. if the frame is normal, sync key, sync counter, and if ace1202t is in the low battery state, the fixed code is followed by the data field which contains the stored key(s) depression information. depending on the information sent in the data field, the rest of the frame assumes the following meaning: if data field = normal frame 32-bit of des code (from msb to lsb) 16-bit des counter lower part (from msb to lsb) 8-bit parity field (byte-wise exclusive of all previous fields excluding preamble) if data field = sync key frame 48-bit of des key (from msb to lsb) 8-bit parity field (byte-wise exclusive of all previous fields excluding preamble) if data field = sync counter frame 48-bit of des counter (from msb to lsb) 8-bit parity field (byte-wise exclusive of all previous fields excluding preamble) after sending a complete frame there will be a pause, determined by the tx_interframe register, where the led will be activated. at the end of the pause the key(s) are sampled again. if no key is depressed, the ace1202t will return to halt mode; otherwise, the frame will be repeated until the keys are released or a transmission timeout is reached (defined by the tx_timeout register). if the distimeout is set, the transmission of the same frame will be repeated until all keys are released. coded '0' coded '1' frame1 - 96 bits frame2 - 96 bits led output led active txd preamble tx_preamble tx_interframe note: the number of pulses in the preamble is defined in numpreamble (0x70) register. figure 10. pwm encoding bits figure 11. frames transmission and preamble
17 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 9.0 battery management each time a key is pressed, the ace1202t will sample the low battery detect (lbd) comparator output where the threshold level is defined in the lowbattlev register. if the battery voltage is lower than the selected threshold level, the lowbattcntr register is decremented. when it reaches zero, the low battery state is asserted. if the voltage is found above the threshold level, the lowbattcntr is set to the initial counting value regardless of the number of low-battery samples found. once in the low battery state, the following operation will be executed: 1. the led will be activated only during the first frame. the duration is determined in the lowbattled register. 2. the data field lower nibble is set to '1111.' 3. a new threshold will be applied on lbd comparator to detect for a battery replacement. this threshold is fixed and corresponds to 2.8 - 2.9v. 4. the maxlbattact register is decremented. 5. the des counter is no longer updated in the data eeprom only ram. on a new key activation, the battery voltage will be compared with the new threshold. if the battery is replaced and the level is above the new threshold, the ace1202t will automatically reset and resume its normal operation. however, a new key must be pressed to clear the low battery condition. if the battery is still low, the maxlbattact is decremented. when it is one, the ace1202t will enter in a disabled state where no further transmission is possible. once in the disabled state, the only process working is the battery replacement check. if a new battery is put in place, the process restarts at the second key activation. when the ace1202t battery is replaced, it is possible that a power-on reset will happen and the des counter copied to ram is lost. to prevent this situation, at every power-on reset, the value of the des counter loaded from user area is added with the value defined in maxlbattact plus 16 since the des counter is updated in eeprom every 16 cycles to minimize the eeprom writing operation.
18 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 10.0 typical rf application circuit: figure 12 shows the ace1202t used in a rf transmitter with four buttons. the message is sent with cw modulation of a carrier frequency generated by the rf output stage with a saw resonator. the saw resonator must be chosen in accordance with the local frequency allocation (433.92mhz for europe, 315mhz for north america). the transmitter uses the programming interface if the user area is loaded after the pcb assembly or if the des information is programmed into the ace1202t with a wire connection not through the sync frame. the signal e is used by the ace1202r to activate the nrz mode and can be omitted in the other case (user area programming only). 7 t +vbatt +vbatt antenna ace1202t saw reson. factory programming interface + e - r 1k1 k2 k3 k4 2 3 led txd 6 4 5 8 v cc gnd figure 12. rf transmitter schematic with programming interface
19 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 11.0 nrz mode (bidirectional) the nrz mode is suited for wired operating applications, such as software protection, where the transmitter unit (ace 1202t) can be connected through a dedicated connector to the receiver (ace1202r). to enable the nrz mode, pins 4 and 6 must be high for at least 200ms following a power-on reset. upon connection, the transmitter senses a polling message coming from the ace1202r txd line on pin 4 (k3/rxd). the polling message contains two bytes. the transmitter uses the first byte (0x55) of the polling message to auto-calibrate its internal baud-rate. the second byte is a request from the receiver for the transmitter s status information. once the transmitter is cali- brated, the status information is sent. the status value can be: programmed (internal codes stored in ace1202t) blanked (not yet coupled with ace1202r) if ace1202r is connected to a blanked transmitter, it will automatically send a frame containing the fixed code, des key, and des counter. in order to send the des information, the bit despar in the options register must be set to 1. the ace1202t will store this information in its user area and will reply to the ace1202r with a new status message informing the receiver of the change to programmed mode. once this information is received, the ace1202r will periodically transmit a status request message (0x55) to the transmitter. (the timing is defined in register rxawake with a 50ms step size.) the ace1202t will use the status request message to adjust the internal baud rate and answer with its internal status. at this point, the ace1202t responds with programmed. the ace1202r will then send the des coded message [des_frame] corresponding to the actual value of the des counter. the ace1202t will compare the information received with its internal des code. if a match is found, the next des code (obtained by incrementing the internal des counter) will be sent back to ace1202r for validation. if there is no match with the des code sent from the ace1202r, the same code will be sent back. once a validation cycle has completed, the value received in the data field (bit7 to 5) is put into the ace1202r output ports (o1 to o4). 7 8 5 4 wup/rxd onr/txd ace1202r ace1202t 6 4 txd rxd 2 6 o1 o2 o3 o4 figure 13. nrz connection
20 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 12.0 connection messages figure 14 shows the communication protocol between the ace1202t and the ace1202r. the ace1202r continuously sends an inquire message (0x55) to the ace1202t until the transmitter answer with its status information. when a blanked ace1202t is connected, the ace1202r provides the des infor- mation needed to perform the des algorithm 10 . the ace1202t will store the des key and counter and change its state to programmed. when the next inquire message is received by the ace1202t, it will inform the ace1202r that it is in the programmed state. the ace1202r will then send the next des code for validation by ace1202t. if the des code is acknowledge, the ace1202t will reply with the next des code (des counter is incremented by one) for validation by ace1202r. after the ace1202r des code is validated, the des counter is updated. otherwise, the old value is maintained and the data field contents will be placed on the outputs (o1-o4.) the data field is loaded with the contents of the datacode register (0x6c) defined in the ace1202t user area. figure 14. ace1202t (ace_t) with ace1202r (ace_r) connection 10 bit despar in the options register must be set to '1.' (refer to ace1202r datasheet for details.) fixedhi fixedmid fixedlo key0 key1 key2 key3 key4 key5 cnt2 cnt3 cnt4 cnt5 cnt6 cnt7 chks 0x55 18 0x44 sync ace_t will store the des information changing the state to programmed 4 0x80 0x6d sw_rev chks 0x55 0x55 0x55 0x55 ace_t status inquire ace_t inquire ace_t ace_r ace_t blanked not connected connected fixedhi fixedmid fixedlo data cnt0 cnt1 roll2 roll3 chks 0x55 12 sync 4 0x80 0xe2 sw_rev chks 0x55 0x55 ace_t status inquire ace_t ace_r ace_t programmed connected des code @ counter fixedhi fixedmid fixedlo data cnt0 cnt1 roll2 roll3 chks 12 sync roll0 roll1 roll0 roll1 des code @ ++counter cycle is repeated sending another inquire tx command 0x55 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 5 ms stop bit start bit note: all the bytes transmitted or received must be spaced at least 5ms apart. a) communicating with a blanked ace_t b) communicating with a programmed ace_t c) serial data protocol
21 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 13.0 application circuits 13.1 2-wire connection 11 the circuit in figure 15, shows how to implement a simple 2-wire connection between the ace1202t and the ace1202r. the line 'a' carries power supply and data information that is roughly one-volt modulation over the established dc voltage level. the power is delivered from the receiver unit while the transmitter acts as a passive key. if needed, the supply source can be inverted (the ace1202t is the source and the ace1202r is the passive element). capacitor c1 delivers current to ace1202t during the message modulation, on both ace1202t and ace1202r, and it is the key element to demodulate information sent. after connection, c1 is charged from r8 in a time faster than 50ms (this time required for the internal power-on reset circuit to operate correctly). after connection, both circuits (ace1202t and ace1202r) detect a nrz connection mode reading '1' on respec- tive rxd and txd lines. at this moment ace1202r starts to interrogate ace1202t with message 0x55 until it receives a status response from ace1202t. the process continues as indicated in section 11.0. the proposed circuit does not provide electrical protection in case the boards are connected to a non-compatible soure or extreme electrical noise. the led informs the user about the correct des algorithm acknowledge and des parameter stored. the use of this led is optional. figure 15. ace1202t/ace1202r 2-wire connection 11 component values and schematic not tested in a real application. + ace1202r gnd 7 gnd 5 4 rxd txd 7 14 v cc +5v r8 150 r6 270 t2 bc557 r7 10k r5 220k c3 100n c2 100n d3 1n414 decoded outputs 8 8 6 3 v cc led 2 6 o1 o2 o3 o4 d2 led a b d1 1n414 4 txd rxd r4 47k r3 2k2 r2 10k t1 bc557 ace1202t c1 10 r1 220
22 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 13.2 rf rke system with active/passive transmitter using the same 2-wire interface described in section 13.1, it is possible to build a rke system that allows the ace1202t to send information in pwm mode using the rf link or act as a passive key if connected through the 2-wire connection in nrz mode. the passive functionality could be employed as emergency enable/ disable of the system or to program des information into the ace1202t user area. in this case, the secret information is not sent through the rf channel.to enable this possibility, pin 1 (lrn) of the ace1202r must be connected to gnd. the system can work with or without a battery on the transmitter battery-holder. + + ace1202r module rf 13 7 gnd 5 11 4 rxd rxin txd 7 14 v cc gnd +5v r8 150 r6 270 t2 bc557 r7 10k +5v r5 220k c4 100n c3 100n c2 100n d5 1n4148 8 8 6 3 2 6 1 o1 o2 o3 o4 lrn d4 led a b d3 1n4148 4 txd k3/rxd r4 47k 5 2 1 v cc led k4 k2 k1 r3 2k2 to switches sw1, sw2, sw4 r2 10k t1 bc557 sw3 push-b ace1202t c1 10 d1 bar43 d2 bar43 3v lithium battery r1 220 rf tx stage figure 16. rke system with 2-wire interface
23 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 13.3 dongle key (coded entry protect) the ace1202 low power consumption makes it possible to realize a dongle key connected to a pc serial port. the power supply is taken from the rs232 handshake lines (cts-rts and dsr-dtr) not used in the communication protocol between the ace1202t and the pc software. the pc software acts as an ace1202r unit, described in section 11.0, programming and verifying the des code exchanged from the two systems. this system can be used in software protection for user validation or access control. figure 17. dongle key 15 11 12 6 c2 10 f c1 10 f d1 bar43 db9 5 4 3 6 7 8 9 2 1 ++ 4 txd rxd 7 c3 c4 c5 c6 100n c7 100n 100n 100n ace1202t u3 ka78rm33 u3 max3232 u2 3 13 14 1 5 c1- r1i t1o c1+ c2- 2 6 t1i r1o v+ v- 16 v cc gnd c2+ 8 v cc gnd
24 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 14.0 brown-out reset the brown-out reset (bor) function is a standard feature of the ace1202 product family used to hold the device in reset when v cc drops below a fixed threshold. (see bor electrical charac- teristics for the threshold voltage.) while in reset, the device is held in its initial condition until v cc rises above the threshold voltage, when an internal reset sequence is started. after the reset sequence, the core fetches the first instruction and starts normal operation. the bor should be used in situations when v cc rises and falls slowly and in situations when v cc does not fall to zero before rising back to its operating range. the bor can be thought of as a supplemental function to the power-on reset when v cc does not fall below ~1.5v. the power-on reset circuit works best when v cc starts from zero and rises sharply. so in applications where v cc is not constant the bor will provide added device stability. 76 1.8/2.2v ref. v cc bor comp to internal reset logic lbd control register + _ lbd comp + _ adj. reference voltage 543210 figure 18. bor/lbd block diagram
25 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter 15.0 power-on reset the power-on reset (por) circuit is guaranteed to work if the rate of rise of v cc is no slower than 10ms/1volt. the por circuit was designed to respond to fast low-to-high transitions between 0v and v cc . the circuit will not work if v cc does not drop to 0v before the next power-up sequence. in applications where 1) the v cc rise is slower than 10ms/1 volt or 2) v cc does not drop to 0v before the next power-up sequence, the external reset option should be used. the external reset provides a way to properly reset the ace1202r if por cannot be used in the application. the external reset pin contains an internal pull-up resistor. therefore, to reset the device, the reset pin should be held low for at least 2ms so that the internal clock has enough time to stabilize. figure 19. bor and por circuit relationship diagram v cc (pin 8) bor reset circuit output global reset to logic external reset pin (14-pin only) b a output por (pin 7) output v cc time bor output 1.75 0 v cc v cc 0 por output por output pulse 1.8v 0 v cc v cc 5.0v 0 the reset circuit will trigger when inputs a or b transition from high to low. at that time the global reset signal will go high which will reset all controller logic. the global reset will go high and stay high for around 1 s.
26 www.fairchildsemi.com ace1202t rev. a.6 ace1202t data encryption standard (des) trasmitter fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 physical dimensions inches (millimeters) unless otherwise noted molded small outline package (m8) order number ACE1202TEM8 package number m08a 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45

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