ht24lc04 4k 2-wire cmos serial eeprom block diagram pin assignment 1 6th may 99 features operating voltage: 2.4v~5.5v low power consumption operation: 5ma max. standby: 5 a max. internal organization 4k (ht24lc04): 512 8 2-wire serial interface write cycle time: 5ms max. automatic erase-before-write operation partial page write allowed 8-byte page write modes write operation with built-in timer hardware controlled write protection 40-year data retention 10 6 erase/write cycles per word 8-pin dip/sop/tssop package commerical temperature range (0 cto+70 c) general description the ht24lc04 is a 4k-bit serial read/write non-volatile memory device using the cmos floating gate process. its 4096 bits of memory are organized into 512 words and each word is 8 bits. the device is optimized for use in many in - dustrial and commercial applications where low power and low voltage operation are essen - tial. up to four ht24lc04 devices may be con - nected to the same two-wire bus. the ht24lc04 is guaranteed for 1m erase/write cy - cles and 40-year data retention.
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pin description pin no. pin name i/o description 1~3 a0~a2 i address inputs 4 vss negative power supply 5 sda i/o serial data inputs/output 6 scl i serial clock data input 7 wp i write protect 8 vcc i positive power supply absolute maximum ratings operating temperature (commercial) ................................................................................. 0 c to 70 c storage temperature ....................................................................................................... C50 c to 125 c applied v cc voltage with respect to vss ........................................................................ C0.3v to 6.0v applied voltage on any pin with respect to vss .................................................................. C0.3v to v cc +0.3v note: these are stress ratings only. stresses exceeding the range specified under absolute maxi- mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=0 c to 70 c symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 2.4 5.5 v i cc1 operating current 5v read at 100khz 2 ma i cc2 operating current 5v write at 100khz 5 ma v il input low voltage C1 0.3v cc v v ih input high voltage 0.7v cc v cc +0.5 v v ol output low voltage 2.4v i ol =2.1ma 0.4 v i li input leakage current 5v v in =0 or v cc 1 m a i lo output leakage current 5v v out =0 or v cc 1 m a i stb1 standby current 5v v in =0 or v cc 5 m a i stb2 standby current 2.4v v in =0 or v cc 4 m a c in input capacitance (see note) f=1mhz 25 c6pf c out output capacitance (see note) f=1mhz 25 c8pf note: these parameters are periodically sampled but not 100% tested ht24lc04 2 6th may 99
a.c. characteristics ta=0 c to 70 c symbol parameter remark standard mode* v cc =5v 10% unit min. max. min. max. f sk clock frequency 100 400 khz t high clock high time 4000 600 ns t low clock low time 4700 1200 ns t r sda and scl rise time note 1000 300 ns t f sda and scl fall time note 300 300 ns t hd:sta start condition hold time after this period the first clock pulse is generated 4000 600 ns t su:sta start condition setup time only relevant for repeated start condition 4000 600 ns t hd:dat data input hold time 0 0 ns t su:dat data input setup time 200 100 ns t su:sto stop condition setup time 4000 600 ns t aa output valid from clock 3500 900 ns t buf bus free time time in which the bus must be free before a new transmission can start 4700 1200 ns t sp input filter time constant (sda and scl pins) noise suppression time 10050ns t wr write cycle time 5 5 ms notes: these parameters are periodically sampled but not 100% tested * the standard mode means v cc =2.4v to 5.5v for relative timing, refer to timing diagrams ht24lc04 3 6th may 99
functional description serial clock (scl) the scl input is used for positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda) the sda pin is bidirectional for serial data transfer. the pin is open-drain driven and may be wired-or with any number of other open-drain or open collector devices. a0, a1, a2 the ht24lc04 uses the a2 and a1 inputs for hard wire addressing and a total of four 4k devices may be addressed on a single bus system. the a0 pin is not connected. (the device addressing is discussed in detail under the device addressing section). write protect (wp) the ht24lc04 has a write protect pin that provides hardware data protection. the write protect pin allows normal read/write opera- tions when connected to the v ss . when the write protect pin is connected to vcc, the write protection feature is enabled and operates as shown in the following table. wp pin status protect array ht24lc04 at v cc full array (4k) at v ss normal read/write operations memory organization ht24lc04, 4k serial eeprom internally organized with 512 8-bit words, random word addressing requires a 9-bit data word address. device operations clock and data transition data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in data line while the clock line is high will be interpreted as a start or stop condition. start condition a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to start and stop defi- nition timing diagram). stop condition a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (refer to start and stop definition timing diagram). acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknow- ledge that it has received each word. this happens during the ninth clock cycle. device addressing the 4k eeprom devices require an 8-bit de- vice address word following a start condition to enable the chip for a read or write operation. the device address word consist of a mandatory one, zero sequence for the first four most signifi- cant bits (refer to diagram showing the device address). this is common to all the eeprom device. the next three bits are the a2, a1 and a0 device address bits for the 1k/2k eeprom. these three bits must compare to their corresponding hard-wired input pins. ht24lc04 4 6th may 99
the 4k eeprom only use the a2 and a1 device address bits with the third bit as a memory page address bit. the two device address bits must compare to their corresponding hardwired input pins. the a0 pin is not connected. the 8th bit of device address is the read/write operation select bit. a read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low. if the comparison of the device address succeed the eeprom will output a zero at ack bit. if not, the chip will return to a standby state. write operations byte write a write operation requires an 8-bit data word address following the device address word and acknowledgment. upon receipt of this ad- dress, the eeprom will again respond with a zero and then clock in the first 8-bit data word. after receiving the 8-bit data word, the eeprom will output a zero and the address- ing device, such as a microcontroller, must terminate the write sequence with a stop con- dition. at this time the eeprom enters an internally-timed write cycle to the non-vola- tile memory. all inputs are disabled during this write cycle and eeprom will not re- spond until the write is completed (refer to byte write timing). page write the 4k device is capable of 16-byte page writes. a page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom ac- knowledges the receipt of the first data word, the microcontroller can transmit up to fifteen more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition. the data word address lower four bits are internally incremented following the receipt of each data word. the higher data word ad- dress bits are not incremented, retaining the memory page row location (refer to page write timing). acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w=0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is completed, then the device will return the ack and the master can then pro- ceed with the next read or write command. ht24lc04 5 6th may 99
write protect the ht24lc04 can be used as a serial rom when the wp pin is connected to vcc. pro- gramming will be inhibited and the entire memory will be write-protected. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read opera- tions: current address read, random address read and sequential read. current address read the internal data word address counter main- tains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address roll over during read from the last byte of the last memory page to the first byte of the first page. the address roll over during write from the last byte of the current page to the first byte of the same page. once the de- vice address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but generates a following stop condition (refer to current read timing). random read a random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the eeprom. the microcontroller must then generate another start condition. the micro- controller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom ac- knowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does gener- ates a following stop condition (refer to ran- dom read timing). acknowledge polling flow ht24lc04 6 6th may 99
timing diagrams note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command. sequential read sequential reads are initiated by either a cur- rent address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledgment. as long as the eeprom receives an acknowledgment, it will continue to increment the data word ad- dress and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read continues. the se- quential read operation is terminated when the microcontroller does not respond with a zero but generates a following stop condition (refer to sequential read timing). ht24lc04 7 6th may 99
ht24lc04 8 may 6, 1999 copyright 1999 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holtek semiconductor (shanghai) ltd. 7th floor, building 2, no.889, yi shan road, shanghai, china tel:021-6485-5560 fax:021-6485-0313 holmate technology corp. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885
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