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may 2007 revision: ebdug18_01.3 latticeecp2 standard evaluation board user? guide
2 latticeecp2 standard evaluation board lattice semiconductor user? guide introduction the latticeecp2 standard evaluation board is a complete, integrated design, featuring a latticeecp2 fpga and a variety of both application-speci? and general-purpose peripheral interfaces. this board provides a convenient platform to evaluate, test, and debug user designs, including designs requiring pci/pci-x. this board includes the following features: latticeecp2 fpga device in 484 fpbga package spi serial flash device included for low-cost, non-volatile con?uration storage pci/pci-x edge connector (188-pin) supporting master or target pci 2.2 - 32/64 bit, 33/66 mhz, 3.3v pci-x - 32/64 bit, 66/133 mhz, parity or ecc, 3.3v (mode 1) rs-232 connector 33.33 mhz oscillator rj-45 connector lcd connector compact flash connector prototyping area with access to over 210 i/o pins optional sma/smb connectors (up to eight) for high-speed clock and data interfacing 7-segment display, eight general purpose switches, two momentary switches, eight user leds, and various sta- tus leds required voltages supplied by pci/pci-x or one external 5v dc supply ispvm system programming support figure 1. lattice ecp2 standard evaluation board electrical, mechanical, and environmental speci?ations the nominal board dimensions are 9.75 inches by 4.2 inches. the environmental speci?ations are as follows: operating temperature: 0? to 55? storage temperature: -40? to 75?
3 latticeecp2 standard evaluation board lattice semiconductor user? guide humidity: < 95% without condensation 5vdc input (+/- 10%) up to 4a, or 3.3v input from pci/pci-x backplane additional resources additional resources relating to the latticeecp2 standard evaluation board (including updated documentation, and sample programs) can be found at the following url: www .latticesemi.com/products/de v elopmenthardw are/fpgafspcboards/ecp2starde v aluationboard.cfm features latticeecp2 device this board features a latticeecp2 fpga with a 1.2v dc core in a 484-ball fpbga package. a complete descrip- tion of this device can be found in the latticeecp2 family data sheet available on the lattice web site at www .lat- ticesemi.com/ecp2 . on-board oscillator the 3.3v oscillator socket at y1 accepts both full-size (14-pin) and half-size (8-pin) oscillators, and will route the oscillator output to a latticeecp2 primary clock input or a pll input, depending on the oscillators position in the socket (see figure 2). when a full size oscillator is installed such that pin 1 of the oscillator aligns with pin 1 of the socket, the output of the oscillator drives the primary clock at latticeecp2 pin j21 (this is the default position). when pin 1 of the oscilla- tor is aligned to pin 2 of the socket, the clock is routed to latticeecp2 pin j21. when using a half size oscillator, align pin 1 of the oscillator to pin 1 of the socket to drive the primary clock, or align pin 1 of the oscillator to pin 5 of the socket to drive the pll. note that pin 1 of the oscillator is expected to be a no-connect pin. figure 2. oscillator options spi serial flash spi serial flash are available in three package styles, two of those packages, 8-pin so and 16-pin so, are sup- ported by this board. in general, the 8-pin devices support densities up to 16mb, while the 16-pin devices support larger densities. the device chosen for inclusion on this board depends on the density of the installed latticeecp2, but the spi serial flash will be large enough to allow two bitstreams to be stored simultaneously in order to support spim mode. 3.3 v g n d 3.3 v g n d 3.3 v pll clock ( n 21) primary clock (j21) g n d half-size 33.33 mhz f u ll-size 33.33 mhz f u ll-size 33.33 mhz 3.3 v g n d half-size 33.33 mhz pin-1 pin-1 pin-1 pin-1 pin-16 pin-16 pin-16 pin-16 pll clock ( n 21) primary cloc k (j21) pll clock ( n 21) primary clock (j21) pll clock ( n 21) primary cloc k (j21) defa u lt position
4 latticeecp2 standard evaluation board lattice semiconductor user? guide the 8-pin device footprint is at u4; the 16-pin device footprint is at u5. only one location can be populated at a time. con?uration/programming headers two programming headers are provided on the evaluation board, providing access to the latticeecp2 jtag port and sysconfig port. the jtag connector is a 1x10 header and the sysconfig connector is a 2x17 header. both the jtag and the sysconfig ports are also provided with loop-through connectors to allow for easy daisy chaining of multiple boards. with proper jumper selection (see the next section) standard idc ribbon cable can be used without the need to swap wires on the cable. see the con?uring/programming the board section of this document for more information on this topic. the pinouts for these headers are provided in the following tables. note: a parallel port ispdownload cable is included with each latticeecp2 standard evaluation board. when using a parallel port (1x8) ispdownload cable, connect pin 1 of the cable to pin 1 of the 1x10 jtag header. for more information on the ispdownload cable, see the ispdownload cables data sheet available on the lat- tice web site at www .latticesemi.com . table 1. jtag programming header pinout table 2. jtag loop-through header pinout function j4 (1x10) vcc (3.3v) 1 tdo 1 2 tdi 3 progn 1 4 n/c 5 tms 6 ground 7 tck 1 8 done 9 init chain 1 10 1. see section below on jumpers. function j5 (1x10) n/c 1 tdo chain 1 2 tdi chain 1 3 progn 1 4 n/c 5 tms 6 ground 7 tck 1 8 done 9 init chain 1 10 1. see section below on jumpers.
5 latticeecp2 standard evaluation board lattice semiconductor user? guide table 3. sysconfig header pinout (j40) table 4. sysconfig loop-through header pinout (j41) jtag and sysconfig jumpers there are several jtag and sysconfig cabling options that can be selected using jumpers. function pin function cclk 1 2 ground busy / sispi 3 4 d6 di/d0 1 5 6 vcc bank8 d7 / dout 1 7 8 initn done 9 10 programn d7 11 12 ground d6 13 14 ground d5 15 16 ground d4 17 18 ground d3 19 20 ground d2 21 22 ground d1 23 24 ground d0 25 26 ground csn 1 27 28 writen cs1n 1 29 30 cfg0 vcc bank8 31 32 cfg1 ground 33 34 cfg2 1. see section below on jumpers. function pin function cclk 1 2 ground n/c 3 4 n/c dout / csson 5 6 n/c n/c 7 8 initn done 9 10 programn d7 11 12 ground d6 13 14 ground d5 15 16 ground d4 17 18 ground d3 19 20 ground d2 21 22 ground d1 23 24 ground d0 25 26 ground csn / n/c 1 27 28 writen cs1n / n/c 1 29 30 n/c n/c 31 32 n/c ground 33 34 n/c 1. see section below on jumpers.
6 latticeecp2 standard evaluation board lattice semiconductor user? guide default jumpers settings this table lists the default settings for all of the jumpers on the latticeecp2 standard evaluation board. for a com- plete description of each jumper refer to the next sections. table 5. default jumper settings jtag jumpers table 6. tdo chain jumper table 7. tck pull-down table 8. programn pin to jtag location position location position j1 1 to 2 j29 1 to 2 j3 1 to 2 j30 1 to 2 3 to 4 5 to 6 j7 2 to 3 j31 open j8 1 to 2 j32 open j9 open j33 1 to 2 j10 open j34 2 to 3 j11 open j35 open j13 open j36 open j17 1 to 2 j37 1 to 2 j18 1 to 2 j38 open j19 open j39 1 to 2 j22 open j43 1 to 2 3 to 4 5 to 6 j23 open j44 1 to 2 j24 open location position function default j7 1 to 2 multiple boards, but not the last board in the chain 2 to 3 single board, or the last board in a chain x determines the jtag tdo path. location position function default j8 1 to 2 pull-down, 4.7k to ground x open no pull-down there should be only one tck pull-down on a jtag chain. location position function default j10 1 to 2 connects programn pin to the jtag chain open disconnects programn pin from jtag chain x this jumper is normally not installed.
7 latticeecp2 standard evaluation board lattice semiconductor user? guide table 9. initn pin to jtag sysconfig jumpers table 10. cs1n table 11. csn table 12. di/d[0] table 13. d[7]/dout table 14. cson to cs1n (loop-through) table 15. cson to csn (loop-through) location position function default j11 1 to 2 connects initn pin to the jtag chain open disconnects initn pin from the jtag chain x this jumper is normally not installed. location position function default j31 1 to 2 pulls cs1n high 2 to 3 pulls cs1n low open no pull-up or pull-down on cs1n x location position function default j32 1 to 2 pulls csn high 2 to 3 pulls csn low open no pull-up or pull-down on csn x location position function default j33 1 to 2 routes di to j40-5 to support serial mode x 2 to 3 routes data bit d[0] to j40-5 for spifast support location position function default j34 1 to 2 routes d[7] to j40-7 for spi sysconfig support 2 to 3 routes dout to j40-7 to support serial mode x location position function default j35 1 to 2 cson drives cs1n on the loop-through connector open cs1n on the loop-through connector is open x location position function default j36 1 to 2 cson drives csn on the loop-through connector open csn on the loop-through connector is open x
8 latticeecp2 standard evaluation board lattice semiconductor user? guide table 16. con?uration mode (j43) table 17. spifast table 18. jumper settings for sysconfig parallel table 19. jumper settings for sysconfig serial con?uration mode cfg[2], 1 to 2 cfg[1], 3 to 4 cfg[0], 5 to 6 spi (default) jumper (0) jumper (0) jumper (0) reserved jumper (0) jumper (0) open (1) spim jumper (0) open (1) jumper (0) reserved jumper (0) open (1) open (1) reserved open (1) jumper (0) jumper (0) slave serial open (1) jumper (0) open (1) reserved open (1) open (1) jumper (0) slave parallel open (1) open (1) open (1) location position function default j44 1 to 2 spi fast read, enables read op-code 0x0b x open spi normal read, enables read op-code 0x03 all spi serial flash shipped with this board support fast read. this jumper must be removed when using the sysconfig par- allel port. location position notes j31 open see schematic j32 open see schematic j33 1 to 2 j34 2 to 3 j43 all open j44 open j35, j36 open bypass over?w j35, j36 1 to 2 flow-through over?w location position notes j31 open j32 open j33 1 to 2 j34 2 to 3 j43 open 3 to 4 open if driven by cable open j44 don? care j35, j36 open bypass over?w j35, j36 1 to 2 not allowed
9 latticeecp2 standard evaluation board lattice semiconductor user? guide table 20. jumper settings for spi emulation via j40 power setup for stand-alone board operation, i.e. outside of a pci/pci-x backplane, the evaluation board must be supplied with a single 5v dc power supply. 5v dc power may be applied using an ac adapter, such as the condor electronics s-5v0-4a0-u11-206ip (or similar), plugged into the power jack at j47, or via the banana jacks at j45 (ground) and j46 (5v dc). table 21. ac adaptor speci?ations when the board is inserted into a pci/pci-x backplane, the on-board 3.3v regulator is automatically disabled; all onboard power will be derived from the pci/pci-x 3.3v power rail. additional on-board regulators supply 1.2v, an adjustable voltage, and 5v (for the optional lcd panel). the adjust- able voltage is set by the potentiometer r36, on the right side of the board, and can be set to any value between 1.22v and 2.5v. the header at j30 allows a current measuring device to be inserted between 1.2v and the fpga core. to measure current remove power from the board, remove all of the jumpers at j30, install a meter between the odd pins and the even pins, for example between pins 1 and 2, and apply power to the board. when measurement is complete, remove power from the board and re-install all three jumpers. table 22. 1.2v to v cc core the header at j29 allows a current measuring device to be inserted between 3.3v and the fpgas v ccaux. to measure current, remove power from the board, remove the jumper at j29, install a meter between pins 1 and 2, and apply power to the board. when measurement is complete, remove power from the board and re-install the jumper. location position notes j31 open j32 open j33 2 to 3 j34 1 to 2 j43 1 to 2 open if driven by cable 3 to 4 open if driven by cable 5 to 6 open if driven by cable j44 open j35, j36 open bypass over?w j35, j36 1 to 2 not allowed voltage 5vdc +/- 10% current capacity up to 4a polarity positive center connector i.d. 0.1 (2.5mm) connector o.d. 0.218 (5.5mm) location position function default j30 1 to 2 connects 1.2v to the fpga core x 3 to 4 x 5 to 6 x
10 latticeecp2 standard evaluation board lattice semiconductor user? guide table 23. 3.3v to v ccaux the latticeecp2 is divided into 10 banks of i/os (see table 24), and each of these banks has a separate and inde- pendent v cc. each bank supports voltages from 1.2v to 3.3v. however, because some banks, such as banks 4 and 5, which connect to pci/pci-x, require a ?ed voltage, not all of the banks on this evaluation board are adjust- able. the jumpers listed in table 24 allow the user to select the voltage (v ccio ) applied to the adjustable banks. note that if the latticeecp2 will be con?ured from the spi serial flash, bank 8 must be set to 3.3v (because spi serial flash is 3.3v). also, if the board is plugged into a pci/pci-x connector, bank 6 must be set to 3.3v (because the pci clock is routed to bank 6 on this board). table 24. bank voltage selection the following tables detail the various i/o standards supported by the latticeecp2 sysio structures. more infor- mation can be found in lattice technical note tn1102, latticeecp2 sysio usage guide, available on the lattice web site at www .latticesemi.com . table 25. mixed voltage i/o support for example, if v ccio is 3.3v, then signals from devices powered by 1.2v, 2.5v, or 3.3v can be input and the thresholds will be correct, assuming the user has also selected the desired input level using isplever software. output levels are tied directly to v ccio. location position function default j29 1 to 2 connects 3.3v to vccaux x bank function jumper settings 0 i/o 3.3v only 1 i/o 3.3v only 2 i/o j37 1 - 2 = 3.3v 3 - 4 = adj 5 - 6 = 1.2v 3 i/o 3.3v only 4 i/o 3.3v only 5 i/o 3.3v only 6 i/o j18 1 - 2 = 3.3v 3 - 4 = adj 5 - 6 = 1.2v 7 i/o j17 1 - 2 = 3.3v 3 - 4 = adj 5 - 6 = 1.2v 8 sysconfig j39 1 - 2 = 3.3v 3 - 4 = adj 5 - 6 = 1.2v v ccj ispjtag 3.3v only j17, 18, 37, and 39 must have no more than one jumper installed. v ccio input sysio standards output sysio standards 1.2v 1.5v 1.8v 2.5v 3.3v 1.2v 1.5v 1.8v 2.5v 3.3v 1.2v ye s ye s ye s ye s 1.5v ye s ye s ye s ye s ye s 1.8v ye s ye s ye s ye s ye s 2.5v ye s ye s ye s ye s 3.3v ye s ye s ye s ye s
11 latticeecp2 standard evaluation board lattice semiconductor user? guide table 26. sysio standards supported per bank pci/pci-x the latticeecp2 standard evaluation board is designed to be compatible with pci (pci sig 2.2 speci?ation) and pci-x (mode 1). all necessary signals required for 64-bit pci/pci-x operation are provided, as shown in table 27 and table 28. description top side, banks 0-1 right side, banks 2-3 bottom side, banks 4-5 left side, banks 6-7 types of i/o buffers single-ended single-ended and differential single-ended single-ended and differential output standards supported lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i, ii sstl25 class i, ii sstl33 class i, ii hstl15 class i hstl18_i, ii sstl18d class i, ii sstl25d class i, ii sstl33d class i, ii hstl15d class i hstl18d class i, ii pci33 lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i, ii sstl25 class i, ii sstl33 class i, ii hstl15 class i hstl18 class i, ii sstl18d class i, ii sstl25d class i, ii sstl33d class i, ii hstl15d class i, ii hstl18d class i, ii pci33 lvds lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl2 class i, ii sstl3 class i, ii hstl15 class i hstl18 class i, ii sstl18d class i, ii sstl25d class i, ii, sstl33d class i, ii hstl15d class i hstl18d class i, ii pci33 lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl2 class i, ii sstl3 class i, ii hstl15 class i, iii hstl18 class i, ii, iii sstl18d class i, sstl25d class i, ii, sstl33d_i, ii hstl15d class i hstl18d class i, ii pci33 lvds lvds25e 1 lvpecl 1 blvds 1 rsds 1 inputs all single-ended, differ- ential all single-ended, differential all single-ended, differential all single-ended, differential clock inputs all single-ended, differ- ential all single-ended, differential all single-ended, differential all single-ended, differential pci support pci33 no clamp pci33 no clamp pci33 with clamp pci33 no clamp lvds output buffers lvds (3.5ma) buffers 2 lvds (3.5ma) buffers 2 1. these differential standards are implemented by using complementary lvcmos drivers and external resistors. 2. available on 50% of the i/os in the bank. table 27. pci connections - solder side j48 signal name latticeecp2 pin sysio bank note 1 pci_trstn - - tp10, pd if master 2 +12v - - decoupling cap 3 pci_tms - - tp11, pu if master 4 pci_tdi - - tp12, j14-4, j13 5 +5v - - nc 6 pci_inta_n - - j19 7 pci_intc_n - - j19
12 latticeecp2 standard evaluation board lattice semiconductor user? guide 8 +5v - - nc 9 pcix_ecc5 w4 5 10 +3.3v - - 11 pcix_ecc3 w5 5 14 +3.3vaux - - tp13 15 pci_rst_n y4 5 16 +3.3v - - 17 pci_gnt_n y5 5 18 gnd - - 19 pme# - - tp9 20 pci_ad30 w6 5 21 3.3v - - 22 pci_ad28 y6 5 23 pci_ad26 w7 5 24 gnd - - 25 pci_ad24 y7 5 26 pci_idsel u9 5 27 +3.3v - - 28 pci_ad22 w8 5 29 pci_ad20 y8 5 30 gnd 31 pci_ad18 v9 5 32 pci_ad16 w9 5 33 +3.3v - - 34 pci_frame_n u10 5 35 gnd - - 36 pci_trdy_n v10 5 37 gnd - - 38 pci_stop_n w10 5 39 +3.3v - - 40 pci_smbclk - - tp8, pu if master 41 pci_smbdat - - tp14, pu if master 42 gnd - - 43 pci_par y10 5 44 pci_ad15 w11 5 45 +3.3v - - 46 pci_ad13 u12 4 47 pci_ad11 y12 4 48 gnd - - 49 pci_ad9 w12 4 52 pci_cbe0_n v12 4 53 +3.3v - - 54 pci_ad6 u13 4 55 pci_ad4 y13 4 table 27. pci connections - solder side (continued) j48 signal name latticeecp2 pin sysio bank note
13 latticeecp2 standard evaluation board lattice semiconductor user? guide 56 gnd - - 57 pci_ad2 w13 4 58 pci_ad0 u14 4 59 +3.3v - - 60 pci_req64_n w14 4 61 nc - - 62 nc - - 63 gnd - - 64 pci_cbe7_n v14 4 65 pci_cbe5_n u15 4 66 +3.3v - - 67 par64 t15 4 68 pci_ad62 y15 4 69 gnd - - 70 pci_ad60 w15 4 71 pci_ad58 u16 4 72 gnd - - 73 pci_ad56 v16 4 74 pci_ad54 t16 4 75 +3.3v - - 76 pci_ad52 y16 4 77 pci_ad50 w16 4 78 gnd - - 79 pci_ad48 y17 4 80 pci_ad46 w17 4 81 gnd - - 82 pci_ad44 y18 4 83 pci_ad42 w18 4 84 +3.3v - - 85 pci_ad40 y19 4 86 pci_ad38 y20 4 87 gnd - - 88 pci_ad36 v17 4 89 pci_ad34 v18 4 90 gnd - - 91 pci_ad32 u18 4 92 nc - - 93 gnd - - 94 nc - - note: pd = pull-down resistor, pu = pull-up resistor, nc = no-connect, tp = test point. table 27. pci connections - solder side (continued) j48 signal name latticeecp2 pin sysio bank note
14 latticeecp2 standard evaluation board lattice semiconductor user? guide table 28. pci connections - component side j14 signal name latticeecp2 pin sysio bank notes 1 -12v - - decoupling cap 2 pci_tck - - tp16, pd if master 3 gnd - - 4 pci_tdo - - tp17, j3, j13 5 +5v - - nc 6 +5v - - nc 7 pci_intb_n - - j19 8 pci_intd_n - - j19 9 pci_prsnt1_n j14 - 10 pcix_ecc4 w3 5 11 pci_prsnt2_n - - j23 14 pcix_ecc2 y2 5 15 gnd - - 16 pci_clk r1 6 d20, j22 17 gnd - - 18 pci_req_n y3 5 19 +3.3v - - 20 pci_ad31 ab2 5 21 pci_ad29 aa3 5 22 gnd - - 23 pci_ad27 ab3 5 24 pci_ad25 ab4 5 25 3.3v - - 26 pci_cbe3_n aa5 5 27 pci_ad23 ab5 5 28 gnd - - 29 pci_ad21 aa6 5 30 pci_ad19 ab6 5 31 3.3v - - 32 pci_ad17 ab7 5 33 pci_cbe2_n aa7 5 34 gnd - - 35 pci_irdy_n ab8 5 36 +3.3v - - 37 pci_devsel_n u11 5 38 pcixcap - - 39 lock# - - tp15 40 pci_perr_n aa8 5 41 +3.3v - - 42 pci_serr_n aa9 5 43 +3.3v - - 44 pci_cbe1_n ab9 5 45 pci_ad14 aa10 5 46 gnd - -
15 latticeecp2 standard evaluation board lattice semiconductor user? guide 47 pci_ad12 ab10 5 48 pci_ad10 aa11 5 49 pci_m66en - - j38 52 pci_ad8 ab11 5 53 pci_ad7 y11 5 54 +3.3v - - 55 pci_ad5 ab12 5 56 pci_ad3 aa12 5 57 pci_gnd_57 - - u6 58 pci_ad1 ab13 5 59 +3.3v - - 60 pci_ack64_n aa13 4 61 +5v - - nc 62 +5v - - nc 63 nc - - 64 gnd - - 65 pci_cbe6_n ab14 5 66 pci_cbe4_n aa14 4 67 gnd - - 68 pci_ad63 ab15 4 69 pci_ad61 aa15 4 70 +3.3v - - 71 pci_ad59 ab16 4 72 pci_ad57 aa16 4 73 gnd - - 74 pci_ad55 ab17 4 75 pci_ad53 aa17 4 76 gnd - - 77 pci_ad51 ab18 4 78 pci_ad49 aa18 4 79 +3.3v - - 80 pci_ad47 ab19 4 81 pci_ad45 ab20 4 82 gnd - - 83 pci_ad43 aa20 4 84 pci_ad41 ab21 4 85 gnd - - 86 pci_ad39 aa22 4 87 pci_ad37 aa21 4 88 +3.3v - - 89 pci_ad35 y22 4 90 pci_ad33 y21 4 91 gnd - - 92 nc - - table 28. pci connections - component side (continued) j14 signal name latticeecp2 pin sysio bank notes
16 latticeecp2 standard evaluation board lattice semiconductor user? guide pci/pci-x jumpers table 29. prsnt1 table 30. prsnt2 table 31. pcixcap and m66en encoding table 32. pci tdi and tdo table 33. pci interrupt 93 nc - - 94 gnd - - note: pd = pull-down resistor, pu = pull-up resistor, nc = no-connect, tp = test point. location position function default j9 1 to 2 master pci/pci-x 2 to 3 target pci/pci-x open target pci/pci-x x not installed. if installing header, ?st cut trace between 2 and 3. if master, also install r51 and c39. location position function default j23 1 to 2 master pci/pci-x open target pci/pci-x x not installed. if master, also install r62 and c47. pcixcap(j24) m66en(j38) frequency default pci pci-x 1 to 2 2 to 3 33mhz 66mhz 1 to 2 open 66mhz 66mhz open 2 to 3 33mhz 133mhz open open 66mhz 133mhz x don? care 1 to 2 master master if master, also install r126 and c111. location position function default j13 1 to 2 target pci/pci-x x open master pci/pci-x not installed. if master then cut the trace between 1 and 2. location position function default j19 2 to 4 int = inta x 1 to 3 int = intb 4 to 6 int = intc 3 to 5 int = intd not installed. if installing header, ?st cut trace between 2 and 4. table 28. pci connections - component side (continued) j14 signal name latticeecp2 pin sysio bank notes
17 latticeecp2 standard evaluation board lattice semiconductor user? guide table 34. pci clk if the board is to be a master, in addition to properly setting the jumpers, the following resistors and capacitors must be installed. table 35. install these resistors and caps if pci/pci-x is a master signal testing this board supports testing of single-ended and differential signals. high-speed single-ended there are eight fpga signals that have been routed to special test points on the board. each signal can include a series resistor, as well as a pull-up resistor and a pull-down resistor (for maximum ?xibility these resistors are not included with the board). each series resistor footprint has a shorting trace that must be cut before installing a resistor (see figure 3). next to each signals test point a ground point has been added in order to make signal integrity measurements easier and more accurate. figure 3. resistor shorting trace table 36. single ended si test points location position function default j22 1 to 2 routes pci_clk to fpga, only used if installing this board in a pci or pci-x backplane. for signal integrity, also remove r27 and r30. d20 provides pci clamping for this signal. open disconnects this signal from the fpga x the differential signals at j20 and j21 can not be used if this jumper is installed (1 to 2). location value manufacturer part number 1 r1, 51, 59, 60, 61, 62, 106, 107, 126 5.6k panasonic erj-3geyj562v c39, 111 0.01uf panasonic ecu-v1h103kbv 1. or equivalent. test point pin resistors series 1 pull-up pull-down tp_si7 j4 r8 r71 r2 tp_si6 j5 r9 r72 r3 tp_si5 l6 r10 r73 r4 tp_si4 l5 r11 r74 r5 tp_si3 k2 r12 r75 r6 tp_si2 k1 r13 r76 r7 tp_si1 l2 r22 r82 r20 tp_si0 l1 r23 r83 r21 1. cut shorting trace before installation. c u t this trace
18 latticeecp2 standard evaluation board lattice semiconductor user? guide high-speed differential the board supports testing of up to eight differential pairs using two types of connectors, sma and rj45. each pair has provision for a ?ine-to-line resistor as well as single-ended series resistors (for maximum ?xibility these resis- tors are not included with the board). the resistors can be used as termination or in combination to provide signal emulation (level shifting). for more information on signal emulation and signal types, please refer to lattice techni- cal note number tn1102, latticeecp2 sysio usage guide, available on the lattice web site at www .lattices- emi.com . table 37. differential si connectors test points for gpio (general purpose i/o) testing or monitoring, numerous test points are provided. the test points are labeled according to the associated i/o pin location, for example tp_a21. these test points have been arranged in grids that have grounds and v ccio s placed nearby to allow for easy prototyping. please refer the schematics at the end of this document for more information. note that the test points for j21 and n21 have locations for zero ohm resistors (r115 and r117) to allow isolation of the test points from the oscillator clock. by default these resistors are not installed on the board. switches switch 1 (sw1) on the top edge of the board is an eight-switch block that is part of the prototyping area. a switch in the down position produces a low (logic 0), while the up position produces a high (logic 1). all sw1 signals go to bank 1. connector latticeecp2 resistors location type pin type 1 series 2 line-to-line j27 sma p1 gdllt in r24 r26 j28 p2 gdllc in r25 j26 sma m5 pclkt in r84 r86 j25 m6 pclkc in r85 j21 sma r1 gpllt in r28 r30 3 j20 r2 gpllc in r29 j15 sma r3 gpllt fb r89 r91 j16 t4 gpllc fb r90 u6-1 rj45 e2 gpio r14 r18 u6-2 e1 gpio r15 u6-3 rj45 j2 gpio r16 r19 u6-4 j1 gpio r17 u6-5 rj45 k3 gpio r77 r80 u6-6 k4 gpio r78 u6-7 rj45 l4 gpio r79 r81 u6-8 l3 gpio r87 1. all support true lvds. 2. the shorting trace must be cut before installing the resistor. 3. r27 must be installed and j22 must be open if using j21.
19 latticeecp2 standard evaluation board lattice semiconductor user? guide table 38. sw1 connections sw2 is a momentary switch that, when pressed, forces the fpga to start a con?uration cycle. sw3 is a momentary switch that the user can de?e for any purpose, such as a global reset. sw3 is wired to i/o e18 (bank 1) and applies a low logic level (0) when pressed. leds eight user-de?able leds are provided on the top of the board under sw1. these leds are each wired to a sepa- rate gpio on bank 1 as de?ed in the table 39. the current limiting resistors associated with these leds are wired to 3.3v, but it is safe to drive these signals with any fpga i/o voltage. the led will light when its associated i/o pin is driven low. table 39. led connections there are also three leds associated with the dedicated programming pins. table 40. programming leds note: during jtag programming, the state of the done led has no meaning. this is because the done pin, which drives the led, is being controlled by the pins bscan cell. see lattice technical note number tn1108, latticeecp2 sysconfig usage guide, for more information on the dedicated programming pins. seven-segment display this board contains a seven-segment display, with decimal point, at u2. the segments are wired to gpio as de?ed in table 41. a low on the pin will turn on the associated segment. switch pin sw1-1 c12 sw1-2 b12 sw1-3 a11 sw1-4 a12 sw1-5 d12 sw1-6 e12 sw1-7 d13 sw1-8 e13 led pin d1 b14 d2 a14 d3 d14 d4 c13 d5 e14 d6 f14 d7 a13 d8 b13 led pin color function d12 programn yellow on when signal is low d11 initn red on when initializing d10 done green on when con?uration is complete
20 latticeecp2 standard evaluation board lattice semiconductor user? guide table 41. seven-segment display connections figure 4. seven-segment display lcd connector the lcd connector has 18 pins, but only 16 are required for simple lcd panels. if using an optrex 51505 or equivalent, use pins 1-16, if using a lumex lcm-s02002dsr or equivalent, use pins 3-18. two potentiometers are provided for lcd control. r34 adjusts the backlight and r35 adjusts the contrast. power for the lcd panel is provided by the 3.3v to 5v converter at u7. segment pin a a15 b a17 c c15 d e15 e f15 f b15 g a16 dp d15 a g d e c b f dp
21 latticeecp2 standard evaluation board lattice semiconductor user? guide table 42. lcd connector compact flash the connector at j12 supports type 1 and type 2 compact flash cards. this connector supports pc card memory mode, pc card i/o mode, and true ide mode. ultra dma is not supported. j42 signal fpga pin 1 anode (r34) 2 cathode (gnd) 3 vss (gnd) 4 vdd (5v) 5 vo (r35) 6 rs d16 7 r/w a20 8 e e16 9 db0 a18 10 db1 c17 11 db2 b18 12 db3 c16 13 db4 g16 14 db5 b17 15 db6 g15 16 db7 b16 17 anode (r34) 18 cathode (gnd) table 43. compact flash connector signal j12 fpga pin j12 signal gnd 1 b11 26 cd1 d03 2 b10 a9 27 d11 d04 3 a10 c10 28 d12 d05 4 c11 f11 29 d13 d06 5 e11 a7 30 d14 d07 6 a8 b9 31 d15 ce1 7 b8 a6 32 ce2 a10 8 b7 d8 33 vs1 oe 9 c8 e10 34 iord a09 10 d10 c6 35 iowr a08 11 c7 b5 36 we a07 12 b6 d9 37 ready 3.3v 13 - 38 3.3v a06 14 f10 e9 39 csel a05 15 f9 a4 40 vs2 a04 16 a5 a2 41 reset a03 17 a3 e8 42 wait a02 18 g8 b3 43 inpack a01 19 c3 d7 44 reg
22 latticeecp2 standard evaluation board lattice semiconductor user? guide rs-232 the db9 connector at j2 provides a standard dce rs-232 connection to the fpga. there are two jumpers, j1 and j3, which allow use of a straight-wired cable or a null modem cable. table 44. rs-232 connector to fpga pins table 45. rs-232 connector to fpga pins con?uring/programming the board requirements pc with lattice semiconductors ispvm system version 16.0 (or later) programming software, installed with appropriate drivers (usb driver for usb cable, windows nt/2000/xp parallel port driver for ispdownload cable). note: an option to install these drivers is included as part of the ispvm system setup. the ispvm system software can be download from the lattice web site at: latticesemi.com/ispvm . any ispdownload or lattice usb cable (pds4102-dl2x, hw7265-dl3x, hw-usb-2x, etc.). for a complete discussion of the latticeecp2s con?uration and programming options, refer to lattice technical note number tn1108, latticeecp2 sysconfig usage guide. sram con?uration the latticeecp2 sram can be con?ured easily via the jtag port. the latticeecp2 device is sram-based, so it must remain powered to retain its con?uration when programming just the sram. to program the sram, perform the following procedure: 1. check that j7 and j8 are properly set (see table 6 and table 7), and that j10 and j11 are open. 2. connect the ispdownload cable to the jtag header at j4. when using a 1x8 connector on the download cable, connect to the 1x10 header by justifying the alignment to pin 1 (pin 1 on the cable to pin 1 on the header, pin 1 is vcc). a00 20 f8 f7 45 bvd2 d00 21 e7 d6 46 bvd1 d01 22 d5 h7 47 d08 d02 23 d4 b1 48 d09 wp 24 b2 c4 49 d10 cd2 25 j7 50 gnd j1 j3 function default 1 to 2 1 to 2 use with a straight-wired cable. x 2 to 3 2 to 3 use with a null modem cable (wires 2 and 3 swapped). fpga pin rs-232 signal c1 cts d1 rts c2 transmit data (to the cable) 1 d3 receive data (from the cable) 1 1. wired to td or rd depending on j1 and j3 table 43. compact flash connector (continued) signal j12 fpga pin j12 signal
23 latticeecp2 standard evaluation board lattice semiconductor user? guide important note: the board must be un-powered when connecting, disconnecting, or reconnecting the isp- download cable. always connect the ispdownload cable's gnd pin (black wire), before connecting any other jtag pins. failure to follow these procedures can in result in damage to the latticeecp2 fpga device and render the board inoperable. 3. connect the latticeecp2 evaluation board to an external 5v supply. 4. start the ispvm system software. 5. press the scan button located on the toolbar. the latticeecp2 device should be automatically detected. the resulting screen should be similar to figure 5. figure 5. ispvm system interface 6. double-click the device to open the device information dialog, as shown in figure 6. in the device information dialog, click the browse button located under data file . locate the desired bitstream ?e (.bit). click ok to both dialog boxes.
24 latticeecp2 standard evaluation board lattice semiconductor user? guide figure 6. device information dialog 7. click the green go button on the toolbar; this will begin the download process into the latticeecp2. 8. upon successful download, the latticeecp2 will be operational. spi flash download for non-volatile storage of con?uration data, the latticeecp2 device features an interface compatible with low- cost spi serial flash. ispvm system has the ability to program the spi serial flash through jtag. after the spi serial flash is programmed the latticeecp2 can con?ure automatically from the con?uration data stored in the flash. the following steps describe the procedure for programming the spi serial flash: 1. install all three jumpers at j43, and the jumper at j44. this enables spi mode by setting the cfg pins of the latticeecp2, and it enables fast spi reads. check that j7 and j8 are properly set (see table 6 and table 7), and that j10 and j11 are open. 2. connect the download cable to j4. when using a 1x8 connector on the download cable, connect to the 1x10 header by justifying the alignment to pin 1 (pin 1 on the cable to pin 1 on the header, pin 1 is vcc). important note: the board must be un-powered when connecting, disconnecting, or reconnecting the isp- download cable. always connect the ispdownload cable's gnd pin (black wire), before connecting any other jtag pins. failure to follow these procedures can in result in damage to the latticeecp2 fpga device and render the board inoperable. 3. connect the evaluation board to an external 5v supply 4. start the ispvm system software.
25 latticeecp2 standard evaluation board lattice semiconductor user? guide 5. press the scan button located on the toolbar. the latticeecp2 device should be automatically detected. the resulting screen should be similar to figure 5. 6. double-click the device to open the device information dialog as shown in figure 6. in the device options drop- down box, select spi flash programming ; you should see a window similar to figure 7. select the flash device that is on your board and then browse to the desired bitstream ?e (.bit). click ok in both dialog boxes. 7. click on the green go button on the ispvm toolbar to program the spi serial flash. 8. press and release sw2 (program) on the board to transfer the con?uration data from the spi serial flash to the latticeecp2. the latticeecp2 should now be running the new code. figure 7. spi serial flash dialog box ordering information technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com description ordering part number china rohs environment- friendly use period (efup) latticeecp2 evaluation board - standard lfe2-50e-l-ev isplever base with latticeecp2 50e standard development kit LS-E2-L-BASE-PC-N 10
26 latticeecp2 standard evaluation board lattice semiconductor user? guide revision history ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal . all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. date version change summary may 2006 01.0 initial release. march 2007 01.1 added ordering information section. april 2007 01.2 added important information for proper connection of ispdownload (programming) cables. may 2007 01.3 replaced two instances of ?3-j21 with ?atticeecp2 pin j21 on page 3.
27 latticeecp2 standard evaluation board lattice semiconductor user? guide appendix a. schematics figure 8. block diagram 5 5 4 4 3 3 2 2 1 1 d d c c b b a a title size document number rev date: sheet of b ecp2 standard -- block diagram a 18 title size document number rev date: sheet of b ecp2 standard -- block diagram a 18 title size document number rev date: sheet of b ecp2 standard -- block diagram a 18 bank 0 bank 3 fpga bank 6 bank 5 bank 7 bank 1 bank 2 bank 4 lattice semiconductor corporation area prototyping differential si testing 64 bit pci, pci-x single ended si testing power supply (page 6) (page 6) (page 3) (page 2) (page 5) (page 4) jtag for fpga sysconfig lcd and compact flash connectors spi flash rs-232 (page 9) bank 8 jtag leds seven seg prototyping area
28 latticeecp2 standard evaluation board lattice semiconductor user? guide figure 9. lcd, cf, rs-232, leds 5 5 4 4 3 3 2 2 1 1 d d c c b b a a anode lcd_rs lcd5 lcd_e lcd6 lcd_db1 lcd7 lcd_db3 lcd8 lcd_db5 lcd9 lcd_db7 lcd10 lcd_rw lcd0 lcd_db0 lcd1 lcd_db2 lcd2 lcd_db4 lcd3 lcd_db6 lcd4 cf_d03 cf0 cf_d04 cf1 cf_d05 cf2 cf_d06 cf3 cf_d07 cf4 cf_d00 cf18 cf_d01 cf19 cf_d02 cf20 cf_d09 cf44 cf_d08 cf43 cf_d10 cf45 cf_d15 cf28 cf_d14 cf27 cf_d13 cf26 cf_d12 cf25 cf_d11 cf24 cf_a10 cf6 cf_a09 cf8 cf_a08 cf9 cf_a07 cf10 cf_a06 cf11 cf_a05 cf12 cf_a04 cf13 cf_a03 cf14 cf_a02 cf15 cf_a01 cf16 cf_a00 cf17 cf_ce1 cf5 cf_oe cf7 cf_wp cf21 cf_cd2 cf22 cf_bvd1 cf42 cf_bvd2 cf41 cf_reg cf40 cf_inpack cf39 cf_wait cf38 cf_reset cf37 cf_vs2 cf36 cf_csel cf35 cf_ready cf34 cf_we cf33 cf_iowr cf32 cf_iord cf31 cf_vs1 cf30 cf_ce2 cf29 cf_cd1 cf23 cf_cd2 cf22 cf_cd1 cf23 cf38 cf_wait cf34 cf_ready cf21 cf_wp cf_inpack cf39 cf36 cf_vs2 cf30 cf_vs1 cf41 cf_bvd2 cf42 cf_bvd1 vcc_3.3v lcd[10..0] cf0 cf_d03 cf23 cf_cd1 cf1 cf_d04 cf24 cf_d11 cf25 cf_d12 cf3 cf_d06 cf26 cf_d13 cf2 cf_d05 cf27 cf_d14 cf5 cf_ce1 cf28 cf_d15 cf4 cf_d07 cf29 cf_ce2 cf7 cf_oe cf30 cf_vs1 cf6 cf_a10 cf31 cf_iord cf9 cf_a08 cf32 cf_iowr cf8 cf_a09 cf33 cf_we cf11 cf_a06 cf34 cf_ready cf10 cf_a07 cf35 cf_csel cf13 cf_a04 cf36 cf_vs2 cf12 cf_a05 cf37 cf_reset cf15 cf_a02 cf38 cf_wait cf14 cf_a03 cf39 cf_inpack cf17 cf_a00 cf40 cf_reg cf16 cf_a01 cf41 cf_bvd2 cf19 cf_d01 cf42 cf_bvd1 cf18 cf_d00 cf45 cf_d10 cf21 cf_wp cf44 cf_d09 cf20 cf_d02 cf22 cf_cd2 cf43 cf_d08 vcc_3.3v rs232_indat lcd0 lcd_rw lcd1 lcd_db0 lcd2 lcd_db2 lcd3 lcd_db4 lcd4 lcd_db6 lcd5 lcd_rs lcd6 lcd_e lcd7 lcd_db1 vcc_3.3v sw7 sw6 sw5 sw4 sw3 sw2 sw1 sw0 sw6 sw5 sw4 sw3 sw2 sw1 sw0 sw[7:0] sw7 vcc_3.3v led1 led0 led7 led6 led5 led4 led3 led2 led[7:0] led7 led6 led5 led4 led3 led2 led1 led0 vcc_3.3v sseg_a sseg_f sseg_e sseg_d sseg_dp sseg_c sseg_g sseg_b cf[45..0] lcd10 lcd_db7 lcd9 lcd_db5 lcd8 lcd_db3 vcc_3.3v rs232_outdat rs232_cts rs232_rts vcc_3.3v vcc_5v title size document number rev date: sheet of b ecp2 standard -- lcd, cf, rs-232, leds c 28 title size document number rev date: sheet of b ecp2 standard -- lcd, cf, rs-232, leds c 28 title size document number rev date: sheet of b ecp2 standard -- lcd, cf, rs-232, leds c 28 optrex 51505 or equiv. use pins 1-16 lumex or equiv. use pins 4-18 [8] contrast backlight [8] lcd connector lattice semiconductor corporation compact flash connector traces from the ecp2 to the cf connector must be less than 6 inches ultra dma is not supported dce rs-232 1 to 2 for straight wired cable (default) 2 to 3 for null cable (wires 2 and 3 swapped) sgnd ri dtr cts td rts rd dsr dcd norcomp 190-009-262-001 or equiv. a(pin 1) d(pin 8) f(pin 2) b(pin 12) e(pin 7) c(pin 10) g(pin 11) dp(pin 9) user defined a1 a2 b2 b1 r109 470 r109 470 r110 470 r110 470 c41 0.1uf c41 0.1uf r95 470 r95 470 sw3 sw pushbutton sw3 sw pushbutton a1 b1 a2 b2 tp_c18 tp_c18 r63 10k r63 10k bank0 bank1 (1 of 6) pad name = pt{12/22/35/50} u3a ecp2-12/22/35/50-fpbga484 bank0 bank1 (1 of 6) pad name = pt{12/22/35/50} u3a ecp2-12/22/35/50-fpbga484 pt2/2/2/2a/vref1_0 c1 pt2/2/2/2b/vref2_0 d1 pt3/3/3/3a c2 pt3/3/3/3b d3 pt4/4/4/4a h7 pt4/4/4/4b j7 pt5/5/5/5a b1 pt5/5/5/5b b2 pt6/6/6/6a c4 pt6/6/6/6b d4 pt7/7/7/7a d6 pt7/7/7/7b d5 pt8/8/8/8a f7 pt8/8/8/8b e7 pt9/9/9/9a d7 pt9/9/9/9b f8 pt10/10/10/10a b3 pt10/10/10/10b c3 pt11/20/20/29a e8 pt11/20/20/29b g8 pt12/21/21/30a a2 pt12/21/21/30b a3 pt13/22/22/31a a4 pt13/22/22/31b a5 pt14/23/23/32a e9 pt14/23/23/32b f9 pt15/24/24/33a d9 pt15/24/24/33b f10 pt16/25/25/34a b5 pt16/25/25/34b b6 pt17/26/26/35a c6 pt17/26/26/35b c7 pt18/27/27/36a e10 pt18/27/27/36b d10 pt20/29/29/38a d8 pt20/29/29/38b c8 pt21/30/30/39a a6 pt21/30/30/39b b7 pt23/32/32/41a b9 pt23/32/32/41b b8 pt24/33/33/42a a7 pt24/33/33/42b a8 pt25/34/34/43a f11 pt25/34/34/43b e11 pt26/35/35/44a c10 pt26/35/35/44b c11 pt27/36/36/45a a9 pt27/36/36/45b a10 vcco1 g11 vcco1 g12 vcco1 g13 vcco1 g14 vcco0 g9 vcco0 g10 vcco0 h8 vcco0 h9 pclkt1_0/pt30/39/39/48a c12 pclkc1_0/pt30/39/39/48b b12 pt31/40/40/49a a11 pt31/40/40/49b a12 pt33/42/42/51a d12 pt33/42/42/51b e12 pt34/43/43/52a d13 pt34/43/43/52b e13 pt35/44/44/53a b13 pt35/44/44/53b a13 pt36/45/45/54a f14 pt36/45/45/54b e14 pt37/46/46/55a c13 pt37/46/46/55b d14 pt39/48/48/57a a14 pt39/48/48/57b b14 pt40/49/49/58a a15 pt40/49/49/58b b15 pt42/51/51/60a f15 pt42/51/51/60b e15 pt43/52/52/61a d15 pt43/52/52/61b c15 pt44/53/53/62a a16 pt44/53/53/62b a17 pt45/54/54/63a b16 pt45/54/54/63b b17 pt46/55/55/64a c16 pt46/55/55/64b c17 pt47/56/65/74a e16 pt47/56/65/74b d16 pt48/57/66/75a g15 pt48/57/66/75b g16 pt49/58/67/76a b18 pt49/58/67/76b a18 pt50/59/68/77a a20 pt50/59/68/77b a21 pt51/60/69/78a c18 pt51/60/69/78b d17 pt52/61/70/79a a19 pt52/61/70/79b b20 pt53/62/71/80a e18 pt53/62/71/80b d18 pt54/63/72/81a c19 pt54/63/72/81b c20 vref1_1/pt55/64/73/82a b22 vref2_1/pt55/64/73/82b b21 pt28/37/37/46a/pclkt0_0 b11 pt28/37/37/46b/pclkc0_0 b10 d9 led_yellow d9 led_yellow r98 10k r98 10k rs-232 u1 max3232 rs-232 u1 max3232 c1+ 1 c1- 3 c2+ 4 c2- 5 v+ 2 v- 6 t1in 11 t2in 10 r1out 12 r2out 9 t1out 14 t2out 7 r1in 13 r2in 8 vcc 16 gnd 15 u2 seven segment led 738milx386mil u2 seven segment led 738milx386mil cathode a 1 cathode f 2 annode1 3 nc1 4 nc2 5 nc3 6 cathode e 7 cathode d 8 cathode dp 9 cathode c 10 cathode g 11 nc4 12 cathode b 13 annode2 14 + c43 10uf sizeb + c43 10uf sizeb r50 100k r50 100k r64 10k r64 10k r35 20k r35 20k 1 3 2 r57 100k r57 100k r55 100k r55 100k gnd17 header 1 gnd17 header 1 1 c38 0.1uf cc0603 c38 0.1uf cc0603 + c49 10uf sizeb + c49 10uf sizeb tp_b21 tp_b21 r67 10k r67 10k r49 100k r49 100k tp_d17 tp_d17 r54 47k r54 47k gnd18 header 1 gnd18 header 1 1 r69 10k r69 10k c48 0.1uf cc0402 c48 0.1uf cc0402 tp_b22 tp_b22 r48 47k r48 47k j3 j3 1 2 3 sw1 sw dip-8 861milx425mil sw1 sw dip-8 861milx425mil 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r92 10k r92 10k j2 db9 j2 db9 5 9 4 8 3 7 2 6 1 r58 100k r58 100k tp_a21 tp_a21 r53 47k r53 47k c34 0.1uf cc0603 c34 0.1uf cc0603 r94 10k r94 10k c40 0.1uf c40 0.1uf r96 10k r96 10k tp_a19 tp_a19 tp_c20 tp_c20 r113 470 r113 470 j1 j1 1 2 3 c116 0.1uf c116 0.1uf jb2 jblock jb2 jblock r114 10k r114 10k d2 d2 j42 lcd_connector j42 lcd_connector anode 1 cathode 2 vss 3 rs 6 vo 5 vdd 4 r/w 7 e 8 db0 9 db1 10 db2 11 db3 12 db4 13 db5 14 db6 15 db7 16 anode 17 cathode 18 tp_c19 tp_c19 r112 470 r112 470 r66 470 r66 470 r104 470 r104 470 tp_b20 tp_b20 d7 d7 r47 100k r47 100k d3 d3 d8 led_green d8 led_green r68 470 r68 470 r99 470 r99 470 r103 470 r103 470 r97 470 r97 470 d1 d1 d4 d4 r102 470 r102 470 r111 470 r111 470 tp_d18 tp_d18 r65 470 r65 470 c36 0.1uf cc0603 c36 0.1uf cc0603 gnd16 header 1 gnd16 header 1 1 c102 1uf cc0603 c102 1uf cc0603 r70 470 r70 470 r56 47k r56 47k c53 0.1uf cc0402 c53 0.1uf cc0402 d5 d5 c93 0.1uf cc0603 c93 0.1uf cc0603 c83 0.1uf cc0402 c83 0.1uf cc0402 r34 100 r34 100 1 3 2 jb1 jblock jb1 jblock r93 470 r93 470 pc card memory mode/ pc card i/o mode/ true ide mode j12 compact_flash_connector pc card memory mode/ pc card i/o mode/ true ide mode j12 compact_flash_connector d03 2 d04 3 d05 4 d06 5 d07 6 oe/oe/atasel 9 d00 21 d01 22 d02 23 ce2/ce2/cs1 32 ready/ireq/intrq 37 gnd 50 bvd1/stschg/pdiag 46 bvd2/spkr/dasp 45 d08 47 d09 48 d10 49 d11 27 d12 28 d13 29 d14 30 d15 31 a00 20 a01 19 a02 18 a03 17 a04 16 a05 15 a06 14 a07 12 a08 11 a09 10 gnd 1 ce1/ce1/cs0 7 a10 8 vcc 13 wp/iois16/iocs16 24 cd1 26 cd2 25 vs1 33 vs2 40 iord 34 iowr 35 we 36 vcc 38 csel 39 reset 41 wait/wait/iordy 42 inpack/inpack/dmarq 43 reg/reg/dmack 44 c33 0.1uf cc0603 c33 0.1uf cc0603 d6 d6 c37 0.1uf cc0603 c37 0.1uf cc0603 r108 470 r108 470 c103 0.1uf cc0402 c103 0.1uf cc0402
29 latticeecp2 standard evaluation board lattice semiconductor user? guide figure 10. prototyping area 5 5 4 4 3 3 2 2 1 1 d d c c b b a a vccio2 vcc_1.2v vcc_adj vcc_3.3v vcc_3.3v osc_pclk osc_pllclk vcc_1.2v vcc_3.3v vcc_adj vcc_3.3v vcc_1.2v vcc_1.2v title size document number rev date: sheet of b ecp2 standard -- prototyping area c 38 title size document number rev date: sheet of b ecp2 standard -- prototyping area c 38 title size document number rev date: sheet of b ecp2 standard -- prototyping area c 38 lattice semiconductor corporation [8] [8] [8] [8] (33.33 mhz osc installed) oscillator socket 33.33 mhz oscillator default is a 14 pin oscillator aligned pin 1 to pin 1 11 2 5 to pclk to pll 14 pin osc. 4 pin osc. oscillator position relative to the socket (default) c d e f g h j k l m n p r 22 21 20 19 18 17 16 gnd vccio3 vccio2 prototype area map = unconnected, plated holes (vccio3) (vccio2) b a tp_gnd1 tp_gnd1 tp_d19 tp_d19 c98 0.01uf cc0603 c98 0.01uf cc0603 c115 0.1uf cc0402 c115 0.1uf cc0402 tp_l20 tp_l20 tp_vcc5 tp_vcc5 tp_k19 tp_k19 tp_h19 tp_h19 tp_g17 tp_g17 tp_j21 tp_j21 tp_m19 tp_m19 tp_g20 tp_g20 c66 0.1uf cc0402 c66 0.1uf cc0402 + c110 10uf sizeb + c110 10uf sizeb tp_vcc7 tp_vcc7 tp_k18 tp_k18 tp_k21 tp_k21 tp_f16 tp_f16 tp_c21 tp_c21 r119 10 r119 10 tp_h16 tp_h16 tp_gnd4 tp_gnd4 tp_vcc6 tp_vcc6 tp_j19 tp_j19 tp_c22 tp_c22 tp_vcc1 tp_vcc1 y4 osc14a y4 osc14a nc 1 gnd 7 vcc 14 clk 8 tp_l22 tp_l22 tp_p18 tp_p18 tp_f20 tp_f20 tp_l19 tp_l19 tp_r22 tp_r22 tp_l18 tp_l18 tp_d22 tp_d22 c105 0.1uf cc0603 c105 0.1uf cc0603 tp_vcc3 tp_vcc3 tp_e19 tp_e19 tp_l17 tp_l17 tp_j17 tp_j17 tp_e21 tp_e21 tp_d20 tp_d20 bank3 (2 of 6) bank2 dqs group dqs group pad name = pr{12/22/35/50} prnnxh = true lvds u3b ecp2-12/22/35/50-fpbga484 bank3 (2 of 6) bank2 dqs group dqs group pad name = pr{12/22/35/50} prnnxh = true lvds u3b ecp2-12/22/35/50-fpbga484 pclkt3_0/pr15/21/27/46ah j21 pclkc3_0/pr15/21/27/46bh k21 prnc/24/30/49a k22 prnc/24/30/49b l22 prnc/26/40/59a m19 prnc/26/40/59b n19 gdllt_in/pr17/27/41/60ah m21 gdllc_in/pr17/27/41/60bh m22 gdllt_fb/pr18/28/42/61a n20 gdllc_fb/pr18/28/42/61b n22 gpllt_in/pr20/30/44/63ah n21 gpllc_in/pr20/30/44/63bh p21 gpllt_fb/pr21/31/45/64a p22 gpllc_fb/pr21/31/45/64b r20 vref1_3/pr16/22/28/47a l21 vref2_3/pr16/22/28/47b m20 prnc/23/29/48ah h22 prnc/23/29/48bh j22 pr22/32/46/65ah p19 pr22/32/46/65bh p18 pr23/33/47/66a r21 pr23/33/47/66b r22 pr2/2/2/2ah/vref1_2 e19 pr2/2/2/2bh/vref2_2 d19 prnc/4/10/12ah c22 prnc/4/10/12bh c21 pr3/5/11/13a f16 pr3/5/11/13b f18 pr4/6/12/14ah d20 pr4/6/12/14bh e20 pr5/7/13/15a f19 pr5/7/13/15b g17 prnc/8/14/16ah/rdqs g19 prnc/8/14/16bh h19 prnc/9/15/17a f20 prnc/9/15/17b g20 prnc/10/16/18ah e21 prnc/10/16/18bh d22 prnc/11/17/19a e22 prnc/11/17/19b f21 prnc/nc/nc/25a/spllt_in h18 prnc/nc/nc/25b/spllc_in h20 prnc/nc/nc/26a/spllt_fb h16 prnc/nc/nc/26b/spllc_fb h17 pr6/12/18/37ah g21 pr6/12/18/37bh h21 pr7/13/19/38a j19 pr7/13/19/38b k20 pr8/14/20/39ah j18 pr8/14/20/39bh j17 pr9/15/21/40a f22 pr9/15/21/40b g22 pr10/16/22/41ah/rdqs k19 pr10/16/22/41bh k18 pr11/17/23/42a k17 pr11/17/23/42b l18 pr12/18/24/43ah l20 pr12/18/24/43bh l19 pr13/19/25/44a/pclkt2_0 l17 pr13/19/25/44b/pclkc2_0 m18 vcco2 h14 vcco2 h15 vcco2 j15 vcco2 k16 vcco3 l16 vcco3 m16 vcco3 n16 pllvcc n18 pllvcc j16 vcco3 p16 pllcap n17 tp_h17 tp_h17 + c101 10uf sizeb + c101 10uf sizeb tp_m18 tp_m18 tp_r21 tp_r21 tp_gnd3 tp_gnd3 tp_p19 tp_p19 tp_f22 tp_f22 c97 0.1uf cc0603 c97 0.1uf cc0603 tp_f19 tp_f19 tp_k22 tp_k22 tp_gnd6 tp_gnd6 y1 dip16 y1 dip16 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 tp_vcc9 tp_vcc9 tp_j22 tp_j22 tp_f18 tp_f18 tp_p21 tp_p21 jb5 jblock jb5 jblock tp_g19 tp_g19 tp_m20 tp_m20 tp_vcc4 tp_vcc4 tp_m22 tp_m22 tp_g21 tp_g21 tp_g22 tp_g22 tp_n19 tp_n19 r115 0 r115 0 tp_n20 tp_n20 tp_j18 tp_j18 tp_h18 tp_h18 tp_h22 tp_h22 tp_gnd2 tp_gnd2 tp_n22 tp_n22 c77 0.1uf cc0402 c77 0.1uf cc0402 tp_p22 tp_p22 r116 10 r116 10 tp_k17 tp_k17 r117 0 r117 0 c96 0.01uf cc0603 c96 0.01uf cc0603 tp_e20 tp_e20 tp_l21 tp_l21 tp_gnd5 tp_gnd5 c104 0.1uf cc0603 c104 0.1uf cc0603 c74 0.1uf cc0402 c74 0.1uf cc0402 tp_m21 tp_m21 tp_k20 tp_k20 tp_vcc8 tp_vcc8 tp_h21 tp_h21 tp_r20 tp_r20 tp_vcc2 tp_vcc2 c84 5.6nf cc0603 c84 5.6nf cc0603 tp_h20 tp_h20 tp_n21 tp_n21 tp_e22 tp_e22 tp_f21 tp_f21 j37 header 3x2 j37 header 3x2 2 4 6 1 3 5
30 latticeecp2 standard evaluation board lattice semiconductor user? guide figure 11. 64-bit pci, pci-x 5 5 4 4 3 3 2 2 1 1 d d c c b b a a vcc_3.3v pci_gnt_n pci_trdy_n pci_devsel_n pci_ad0 pci_ack64_n pci_ad2 pci_req64_n pci_ad4 pci_ad6 pci_ad9 pci_ad11 pci_ad13 pci_intb_n pci_intd_n pci_inta_n pci_intc_n pci_prsnt1_n pci_ad48 pci_prsnt2_n pci_rst_n pci_ad18 pci_ad20 pci_tms pci_ad22 pci_tdi pci_ad24 pcix_ecc3 pci_ad41 pci_ad63 pci_tdo pci_ad54 vcc_3.3v pci_prsnt1_n pci_ad49 pcix_ecc4 pci_ad61 pci_ad39 pci_cbe7_n pci_ad52 pcix_ecc2 pci_ad59 pci_ad37 pci_prsnt2_n pci_ad50 pci_cbe5_n pci_inta_n pci_intc_n pci_intb_n pci_intd_n pci_ad57 pci_ad35 pci_ad46 pci_ad32 pci_cbe6_n pci_cbe4_n pci_ad55 pci_ad23 pci_ad33 pci_pcixcap pci_ad44 pci_ad53 pci_ad42 pci_trstn pci_ad51 pci_ad40 pci_ad62 pci_smbclk pci_ad47 pci_ad38 pci_ad60 pci_smbdat pci_ad45 pci_ad36 pci_ad58 pci_cbe3_n pci_ad26 pci_ad28 pci_ad30 pci_m66en pcix_ecc5 pci_ad16 pci_ad43 pci_ad15 pci_ad1 pci_ad3 pci_ad34 pci_clk pci_ad5 pci_ad7 pci_ad8 pci_ad10 pci_ad12 pci_ad14 pci_ad17 pci_ad19 pci_ad21 pci_ad25 pci_ad27 pci_ad29 pci_ad31 pci_tck pci_ad56 pci_ad[63:0] pci_stop_n pci_cbe0_n pci_cbe1_n pci_cbe2_n pci_frame_n pci_irdy_n pci_req_n pci_idsel pci_serr_n pci_perr_n pci_par pci_ad31 pci_ad27 pci_ad29 pci_ad25 pci_ad23 pci_ad30 pci_ad21 pci_ad19 pci_ad28 pci_ad26 pci_ad24 pci_ad22 pci_ad20 pci_ad17 pci_ad16 pci_ad18 pci_ad12 pci_ad14 pci_ad15 pci_ad7 pci_ad10 pci_ad8 pci_ad5 pci_ad3 pci_ad1 pci_ad13 pci_ad11 pci_ad9 pci_ad4 pci_ad59 pci_ad6 pci_ad63 pci_ad62 pci_ad61 pci_ad60 pci_ad58 pci_ad56 pci_ad50 pci_ad52 pci_ad45 pci_ad51 pci_ad49 pci_ad44 pci_ad42 pci_ad34 pci_ad32 pci_ad40 pci_ad47 pci_ad38 pci_ad43 pci_ad41 pci_ad37 pci_ad33 pci_ad35 pci_ad39 pci_ad2 pci_ad48 pci_ad36 pci_ad46 pci_ad53 pci_ad55 pci_ad57 pci_req_n pcix_ecc2 pcix_ecc5 pcix_ecc4 pcix_ecc3 pci_rst_n pci_cbe3_n pci_gnt_n pci_cbe2_n pci_int_n pci_idsel pci_perr_n pci_stop_n pci_trdy_n pci_irdy_n pci_serr_n pci_cbe1_n pci_par pci_frame_n pci_cbe6_n pci_cbe7_n pci_req64_n pci_cbe4_n pci_ad0 pci_ack64_n pci_cbe0_n pci_ad54 pci_cbe5_n pci_devsel_n pci_pcixcap pci_m66en vcc_3.3v par64 par64 vcc_3.3v pci_clk pci_gnd_57 title size document number rev date: sheet of b ecp2 standard -- 64 bit pci, pci-x c 48 title size document number rev date: sheet of b ecp2 standard -- 64 bit pci, pci-x c 48 title size document number rev date: sheet of b ecp2 standard -- 64 bit pci, pci-x c 48 lattice semiconductor corporation these 0.01 f capacitors must be located within 0.25 inches of their pci edge connector pin. these 0.01 f capacitors must be located within 0.25 inches of their pci edge connector pin. [5] load for master only load for master only load for master only load for master only 1-2 = master 2-3 = 33 mhz pci n/c = 66 mhz pci 1-2 = 66mhz pci-x n/c = 133 mhz pci-x 1-2 = target n/c = master [8] 1-2 = master 2-3 = target n/c = target 1-2 = master n/c = target load for master only load for master only load for master only load for master only pci decoupling [8] r51 5.6k r51 5.6k c109 0.1uf cc0603 c109 0.1uf cc0603 c112 0.1uf cc0603 c112 0.1uf cc0603 c51 0.1uf cc0603 c51 0.1uf cc0603 c52 0.1uf cc0603 c52 0.1uf cc0603 tp17 tp17 tp12 tp12 r88 10k r88 10k (3 of 6) bank5 bank4 dqs group dqs group dqs group dqs group dqs group dqs group pad name = pb{12/22/35/50} u3c ecp2-12/22/35/50-fpbga484 (3 of 6) bank5 bank4 dqs group dqs group dqs group dqs group dqs group dqs group pad name = pb{12/22/35/50} u3c ecp2-12/22/35/50-fpbga484 pb2/2/2/2a/vref2_5 y3 pb3/3/3/3a w4 pb4/4/4/4a w5 pb5/5/5/5a ab3 pb6/6/6/6a/bdqs y4 pb7/7/7/7a ab5 pb8/8/8/8a aa5 pb9/9/9/9a ab6 pb11/20/20/29a w7 pb12/21/21/30a y6 pb13/22/22/31a aa7 pb14/23/23/32a u8 pb15/24/24/33a/bdqs w9 pb16/25/25/34a y8 pb17/26/26/35a w10 pb18/27/27/36a ab8 pb20/29/29/38a ab9 pb21/30/30/39a y10 pb22/31/31/40a u10 pb23/32/32/41a ab11 pb24/33/33/42a/bdqs y11 pb25/34/34/43a ab12 pb26/35/35/44a/pclkt5_0 ab13 pb2/2/2/2b/vref1_5 y2 pb3/3/3/3b w3 pb4/4/4/4b w6 pb5/5/5/5b ab2 pb6/6/6/6b aa3 pb7/7/7/7b ab4 pb8/8/8/8b y5 pb9/9/9/9b aa6 pb11/20/20/29b w8 pb12/21/21/30b y7 pb13/22/22/31b ab7 pb14/23/23/32b u9 pb15/24/24/33b v9 pb16/25/25/34b aa8 pb17/26/26/35b v10 pb18/27/27/36b aa9 pb20/29/29/38b ab10 pb21/30/30/39b aa10 pb22/31/31/40b u11 pb23/32/32/41b aa11 pb24/33/33/42b w11 pb25/34/34/43b aa12 pb26/35/35/44b/pclkc5_0 ab14 pclkt4_0/pb31/40/40/49a u12 pb32/41/41/50a y12 bdqs/pb33/42/42/51a aa13 pb34/43/43/52a u13 pb35/44/44/53a ab15 pb36/45/45/54a ab16 pb37/46/46/55a w13 pb39/48/48/57a ab18 pb40/49/49/58a v14 pb41/50/50/59a y15 bdqs/pb42/51/51/60a aa16 pb43/52/52/61a ab20 pb44/53/53/62a u15 pb45/54/54/63a y16 pb46/55/55/64a aa18 pb48/57/66/75a aa21 pb49/58/67/76a v16 pb50/59/68/77a y18 bdqs/pb51/60/69/78a y19 pb52/61/70/79a w17 pb53/62/71/80a y21 pb54/63/72/81a u18 vref2_4/pb55/64/73/82a t15 pclkc4_0/pb31/40/40/49b v12 pb32/41/41/50b w12 pb33/42/42/51b y13 pb34/43/43/52b u14 pb35/44/44/53b aa14 pb36/45/45/54b ab17 pb37/46/46/55b w14 pb39/48/48/57b ab19 pb40/49/49/58b w15 pb41/50/50/59b aa15 pb42/51/51/60b aa17 pb43/52/52/61b ab21 pb44/53/53/62b u16 pb45/54/54/63b w16 pb46/55/55/64b aa20 pb48/57/66/75b aa22 pb49/58/67/76b v17 pb50/59/68/77b y17 pb51/60/69/78b y20 pb52/61/70/79b w18 pb53/62/71/80b y22 pb54/63/72/81b v18 vref1_4/pb55/64/73/82b t16 vcco5 r9 vcco5 t9 vcco5 t10 vcco5 t11 vcco4 t14 vcco4 t13 vcco4 t12 vcco4 r14 c111 0.01uf cc0603 c111 0.01uf cc0603 + c7 10uf sizeb + c7 10uf sizeb c59 0.1uf cc0603 c59 0.1uf cc0603 c4 0.1uf cc0603 c4 0.1uf cc0603 c46 0.01uf cc0603 c46 0.01uf cc0603 c1 0.1uf cc0603 c1 0.1uf cc0603 c114 0.1uf cc0603 c114 0.1uf cc0603 j9 j9 1 2 3 + c9 10uf sizeb + c9 10uf sizeb j23 header 2 j23 header 2 1 2 c10 0.1uf cc0402 c10 0.1uf cc0402 j38 j38 1 2 3 r106 5.6k r106 5.6k c107 0.1uf cc0603 c107 0.1uf cc0603 + c12 10uf sizeb + c12 10uf sizeb tp16 tp16 tp11 tp11 r107 5.6k r107 5.6k tp9 tp9 c61 0.1uf cc0402 c61 0.1uf cc0402 c108 0.1uf cc0603 c108 0.1uf cc0603 c42 0.1uf cc0603 c42 0.1uf cc0603 tp14 tp14 c100 0.1uf cc0603 c100 0.1uf cc0603 r1 5.6k r1 5.6k tp10 tp10 j19 header 3x2 j19 header 3x2 2 4 6 1 3 5 r59 5.6k r59 5.6k c90 0.1uf cc0603 c90 0.1uf cc0603 r62 5.6k r62 5.6k c3 0.1uf cc0603 c3 0.1uf cc0603 c11 0.1uf cc0603 c11 0.1uf cc0603 c113 0.1uf cc0603 c113 0.1uf cc0603 c47 0.01uf cc0603 c47 0.01uf cc0603 tp15 tp15 + c45 10uf sizeb + c45 10uf sizeb c99 0.1uf cc0402 c99 0.1uf cc0402 r126 5.6k r126 5.6k c6 0.1uf cc0603 c6 0.1uf cc0603 r60 5.6k r60 5.6k c39 0.01uf cc0603 c39 0.01uf cc0603 c5 0.1uf cc0603 c5 0.1uf cc0603 r61 5.6k r61 5.6k j48 pci/pci-x 64bit edge con bottom j48 pci/pci-x 64bit edge con bottom trst# 1 +12v 2 tms 3 tdi 4 +5v_5 5 inta# 6 intc# 7 +5v_8 8 reserved_9 9 +vio_10 10 reserved_11 11 3.3vaux 14 rst# 15 +vio_16 16 gnt# 17 ground_18 18 pme# 19 ad[30] 20 +3.3v_21 21 ad[28] 22 ad[26] 23 ground_24 24 ad[24] 25 idsel 26 +3.3v_27 27 ad[22] 28 ad[20] 29 ground_30 30 ad[18] 31 ad[16] 32 +3.3v_33 33 frame# 34 ground_35 35 trdy# 36 ground_37 37 stop# 38 +3.3v_39 39 reserved_40 40 reserved_41 41 ground_42 42 par 43 ad[15] 44 +3.3v_45 45 ad[13] 46 ad[11] 47 ground_48 48 ad[09] 49 c/be#[0] 52 +3.3v_53 53 ad[06] 54 ad[04] 55 ground_56 56 ad[02] 57 ad[00] 58 +vio_59 59 req64# 60 +5v_61 61 +5v_62 62 ground_63 63 ground_69 69 ground_72 72 ground_78 78 ground_81 81 ground_87 87 ground_90 90 ground_93 93 +vio_66 66 +vio_75 75 +vio_84 84 reserved_92 92 reserved_94 94 c/be[7]# 64 cbe[5]#/ad[48] 65 par64/ecc[7] 67 ad[48]/cbe[5]# 79 ad[62] 68 ad[60] 70 ad[58] 71 ad[56] 73 ad[54] 74 ad[52] 76 ad[50] 77 ad[46] 80 ad[44] 82 ad[42] 83 ad[40] 85 ad[38] 86 ad[36] 88 ad[34] 89 ad[32] 91 c8 0.1uf cc0603 c8 0.1uf cc0603 c50 0.1uf cc0603 c50 0.1uf cc0603 j13 header 2 j13 header 2 1 2 c58 0.1uf cc0603 c58 0.1uf cc0603 tp13 tp13 tp8 tp8 c92 0.1uf cc0402 c92 0.1uf cc0402 j14 pci/pci-x 64bit edge con top j14 pci/pci-x 64bit edge con top -12v 1 tck 2 ground_3 3 tdo 4 +5v_5 5 +5v_7 6 intb# 7 intd# 8 prsnt1# 9 reserved_10 10 prsnt2# 11 reserved_14 14 ground_15 15 clk 16 ground_17 17 req# 18 +vio_19 19 ad[31] 20 ad[29] 21 ground_22 22 ad[27] 23 ad[25] 24 +3.3v_25 25 c/be#[3] 26 ad[23] 27 ground_28 28 ad[21] 29 ad[19] 30 +3.3v_31 31 ad[17] 32 c/be#[2] 33 ground_34 34 irdy# 35 +3.3v_36 36 devsel# 37 ground_38 38 lock# 39 perr# 40 +3.3v_41 41 serr# 42 +3.3v_43 43 c/be#[1] 44 ad[14] 45 ground_46 46 ad[12] 47 ad[10] 48 m66en 49 ad[08] 52 ad[07] 53 +3.3v_54 54 ad[05] 55 ad[03] 56 ground_57 57 ad[01] 58 +vio_59 59 ack64# 60 +5v_61 61 +5v_62 62 reserved_63 63 ground_64 64 c/be[6]# 65 cbe[4]#/ad[49] 66 ground_67 67 ad[63] 68 ad[61] 69 +vio_70 70 ad[59] 71 ad[57] 72 ground_73 73 ad[55] 74 ad[53] 75 ground_76 76 ad[51] 77 ad[49]/cbe[4]# 78 +vio_79 79 ad[47] 80 ad[45] 81 ground_85 85 ground_82 82 +vio_88 88 ground_91 91 ground_94 94 reserved_92 92 reserved_93 93 ad[43] 83 ad[41] 84 ad[39] 86 ad[37] 87 ad[35] 89 ad[33] 90 c60 0.1uf cc0603 c60 0.1uf cc0603 j24 header 2 j24 header 2 1 2
31 latticeecp2 standard evaluation board lattice semiconductor user? guide figure 12. si testing 5 5 4 4 3 3 2 2 1 1 d d c c b b a a si7 si6 si5 si4 si3 si2 si1 si0 vccio7 vccio6 si7 si6 si5 si4 si3 si2 si1 si0 si[7:0] vcc_1.2v vcc_3.3v vcc_adj vcc_adj vcc_1.2v vcc_3.3v vcc_1.2v pci_clk vcc_1.2v vcc_3.3v title size document number rev date: sheet of b ecp2 standard -- si testing c 58 title size document number rev date: sheet of b ecp2 standard -- si testing c 58 title size document number rev date: sheet of b ecp2 standard -- si testing c 58 lattice semiconductor corporation 50 ohm sma connectors diff pair, equal length, 50 ohms diff pair, equal length, 50 ohms diff pair, equal length, 50 ohms diff pair, equal length, 50 ohms place pad for header pin 2 directly on the trace to avoid a stub. [4] add jumper if using pci or pci-x [8] [8] [8] [8] = unconnected, plated holes 6 5 4 3 2 1 gnd m n p r t u v vccio6 w y prototype area map 7 vccio6 (vccio6) amp 6368150-1 vertical mount diff pair, equal length, 50 ohms diff pair, equal length, 50 ohms diff pair, equal length, 50 ohms diff pair, equal length, 50 ohms 456 23 1 e gnd f g j h vccio7 7 = unconnected, plated holes prototype area map (vccio7) aa place resistor trio as close to the fpga as possible place resistor trio as close to the fpga as possible place resistor trio as close to the fpga as possible place resistor trio as close to the fpga as possible place resistor trio as close to the fpga as possible place resistor trio as close to the fpga as possible place resistor trio as close to the fpga as possible place resistor trio as close to the fpga as possible [8] 13 2 sot-23 bas70-04 r28 dnl r28 dnl j25 sma connector j25 sma connector 2 3 4 5 1 tp_gsi2 tp_gsi2 tp_y1 tp_y1 r23 dnl r23 dnl r7 dnl r7 dnl tp_g3 tp_g3 j16 sma connector j16 sma connector 2 3 4 5 1 + c2 10uf sizeb + c2 10uf sizeb tp_v4 tp_v4 tp_vcc10 tp_vcc10 j27 sma connector j27 sma connector 2 3 4 5 1 tp_g1 tp_g1 jb11 jblock jb11 jblock r29 dnl r29 dnl tp_gsi3 tp_gsi3 r20 dnl r20 dnl tp_gnd12 tp_gnd12 j15 sma connector j15 sma connector 2 3 4 5 1 tp_gsi4 tp_gsi4 r81 dnl r81 dnl tp_t7 tp_t7 tp_h6 tp_h6 + c44 10uf sizeb + c44 10uf sizeb j18 header 3x2 j18 header 3x2 2 4 6 1 3 5 r75 dnl r75 dnl c69 0.1uf cc0402 c69 0.1uf cc0402 tp_gsi5 tp_gsi5 tp_v1 tp_v1 r79 dnl r79 dnl r26 dnl r26 dnl r22 dnl r22 dnl tp_t2 tp_t2 tp_h3 tp_h3 tp_t3 tp_t3 r76 dnl r76 dnl tp_vcc13 tp_vcc13 tp_vcc18 tp_vcc18 c54 0.1uf cc0603 c54 0.1uf cc0603 r87 dnl r87 dnl tp_f3 tp_f3 r24 dnl r24 dnl r91 dnl r91 dnl r73 dnl r73 dnl r21 dnl r21 dnl tp_m2 tp_m2 tp_gsi6 tp_gsi6 r25 dnl r25 dnl j22 header 2 j22 header 2 1 2 r89 dnl r89 dnl tp_f5 tp_f5 r82 dnl r82 dnl tp_gsi7 tp_gsi7 r90 dnl r90 dnl r9 dnl r9 dnl tp_g7 tp_g7 j26 sma connector j26 sma connector 2 3 4 5 1 tp_n4 tp_n4 tp_u1 tp_u1 tp_h5 tp_h5 tp_r7 tp_r7 c79 5.6nf cc0603 c79 5.6nf cc0603 tp_n2 tp_n2 r10 dnl r10 dnl r83 dnl r83 dnl tp_p5 tp_p5 r18 dnl r18 dnl d20 bas70-04 d20 bas70-04 1 3 2 tp_t1 tp_t1 tp_f2 tp_f2 tp_e5 tp_e5 tp_vcc12 tp_vcc12 tp_t5 tp_t5 tp_n1 tp_n1 tp_u4 tp_u4 r14 dnl r14 dnl tp_aa1 tp_aa1 r3 dnl r3 dnl c68 0.1uf cc0402 c68 0.1uf cc0402 tp_gnd13 tp_gnd13 tp_g4 tp_g4 c55 0.01uf cc0603 c55 0.01uf cc0603 r101 10 r101 10 tp_m4 tp_m4 tp_vcc17 tp_vcc17 tp_m3 tp_m3 r12 dnl r12 dnl r86 dnl r86 dnl tp_vcc15 tp_vcc15 tp_si7 tp_si7 tp_gnd10 tp_gnd10 tp_m1 tp_m1 tp_t6 tp_t6 tp_g2 tp_g2 r15 dnl r15 dnl tp_si0 tp_si0 r84 dnl r84 dnl r4 dnl r4 dnl tp_gnd15 tp_gnd15 tp_r4 tp_r4 tp_gsi1 tp_gsi1 c57 0.01uf cc0603 c57 0.01uf cc0603 tp_j6 tp_j6 tp_u2 tp_u2 tp_gnd11 tp_gnd11 j17 header 3x2 j17 header 3x2 2 4 6 1 3 5 r2 dnl r2 dnl r72 dnl r72 dnl tp_e3 tp_e3 tp_si2 tp_si2 c81 0.1uf cc0402 c81 0.1uf cc0402 tp_w 1 tp_w 1 j20 sma connector j20 sma connector 2 3 4 5 1 tp_p4 tp_p4 r74 dnl r74 dnl j6a rj-45 j6a rj-45 1 2 3 4 5 6 7 8 r19 dnl r19 dnl r13 dnl r13 dnl r85 dnl r85 dnl tp_h2 tp_h2 tp_n3 tp_n3 tp_n5 tp_n5 r27 0 r27 0 tp_si3 tp_si3 r8 dnl r8 dnl tp_v3 tp_v3 tp_f4 tp_f4 tp_vcc11 tp_vcc11 r5 dnl r5 dnl c80 0.1uf cc0402 c80 0.1uf cc0402 r16 dnl r16 dnl 6 k n a b 7 k n a b (4 of 6) pad name = pl{12/22/35/50} dqs group dqs group dqs group dqs group plnnxh = true lvds u3d ecp2-12/22/35/50-fpbga484 6 k n a b 7 k n a b (4 of 6) pad name = pl{12/22/35/50} dqs group dqs group dqs group dqs group plnnxh = true lvds u3d ecp2-12/22/35/50-fpbga484 pl2/2/2/2/2ah/vref2_7 e4 pl2/2/2/2/2bh/vref1_7 e5 plnc/4/10/12ah e3 plnc/4/10/12bh f3 pl3/5/11/13a f4 pl3/5/11/13b f5 pl4/6/12/14ah e2 pl4/6/12/14bh e1 pl5/7/13/15a g6 pl5/7/13/15b g7 plnc/8/14/16ah/ldqs h4 plnc/8/14/16bh h5 plnc/9/15/17a f1 plnc/9/15/17b f2 plnc/10/16/18ah g3 plnc/10/16/18bh g4 plnc/11/17/19a g1 plnc/11/17/19b g2 plnc/nc/nc/25a/spllt_in h6 plnc/nc/nc/25b/spllc_in j6 plnc/nc/nc/26a/spllt_fb h3 plnc/nc/nc/26b/spllc_fb h2 pl6/12/18/37a h1 pl7/13/19/38a j4 pl7/13/19/38b j5 pl8/14/20/39ah j2 pl8/14/20/39bh j1 pl9/15/21/40a l6 pl9/15/21/40b l5 pl10/16/22/41ah/ldqs k3 pl10/16/22/41bh k4 pl11/17/23/42a k2 pl11/17/23/42b k1 pl12/18/24/43ah l4 pl12/18/24/43bh l3 pl13/19/25/44a/pclkt7_0 l2 pl13/19/25/44b/pclkc7_0 l1 vcco7 j8 vcco7 k7 vcco7 l7 vcco7 m7 pclkt6_0/pl15/21/27/46ah m5 pclkc6_0/pl15/21/27/46bh m6 vref2_6/pl16/22/28/47a m3 vref1_6/pl16/22/28/47b m4 plnc/23/29/48ah m2 plnc/23/29/48bh m1 plnc/24/30/49a n1 plnc/24/30/49b n2 ldqs/plnc/25/39/58ah n3 plnc/25/39/58bh n4 plnc/26/40/59a n5 plnc/26/40/59b p5 gdllt_in/pl17/27/41/60ah p1 gdllc_in/pl17/27/41/60bh p2 gdllt_fb/pl18/28/42/61a p4 gdllc_fb/pl18/28/42/61b r4 gpllt_in/pl20/30/44/63ah r1 gpllc_in/pl20/30/44/63bh r2 gpllt_fb/pl21/31/45/64a r3 gpllc_fb/pl21/31/45/64b t4 pl22/32/46/65ah t1 pl22/32/46/65bh t2 pl23/33/47/66a t5 pl23/33/47/66b t3 pl24/38/52/71ah u1 pl24/38/52/71bh u2 pl25/39/53/72a v1 pl25/39/53/72b v2 pl26/40/54/73ah r6 pl26/40/54/73bh t6 pl27/41/55/74a u3 pl27/41/55/74b u4 ldqs/pl28/42/56/75ah y1 pl28/42/56/75bh w1 pl29/43/57/76a r7 pl29/43/57/76b t7 pl30/44/58/77ah v4 pl30/44/58/77bh v3 pl31/45/59/78a aa2 pl31/45/59/78b aa1 vcco6 n7 vcco6 p7 vcco6 p8 vcco6 r8 pllcap p6 pllvcc k6 pllvcc n6 tp_aa2 tp_aa2 j21 sma connector j21 sma connector 2 3 4 5 1 tp_g6 tp_g6 r11 dnl r11 dnl r17 dnl r17 dnl r80 dnl r80 dnl tp_si4 tp_si4 r71 dnl r71 dnl tp_u3 tp_u3 tp_e4 tp_e4 r6 dnl r6 dnl tp_vcc14 tp_vcc14 tp_si5 tp_si5 tp_v2 tp_v2 r77 dnl r77 dnl tp_h4 tp_h4 tp_r6 tp_r6 tp_gsi0 tp_gsi0 jb12 jblock jb12 jblock tp_si6 tp_si6 r100 10 r100 10 r30 dnl r30 dnl tp_vcc19 tp_vcc19 r78 dnl r78 dnl c56 0.1uf cc0603 c56 0.1uf cc0603 tp_h1 tp_h1 tp_gnd14 tp_gnd14 tp_si1 tp_si1 tp_f1 tp_f1 j28 sma connector j28 sma connector 2 3 4 5 1
32 latticeecp2 standard evaluation board lattice semiconductor user? guide figure 13. jtag and sysconfig 5 5 4 4 3 3 2 2 1 1 d d c c b b a a cfg2 cfg0 cfg1 cclk cfg0 tms tdo_dl tms cfg1 cfg2 tdi_ch tdo_ch tdo tdi tdi tck init_chn done progn tms tck tck progn progn programn programn vcc_3.3v programn programn init_chn initn initn initn done done done done spifastn vcc_3.3v vcc_3.3v vcc_3.3v initn init_chn vcc_bank8 vcc_bank8 csspin fpga_d0 cclk busy writen cson cclk fpga_d7 dout fpga_d6 fpga_d5 fpga_d4 fpga_d7 fpga_d7 fpga_d3 fpga_d2 fpga_d6 dout fpga_d1 fpga_d5 fpga_d0 cfg2 csn fpga_d4 cs1n cfg1 fpga_d3 fpga_d6 fpga_d2 initn fpga_d1 writen vcc_bank8 di fpga_d0 fpga_d0 cfg0 cclk initn cson programn done writen sispi vcc_3.3v fpga_d1 fpga_d2 fpga_d3 fpga_d4 fpga_d5 fpga_d6 fpga_d7 fpga_d7 fpga_d0 fpga_d6 dout programn fpga_d[0:7] spid0 programn done vcc_3.3v vcc_3.3v vcc_bank8 cclk vcc_1.2v vcc_adj vcc_3.3v title size document number rev date: sheet of b ecp2 standard -- jtag & sysconfig c 68 title size document number rev date: sheet of b ecp2 standard -- jtag & sysconfig c 68 title size document number rev date: sheet of b ecp2 standard -- jtag & sysconfig c 68 1x10 jtag chain input header e d o m n o i t a r u g i f n o c 2 g f c cfg1 cfg0 ispjtag slave serial spim flash reserved spi flash (default) slave parallel reserved 0(on) 0(on) xxx 1(off) 1(off) 1(off) 1(off) 1(off) 1(off) 1(off) 1(off) 0(on) 0(on) 1(off) 0(on) 0(on) 0(on) 0(on) 0(on) program push button jtag 1x10 jtag chain output header jumper normally not installed only one board in the chain should have this jumper installed 1 to 2 = multiple devices and not last in the chain 2 to 3 = single device or last in the chain (defaul t) gate source drain sot-23 program done initializing spi serial flash (dual footprint) installed = fast read (0bx) (default) removed = normal read (03x) note: not all spi serial flash support fast read reserved 0(on) 1(off) 1(off) d e v r e s e r ) f f o ( 1 0(on) 0(on) on when low on when high on when low lattice semiconductor corporation jumper normally not installed sysconfig sysconfig output jumpers normally not installed jumpers normally not installed [8] load one flash, not both configuration status a1 a2 b2 b1 sysconfig connectors u5 w25p32vsfig u5 w25p32vsfig /hold 1 vcc 2 n/c1 3 n/c2 4 n/c3 5 n/c4 6 /s 7 q 8 /w 9 vss 10 n/c5 11 n/c6 12 n/c7 13 n/c8 14 d 15 c 16 j43 header 3x2 j43 header 3x2 2 4 6 1 3 5 j44 header 2 j44 header 2 1 2 sw2 sw pushbutton sw2 sw pushbutton a1 b1 a2 b2 j7 j7 1 2 3 c35 0.1uf cc0603 c35 0.1uf cc0603 jb22 jblock jb22 jblock jb14 jblock jb14 jblock jb7 jblock jb7 jblock jb18 jblock jb18 jblock (5 of 6) vccj u3e ecp2-12/22/35/50-fpbga484 (5 of 6) vccj u3e ecp2-12/22/35/50-fpbga484 tck u7 tms v5 tdo v6 tdi u5 vccj t8 cfg0 w20 cfg1 v19 cfg2 w19 programn v20 cclk w22 done v21 initn v22 busy/sispi/pr71a r19 dout/cson/pr71b r18 pr72a/di/csspin t22 pr73b/d5 t17 pr72b/d7(lsb)/spid0 t21 pr73a/d6 t18 pr75a/d2 u21 pr74a/d4 t19 pr76b/csn u19 pr74b/d3 t20 pr76a/d0(msb)/spifastn u20 pr75b/d1 u22 pr77a/cs1n r17 pr77b/writen r16 vcco8 p15 vcco8 r15 j10 header 2 j10 header 2 1 2 j11 header 2 j11 header 2 1 2 + c13 10uf sizeb + c13 10uf sizeb tp_102 tp_102 jb17 jblock jb17 jblock j33 j33 1 2 3 j35 header 2 j35 header 2 1 2 r130 10k r130 10k r125 10k r125 10k c86 0.1uf cc0402 c86 0.1uf cc0402 r32 470 r32 470 j5 header 10 j5 header 10 1 2 3 4 5 6 7 8 9 10 r129 10k r129 10k j32 j32 1 2 3 c106 0.1uf cc0603 c106 0.1uf cc0603 r52 4.7k r52 4.7k j34 j34 1 2 3 r122 10k r122 10k jb16 jblock jb16 jblock gnd20 header 1 gnd20 header 1 1 c62 0.1uf cc0402 c62 0.1uf cc0402 j39 header 3x2 j39 header 3x2 2 4 6 1 3 5 r128 10k r128 10k tp_101 tp_101 jb15 jblock jb15 jblock u4 w25p16vssig u4 w25p16vssig /s 1 q 2 /w 3 vss 4 vcc 8 /hold 7 c 6 d 5 r31 470 r31 470 j4 header 10 j4 header 10 1 2 3 4 5 6 7 8 9 10 r127 10k r127 10k r123 10k r123 10k q1 bss138lt1 q1 bss138lt1 tp_103 tp_103 gnd19 header 1 gnd19 header 1 1 d11 led_red d11 led_red r121 10k r121 10k jb19 jblock jb19 jblock r120 4.7k r120 4.7k j36 header 2 j36 header 2 1 2 j31 j31 1 2 3 j8 header 2 j8 header 2 1 2 j40 header 17x2 j40 header 17x2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 d12 led_yellow d12 led_yellow j41 header 17x2 j41 header 17x2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 jb13 jblock jb13 jblock r118 10k r118 10k tp_100 tp_100 r124 10k r124 10k r33 470 r33 470 d10 led_green d10 led_green
33 latticeecp2 standard evaluation board lattice semiconductor user? guide figure 14. fpga power 5 5 4 4 3 3 2 2 1 1 d d c c b b a a xres vcc_aux vcc_core vcc_1.2v vcc_3.3v title size document number rev date: sheet of b ecp2 standard -- fpga power b 78 title size document number rev date: sheet of b ecp2 standard -- fpga power b 78 title size document number rev date: sheet of b ecp2 standard -- fpga power b 78 current measurement (remove jumpers, insert meter) [8] [8] current measurement (remove jumper, insert meter) lattice semiconductor corporation c72 0.1uf cc0402 c72 0.1uf cc0402 c78 0.1uf cc0402 c78 0.1uf cc0402 c73 0.1uf cc0402 c73 0.1uf cc0402 c85 0.1uf cc0402 c85 0.1uf cc0402 jb27 jblock jb27 jblock c91 0.1uf cc0402 c91 0.1uf cc0402 c64 0.1uf cc0402 c64 0.1uf cc0402 c75 0.1uf cc0402 c75 0.1uf cc0402 c82 0.1uf cc0402 c82 0.1uf cc0402 c71 0.1uf cc0402 c71 0.1uf cc0402 c65 0.1uf cc0402 c65 0.1uf cc0402 c70 0.1uf cc0402 c70 0.1uf cc0402 j30 header 3x2 j30 header 3x2 2 4 6 1 3 5 + c95 10uf sizeb + c95 10uf sizeb j29 header 2 j29 header 2 1 2 (6 of 6) u3f ecp2-12/22/35/50-fpbga484 (6 of 6) u3f ecp2-12/22/35/50-fpbga484 vcc core j10 vcc core j11 vcc core j12 vcc core j13 vcc core k9 vcc core k14 vcc core l9 vcc core l14 vcc core m9 vcc core m14 vcc core n9 vcc core n14 vcc core p10 vcc core p11 vcc core p12 vcc core p13 xres (10k 1% to gnd) f12 gnd a1 vccaux c5 vccaux d11 vccaux e6 vccaux e17 vccaux f13 vccaux g5 vccaux g18 vccaux k5 vccaux m17 vccaux p17 vccaux r5 vccaux v7 gnd a22 gnd aa4 gnd aa19 gnd ab1 gnd ab22 gnd b4 gnd b19 gnd c9 gnd c14 gnd d2 gnd d21 gnd f6 gnd f17 gnd h10 gnd h11 gnd h12 gnd h13 gnd j3 gnd j9 gnd j14 gnd j20 gnd k8 gnd k10 gnd k11 gnd k12 gnd k13 gnd k15 gnd l8 gnd l10 gnd l11 gnd l12 gnd l13 gnd l15 gnd m8 gnd m10 gnd m11 gnd m12 gnd m13 gnd m15 gnd n8 gnd n10 gnd n11 vccaux v8 vccaux v11 vccaux v13 vccaux v15 gnd n12 gnd w21 gnd n15 gnd n13 gnd w2 gnd u17 gnd r12 gnd p20 gnd r11 gnd y9 gnd r10 gnd p14 gnd u6 gnd p9 gnd p3 gnd r13 gnd y14 jb25 jblock jb25 jblock c67 0.1uf cc0402 c67 0.1uf cc0402 jb26 jblock jb26 jblock c63 0.1uf cc0402 c63 0.1uf cc0402 c89 0.1uf cc0402 c89 0.1uf cc0402 + c94 10uf sizeb + c94 10uf sizeb r105 10k 1% r105 10k 1% c87 0.1uf cc0402 c87 0.1uf cc0402 c88 0.1uf cc0402 c88 0.1uf cc0402 jb24 jblock jb24 jblock c76 0.1uf cc0402 c76 0.1uf cc0402
34 latticeecp2 standard evaluation board lattice semiconductor user? guide figure 15. power 5 5 4 4 3 3 2 2 1 1 d d c c b b a a drain_adv vcc_in drain_1.2 vcc_in vcc_3.3v vcc_in vcc_in vcc_in vcc_3.3v vcc_in vcc_3.3v vcc_1.2v vcc_5v pci_gnd_57 vcc_adj title size document number rev date: sheet of b ecp2 standard -- power c 88 title size document number rev date: sheet of b ecp2 standard -- power c 88 title size document number rev date: sheet of b ecp2 standard -- power c 88 banana jack banana jack output voltage adjust 5v dc only place switch next to dc input jack lattice semiconductor corporation 2.5mm pin, (+) 5.5mm barrel, (-) 3.3v, 3a adjustable, 1.2v to 2.5v, 3a 1.2v, 3a [2,3,4,5,6,7] [3,5,6,7] x7r [2] 5v, 300ma x7r lmk212bj225mg-t lmk325bj106mn-t x7r x5r x7r lmk325bj106mn-t lmk432bj226mm-t for lcd module 5w to 23w [4] when this board is plugged into pci this signal disables the 3.3v converter. 3.3v will then come from the pci bus. [3,5,6] c3225x5r1c226m 16v x5r ecj-2vb1h472k ecj-1vb1h103k t520b476m006ase070 sumida cdrh8d43-100nc reverse polarity protection c117 22uf cc1210 c117 22uf cc1210 u7 tps60131 u7 tps60131 in 7 in 14 nc 18 c1+ 6 c1- 8 enable 3 out 5 out 16 fb 4 pg 17 c2+ 15 c2- 13 pgnd 9 pgnd 10 pgnd 11 pgnd 12 gnd 1 gnd 2 gnd 19 gnd 20 pad 21 q3 si5447dc q3 si5447dc d 1 d 2 d 3 g 4 s 5 d 6 d 7 d 8 c24 0.1uf cc0603 c24 0.1uf cc0603 c27 10uf cc1210 c27 10uf cc1210 u6 mp2307 u6 mp2307 vin 2 bs 1 en 7 ss 8 sw 3 fb 5 gnd 4 comp 6 pad 9 j47 pwr jack j47 pwr jack 3 2 1 d15 1n5820 267-05 d15 1n5820 267-05 r38 26.1k 1% cr0603 r38 26.1k 1% cr0603 + c21 47uf sizeb + c21 47uf sizeb c25 2.2uf cc0805 c25 2.2uf cc0805 j45 conn_black j45 conn_black s 1 r45 200k r45 200k r36 500k r36 500k 1 3 2 gnd22 header 1 gnd22 header 1 1 u8 tps64203dvb sot23-6 u8 tps64203dvb sot23-6 /en 1 gnd 2 fb 3 isense 4 vin 5 sw 6 + c31 10uf sizec + c31 10uf sizec + c18 100uf sized + c18 100uf sized c28 1800pf cc0603 c28 1800pf cc0603 j46 conn_red j46 conn_red s 1 + c14 100uf sized + c14 100uf sized r37 10k 1% cr0603 r37 10k 1% cr0603 d14 b320a sma d14 b320a sma c30 1800pf cc0603 c30 1800pf cc0603 r40 100k cr0603 r40 100k cr0603 c22 4.7nf cc0603 c22 4.7nf cc0603 r43 100 cr0805 r43 100 cr0805 r46 10 r46 10 q2 si5447dc q2 si5447dc d 1 d 2 d 3 g 4 s 5 d 6 d 7 d 8 c15 22uf cc1812 c15 22uf cc1812 r39 5.6k cr0603 r39 5.6k cr0603 r44 100 cr0805 r44 100 cr0805 d16 1n5820 267-05 d16 1n5820 267-05 c19 4.7pf cc0603 c19 4.7pf cc0603 l2 6.2uh 7mmx7mm l2 6.2uh 7mmx7mm 1 2 c17 10uf cc1210 c17 10uf cc1210 c32 10nf cc0603 c32 10nf cc0603 d13 b320a sma d13 b320a sma r42 10 r42 10 r41 10k r41 10k d17 1n5819 sod-123 d17 1n5819 sod-123 + c16 1uf sizea + c16 1uf sizea d18 bat54 sod-123 d18 bat54 sod-123 l1 6.2uh 7mmx7mm l1 6.2uh 7mmx7mm 1 2 c26 2.2uf cc0805 c26 2.2uf cc0805 c23 dnl cc0603 c23 dnl cc0603 + c20 1uf sizea + c20 1uf sizea d19 mbrs340 smc d19 mbrs340 smc gnd21 header 1 gnd21 header 1 1 + c29 10uf sizec + c29 10uf sizec u9 tps64203dvb sot23-6 u9 tps64203dvb sot23-6 /en 1 gnd 2 fb 3 isense 4 vin 5 sw 6 l3 10uh 8.3mmx8.3mm l3 10uh 8.3mmx8.3mm 1 2

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