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data sheet powerpc 403gc 32-bit risc embedded controller features ? powerpc ? risc cpu and instruction set architecture ? glueless interfaces to dram, sram, rom, and peripherals, including byte and half-word devices ? separate instruction cache and write-back data cache, both two-way set-associative ? memory management unit C64-entry, fully associative tlb array Cvariable page size (1kb-16mb) Cflexible tlb management ? individually programmable on-chip controllers for: Cfour dma channels Cdram, sram, and rom banks Cexternal interrupts ? flexible interface to external bus masters ? hardware multiplier and divider ? thirty-two 32-bit general purpose registers applications ? set-top boxes ? consumer electronics and video games ? telecommunications and networking ? office automation (printers, copiers, fax) ? personal digital assistants (pda) specifications ? 25mhz, 33mhz, and 40mhz versions ? interfaces to both 3v and 5v technologies ? low-power 3.3v operation with built-in power management and stand-by mode ? low-cost 160 lead pqfp package ? 0.5 m m triple-level-metal cmos overview the powerpc 403gc 32-bit risc embedded controller offers high performance and functional integration with low power consumption. the 403gc risc cpu executes at sustained speeds approaching one cycle per instruction. on-chip caches and integrated dram and sram control functions reduce chip count and design complexity in systems, while improving system throughput. external i/o devices or sram/dram memory banks can be directly attached to the 403gc bus interface unit (biu). interfaces for up to eight memory banks and i/o devices, including a maximum of four dram banks, can be configured individually, allowing the biu to manage devices or memory banks with differing control, timing, or bus width requirements. risc execution unit cache unit instruction cache unit data 4-channel dma controller serial port jtag port dram controller i/o controller bus interface unit sram, rom, i/o controls controls address bus data bus timers (address and control) on-chip peripheral bus dram interrupt controller memory management unit
ibm powerpc 403gc 2 the 403gc risc controller consists of a pipelined risc processor core and several peripheral interface units: biu, dma controller, asynchronous interrupt controller, serial port, and jtag debug port. the risc processor core includes the internal 2kb instruction cache and 1kb data cache, reducing overhead for data transfers to or from external memory. the instruction queue logic manages branch prediction, folding of branch and condition register logical instructions, and instruction prefetching to minimize pipeline stalls.the integrated memory management unit provides robust memory management and protection functions, optimized for embedded environments. risc cpu the risc core comprises four tightly coupled functional units: the execution unit (exu), the memory management unit (mmu), the data cache unit (dcu), and the instruction cache unit (icu). each cache unit consists of a data array, tag array, and control logic for cache management and addressing. the execution unit consists of general purpose registers (gpr), special purpose registers (spr), alu, multiplier, divider, barrel shifter, and the control logic required to manage data flow and instruction execution within the exu. the exu handles instruction decoding and execution, queue management, branch prediction, and branch folding. the instruction cache unit passes instructions to the queue in the exu or, in the event of a cache miss, requests a fetch from external memory through the bus interface unit. the mmu provides translation and memory protection for instruction and data accesses, using a unified 64-entry, fully associative tlb array. general purpose registers data transfers to and from the exu are handled through the bank of 32 gprs, each 32 bits wide. load and store instructions move data operands between the gprs and the data cache unit, except in the cases of noncacheable data or cache misses. in such cases the dcu passes the address for the data read or write to the biu. when noncacheable operands are being transferred, data can pass directly between the exu and the biu, which interfaces to the external memory being accessed. special purpose registers special purpose registers are used to control debug facilities, timers, interrupts, the protection mechanism, memory cacheability, and other architected processor resources. sprs are accessed using move to/from special purpose register (mtspr/mfspr) instructions, which move operands between gprs and sprs. supervisory programs can write the appropriate sprs to configure the operating and interface modes of the execution unit. the condition register (cr) and machine state register (msr) are written by internal control logic with program execution status and machine state, respectively. status of external interrupts is maintained in the external interrupt status register (exisr). fixed- point arithmetic exception status is available from the exception register (xer). device control registers device control registers (dcr) are used to manage i/o interfaces, dma channels, sram and dram memory configurations and timing, and status/address information regarding bus errors. dcrs are accessed using move to/from device control register (mtdcr/mfdcr) instructions, which move operands between gprs and dcrs. instruction set table 1 summarizes the 403gc instruction set by categories of operations. most instructions execute in a single cycle, with the exceptions of load/store multiple, load/store string, multiply, and divide instructions. bus interface unit the bus interface unit integrates the functional controls for data transfers and address operations other than those which the dma controller handles. dma transfers use the address logic in the biu to output the memory addresses being accessed.
ibm powerpc 403gc 3 control functions for direct-connect i/o devices and for dram, sram, or rom banks are provided by the biu. burst access for sram, rom, and page-mode dram devices is supported for cache fill and flush operations. the biu controls the transfer of data between the external bus and the instruction cache, the data cache, or registers internal to the processor core. the biu also arbitrates among external bus master and dma transfers, the internal buses to the cache units and the register banks, and the serial port on the on-chip peripheral bus (opb). memory addressing regions the 403gc can address an effective range of four gigabytes, mapped to 3.5gb (256mb for sram/rom or other i/o, 256mb dram, and 3gb opb/reserved) of physical address space containing twenty-eight 128mb regions. cacheability with respect to the instruction or data cache is programmed via the instruction and data cache control registers, respectively. within the dram and sram/rom regions, a total of eight banks of devices are supported. each bank can be configured for 8-, 16-, or 32-bit devices. for individual dram banks, the number of wait states, bank size, ras -to- cas timing, use of an external address multiplexer (for external bus masters), and refresh rate are user- programmable. for each sram/rom bank, the bank size, bank location, number of wait states, and timings of chip selects, byte enables, and output enables are all user-programmable. memory management unit the memory management unit (mmu) supports address translation and protection functions for embedded applications. when used with appropriate system level software, the mmu provides the following functions: translation of 4gb logical address space into physical addresses, independent enabling of instruction and data translation/protection, page level cacheability and access control via the translation mechanism, software control of page replacement strategy, and additional control over protection via zones. the fully associative 64-entry tlb array handles both instruction and data accesses. the translation for any virtual address can be placed in any one of the 64 entries, allowing maximum flexibility by tlb management software. each tlb entry contains a translation for a page that can be any one of eight sizes from 1kb to 16mb, incrementing by powers of 4. the tlb can simultaneously contain any mix of page sizes. this feature enables the use of small pages when maximum granularity is required, reducing the amount of wasted memory when compared to the more common fixed 4kb page size. table 1. 403gc instructions by category category base instructions data movement load, store arithmetic / logical add, subtract, negate, multiply, divide, and, or, xor, nand, nor, xnor, sign extension, count leading zeros comparison compare, compare logical, compare immediate branch branch, branch conditional condition condition register logical rotate/shift rotate, rotate and mask, shift left, shift right cache control invalidate, touch, zero, flush, store interrupt control write to external interrupt enable bit, move to/from machine state register, return from interrupt, return from critical interrupt processor management system call, synchronize, move to/from device control registers, move to/ from special purpose registers
ibm powerpc 403gc 4 instruction cache unit the instruction cache unit (icu) is a two-way set- associative 2kb cache memory unit with enhancements to support branch prediction and folding. the icu is organized as 64 sets of 2 lines, each line containing 16 bytes. a separate bypass path is available to handle cache- inhibited instructions and to improve performance during line fill operations. the cache can send two cached instructions per cycle to the execution unit, allowing instructions to be folded out of the queue without interrupting normal instruction flow. when a branch instruction is folded and executed in parallel with another instruction, the icu provides two more instructions to replace both of the instructions just executed so that bandwidth is balanced between the icu and the execution unit. data cache unit the data cache unit is provided to minimize the access time of frequently used data items in main store. the 1kb cache is organized as a two-way set associative cache. there are 32 sets of 2 lines, each line containing 16 bytes of data. the cache features byte-writeability to improve the performance of byte and halfword store operations. cache operations are performed using a write- back strategy. a write-back cache only updates locations in main storage that corresponds to changed locations in the cache. data is flushed from the cache to main storage whenever changed data needs to be removed from the cache to make room for other data. the data cache may be disabled for a 128mb memory region via control bits in the data cache control register or on a per-page basis if the mmu is enabled for data translation. a separate bypass path is available to handle cache- inhibited data operations and to improve performance during line fill operations. cache flushing and filling are triggered by load, store, and cache control instructions executed by the processor. cache blocks are loaded starting at the requested fullword, continuing to the end of the block and then wrapping around to fill the remaining fullwords at the beginning of the block. dma controller the four-channel dma controller manages block data transfers in buffered, fly-by and memory-to- memory transfer modes with options for burst- mode operation. in fly-by and buffered modes, the dma controller supports transactions between memory and peripheral devices. each dma channel provides a control register, a source address register, a destination address register, a transfer count register, and a chained count register. peripheral set-up cycles, wait cycles, and hold cycles can be programmed into each dma channel control register. each channel supports chaining operations. the dma status register holds the status of all four channels. exception handling table 2 summarizes the 403gc exception priorities, types, and classes. exceptions are generated by interrupts from internal and external peripherals, instructions, the internal timer facility, debug events or error conditions. six external interrupt signals are provided on the 403gc: one critical and five general-purpose, all individually maskable. all exceptions fall into three basic classes: asynchronous imprecise exceptions, synchronous precise exceptions, and asynchronous precise exceptions. asynchronous exceptions are caused by events external to processor execution, while synchronous exceptions are caused by instructions. except for a system reset or machine check, all 403gc exceptions are handled precisely. precise handling implies that the address of the excepting instruction (synchronous exceptions other than system call) or the address of the next sequential instruction (asynchronous exceptions and system call) is passed to the exception handling routine. precise handling also implies that all instructions prior to the excepting instruction have completed execution and have written back their results.
ibm powerpc 403gc 5 asynchronous imprecise exceptions include system resets and machine checks. synchronous precise exceptions include most debug exceptions, program exceptions, data storage violations, tlb misses, system calls, and alignment error exceptions. asynchronous precise exceptions include the critical interrupt exception, external interrupts, and internal timer facility exceptions and some debug events. only one exception is handled at a time. if multiple exceptions occur simultaneously, they are handled in priority order. the 403gc processes exceptions as reset, critical, or noncritical. four exceptions are defined as critical: machine check exceptions, debug exceptions, exceptions caused by an active level on the critical interrupt pin, and the first time-out from the watchdog timer. when a noncritical exception is taken, special purpose register save/restore 0 (srr0) is loaded with the address of the excepting instruction (synchronous exceptions other than system call) or the next sequential instruction to be processed (asynchronous exceptions and system call). if the 403gc is executing a multicycle instruction (load/store multiple, load/ store string, multiply or divide), the instruction is terminated and its address stored in srr0. save/restore register 1 (srr1) is loaded with the contents of the machine state register. the msr is then updated to reflect the new context of the machine. the new msr contents take effect beginning with the first instruction of the exception handling routine. at the end of the exception handling routine, execution of a return from interrupt (rfi) instruction forces the contents of srr0 and srr1 to be loaded into the program counter and the msr, respectively. execution then begins at the address in the program counter. the four critical exceptions are processed in a similar manner. when a critical exception is taken, srr2 and srr3 hold the next sequential address to be processed when returning from the exception and the contents of the machine state register, respectively. after the critical exception handling routine, return from critical interrupt (rfci) forces the contents of srr2 and srr3 to be loaded into the program counter and the msr, respectively. timers the 403gc contains four timer functions: a time base, a programmable interval timer (pit), a fixed interval timer (fit), and a watchdog timer. the time base is a 64-bit counter incremented at the timer clock rate. the timer clock may be driven by either an internal signal equal to the processor clock rate or by a separate external timer clock pin. no interrupts are generated when the time base rolls over. table 2. 403gc exception priorities, types and classes priority exception type exception class 1 system reset asynchronous imprecise 2 machine check asynchronous imprecise 3debug synchronous precise (except ude and exc) 4 critical interrupt asynchronous precise 5 watchdogtimer time-out asynchronous precise 6 program exception, data storage exception,tlb miss, and system calls synchronous precise 7 alignment exceptions synchronous precise 8 external interrupts asynchronous precise 9 fixed interval timer asynchronous precise 10 programmable interval timer asynchronous precise
ibm powerpc 403gc 6 the programmable interval timer is a 32-bit register that is decremented at the same rate as the time base is incremented. the user preloads the pit register with a value to create the desired delay. when the register is decremented to zeros, the timer stops decrementing, a bit is set in the timer status register (tsr), and a pit interrupt is generated. optionally, the pit can be programmed to reload automatically the last value written to the pit register, after which the pit begins decrementing again.the timer control register (tcr) contains the interrupt enable for the pit interrupt. the fixed interval timer generates periodic interrupts based on selected bits in the time base. users may select one of four intervals for the timer period by setting the correct bits in the tcr. when the selected bit in the time base changes from 0 to 1, a bit is set in the tsr and a fit interrupt is generated. the fit interrupt enable is contained in the tcr. the watchdog timer generates a periodic interrupt based on selected bits in the time base. users may select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an intervening clear from software. if enabled, the watchdog timer generates a system reset unless an exception handler updates the watchdog timer status bit before the timer has completed two of the selected timer intervals. serial port the 403gc serial port is capable of supporting rs232 standard serial communication, as well as high-speed execution (bit speed at a maximum of one-sixteenth of the sysclk processor clock rate). the serial clock which drives the serial port can come from the internal sysclk or an external clock source at the external serial clock pin (maximum of one-half the sysclk rate). the 403gc serial port contains many features found only on advanced communications controllers, including the capability of being a peripheral for dma transfers. an internal loopback mode supports diagnostic testing without requiring external hardware. an auto echo mode is included to retransmit received bits to the external device. auto-resynchronization after a line break and false start bit detection are also provided, as well as operating modes that allow the serial port to react to handshaking line inputs or control handshaking line outputs without software interaction. program generation mode allows the serial port transmitter to be used for pulse width modulation with duty cycle variation controlled by frame size, baud rate, and data pattern. jtag port the jtag port has been enhanced to allow it to be used as a debug port. through the jtag test access port, debug software on a workstation or pc can single-step the processor and interrogate internal processor state to facilitate software debugging. the standard jtag boundary-scan register allows testing of circuitry external to the chip, primarily the board interconnect. alternatively, the jtag bypass register can be selected when no other test data register needs to be accessed during a board-level test operation. real-time debug port the real-time debug port supports tracing the instruction stream being executed out of the instruction cache in real time. the trace status signals provide trace information while in real- time trace debug mode. this mode does not alter the performance of the processor. p/n code notes: 1. the dash number indicates the speed version. 2. the characters in the dash number indicate reliability grade, package type (j or b), revision level (a), and commercial version (c), and the ratio of internal cpu core clock rate to external bus speed. 3. pqfp and pbga versions are both reliability grade 3, but only the pbga part numbers specify the grade. table 3. ppc403gc part numbers mhz part number package 25 ppc403gc-ja25c1 403gc-3ba25c1 pqfp pbga 33 PPC403GC-JA33C1 403gc-3ba33c1 pqfp pbga 40 ppc403gc-ja40c1 403gc-3ba40c1 pqfp pbga
ibm powerpc 403gc 7 logic symbol signals in brackets are multiplexed. sysclk serclk dsr [cts ] recvd xmitd dtr [rts ] holdreq holdack busreq/ int0 int4 error bootw cint buserror reset ready dmar0 dmar3 [xreq ] dmaa0 dmaa3 [xack ] eot0 [tc0 ] eot3 [tc3 ][xsize0] r/w cs0 cs3 cs4 [ras3 ] cs7 [ras0 ] cas0 cas3 amuxcas tck tms tdi tdo dramoe dramwe d0 d31 a6 a29 halt ? ? ? ? ? ? ts0 ts2 ? ? ? ? ? ? ? ts1 address bus data bus ? ? serial port external master interrupts trace jtag dram controls sram/dram controls sram controls ? ? ? ? ? ? ? ? ? dma controls ? ? ? timerclk status [dmadxfer ] testc/ [holdpri] ppc403gc risc controller wbe0 [a4][be0 ] wbe1 [a5][be1 ] wbe2 [a30][be2 ] wbe3 [a31][be3 ] oe [xsize1] ts3 ts4 ts5 ts6
ibm powerpc 403gc 8 pin functional descriptions active-low signals are shown with overbars: dmar0 . multiplexed signals are alphabetized under the first (unmultiplexed) signal names on the same pins. the logic symbol on the preceding page shows all 403gc signals arranged by functional groups. table 4. 403gc signal descriptions signal name pin ball i/o type function a6 92 k12 i/o address bus bit 6. when the 403gc is bus master, this is an address output from the 403gc. when the 403gc is not bus mas- ter, this is an address input from the external bus master, to deter- mine bank register usage. a7 93 k11 i/o address bus bit 7. see description of a6. a8 94 j13 i/o address bus bit 8. see description of a6. a9 95 j14 i/o address bus bit 9. see description of a6. a10 96 j12 i/o address bus bit 10. see description of a6. a11 97 j11 i/o address bus bit 11. see description of a6. a12 98 h13 o address bus bit 12. when the 403gc is bus master, this is an address output from the 403gc. a13 99 h14 o address bus bit 13. see description of a12. a14 103 g14 o address bus bit 14. see description of a12. a15 104 g13 o address bus bit 15. see description of a12. a16 105 g11 o address bus bit 16. see description of a12. a17 106 f14 o address bus bit 17. see description of a12. a18 107 f12 o address bus bit 18. see description of a12. a19 108 f13 o address bus bit 19. see description of a12. a20 109 f11 o address bus bit 20. see description of a12. a21 110 e14 o address bus bit 21. see description of a12. a22 112 e13 i/o address bus bit 22. when the 403gc is bus master, this is an address output from the 403gc. when the 403gc is not bus mas- ter, this is an address input from the external bus master, to deter- mine page crossings. a23 113 e11 i/o address bus bit 23. see description of a22. a24 114 d14 i/o address bus bit 24. see description of a22. a25 115 d12 i/o address bus bit 25. see description of a22. a26 116 d13 i/o address bus bit 26. see description of a22. a27 117 c14 i/o address bus bit 27. see description of a22. a28 118 c12 i/o address bus bit 28. see description of a22.
ibm powerpc 403gc 9 a29 119 c13 i/o address bus bit 29. see description of a22. amuxcas 139 a8 o dram external address multiplexer select. amuxcas controls the select logic on an external multiplexer. if amuxcas is low, the multi- plexer should select the row address for the dram and when amux- cas is 1, the multiplexer should select the column address. bootw 11 e1 i boot-up rom width select. bootw is sampled while the reset pin is active and again after reset becomes inactive to determine the width of the boot-up rom. if this pin is tied to logic 0 when sampled on reset, an 8-bit boot width is assumed. if bootw is tied to 1, a 32- bit boot width is assumed. for 16-bit boot widths, this pin should be tied to the reset pin. buserror 12 e3 i bus error input. a logic 0 input to the buserror pin by an external device signals to the 403gc that an error occurred on the bus trans- action. buserror is only sampled during the data transfer cycle or the last wait cycle of the transfer. busreq/ dmadxfer 135 a9 o bus request. while holdack is active, busreq is active when the 403gc has a bus operation pending and needs to regain control of the bus. dma data transfer. when holdack is not active, dmadxfer indi- cates a valid data transfer cycle. for dma use, dmadxfer controls burst-mode fly-by dma transfers between memory and peripherals. dmadxfer is not meaningful unless a dma acknowledge signal (dmaa0:3 ) is active. for transfer rates slower than one transfer per cycle, dmadxfer is active for one cycle when one transfer is com- plete and the next one starts. for transfer rates of one transfer per cycle, dmadxfer remains active throughout the transfer. cas0 142 c8 o dram column address select 0. cas0 is used with byte 0 of all dram banks. cas1 143 a7 o dram column address select 1. cas1 is used with byte 1 of all dram banks. cas2 144 b7 o dram column address select 2. cas2 is used with byte 2 of all dram banks. cas3 145 d7 o dram column address select 3. cas3 is used with byte 3 of all dram banks. cint 36 l2 i critical interrupt. to initiate a critical interrupt, the user must main- tain a logic 0 on the cint pin for a minimum of one sysclk clock cycle followed by a logic 1 on the cint pin for at least one sysclk cycle. cs0 155 c4 o sram chip select 0. bank register 0 controls an sram bank, cs0 is the chip select for that bank. cs1 154 a4 o sram chip select 1. see description of cs0 but controls bank 1. table 4. 403gc signal descriptions signal name pin ball i/o type function
ibm powerpc 403gc 10 cs2 153 d5 o sram chip select 2. see description of cs0 but controls bank 2. cs3 152 b5 o sram chip select 3. see description of cs0 but controls bank 3. cs4 /ras3 151 c5 o chip select 4/ dram row address select 3. when bank register 4 is configured to control an sram bank, cs4 /ras3 functions as a chip select. when bank register 4 is configured to control a dram bank, cs4 /ras3 is the row address select for that bank. cs5 /ras2 148 b6 o chip select 5/ dram row address select 2. see description of cs4 /ras3 but controls bank 5. cs6 /ras1 147 c6 o chip select 6/ dram row address select 1. see description of cs4 /ras3 but controls bank 6. cs7 /ras0 146 a6 o chip select 7/ dram row address select 0. see description of cs4 /ras3 but controls bank 7. d0 42 n2 i/o data bus bit 0 (most significant bit). d1 43 p2 i/o data bus bit 1. d2 44 n3 i/o data bus bit 2. d3 45 p3 i/o data bus bit 3. d4 46 n4 i/o data bus bit 4. d5 47 m4 i/o data bus bit 5. d6 48 p4 i/o data bus bit 6. d7 51 p5 i/o data bus bit 7. d8 52 m5 i/o data bus bit 8. d9 53 l5 i/o data bus bit 9. d10 54 n6 i/o data bus bit 10. d11 55 p6 i/o data bus bit 11. d12 56 m6 i/o data bus bit 12. d13 57 l6 i/o data bus bit 13. d14 58 n7 i/o data bus bit 14. d15 62 m7 i/o data bus bit 15. d16 63 p8 i/o data bus bit 16. d17 64 n8 i/o data bus bit 17. d18 65 l8 i/o data bus bit 18. d19 66 p9 i/o data bus bit 19. d20 67 m9 i/o data bus bit 20. d21 68 n9 i/o data bus bit 21. table 4. 403gc signal descriptions signal name pin ball i/o type function
ibm powerpc 403gc 11 d22 71 m10 i/o data bus bit 22. d23 72 n10 i/o data bus bit 23. d24 73 l10 i/o data bus bit 24. d25 74 p11 i/o data bus bit 25. d26 75 m11 i/o data bus bit 26. d27 76 n11 i/o data bus bit 27. d28 77 p12 i/o data bus bit 28. d29 78 m12 i/o data bus bit 29. d30 79 n12 i/o data bus bit 30. d31 82 n13 i/o data bus bit 31. dmaa0 156 b4 o dma channel 0 acknowledge. dmaa0 has an active level when a transaction is taking place between the 403gc and a peripheral. dmaa1 157 a3 o dma channel 1 acknowledge. see description of dmaa0 . dmaa2 158 c3 o dma channel 2 acknowledge. see description of dmaa0 . dmaa3 / xack 159 b3 o dma channel 3 acknowledge / external master transfer acknowl- edge. when the 403gc is bus master, this signal is dmaa3; see description of dmaa0. when the 403gc is not the bus master, this signal is xack , an output from the 403gc which has an active level when data is valid during an external bus master transaction. dmar0 2 b2 i dma channel 0 request. external devices request a dma transfer on channel 0 by putting a logic 0 on dmar0 . dmar1 3 b1 i dma channel 1 request. see description of dmar0 . dmar2 4 c2 i dma channel 2 request. see description of dmar0 . dmar3 / xreq 5 c1 i dma channel 3 request. when the 403gc is the bus master, exter- nal devices request a dma transfer on channel 3 by putting a logic 0 on dmar3 . see description of dmar0 . when the 403gc is not the bus master, dmar3 is used as the xreq input. the external bus master places a logic 0 on xreq to initiate a transfer to the dram controlled by the 403gc dram con- troller. dramoe 137 d9 o dram output enable. dramoe has an active level when either the 403gc or an external bus master is reading from a dram bank. this signal enables the selected dram bank to drive the data bus. dramwe 138 b8 o dram write enable. dramwe has an active level when either the 403gc or an external bus master is writing to a dram bank. table 4. 403gc signal descriptions signal name pin ball i/o type function
ibm powerpc 403gc 12 dsr /cts 28 j2 i data set ready / clear to send. the function of this pin as either dsr or cts is selectable via the serial port configuration bit in the iocr. dtr /rts 88 l14 o data terminal ready / request to send. the function of this pin as either dtr or rts is selectable via the serial port configuration bit in the iocr. eot0 /tc0 128 a11 i/o end of transfer 0 / terminal count 0. the function of the eot0 /tc0 is controlled via the eot /tc bit in the dma channel 0 control reg- ister. when eot0 /tc0 is configured as an end of transfer pin, external users may stop a dma transfer by placing a logic 0 on this input pin. when configured as a terminal count pin, the 403gc sig- nals the completion of a dma transfer by placing a logic 0 on this pin. eot1 /tc1 131 a10 i/o end of transfer 1 / terminal count 1. see description of eot0 /tc0 . eot2 /tc2 132 c10 i/o end of transfer 2 / terminal count 2. see description of eot0 /tc0 . eot3 /tc3 / xsize0 133 d10 i/o end of transfer 3 / terminal count 3 / external master transfer size 0. when the 403gc is bus master, this pin has the same function as eot0 /tc0 . when the 403gc is not bus master, eot3 /tc3 /xsize0 is used as one of two external transfer size input bits, xsize0:1. error 136 c9 o system error. error goes to a logic 1 whenever a machine check error is detected in the 403gc. the error pin then remains a logic 1 until the machine check error is cleared in the exception syndrome register and/or bus error syndrome register. gnd 1 g7 ground. all ground pins must be used. 10 e2 ground. all ground pins must be used. 15 f1 ground. all ground pins must be used. 29 j4 ground. all ground pins must be used. 30 k1 ground. all ground pins must be used. 41 h7 ground. all ground pins must be used. 50 n5 ground. all ground pins must be used. 59 p7 ground. all ground pins must be used. 60 l7 ground. all ground pins must be used. 70 p10 ground. all ground pins must be used. 81 h8 ground. all ground pins must be used. table 4. 403gc signal descriptions signal name pin ball i/o type function
ibm powerpc 403gc 13 gnd 90 k13 ground. all ground pins must be used. 101 g12 ground. all ground pins must be used. 102 h12 ground. all ground pins must be used. 111 e12 ground. all ground pins must be used. 121 g8 ground. all ground pins must be used. 130 b10 ground. all ground pins must be used. 141 c7 ground. all ground pins must be used. 150 a5 ground. all ground pins must be used. halt 9 d4 i halt from external debugger, active low. holdack 134 b9 o hold acknowledge. holdack outputs a logic 1 when the 403gc relinquishes its external buses to an external bus master. holdack outputs a logic 0 when the 403gc regains control of the bus. holdreq 14 f2 i hold request. external bus masters can request the 403gc bus by placing a logic1 on this pin. the external bus master relinquishes the bus to the 403gc by deasserting holdreq. int0 31 k3 i interrupt 0. int0 is an interrupt input to the 403gc and users may program the pin to be either edge-triggered or level-triggered and may also program the polarity to be active high or active low. the iocr contains the bits necessary to program the trigger type and polarity. int1 32 k2 i interrupt 1. see description of int0. int2 33 k4 i interrupt 2. see description of int0. int3 34 l1 i interrupt 3. see description of int0. int4 35 l3 i interrupt 4. see description of int0. ivr 39 interface voltage reference. when connected to 3.3v supply, allows the device to interface to an exclusively 3v system. when connected to 5v supply, allows the device to interface to 5v or mixed 3v/5v system. if any input or output connects to 5v system, this pin must be connected to 5v supply. oe /xsize1 126 b11 o/i output enable / external master transfer size 1. when the 403gc is bus master, oe enables the selected srams to drive the data bus. the timing parameters of oe relative to the chip select, cs , are programmable via bits in the 403gc bank registers. when the 403gc is not bus master, oe /xsize1 is used as one of two external transfer size input bits, xsize0:1. ready 13 e4 i ready. ready is used to insert externally generated (device-paced) wait states into bus transactions. the ready pin is enabled via the ready enable bit in 403gc bank registers. recvd 27 j3 i serial port receive data. table 4. 403gc signal descriptions signal name pin ball i/o type function
ibm powerpc 403gc 14 reset 91 i/o reset . a logic 0 input placed on this pin for eight sysclk cycles causes the 403gc to begin a system reset. when a system reset is invoked, the reset pin becomes a logic 0 output for eight sysclk cycles. r/w 127 c11 i/o read / write. when the 403gc is bus master, r/w is an output which is high when data is read from memory and low when data is written to memory. when the 403gc is not bus master, r/w is an input from the exter- nal bus master which indicates the direction of data transfer. serclk 26 j1 i serial port clock. through the serial port clock source bit in the input/output configuration register (iocr), users may choose the serial port clock source from either the input on the serclk pin or processor sysclk. the maximum allowable input frequency into ser- clk is half the sysclk frequency. sysclk 22 g3 i sysclk is the processor system clock input. sysclk supports a 50/50 duty cycle clock input at the rated chip frequency. tck 6 d2 i jtag test clock input. tck is the clock source for the 403gc test access port (tap). the maximum clock rate into the tck pin is one half of the processor sysclk clock rate. tdi 8 d1 i test data in. the tdi is used to input serial data into the tap. when the tap enables the use of the tdi pin, the tdi pin is sampled on the rising edge of tck and this data is input to the selected tap shift register. tdo 16 f3 o test data output. tdo is used to transmit data from the 403gc tap. data from the selected tap shift register is shifted out on tdo. testa 23 h1 i reserved for manufacturing test. tied low for normal operation. te s t b 24 h2 i reserved for manufacturing test. tied high for normal operation. testc/hold- pri 37 m1 i testc. reserved for manufacturing test during the reset interval. while reset is active, this signal should be tied low for normal oper- ation. holdreq priority. when reset is not active, this signal is sampled to determine the priority of the external bus master signal holdreq. if holdpri = 0 then the holdreq signal is considered high priority, oth- erwise holdreq is considered low priority. testd 38 m3 i reserved for manufacturing test. tied low for normal operation. timerclk 25 h4 i timer facility clock. through the timer clock source bit in the input/output configuration register (iocr), users may choose the clock source for the timer facility from either the input on the timer- clk pin or processor coreclk. the maximum input frequency into timerclk is half the coreclk frequency. table 4. 403gc signal descriptions signal name pin ball i/o type function
ibm powerpc 403gc 15 tms 7 d3 i test mode select. the tms pin is sampled by the tap on the rising edge of tck. the tap state machine uses the tms pin to deter- mine the mode in which the tap operates. ts0 17 f4 o trace status 0. ts1 18 g2 o trace status 1. ts2 19 g1 o trace status 2. ts3 86 l13 o/i trace status 3. ts4 85 m14 o/i trace status 4. ts5 84 m13 o/i trace status 5. ts6 83 n14 o/i trace status 6. v dd 20 g4 power. all power pins must be connected to 3.3v supply. 21 h3 power. all power pins must be connected to 3.3v supply. 40 n1 power. all power pins must be connected to 3.3v supply. 49 l4 power. all power pins must be connected to 3.3v supply. 61 m8 power. all power pins must be connected to 3.3v supply. 69 l9 power. all power pins must be connected to 3.3v supply. 80 p13 power. all power pins must be connected to 3.3v supply. 89 l11 power. all power pins must be connected to 3.3v supply. 100 h11 power. all power pins must be connected to 3.3v supply. 120 b14 power. all power pins must be connected to 3.3v supply. 129 d11 power. all power pins must be connected to 3.3v supply. 140 d8 power. all power pins must be connected to 3.3v supply. 149 d6 power. all power pins must be connected to 3.3v supply. 160 a2 power. all power pins must be connected to 3.3v supply. table 4. 403gc signal descriptions signal name pin ball i/o type function
ibm powerpc 403gc 16 wbe0 /a4/ be0 122 b13 o/i/o write byte enable 0 / address bus bit 4 / byte enable 0. when the 403gc is bus master, the write byte enable outputs, wbe0:3 , select the active byte(s) in a memory write access to sram. the byte enables can also be programmed as read/write byte enables, depending on the mode set in the iocr. note 3 on page 33 summarizes the functional and timing differences in these signals when programmed as read/write byte enables. for 8-bit memory regions, wbe2 and wbe3 become address bits 30 and 31 and wbe0 is the byte-enable line. for 16-bit memory regions, wbe2 and w be3 become address bits 30 and 31 and wbe0 and wbe1 are the high byte and low byte enables, respec- tively. for 32-bit memory regions, wbe0:3 are byte enables for bytes 0-3 on the data bus, respectively. when the 403gc is not bus master, wbe0:1 are used as the a4:5 inputs (for bank register selection) and wbe2:3 are used as the a30:31 inputs (for byte selection and page crossing detection). wbe1 /a5/ be1 123 a13 o/i/o write byte enable 1 / address bus bit 5 / byte enable 1. see description of wbe0 / a4 above. wbe2 /a30/ be2 124 b12 o/i/o write byte enable 2 / address bus bit 30 / byte enable 2. see description of wbe0 / a4 above. wbe3 /a31/ be3 125 a12 o/i/o write byte enable 3 / address bus bit 31 / byte enable 3. see description of wbe0 / a4 above. xmitd 87 l12 o serial port transmit data. table 4. 403gc signal descriptions signal name pin ball i/o type function
ibm powerpc 403gc 17 table 5. signals ordered by pqfp pin number pin signal name pin signal name pin signal name pin signal name pin signal name 1 gnd 33 int2 65 d18 97 a11 129 v dd 2 dmar0 34 int3 66 d19 98 a12 130 gnd 3 dmar1 35 int4 67 d20 99 a13 131 eot1 /tc1 4 dmar2 36 cint 68 d21 100 v dd 132 eot2 /tc2 5 dmar3 /xreq 37 testc/holdpri 69 v dd 101 gnd 133 eot3 /tc3 /xsize0 6 tck 38 testd 70 gnd 102 gnd 134 holdack 7 tms 39 ivr 71 d22 103 a14 135 busreq/ dmadxfer 8 tdi 40 v dd 72 d23 104 a15 136 error 9halt 41 gnd 73 d24 105 a16 137 dramoe 10 gnd 42 d0 74 d25 106 a17 138 dramwe 11 bootw 43 d1 75 d26 107 a18 139 amuxcas 12 buserror 44 d2 76 d27 108 a19 140 v dd 13 ready 45 d3 77 d28 109 a20 141 gnd 14 holdreq 46 d4 78 d29 110 a21 142 cas0 15 gnd 47 d5 79 d30 111 gnd 143 cas1 16 tdo 48 d6 80 v dd 112 a22 144 cas2 17 ts0 49 v dd 81 gnd 113 a23 145 cas3 18 ts1 50 gnd 82 d31 114 a24 146 cs7 /ras0 19 ts2 51 d7 83 ts6 115 a25 147 cs6 /ras1 20 v dd 52 d8 84 ts5 116 a26 148 cs5 /ras2 21 v dd 53 d9 85 ts4 117 a27 149 v dd 22 sysclk 54 d10 86 ts3 118 a28 150 gnd 23 testa 55 d11 87 xmitd 119 a29 151 cs4 /ras3 24 testb 56 d12 88 dtr /rts 120 v dd 152 cs3 25 timerclk 57 d13 89 v dd 121 gnd 153 cs2 26 serclk 58 d14 90 gnd 122 wbe0 /a4/ be0 154 cs1 27 recvd 59 gnd 91 reset 123 wbe1 /a5/ be1 155 cs0 28 dsr /cts 60 gnd 92 a6 124 wbe2 /a30/ be2 156 dmaa0 29 gnd 61 v dd 93 a7 125 wbe3 /a31/ be3 157 dmaa1 30 gnd 62 d15 94 a8 126 oe /xsize1 158 dmaa2 31 int0 63 d16 95 a9 127 r/w 159 dmaa3 /xack 32 int1 64 d17 96 a10 128 eot0 /tc0 160 v dd
ibm powerpc 403gc 18 pqfp mechanical drawing (top view) index mark 140 41 80 81 120 121 160 0.3 0.1 0.012 0.004 0.65 basic 0.0256 dimensions: mm inches 3.95 max 0.155 see detail note: english dimensions are for reference only. 0.25 min 0.01 0 - 7 0.015 0.05 0.006 0.002 0.8 0.15 0.032 0.006 28 0.2 1.102 0.008 31.2 0.25 1.228 0.01
ibm powerpc 403gc 19 table 6. signals ordered by pbga ball assignment ball signal name ball signal name ball signal name ball signal name ball signal name a2 v dd c7 gnd f3 tdo j13 a8 m9 d20 a3 dmaa1 c8 cas0 f4 ts0 j14 a9 m10 d22 a4 cs1 c9 error f11 a20 k1 gnd m11 d26 a5 gnd c10 eot2 /tc2 f12 a18 k2 int1 m12 d29 a6 cs7 /ras0 c11 r/w f13 a19 k3 int0 m13 ts5 a7 cas1 c12 a28 f14 a17 k4 int2 m14 ts4 a8 amuxcas c13 a29 g1 ts2 k11 a7 n1 v dd a9 busreq/ dmadxfer c14 a27 g2 ts1 k12 a6 n2 d0 a10 eot1 /tc1 d1 tdi g3 sysclk k13 gnd n3 d2 a11 eot0 /tc0 d2 tck g4 v dd k14 reset n4 d4 a12 wbe3 /a31/ be3 d3 tms g7 gnd l1 int3 n5 gnd a13 wbe1 /a5/ be1 d4 halt g8 gnd l2 cint n6 d10 b1 dmar1 d5 cs2 g11 a16 l3 int4 n7 d14 b2 dmar0 d6 v dd g12 gnd l4 v dd n8 d17 b3 dmaa3 /xack d7 cas3 g13 a15 l5 d9 n9 d21 b4 dmaa0 d8 v dd g14 a14 l6 d13 n10 d23 b5 cs3 d9 dramoe h1 testa l7 gnd n11 d27 b6 cs5 /ras2 d10 eot3 /tc3 / xsize0 h2 testb l8 d18 n12 d30 b7 cas2 d11 v dd h3 v dd l9 v dd n13 d31 b8 dramwe d12 a25 h4 timerclk l10 d24 n14 ts6 b9 holdack d13 a26 h7 gnd l11 v dd p2 d1 b10 gnd d14 a24 h8 gnd l12 xmitd p3 d3 b11 oe /xsize1 e1 bootw h11 v dd l13 ts3 p4 d6 b12 wbe2 /a30/ be2 e2 gnd h12 gnd l14 dtr /rts p5 d7 b13 wbe0 /a4/ be0 e3 buserror h13 a12 m1 testc/holdpri p6 d11 b14 v dd e4 ready h14 a13 m2 ivr p7 gnd c1 dmar3 /xreq e11 a23 j1 serclk m3 testd p8 d16 c2 dmar2 e12 gnd j2 dsr /cts m4 d5 p9 d19 c3 dmaa2 e13 a22 j3 recvd m5 d8 p10 gnd c4 cs0 e14 a21 j4 gnd m6 d12 p11 d25 c5 cs4 /ras3 f1 gnd j11 a11 m7 d15 p12 d28 c6 cs6 /ras1 f2 holdreq j12 a10 m8 v dd p13 v dd
ibm powerpc 403gc 20 pbga mechanical drawing (top view) 1 a s 1.0 typ 0.50 0.10 solderball x 160 14 p 15.0 13.0 15.0 b a c 0.20 ? 0.30 ? 0.10 s c a b s s 13.5 ref gold gate release corresponds to a1 ball location corner shape is chamferred or rounded 0.20 c c 0.35 c 0.25 c 1.8 max 0.40 0.10 pcb substrate mold compound dimensions: mm index mark
ibm powerpc 403gc 21 package thermal specifications the 403gc is designed to operate within the case temperature range from -40c to 120c. thermal resistance values are shown in table 7: notes: 1. case temperature tm c is measured at top center of case surface with device soldered to circuit board. 2. tm a = tm c C p q ca , where tm a is ambient temperature. 3. tm cmax = tm jmax C p q jc , where tm jmax is maximum junction temperature and p is power consumption. 4. the above assumes that the chip is mounted on a card with at least one signal and two power planes. electrical specifications absolute maximum ratings the absolute maximum ratings in table 8 below are stress ratings only. operation at or beyond these maximum ratings may cause permanent damage to the device. operating conditions the 403gc can interface to either 3v or 5v technologies. the range for supply voltages is specified for five-percent margins relative to a nominal 3.3v power supply. device operation beyond the conditions specified in table 9 is not recommended. extended operation beyond the recommended conditions may affect device reliability: note: 1. these frequencies do not account for t cs . see table 12. power considerations power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. typical power dissipation is 0.2 w at 25 mhz, 0.26 w at 33 mhz, or 0.32 w at 40 mhz, tm c = 55 c, and v cc = 3.3 v, with an average 10pf capacitive load. estimated supply current as a function of frequency is shown in the figure, "supply current vs operating frequency," on page 30. derating curves are provided in the section, "output derating for capacitance and voltage," on page 28. recommended connections power and ground pins should all be connected to separate power and ground planes in the circuit board to which the 403gc is mounted. unused input pins must be tied inactive, either high or low. the interface voltage reference (ivr) pin should be connected to 3.3v supply if all signal pins connecting to the 403gc pins operate at 3v levels. if any signal pin connecting to the 403gc operates with 5v levels, the ivr pin should be connected to 5v supply. table 7. thermal resistance (c/watt) parameter airflow-ft/min (m/sec) 0 (0) 100 (0.51) 200 (1.02) q jc junction to case 222 q ca case to ambient pqfp (no heatsink) pbga (no heatsink) 37.2 30 31.6 29.8 table 8. 403gc maximum ratings parameter maximum rating supply voltage with respect to gnd -0.5v to +3.8v voltage on other pins with respect to gnd -0.5v to +5.5v case temperature under bias -40c to +120c storage temperature -65c to +150c table 9. operating conditions symbol parameter min max unit v dd supply voltage: ppc403gc-ja25/33/40 403gc-3ba25/33/40 3.14 3.14 3.47 3.47 v f c clock frequency 1 : ppc403gc-ja25/3ba25 ppc403gc-ja33/3ba33 ppc403gc-ja40/3ba40 0 0 0 25 33 40 mhz tm c case temperature under bias: ppc403gc-ja25/33/40 403gc-3ba25/33/40 -40 -40 85 85 c
ibm powerpc 403gc 22 dc specifications notes: 1. v ivr is the interface voltage reference to which the ivr pin is tied to select either a 3.3v or 5v interface. for additional information, see "recommended connections," on page 21. 2. the 403gc drives its outputs to the level of v dd and, when not driving, the 403gc outputs can be pulled up to 5v by other devices in a system if the 403gc ivr pin has been tied to 5v properly. 3. i cc max is measured at tm c = 85 c , worst-case recommended operating conditions for frequency and voltage as specified in table 9 on page 21, and a capacitive load of 50 pf. note: 1. c out is specified as the load capacitance of a floating output in high impedance. ac specifications clock timing and switching characteristics are specified in accordance with recommended operating conditions in table 9. ac specifications are characterized at v dd = 3.14v and t j = 85c with the 50pf test load shown in the figure at right. derating of outputs for capacitive loading is shown in the figure "output derating for capacitance and voltage," on page 28. table 10. 403gc dc characteristics symbol parameter min max units v il input low voltage (except for sysclk) gnd - 0.1 0.8 v v ilc input low voltage for sysclk gnd - 0.1 0.8 v v ih input high voltage (except for sysclk) 1 2.0 v ivr + 0.1 v v ihc input high voltage for sysclk 1 2.0 v ivr + 0.1 v v ol output low voltage 0.4 v v oh output high voltage 2.4 v dd v i oh output high current 2 ma i ol output low current 4 ma i li input leakage current 50 m a i lo output leakage current 10 m a i cc supply current (i cc max at f c of 25 mhz) 2 200 ma supply current (i cc max at f c of 33 mhz) 2 260 ma supply current (i cc max at f c of 40 mhz) 2, 3 315 ma table 11. 403gc i/o capacitance symbol parameter min max units c in input capacitance (except for sysclk) 5 pf c inc input capacitance for sysclk 25 pf c out output capacitance 1 7pf c i/o i/o pin capacitance 8 pf output pin c l c l = 50 pf for all signals
ibm powerpc 403gc 23 sysclk timing notes: 1. these values do not include the allowable tolerance for clock edge instability represented by t cs . 2. cycle-to-cycle jitter allowed between any two edges. 3. rise and fall times measured between 0.8v and 2.0v. timer clock and serial port timing characteristics notes: 1. maximum input frequency of timerclk and serclk must be less than or equal to half of sysclk input frequency. 2. timerclk and serclk input high times must be greater than or equal to sysclk period t c . 3. timerclk and serclk input low times must also be greater than or equal to sysclk period t c . table 12. 403gc system clock timing symbol parameter 25 mhz 33 mhz 40 mhz units min max min max min max f c sysclk clock input frequency 1 25 33 40 mhz t c sysclk clock period 1 40 30 25 ns t cs clock edge stability 2 0.2 0.2 0.2 ns t ch clock input high time 16 13 11 ns t cl clock input low time 16 13 11 ns t cr clock input rise time 3 0.5 2.5 0.5 2.5 0.5 1.5 ns t cf clock input fall time 3 0.5 2.5 0.5 2.5 0.5 1.5 ns table 13. 403gc timer clock and serial clock timings symbol parameter min max units f sc timerclk, serclk input frequency 0.5 f c mhz t sc timerclk, serclk period 2t c ns t sch timerclk, serclk input high time 1/f c ns t scl timerclk, serclk input low time 1/f c ns t cr t cf t cl t ch t c 2.0v 1.5v 0.8v
ibm powerpc 403gc 24 note: 1. output times are measured with a standard 50 pf capacitive load, unless otherwise noted. input setup and hold waveform notes: 1. the 403gc may be programmed to latch data from the data bus either on the rise of sysclk or the rise of cas . when the 403gc is programmed to latch data on cas , bit 26 of the i/o control register (iocr) is set to 1. 2. t cas2clk 3 15.5 ns. the capacitive load on the cas outputs must not delay the cas low-to-high transition such that the period from the cas rising edge to the next sysclk rising edge becomes less than 15.5 ns. the maximum value of cas capacitive loading can be determined by using the output time for cas from table 17 on page 27, and applying the appropriate derating factor for your application. see the figure, "output derating for capacitance and voltage," on page 28. table 14. 403gc serial port output timings symbol parameter 25 mhz 33 mhz 40 mhz units t ohmin t ovmax t ohmin t ovmax t ohmin t ovmax t oh , t ov output hold, output valid time t oh1 , t ov1 dtr/rts t oh2 , t ov2 xmitd 14 12 13 11 12 10 ns
ibm powerpc 403gc 25 note: 1. data bus setup and hold times for dram cas mode are measured relative to cas deactivation. table 15. 403gc synchronous input timings symbol parameter 25 mhz 33 mhz 40 mhz units min max min max min max t is input setup: t is1 t is2 t is3 t iscas t is4 t is5 t is6 t is7 t is8 t is9 a4:11,a22:31 buserror d0:31 (to sysclk) d0:31 (to cas ) holdpri holdreq r/w ready xreq xsize0:1 4 5 5 2 3 4 3 6 5 5 3 5 4 2 3 3 3 5 4 4 3 5 4 2 3 3 3 5 4 4 ns t ih input hold: t ih1 t ih2 t ih3 t ihcas t ih4 t ih5 t ih6 t ih7 t ih8 t ih9 a4:11,a22:31 buserror d0:31 (after sysclk) d0:31 (after cas ) holdpri holdreq r/w ready xreq xsize0:1 2 2 2 3 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 ns t r ,t f rise/fall time 0.5 2.5 0.5 2.5 0.5 2.5 ns table 16. 403gc asynchronous input timings symbol parameter 25 mhz 33 mhz 40 mhz units min max min max min max t is input setup time t is10 t is11 t is12 t is13 t is14 t is15 cint dmar0:3 eot0:3 halt int0:4 reset 5 3 3 3 6 8 3 3 3 3 5 8 3 3 3 3 5 8 ns
ibm powerpc 403gc 26 notes: 1. during a system-initiated reset, reset must be taken low for a minimum of 2048 sysclk cycles. 2. the bootw input has a maximum rise time requirement of 10 ns when it is tied to reset . 3. input hold times are measured at 3.47v and t j = 0 c. output delay and float timing waveform t ih input hold time t ih10 t ih11 t ih12 t ih13 t ih14 t ih15 cint dmar0:3 eot0:3 halt int0:4 reset t c t c t c t c t c note 1, 2 t c t c t c t c t c note 1, 2 t c t c t c t c t c note 1, 2 ns table 16. 403gc asynchronous input timings symbol parameter 25 mhz 33 mhz 40 mhz units min max min max min max valid t ov t oh 1.5v 1.5v 1.5v min outputs sysclk outputs t of min max max 1.5v 1.5v 1.5v
ibm powerpc 403gc 27 notes: 1. for normal ras and cas timing, t oh is relative to the rising edge of sysclk and t ov is relative to the falling edge of sysclk. in early ras mode, t ov is relative to the rising edge of sysclk. cas access time assumes a sysclk 50% duty cycle. 2. in early ras mode, the ras output delay varies with the 403gc operating frequency. use the following equation to determine the worst-case output delay for this signal: t ov max = 12 ns + tc/4; t oh min remains unchanged. valid for t c greater than 30 ns and less than 80 ns. 3. when initiating a system reset, the 403gc pulls the reset output low for 2048 cycles minimum and then samples to determine whether reset is held low externally. thirty-two cycles after reset has been sampled as low, the 403gcbegins its internal reset. 4. output times are measured with a standard 50 pf capacitive load, unless otherwise noted. output hold times are measured at 3.47v and t j = 10 c. 5. all output hold and float times are guaranteed by design and not tested. table 17. 403gc synchronous output timings symbol parameter 25 mhz 33 mhz 40 mhz units t ohmin t ovmax t ohmin t ovmax t ohmin t ovmax t oh , t ov output hold, output valid time t oh1 , t ov1 a6:31 t oh2 , t ov2 amuxcas t oh3 , t ov3 busreq t oh4 , t ov4 cas0:3 t oh5 , t ov5 cs0:7 t oh6 , t ov6 d0:31 t oh7 , t ov7 dmaa0:3 t oh8 , t ov8 dmadxfer t oh9 , t ov9 dramoe t oh10 , t ov10 dramwe t oh11 , t ov11 error t oh12 , t ov12 holdack t oh13 , t ov13 oe t oh14 , t ov14 ras0:3 t oh15 , t ov15 ras0:3 (early) t oh16 , t ov16 reset t oh17 , t ov17 r/w t oh18 , t ov18 tc0:3 t oh19 , t ov19 ts0:6 t oh20 , t ov20 wbe0:3 (be0:3) t oh21 , t ov21 xack 4 3 3 4 2 4 3 3 3 2 4 3 3 3 12 3 3 3 4 3 3 15 11 12 13 13 16 11 13 11 10 14 12 11 12 22 14 11 13 30 12 13 4 3 3 4 2 4 3 3 3 3 4 3 3 3 11 3 3 3 4 3 3 13 11 11 12 11 15 10 11 11 10 12 11 10 11 20 12 10 12 25 11 12 4 3 3 4 2 4 3 3 3 3 4 3 3 3 11 3 3 3 4 3 3 11 10 10 11 10 14 9 10 10 9 12 10 9 10 18 12 9 11 22 10 11 ns t of output float time t of1 a6:31 t of2 cs0:7 t of3 d0:31 t of4 oe t of5 reset t of6 r/w t of7 tc0:3 t of8 wbe0:3 (be0:3) min 2 3 3 3 2 3 3 3 max 10 12 11 12 8 12 12 12 min 2 3 3 3 2 3 3 3 max 9 10 9 10 7 10 10 10 min 2 3 3 3 2 3 3 3 max 9 10 9 10 7 10 10 10 ns t cas available cas access time min max min max min max ns 2-1-1-1 access mode (note ) 3-2-2-2 access mode (note ) 0.5t c -2.5 1.5t c -2.5 0.5t c - 2.5 1.5t c -2.5 0.5t c - 2.5 1.5t c -2.5
ibm powerpc 403gc 28 output derating for capacitance and voltage output propagation delay derating vs output voltage level note: test conditions v t = 1.5v at t j = 85c 0 50 100 150 0 -10 +10 +20 d output delay (ns) c l (pf) tp zl d c = 0.14 c l - 1.2ns tp lh d c = 0.04 c l - 1.9ns tp hl d c = 0.06 c l - 2.3ns output propagation delay derating derating equations for output delays: 1. d tp lh (c l , v) = tp lh d c + tp lh d v 2. d tp hl (c l , v) = tp hl d c + tp hl d v 3 . d tp zl5v (c l , v) = tp zl d c + tp hl d v (from 5.5v) 1.5 3 0 0 +2 +4 +6 tp lh d v (c l = 25 pf) tp lh d v (c l = 50pf) tp lh d v (c l = 100 pf) v out (v) note: test condition t j = 85c d output delay (ns) tp hl d v (c l = 100 pf) tp hl d v (c l = 50pf) tp hl d v (c l = 25 pf)
ibm powerpc 403gc 29 output rise and fall time derating output voltage vs output current note: test conditions v t = 0.8v to 2v at t j = 85c 0 +6 +2 0 50 100 150 +4 -2 d output transition (ns) c l (pf) tp r d c tp f d c output transition time derating 4. t r (c l ) = 2ns + tp r d c 5. t f (c l ) = 2.5ns + tp f d c derating equations for output rise and fall times: 3.5 3 2.5 2 3 2 1 0 i ol (ma) 0.6 0.3 0 0 1 2 3 4 i oh (ma) v oh min (v) v ol max (v) note: test conditions 3.14v at t j = 85c
ibm powerpc 403gc 30 receiver input voltage vs dc input current note: 1. applies to receivers for asynchronous inputs on pins 2-9, 11,13, 23, 25-28, 31-38, and 91, and synchronous inputs on pins 5, 12, and 14. receiver noise sensitivity supply current vs operating frequency 2.0 2.2 2.4 2.6 0.6 0.4 0.2 0 t j = 25c at 3.47v t j = 85c at 3.14v t j = 25c at 3.47v t j = 85c at 3.14v 100 80 60 40 20 0 v in (v) i in ( m a) noise pulse width (ns) note: test conditions 3.14v at t j = 85c 5 4 3 2 1 1 2 345 0 amplitude (v) positive spike negative spike amplitude 50% pulse width 0.4v amplitude pulse width 50% 2.4v i cc (ma) 0 0 260ma 33 f c (mhz) test conditions: 3.47v at t j = 85c 79ma (worst case) test conditions: (typical) 3.3v at t j = 55c 25 60 ma 200 ma 96 ma 315 ma 40
ibm powerpc 403gc 31 reset and holdack the following table summarizes the states of signals on output pins when reset or holdack is active. note: 1. signal may be active while holdack is asserted, depending on the operation being performed by the 403gc. bus waveforms the waveforms in this section represent external bus operations, including sram and dram accesses, dma transfers, and external master operations. write byte enable encoding the 403gc provides four write byte enable signals (wbe0:3 ) to support 8-, 16-, and 32-bit devices, as shown in table 19. for an eight-bit memory region, wbe2:3 are encoded as a30:31 and wbe0 is the byte-enable line. for a 16-bit region, wbe0 is the high-byte enable, wbe1 is the low-byte enable and wbe2:3 are encoded as a30:31. for a 32-bit region, address bits 6:29 select the word address and wbe0:3 select data bytes 0:3, respectively. table 18. signal states during reset or hold acknowledge signal names state when reset active state when holdack active a6:29 amuxcas busreq cas0:3 floating inactive (low) inactive (low) inactive (high) floating (set to input mode) operable (see note 1) operable (see note 1) operable (see notes 1 and 2) cs0:3 cs4:7 /ras3:0 d0:31 dmaa0:3 floating floating floating inactive (high) floating cs floating, ras operable (notes 1 and 2) floating (external master drives bus) inactive (high) xack dramoe dramwe inactive (high) inactive (high) inactive (high) operable (see note 1) operable (see notes 1 and 2) operable (see notes 1 and 2) error holdack oe reset inactive (low) inactive (low) floating floating unless initiating system reset operable (see note 1) active floating (input for xsize1) floating unless initiating system reset r/w tc0:2 tc3 tdo floating floating (set to input) floating (set to input) floating floating (set to input) inactive (high) floating (input for xsize0) operable (see note 1) ts0:6 wbe0:3 xmitd inactive (low) floating inactive (high) operable (see note 1) operable (inputs for a4:5, a30:31) operable (see note 1)
ibm powerpc 403gc 32 address bus multiplexing to support dram memories with differing configurations and bus widths, the 403gc provides an internally multiplexed address bus controlled by the biu. table 20 shows the multiplexed address outputs referenced by waveforms later in this section. when the 403gc is bus master and there are no bus operations in progress, the states of the address bus outputs are determined by the setting of iocr[atc]. if this bit is set to zero, the address bus will be placed in high impedance. if this bit is set to one, the last address held in the biu address register will be driven out on the address bus until bus operations resume. table 19. write byte enable encoding 8-bit bus width transfer size address wbe0 = we wbe1 = 1 wbe2 = a30 wbe3 = a31 byte 0 0 1 0 0 byte 1 0 1 0 1 byte 2 0 1 1 0 byte 3 0 1 1 1 16-bit bus width transfer size address wbe0 = bhe wbe1 = ble wbe2 = a30 wbe3 =a31 half-word 0 0 0 0 0 half-word 2 0 0 1 0 byte 0 0 1 0 0 byte 1 1 0 0 1 byte 2 0 1 1 0 byte 3 1 0 1 1 32-bit bus width transfer size address wbe0 wbe1 wbe2 wbe3 word 0 0 0 0 0 half-word 0 0 0 1 1 half-word 2 1 1 0 0 byte 0 0 1 1 1 byte 1 1 0 1 1 byte 2 1 1 0 1 byte 3 1 1 1 0 table 20. multiplexed address outputs address pins a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 addr bits out in ras cycle a6 a7 a8 a9 a10 a11 a12 a13 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 addr bits out in cas cycle xx a6 a7 a8 a9 a10 a11 a12 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31
ibm powerpc 403gc 33 sram read-write-read with zero wait and one hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 19 on page 32 for wbe signal definitions based on bus width. 3. wbe signals can be read/write byte enables based on the setting of a control bit in the iocr. when programmed as read/write byte enables, these outputs will indicate valid bytes of the bus for both read and write operations. in addition, the timing of these outputs will match the timing of the address bus, and the wbe on and wbe off parameters will be ignored. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 0 00 0000 0 0 0 0 001 a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx oe wbe0:3 2 d0:31 read address sysclk 1 2 3 4 5 6 7 8 data in data out data in write address read address buserror error? error? error? valid C be wbe0:3 3 valid C be valid C be
ibm powerpc 403gc 34 sram, rom, or i/o write request with wait and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 19 for wbe signal definitions based on bus width. 3. wbe signals can be read/write byte enables based on the setting of a control bit in the iocr. see waveform and note 3 on page 33. 4. 403gcwait must be programmed to a value 3 (cson + weon + weoff) and 3 (cson + oeon + weoff). if wait > (cson + weon) and > (cson + oeon), then all signals retain the values shown in cycle 4 until the wait time expires. 5. if hold is programmed > 001, all signals retain the values shown in cycle 6 until the hold timer expires. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 0 00 0011 0 or 1 0 or 1 0 or 1 0 or 1 001 sysclk a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 5 oe 4,5 wbe0:3 2,3,5 d0:31 address valid data out cson=0 cson=1 cson=0 weon=0 cson=1,0 weon=0,1 cson=1 weon=1 wait + 1 cycle hold weoff=1 weoff=0 1 2 3 4 5 6 7 8 buserror error? cson=0 oeon=0 cson=1,0 oeon=0,1 cson=1 oeon=1
ibm powerpc 403gc 35 sram, rom, or i/o read request, wait extended with ready bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 19 on page 32 for wbe signal definitions based on bus width. 3. wbe signals can be read/write byte enables based on the setting of a control bit in the iocr. see waveform and note 3 on page 33. 4. wait must be programmed to a value 3 (cson + oeon). if wait > (cson + oeon), then all signals will retain the values shown in cycle 4 until the wait timer expires. 5. if hold is programmed > 001, all 403gc output signals retain the values shown in cycle 7 until the hold timer expires. 6. if wait = 00 0000, the ready input is ignored and single-cycle transfers occur. if wait = 00 0001, ready is sampled starting in cycle 2. if wait > 00 0001, ready is sampled starting after the wait cycles have expired. 7. the ready input can be synchronous or asynchronous based on the setting of a control bit in the iocr. when ready is synchronous, data is captured one cycle after ready is sampled active. when ready is asynchronous, data is transferred in the third cycle after ready is sampled active. 8. if the ready input has not been sampled active within 128 cycles from the start of the bus operation, and the device-paced timeout disable in the iocr is not set to one, the operation will terminate and a timeout error will occur. slf burst mode bus width ready enable wait states cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 0 xx 1 00 0010 0 or 1 0 or 1 0 or 1 x 001 a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 5 oe 4,5 wbe0:3 2,3 d0:31 address valid data in cson=0 cson=1 cson=0 oeon=0 cson=0,1 oeon=1,0 cson=1 oeon=1 ready 7 wait not ready not ready sample ready sample data ready hold sysclk 1 2 3 4 5 6 7 8 buserror error?
ibm powerpc 403gc 36 sram, rom or i/o burst read with wait and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 19 on page 32 for wbe signal definitions based on bus width. 3. see waveform and note 3 on page 33. wbe signals can be read/write byte enables based on the setting of a control bit in the iocr. see waveform and note 3 on page 33. 4. wait must be programmed to a value 3 (cson + oeon). if wait > (cson + oeon), then all signals will retain the values shown in cycle 3 until the wait timer expires. 5. if hold is programmed > 001, all 403gc output signals retain the values shown in cycle 7 until the hold timer expires. slf burst mode bus width ready enable wait states burst wait cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:21 bits 22:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 1 xx 0 0001 00 0 or 1 0 or 1 x x 001 valid be be be valid be a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 5 oe 4,5 wbe0:3 2,3 cson=0 cson=1 cson=0 oeon=0 cson=0,1 oeon=1,0 sysclk 1 2 3 4 5 6 7 8 address1 addr2 addr3 address4 d1 d2 d3 d4 wait + 1 cycles 5 hold burst + 1 cycles burst + 1 cycles burst + 1 cycles 6 buserror error? error? error? error? d0:31 be0:3 3 blast 4
ibm powerpc 403gc 37 sram, rom or i/o burst write with wait, burst wait, and hold bank register bit settings notes: 1. wbe2:3 are address bits 30:31 if the bus width is programmed as byte or halfword. 2. see table 19 on page 32 for wbe signal definitions based on bus width. 3. see waveform and note 3 on page 33. wbe signals can be read/write byte enables based on the setting of a control bit in the iocr. see waveform and note 3 on page 33. 4. wait must be programmed to a value 3 (cson + weon + weoff) and 3 (cson + oeon + weoff). if wait > (cson + weon) and > (cson + oeon), then all signals retain the values shown in cycle 3 until the wait timer expires. 5. if hold is programmed > 001, all 403gc output signals retain the values shown in cycle 12 until the hold timer expires. slf burst mode bus width ready enable wait states burst wait cson oeon weon weoff hold bit 13 bit 14 bits 15:16 bit 17 bits 18:21 bits 22:23 bit 24 bit 25 bit 26 bit 27 bits 28:30 0 or 1 1 xx 0 0100 01 0 or 1 0 or 1 0 or 1 0 or 1 001 2 3 4 5 6 7 8 9 10 11 12 13 14 1 a6:29, 1 wbe2 [a30], wbe3 [a31] r/w csx 5 wbe0:3 2,3 sysclk address1 addr2 addr3 address4 data1 data2 data3 data4 wait + 1 cycles hold burst + 1 cycles burst + 1 cycles burst + 1 cycles weon=0,1 weon=0 cson=1,0 cson=0 weon=1 cson=1 weoff=1 weoff=1 weoff=1 weoff=1 weoff=0 cson=1 cson=0 buserror error error error error oeon=0,1 oeon=0 cson=1,0 cson=0 oeon=1 cson=1 ? ? ? ? d0:31 valid be be be valid be be0:3 3 oe 4,5
ibm powerpc 403gc 38 dram 2-1-1-1 page mode read bank register bit settings notes: 1. for burst access, the addresses represented by columns 1 to 4 does not necessarily indicate that they are in incremental address order. typically, burst access is target word first. 2. if internal mux mode is used, address bits a11:29 represent address bits described in table 20 on page 32. 3. during internal mux mode access, a6:10 retain their unmultiplexed values. 4. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 5. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 6. wbe0:1 are always ones during dram transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 1 00 00 0 x xxxx 1 2 3 4 5 6 7 8 sysclk a11:29, r/w ras cas0:3 dramoe dramwe d0:31 amuxcas ras cas cas cas cas pre- charge row column2 column3 column4 column1 data1 data2 data3 data4 wbe2 [a30], wbe3 [a31] buserror error error error error ? ? ??
ibm powerpc 403gc 39 dram 3-2-2-2 page mode write bank register bit settings notes: 1. for burst access, the addresses represented by columns 1 to 4 do not necessarily indicate that they are in incremental address order. typically, burst access is target word first. 2. if internal mux mode is used, address bits a11:29 represent address bits described in table 20 on page 32. 3. during internal mux mode access, a6:10 retain their unmultiplexed values. 4. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 5. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 6. wbe0:1 are always ones during dram transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 1 01 01 0 x xxxx sysclk a11:29 r/w ras cas0:3 dramoe dramwe d0:31 1 2 3 4 5 6 7 8 9 10 11 12 amuxcas row column1 column2 column3 column4 ras cas cas cas cas pre- charge cas cas cas cas data1 data2 data3 data4 buserror error? error? error? error?
ibm powerpc 403gc 40 dram read-write-read, one wait bank register bit settings notes: 1. if internal mux mode is used, address bits a11:29 represent address bits described in table 20 on page 32. 2. during internal mux mode access, a6:10 retain their unmultiplexed values. 3. if external mux mode is used, a11:29 are unaffected and do not change between cas and ras cycles. 4. if bus width is programmed as byte or half-word, wbe2:3 represent address bits a30:31 regardless of mux mode. 5. wbe0:1 are always ones during dram transfers. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 xx x 0 0 0 01 xx 0 x xxxx sysclk a11:29 r/w ras cas0:3 dramoe dramwe d0:31 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 amuxcas data1 data2 data3 ras cas cas pre- charge ras cas cas pre- charge ras cas cas pre- charge row1 column1 row2 column2 row3 column3 buserror error error error ? ??
ibm powerpc 403gc 41 dma buffered single transfer from peripheral to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be sampled inactive at the start of cycle 9 to guarantee a single transfer. 2. peripheral data bus width must match dram bus width. 3. this waveform assumes that the internal address mux is used. 4. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 0 01 xx 0 x xxxx transfer direction transfer width transfer mode peripheralsetup peripheral wait peripheral hold bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 1 10 00 00 00 0000 000 dmar dmaa a11:29 r/w ras cas0:3 dramoe dramwe d0:31 oe wbe0:3 1 2 3 4 5 6 7 8 9 10 11 12 sysclk sync sync biu req dma ack ras cas cas pre- charge row column data data
ibm powerpc 403gc 42 dma fly-by single transfer, write to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be inactive in cycle 7 (last dmaa cycle) to guarantee a single transfer. 2. peripheral data bus width must match dram bus width. 3. see diagram for settings. 4. this waveform assumes that the internal address mux is used. 5. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 0 01 xx 0 x xxxx transfer direction transfer width transfer mode peripheralsetup peripheral wait peripheral hold bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 1 10 01 note 3 xx xxxx xxx 1 sysclk dmar dmaa 2 3 4 5 6 7 8 9 10 11 12 s=0 s=1 s=2 sync sync biu req ras cas cas pre- charge (s = peripheral setup time) a11:29 r/w ras cas0:3 dramoe dramwe d0:31 row column data dmadxfer
ibm powerpc 403gc 43 dma fly-by continuous burst to 3-cycle dram bank register bit settings dma control register bit settings notes: 1. dmar must be inactive at the end of cycle 9 to guarantee three transfers. 2. peripheral data bus width must match dram bus width. 3. see diagram for settings. 4. this waveform assumes that the internal address mux is used. 5. cas0 is used for byte accesses, cas0:1 for halfwords, and cas0:3 for fullwords. 6. numbers ( 1 , 2 , 3 ,...) in the dmar signal represent when dmar is sampled and accepted. numbers ( 1 , 2 , 3 ,...) in the dmaa signal represent the transfers associated with the accepted dmar . slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 0 0 0 1 01 01 0 x xxxx transfer direction transfer width transfer mode peripheral setup peripheral wait peripheral hold burst mode bit 2 bits 4:5 bits 9:10 bits 11:12 bits 13:18 bits 19-21 bit 25 1 10 01 note 3 xx xxxx xxx 1 1 sysclk dmar dmaa a11:29 r/w ras cas0:3 dramoe dramwe d0:31 2 3 4 5 6 7 8 9 10 11 12 s=0 s=1 (s = peripheral setup time) dmadxfer sync sync biu req ras cas cas cas cas cas cas pre- charge row column1 column2 column3 data1 data2 data3 1 2 3 1 1 1 2 2 3 3
ibm powerpc 403gc 44 external master nonburst dram read with holdreq/holdack bank register bit settings notes: 1. xreq , xsize0, xsize1, and xack are multiplexed with dmar3 , eot3 /tc3 , oe , and dmaa3 , respectively. 2. a4, a5, a30, and a31 are multiplexed with wbe0 , wbe1 , wbe2 , and wbe3 , respectively. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 1 0 0 0 01 xx 0 x xxxx sysclk r/w rasx cas0:3 dramoe dramwe d0:31 1 2 3 4 5 6 7 8 9 10 11 12 amuxcas ras cas pre- charge cas holdreq holdack xsize0:1 1 xreq bsel ext bus master dram control 10 valid address - ext master 403 address 403 data hiz hiz 403 master 403 master dram drives bus a4:31 2 xreq 1 xack 1
ibm powerpc 403gc 45 external master dram burst write, 3-2-2-2 page mode bank register bit settings notes: 1. xreq , xsize0, xsize1, and xack are multiplexed with dmar3 , eot3 /tc3 , oe , and dmaa3 , respectively. 2. xsize0:1 = 11 indicates a burst transfer at the width of the dram device. 3. the burst is terminated in cycle 12 by deasserting the xreq input signal. a burst may also be terminated by deasserting either xsize0 or xsize1. 4. a4, a5, a30, and a31 are multiplexed with wbe0 , wbe1 , wbe2 , and wbe3 , respectively. slf erm bus width ext mux ras-to- cas refresh mode page mode first access burst access prechg cycles refresh ras refresh rate bit 13 bit 14 bits 15:16 bit 17 bit 18 bit 19 bit 20 bits 21:22 bits 23:24 bit 25 bit 26 bits 27:30 0 or 1 0 10 1 0 0 1 01 01 0 x xxxx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 sysclk r/w rasx cas0:3 dramoe dramwe d0:31 amuxcas holdreq holdack xsize0:1 1,2,3 ext bus master dram control ras cas pre- charge cas xreq bsel cas cas cas cas cas cas 11 11 11 valid address1 - ext master valid data1 - ext master address2 address3 address4 data2 data3 data4 a4:31 4 xreq 3 xack 17 18
ibm powerpc 403gc 46
ibm powerpc 403gc 47
? copyright ibm corporation 1996,1998. all rights reserved. printed in the usa on recycled paper. 9-98 ibm microelectronics, powerpc, powerpc architecture, and 403gc are trademarks, ibm and the ibm logo are registered trademarks of ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility of liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including but not limited to the implied warranties of merchantability or fitness for a particular purpose, are offered in this document. ibm microelectronics division 1580 route 52, bldg. 502 hopewell junction, ny 12533-6531 tel: (800) powerpc sc22-9893-04 09.09.98

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