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w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 1 - revision 1.0 w83194br - p4x data sheet revision history pages dates version version on web main contents 1 n.a. n.a. all of the versions before 0.50 are for internal use. 2 n.a. 02/july 1.0 n.a change version and version on web site to 1.0 3 4 , 10 07/aug 1.1 1.1 fs1 internal 120k pull up change to pull down . register 3: bit 0,1 pcistopb read back & cpustopb read back exchange. ch ange version and version on web site to 1.1 4 5 6 7 8 9 10 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this data sh eet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond c ustomers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 2 - revision 1.0 1. general description the w83194br - p4x is a clock synthesizer for v ia p4 chipset. w83194br - p4x provides all clocks required for high - speed microprocessor and provides step - less frequency programming and 32 different frequencies of cpu, pci, agp clocks setting. all clocks are externally selectable with smooth transitions. the w83194br - p4x provides i 2 c serial bus interface to program the registers to enable or disable each clock outputs and provides - 0.5% and +/ - 0.25% center type spread spectrum or programmable s.s.t. scale to reduce emi. the w83194br - p4x also has watch dog timer and reset output pin to support auto - reset when systems hanging caused by improper frequency setting. the w83194br - p4x accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. high drive pci clock outputs typically provide great er than 1 v /ns slew rate into 30 pf loads. the fixed frequency outputs as ref and 48 mhz provide better than 0.5v /ns slew rate. 2. product features 2 differential pairs of cpu clock outputs 1 differential pairs push pull of cpu_cs clock outputs 3 agp cloc k outputs 9 pci synchronous clocks 24_48mhz clock output for super i/o. 48 mhz clock output for usb. 2 ioapic clock outputs. 1 ref clock output. skew form cpu to pci clock 1 to 4 ns, center 2.6 ns smooth frequency switch with selections from 66.8 to 200mh z step - less frequency programming i 2 c 2 - wire serial interface and support byte read/write and block read/write. - 0.5% and +/ - 0.25% center type spread spectrum programmable s.s.t. scale to reduce emi programmable registers to enable/stop each output and se lect modes watch dog timer and reset# output pins 48 - pin ssop package
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 3 - revision 1.0 3. block diagram pll2 mux control logic & config register divider /2,/4,/8,/16 /3,/6,/12 /5,/10,/20 /7,/14 /9,/18 1/2 stop xtal osc pll1 spread spectrum stop m/n/ratio s.s.p rom driver vcoclk 48mhz 24_48mhz ref cpuclk_t 0:1, cs cpuclk_c 0:1, cs agp 0:2 pciclk_f pciclk_0:7 reset# rref xin xout *sdata *sdclk fs<4:0> pd# cpu_stop# pci_stop# multisel0 vttpwrgd# latch & por i2c interface 9 3 3 3 ioapic 0:1 2 **sel24_48 4. pin configuration gnd cpuclkc_cs cpuclk_t0 vddcpu(3.3v) iref * :internal 120k pull-up #: active low ioapic1 vddapic(2.5v) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 &sel24_48/ref vddref xin xout vdd48 gnd gnd *fs0/pciclk_f &fs1/pciclk0 *multisel0/pciclk1 pciclk2 gnd vddpci pciclk6 agp0 gnd *sdata *sdclk gnd ioapic0 vddcpu(2.5v) cpuclkt_cs cpuclk_c0 cpuclk_t1 gnd cpuclk_c1 vttpwrg# cpu_stop agp1 gnd pciclk7 pd# &fs3/48mhz &fs2/24_48mhz pciclk3 pciclk4 pciclk5 vddagp agp2 reset# pci_stop &:internal 120k pull-down
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 4 - revision 1.0 5. pin description in ? input in t p 12 0 k ? latched i nput at power up, internal 120ko pull up. in td12 0 k ? latched i nput at power up, internal 120ko pull down. out ? output od ? open drain i/o - bi - directional pin i/od ? bi - directional pin, open drain. # - active low * - internal 120k w pull - up & - internal 120 k w pull - down 5.1. crys tal i/o pin symbol i/o function 4 xin in crystal input with internal loading capacitors (18pf) and feedback resistors. 5 xout out crystal output at 14.318mhz nominally with internal loading capacitors (18pf). 5.2. cpu, agp, and pci, ioapic clock outputs pin symbol i/o function 34,35,39,40 cpuclk_t [0:1] cpuclk_c [0:1] out low skew (< 250ps) differential clock outputs for host frequencies of cpu 41,42 cpuclkt_cs cpuclkc_cs out low skew (< 250ps) differential push pull clock outputs for host frequencies of chipset 23,26,27 agp0: 2 out 3.3v agp clock outputs. pciclk_f out 3.3v free running pci clock output. 10 *fs0 in tp120k latched input for fs0 at initial power up for h/w selecting the output frequency. this is internal 120k pull up. pciclk0 out 3. 3v pci clock output. 11 *fs1 in tp120k latched input for fs1 at initial power up for h/w selecting the output frequency, this is internal 120k pull down. pciclk1 out 3.3v pci clock output. 12 *multi_sel0 in tp120k latched input for multsel0 at initial po wer up, internal 120k pull up 14,15,17,18, 19,21 pciclk [2:7] out low skew (< 250ps) pci clock outputs. 45,46 ioapic0: 1 out 2.5v pci/2 clock outputs.
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 5 - revision 1.0 5.3. i 2 c control interface pin number pin name type description 25 *sdata i/od serial data of i 2 c 2 - wire control interface with internal pull - up resistor . 26 *sdclk in serial clock of i 2 c 2 - wire control interface with internal pull - up resistor . 5.4. fixed frequency outputs pin symbol i/o function ref out 14.318mhz o utput. 1 &sel24_48 in tp120k latched input for 24mhz or 48mhz select pin. this is internal 120k pull down default 24mhz. in power on reset period, it is a hardware - latched pin, and it can be r/w by i2c control after power on reset period. select by registe r 16 bit 6. 48mhz out 48mhz clock output for usb. 7 &fs3 in tp120k latched input for fs3 at initial power up for h/w selecting the output frequency. this is internal 120k pull down. 24_48mhz out 24(default) or 48mhz clock output, in power on reset pe riod, it is a hardware - latched pin, and it can be r/w by i2c control after power on reset period. select by register 16 bit 7. 8 &fs2 in tp120k latched input for fs2 at initial power up for h/w selecting the output frequency. this is internal 120k pull down . 5.5 power management pins pin symbol i/o function 33 vttpwgd in power good input signal comes from acpi with high active. this 3.3v input is level sensitive strobe used to determine fs [4:0] and multisel input are valid and is ready to sample. this pin is high active. 32 *cpu_stop# in cpu clock stop control pin, this pin is low active. internal 120k w pull - up. 31 *pci_stop# in pci clock stop control pin, this pin is low active. internal 120k w pull - up. 37 iref in deciding the reference current for the cpuclk pairs. the pin was connected to the precision resistor tied to ground to decide the appropriate current. there are several modes to select different current via power on trapping the pin 12 (multisel). the table is show as follows. 30 reset# od sys tem reset signal when the watchdog is time out. this pin will generate 250ms low phase when the watchdog timer is timeout. 22 *pd# in power down function. this is power down pin, low active (pd#). internal 120k pull up
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 6 - revision 1.0 5.6 power pins pin number pin name t ype description 2 vddref pwr 3.3v power supply for ref. 16 vddpci pwr 3.3v power supply for pci. 24 vddagp pwr 3.3v power supply for agp. 38 vddcpu pwr 3.3v power supply for cpu. 43 vddcpu_cs pwr 2.5v power supply for cpuclkt & c _cs. 48 vddapic pwr 2.5v power supply for ioapic. 6 vdd48 pwr analog power 3.3v for 48mhz. 3,9,13,20,25, 36,44,47 gnd pwr ground pin for 3.3 v
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 7 - revision 1.0 hardware multsel [1:0] selects function multsel1 multsel0 board target trace/term z reference r, iref = add/(3*rr) output curr ent voh @ z 0 0 50 ? rr =221 1% iref = 5.00ma ioh=4*iref 1.0v @ 50 0 0 60 ? rr =221 1% iref = 5.00ma ioh=4*iref 1.2v @ 60 0 1 50 ? rr =221 1% iref = 5.00ma ioh=5*iref 1.25v @ 50 0 1 60 ? rr =221 1% iref = 5.00ma ioh=5*iref 1.5v @ 60 1 0 50 ? rr =221 1% iref = 5.00ma ioh= 6*iref 1.5v @ 50 1 0 60 ? rr =221 1% iref = 5.00ma ioh=6*iref 1.8v @ 60 1 1 50 ? rr =221 1% iref = 5.00ma ioh=7*iref 1.75v @ 50 1 1 60 ? rr =221 1% iref = 5.00ma ioh=7*iref 2.1v @ 50 0 0 50 ? rr =475 1% iref = 2.32ma ioh=4*iref 0.47v @ 50 0 0 60 ? rr =475 1% iref = 2.32ma ioh=4*iref 0.56v @ 50 0 1 50 ? rr =475 1% iref = 2.32ma ioh=5*iref 0.58v @ 50 0 1 60 ? rr =475 1% iref = 2.32ma ioh=5*iref 0.7v @ 60 1 0 50 ? rr =475 1% iref = 2.32ma ioh=6*iref 0.7v @ 50 1 0 60 ? rr =475 1% iref = 2.32ma ioh=6*ir ef 0.84v @ 60 1 1 50 ? rr =475 1% iref = 2.32ma ioh=7*iref 0.81v @ 50 1 0 60 ? rr =475 1% iref = 2.32ma ioh=6*iref 0.97v @ 60
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 8 - revision 1.0 frequency selection by hardware or softw are this frequency table is used at power on latched fs [4:0] value or software progra mming at ssel [4:0] (register 0 bit 6 ~ 2). fs4 fs3 fs2 fs1 fs0 cpu (mhz) agp (mhz) pci (mhz) ioapic (mhz) spread % 0 0 0 0 0 66.7 66.66 33.33 16.665 +/ - 0.25% 0 0 0 0 1 100.0 66.67 33.335 16.668 +/ - 0.25% 0 0 0 1 0 133.3 66.67 33.335 16.668 +/ - 0.25% 0 0 0 1 1 200.0 66.66 33.33 16.665 +/ - 0.25% 0 0 1 0 0 100.9 67.27 33.635 16.818 +/ - 0.25% 0 0 1 0 1 103.0 68.67 34.335 17.168 +/ - 0.25% 0 0 1 1 0 107.0 71.33 35.665 17.833 +/ - 0.25% 0 0 1 1 1 110.0 73.33 36.665 18.333 +/ - 0.25% 0 1 0 0 0 133.9 66.95 33.475 1 6.738 +/ - 0.25% 0 1 0 0 1 137.3 68.66 34.33 17.165 +/ - 0.25% 0 1 0 1 0 140.0 70 35 17.5 +/ - 0.25% 0 1 0 1 1 142.7 71.33 35.665 17.833 +/ - 0.25% 0 1 1 0 0 145.3 72.66 36.33 18.165 +/ - 0.25% 0 1 1 0 1 146.7 73.33 36.665 18.333 +/ - 0.25% 0 1 1 1 0 153.3 76.66 38.33 19.165 +/ - 0.25% 0 1 1 1 1 160.0 80 40 20 +/ - 0.25% 1 0 0 0 0 66.7 66.66 33.33 16.665 - 0.5% 1 0 0 0 1 100.0 66.67 33.335 16.668 - 0.5% 1 0 0 1 0 133.3 66.67 33.335 16.668 - 0.5% 1 0 0 1 1 200.0 66.66 33.33 16.665 - 0.5% 1 0 1 0 0 66.7 66.66 33.33 1 6.665 +/ - 0.25% 1 0 1 0 1 100.0 66.67 33.335 16.668 +/ - 0.25% 1 0 1 1 0 133.3 66.67 33.335 16.668 +/ - 0.25% 1 0 1 1 1 200.0 66.66 33.33 16.665 +/ - 0.25% 1 1 0 0 0 201.0 67 33.5 16.75 +/ - 0.25% 1 1 0 0 1 203.0 67.67 33.835 16.918 +/ - 0.25% 1 1 0 1 0 205.0 6 8.33 34.165 17.083 +/ - 0.25% 1 1 0 1 1 207.0 69 34.5 17.25 +/ - 0.25% 1 1 1 0 0 209.0 69.67 34.835 17.418 +/ - 0.25% 1 1 1 0 1 211.0 70.33 35.165 17.583 +/ - 0.25% 1 1 1 1 0 213.0 71 35.5 17.75 +/ - 0.25% 1 1 1 1 1 215.0 71.67 35.835 17.918 +/ - 0.25%
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 9 - revision 1.0 6. i 2 c con trol and status regi sters 6.1. register 0: frequency select register (default = 0) bit name pwd description 7 ssel [3] 0 6 ssel [2] 0 5 ssel [1] 0 4 ssel [0] 0 frequency selection by software via i 2 c 3 en_ssel 0 enable software program fs [4:0]. 0 = s elect frequency by hardware. 1= select frequency by software i 2 c - bit 7~ 4,2. 2 ssel [4] 0 frequency selection bit 4 1 en_spsp 0 enable spread spectrum in the frequency table. 0 = normal 1 = spread spectrum enabled 0 en_safe_freq 0 enable reload safe f requency when the watchdog is timeout. 0 = reload the fs [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at register 5 bit 4~0. 6.2. register 1: cpu clock register (1 = enable, 0 = stopped) bit pin # pwd description 7 42,4 1 1 cpuclk_t / c_cs 6 35,34 1 cpuclk_t1 / c1 5 40,39 1 cpuclk_t0 / c0 4 - x fs [4] read back. 3 - x fs [3] read back 2 - x fs [2] read back 1 - x fs [1] read back 0 - x fs [0] read back 6.3. register 2: pci clock register (1 = enable, 0 = stopped) bit p in # pwd description 7 21 1 pciclk7 6 19 1 pciclk6 5 18 1 pciclk5
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 10 - revision 1.0 4 17 1 pciclk4 3 15 1 pciclk3 2 14 1 pciclk2 1 12 1 pciclk1 0 11 1 pciclk0 6.4. register 3: pci, ref, 48mhz clock register (1 = enable, 0 = stopped) bit pin # pwd description 7 7 1 48mh z 6 8 1 24_48mhz 5 1 1 ref 4 10 1 pciclk_f 3 41,42 1 cpucs stop control: 0: cpuclk1 free run 1: cpuclk1 can stopped by cpu_stop# 2 8 0 pci_f stop control 0: pci_f free run 1: pci_f can stopped by pci_stop# 1 32 1 pcistopb read back 0 31 1 cpustopb read back 6.5. register 4:multisel1 ioapic, agp control register (1 = enable, 0 = stopped) bit pin # pwd description 7 - 0 multisel1 i2c r/w 6 - 1 reserved 5 - 1 reserved 4 45 1 ioapic1 3 46 1 ioapic0 2 27 1 agp2 1 26 1 agp1 0 23 1 agp0 6.6. register 5: watchdog control register bit name pwd description 7 multisel0 x pin 12 multisel0 power on trapping pin data read back 6 en_wd 0 enable watchdog timer if set to 1. set to 0, disable watchdog timer. read this bit will return a counting state. if timer continues down count, this bit will return 1.
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 11 - revision 1.0 otherwise, this bit will return 0. 5 wd_timeout 0 watchdog timeout status. if the watchdog is started and timer down counts to zero, this bit will be set to 1. clear this bit to logic 0, if set to 1, when the watchdog is restart in the next time. this bit is read only. 4 saf_freq [4] 0 3 s af_freq [3] 0 2 saf_freq [2] 0 1 saf_freq [1] 0 0 saf_freq [0] 0 watchdog safe frequency bits. these bits will be reloaded into fs [4:0], if the watchdog is timeout and enable reload safe frequency bits. ###### the register 6, 7 is reserved for buffer ###### 6.7. register 8: watchdog timer register bit name pwd description 7 wd_time [7] 0 6 wd_time [6] 0 5 wd_time [5] 0 4 wd_time [4] 0 3 wd_time [3] 1 2 wd_time [2] 0 1 wd_time [1] 0 0 wd_time [0] 0 watchdog timeout time. the bit resolution is 250 ms. the default time is 8*250ms = 2.0 seconds. if the watchdog timer is start, this register will be down count. read this register will return a down count value. 6.8. register 9: m/n program register bit name pwd description 7 n_div [8] 1 programmable n divisor value. bit 7 ~0 are defined in the register 10. 6 test2 0 test bit 2. winbond test bit, do not change them. 5 test1 1 test bit 1. winbond test bit, do not change them. 4 m_div [4] 0 3 m_div [3] 1 2 m_div [2] 1 1 m_div [1] 0 0 m_div [0] 1 programmable m divisor value.
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 12 - revision 1.0 6.9. register 10: m/n program register bit name pwd description 7 n_div [7] 0 6 n_div [6] 1 5 n_div [5] 1 4 n_div [4] 0 3 n_div [3] 0 2 n_div [2] 1 1 n_div [1] 1 0 n_div [0] 1 programmable n divisor va lue bit 7 ~0. the bit 8 is defined in register 9. 6.10. register 11: spread spectrum programming register bit name pwd description 7 sp_up [3] 0 spr ead spectrum up counter bit 3. 6 sp_up [2] 0 spread spectrum up counter bit 2. 5 sp_up [1] 0 spread spectrum up counter bit 1. 4 sp_up [0] 1 spread spectrum up counter bit 0 3 sp_down [3] 1 spread spectrum down counter bit 3 2 sp_down [2] 1 spread spe ctrum down counter bit 2 1 sp_down [1] 1 spread spectrum down counter bit 1 0 sp_down [0] 1 spread spectrum down counter bit 0 6.11. register 12: divisor and step - less enable control register bit name pwd description 7 en_mn_prog 0 0: use frequency table 1: use m/n register to program frequency the equation is vco freq. = 14.318mhz * (n+4)/ m . when the watchdog timer is timeout, this will be clear. in this time, the frequency is set to hardware default latched or safe frequency set by en_sfae_freq (register 0 bit 0). 6 ratio_sel [4] 0 5 ratio_sel [3] 0 4 ratio_sel [2] 0 3 ratio_sel [1] 1 2 ratio_sel [0] 0 cpu, pci, agp, ratio selection. the ratio is shown as following table.
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 13 - revision 1.0 1 test0 0 0 reserved 0 test bit 0. winbond test bit, do not change them. i2c reg12 definition reg12 reg12 reg12 reg12 reg12 bit6 bit5 bit4 bit3 bit2 cpu cpu_cs ioapic agp pci ssel4 ssel3 ssel2 ssel1 ssel0 ratio ratio ratio ratio ratio 0 0 0 0 0 2 2 24 6 12 0 0 0 0 1 3 3 24 6 12 0 0 0 1 0 4 4 24 6 12 0 0 0 1 1 6 6 24 6 12 0 0 1 0 0 4 4 24 6 12 0 0 1 0 1 4 4 24 6 12 0 0 1 1 0 4 4 24 6 12 0 0 1 1 1 4 4 24 6 12 0 1 0 0 0 4 4 24 6 12 0 1 0 0 1 5 5 16 8 16 0 1 0 1 0 5 5 16 8 16 0 1 0 1 1 5 5 24 6 12 0 1 1 0 0 5 5 24 6 12 0 1 1 0 1 5 5 16 8 16 0 1 1 1 0 5 5 20 10 20 0 1 1 1 1 5 5 16 8 16 1 0 0 0 0 5 5 20 10 20 1 0 0 0 1 5 5 20 10 20 1 0 0 1 0 6 6 20 10 20 1 0 0 1 1 6 6 24 6 12 1 0 1 0 0 6 6 16 8 16 1 0 1 0 1 6 6 14 7 14 1 0 1 1 0 6 6 18 9 18 1 0 1 1 1 6 6 14 12 14 1 1 0 0 0 2 2 16 8 16 1 1 0 0 1 3 3 24 12 24 1 1 0 1 0 4 4 16 8 16 1 1 0 1 1 6 6 16 8 16 1 1 1 0 0 2 2 14 7 14 1 1 1 0 1 2 2 18 9 18
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 14 - revision 1.0 1 1 1 1 0 4 4 14 7 14 1 1 1 1 1 4 4 18 9 18 6.12. register 13: cpu to ioapic skew control bit name pwd description 7 cpu_ioapic_skew [2] 1 cpu to ioapic skew control 6 reserved 0 reserved 5 reserved 1 4 reserved 0 3 reserved 0 2 reserved 1 1 reserved 1 0 reserved 1 re served for winbond internal use, do not change them 6.13. register 14: cpu to pci and ioapic skew control bit name pwd description 7 cpu_pci_skew [2] 1 6 cpu_pci_skew [1] 0 5 cpu_pci_skew [0] 0 cpu to pci skew 4 cpu_agp_skew [2] 1 3 cpu_agp_skew [1] 0 2 cpu_agp_skew [0] 0 cpu to agp skew 1 cpu_ioapic_skew [1] 0 0 cpu_ioapic_skew [0] 0 cpu to ioapic skew control 6.14. register 15: sel24_48 and cpu to cpucs skew control bit name p wd description 7 sel24_48 x in power on reset period, it is a hardware - latched pin, and it can be r/w by i2c control after power on reset period. 0 - > 24 mhz, 1 - >48mhz. default is 24mhz 6 reserved 0 reserved 5 reserved 0 reserved for winbond internal u se, do not change them 4 reserved 0 3 reserved 0 reserved for winbond internal use, do not change them 2 cpu_cpucs_skew [2] 1 1 cpu_cpucs_skew [1] 0 cpu to cpucs skew
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 15 - revision 1.0 0 cpu_cpucs_skew [0] 0 6.15. register 16: reserved bit name pwd description 7 rese rved 1 6 reserved 1 reserved for winbond internal use, do not change them 5 reserved 1 4 reserved 1 reserved for winbond internal use, do not change them 3 reserved 1 2 reserved 1 reserved for winbond internal use, do not change them 1 reserved 1 0 reserved 1 reserved for winbond internal use, do not change them 6.16. register 17: reserved bit name pwd description 7 reserved 1 6 reserved 1 reserved for winbond internal use, do not change them 5 reserved 1 4 reserved 1 reserved for winbond internal use, do not change them 3 reserved 1 2 reserved 1 reserved for winbond internal use, do not change them 1 reserved 0 0 reserved 0 reserved for winbond internal use, do not change them 6.17. register 18: reserved bit name pwd description 7 reserved 1 6 reserved 1 reserved for winbond internal use, do not change them 5 reserved 1 4 reserved 1 reserved for winbond internal use, do not change them 3 reserved 1 2 reserved 1 reserved
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 16 - revision 1.0 1 reserved 1 0 reserved 1 reserved 6.18. register 19: winbond ch ip id register (read only) bit name pwd description 7 chpi_id [7] 0 winbond chip id. w83194br - p4x is 0x57. 6 chpi_id [6] 1 winbond chip id. 5 chpi_id [5] 0 winbond chip id. 4 chpi_id [4] 1 winbond chip id. 3 chpi_id [3] 0 winbond chip id. 2 chpi_id [2] 1 winbond chip id. 1 chpi_id [1] 1 winbond chip id. 0 chpi_id [0] 1 winbond chip id. 6.19. register 20: winbond chip id register (read only) bit name pwd description 7 sub_id [3] 0 winbond sub - chip id. the sub - chip id of w83194br - p4x is defined as 0010b . 6 sub_id [2] 0 winbond sub - chip id. 5 sub_id [1] 0 winbond sub - chip id. 4 sub_id [0] 1 winbond sub - chip id. 3 ver_id [3] 0 winbond version id. the version id of w83194br - p4x is 0001b. 2 ver_id [2] 0 winbond version id. 1 ver_id [1] 0 winbond versio n id. 0 ver_id [0] 1 winbond version id. 7. access interface the w83194br - p4x provides i 2 c serial bus for microprocessor to read/write internal registers. in the w83194br - p4x is provided block read/block write and byte - data read/write protocol . the i 2 c a ddress is defined at 0xd2. 7.1. block read and block write protocol 7.1 block write protocol
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 17 - revision 1.0 7.2 block read protocol ## in block mode, the command code must filled 8?h00 7.3 byte write protocol 7.4 byte read protocol 7.2. the serial bus access timing (a ) serial bus writes to internal address register followed by the data byte 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by slave r/w ack by slave scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack by 784r stop by master scl sda (continued) 7 8 0 7 8 0 7 8 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte figure 1. serial bus write to internal address register followed by the data byte
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 18 - revision 1.0 (b) serial bus writes to internal address register only 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by slave r/w ack by slave scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte figure 2. serial bus write to internal address register only stop by master (c) serial bus read from a register with the internal address register prefer to desired location 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/w ack by slave scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte figure 3. serial bus read from internal address register stop by master (d) serial bus read from a register with writing to internal address register 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by slave r/w ack by slave scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte 0 repeat start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/w ack by slave scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte figure 4. serial bus read from writing internal address register stop by master ... ... ... ...
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 19 - revision 1.0 8. ordering informatio n part number package type production flow w83194br - p4x 48 pin ssop commercial, 0 c to +70 c 9. how to read the top marking 1st line: winbond logo and the type number: w83194br - p4x 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 814 g b b 214 : packages made in ' 2002 , week 14 g : assembly house id; o means ose, g means gr a : internal use code b : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their resp ective owners. w83194br - p4x 28051234 214gab
w83194br - p4x stepless clock for via p4 chipset publication release date:july.2002 - 20 - revision 1.0 10. package drawing and dimensions headquarters no. 4, creation rd. iii science - based industrial park hsinchu, taiwan tel: 886 - 35 - 770066 fax: 886 - 35 - 789467 www: http://www.winbond.com.tw/ taipei office 9f, no. 480, rueiguang road, neihu district, taipei, 114, taiwa n tel: 886 - 2 - 81777168 fax: 886 - 2 - 87153579 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852 - 27516023 - 7 fax: 852 - 27552064 winbond electronics (north america) corp. 2727 n orth first street san jose, california 95134 tel: 1 - 408 - 9436666 fax: 1 - 408 - 9436668 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their re spective owners . these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale.

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